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8
9#include <drm/drmP.h>
10#include <drm/exynos_drm.h>
11
12#include <linux/clk.h>
13#include <linux/component.h>
14#include <linux/kernel.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pm_runtime.h>
20
21#include <video/of_display_timing.h>
22#include <video/of_videomode.h>
23
24#include "exynos_drm_crtc.h"
25#include "exynos_drm_plane.h"
26#include "exynos_drm_drv.h"
27#include "exynos_drm_fb.h"
28#include "regs-decon7.h"
29
30
31
32
33
34#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
35
36#define WINDOWS_NR 2
37
38struct decon_context {
39 struct device *dev;
40 struct drm_device *drm_dev;
41 struct exynos_drm_crtc *crtc;
42 struct exynos_drm_plane planes[WINDOWS_NR];
43 struct exynos_drm_plane_config configs[WINDOWS_NR];
44 struct clk *pclk;
45 struct clk *aclk;
46 struct clk *eclk;
47 struct clk *vclk;
48 void __iomem *regs;
49 unsigned long irq_flags;
50 bool i80_if;
51 bool suspended;
52 wait_queue_head_t wait_vsync_queue;
53 atomic_t wait_vsync_event;
54
55 struct drm_encoder *encoder;
56};
57
58static const struct of_device_id decon_driver_dt_match[] = {
59 {.compatible = "samsung,exynos7-decon"},
60 {},
61};
62MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
63
64static const uint32_t decon_formats[] = {
65 DRM_FORMAT_RGB565,
66 DRM_FORMAT_XRGB8888,
67 DRM_FORMAT_XBGR8888,
68 DRM_FORMAT_RGBX8888,
69 DRM_FORMAT_BGRX8888,
70 DRM_FORMAT_ARGB8888,
71 DRM_FORMAT_ABGR8888,
72 DRM_FORMAT_RGBA8888,
73 DRM_FORMAT_BGRA8888,
74};
75
76static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
77 DRM_PLANE_TYPE_PRIMARY,
78 DRM_PLANE_TYPE_CURSOR,
79};
80
81static void decon_wait_for_vblank(struct exynos_drm_crtc *crtc)
82{
83 struct decon_context *ctx = crtc->ctx;
84
85 if (ctx->suspended)
86 return;
87
88 atomic_set(&ctx->wait_vsync_event, 1);
89
90
91
92
93
94 if (!wait_event_timeout(ctx->wait_vsync_queue,
95 !atomic_read(&ctx->wait_vsync_event),
96 HZ/20))
97 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
98}
99
100static void decon_clear_channels(struct exynos_drm_crtc *crtc)
101{
102 struct decon_context *ctx = crtc->ctx;
103 unsigned int win, ch_enabled = 0;
104
105
106 for (win = 0; win < WINDOWS_NR; win++) {
107 u32 val = readl(ctx->regs + WINCON(win));
108
109 if (val & WINCONx_ENWIN) {
110 val &= ~WINCONx_ENWIN;
111 writel(val, ctx->regs + WINCON(win));
112 ch_enabled = 1;
113 }
114 }
115
116
117 if (ch_enabled)
118 decon_wait_for_vblank(ctx->crtc);
119}
120
121static int decon_ctx_initialize(struct decon_context *ctx,
122 struct drm_device *drm_dev)
123{
124 ctx->drm_dev = drm_dev;
125
126 decon_clear_channels(ctx->crtc);
127
128 return exynos_drm_register_dma(drm_dev, ctx->dev);
129}
130
131static void decon_ctx_remove(struct decon_context *ctx)
132{
133
134 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
135}
136
137static u32 decon_calc_clkdiv(struct decon_context *ctx,
138 const struct drm_display_mode *mode)
139{
140 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
141 u32 clkdiv;
142
143
144 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->vclk), ideal_clk);
145
146 return (clkdiv < 0x100) ? clkdiv : 0xff;
147}
148
149static void decon_commit(struct exynos_drm_crtc *crtc)
150{
151 struct decon_context *ctx = crtc->ctx;
152 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
153 u32 val, clkdiv;
154
155 if (ctx->suspended)
156 return;
157
158
159 if (mode->htotal == 0 || mode->vtotal == 0)
160 return;
161
162 if (!ctx->i80_if) {
163 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
164
165 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
166 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
167 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
168
169 val = VIDTCON0_VBPD(vbpd - 1) | VIDTCON0_VFPD(vfpd - 1);
170 writel(val, ctx->regs + VIDTCON0);
171
172 val = VIDTCON1_VSPW(vsync_len - 1);
173 writel(val, ctx->regs + VIDTCON1);
174
175
176 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
177 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
178 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
179
180
181 val = VIDTCON2_HBPD(hbpd - 1) | VIDTCON2_HFPD(hfpd - 1);
182 writel(val, ctx->regs + VIDTCON2);
183
184 val = VIDTCON3_HSPW(hsync_len - 1);
185 writel(val, ctx->regs + VIDTCON3);
186 }
187
188
189 val = VIDTCON4_LINEVAL(mode->vdisplay - 1) |
190 VIDTCON4_HOZVAL(mode->hdisplay - 1);
191 writel(val, ctx->regs + VIDTCON4);
192
193 writel(mode->vdisplay - 1, ctx->regs + LINECNT_OP_THRESHOLD);
194
195
196
197
198
199 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
200 writel(val, ctx->regs + VIDCON0);
201
202 clkdiv = decon_calc_clkdiv(ctx, mode);
203 if (clkdiv > 1) {
204 val = VCLKCON1_CLKVAL_NUM_VCLK(clkdiv - 1);
205 writel(val, ctx->regs + VCLKCON1);
206 writel(val, ctx->regs + VCLKCON2);
207 }
208
209 val = readl(ctx->regs + DECON_UPDATE);
210 val |= DECON_UPDATE_STANDALONE_F;
211 writel(val, ctx->regs + DECON_UPDATE);
212}
213
214static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
215{
216 struct decon_context *ctx = crtc->ctx;
217 u32 val;
218
219 if (ctx->suspended)
220 return -EPERM;
221
222 if (!test_and_set_bit(0, &ctx->irq_flags)) {
223 val = readl(ctx->regs + VIDINTCON0);
224
225 val |= VIDINTCON0_INT_ENABLE;
226
227 if (!ctx->i80_if) {
228 val |= VIDINTCON0_INT_FRAME;
229 val &= ~VIDINTCON0_FRAMESEL0_MASK;
230 val |= VIDINTCON0_FRAMESEL0_VSYNC;
231 }
232
233 writel(val, ctx->regs + VIDINTCON0);
234 }
235
236 return 0;
237}
238
239static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
240{
241 struct decon_context *ctx = crtc->ctx;
242 u32 val;
243
244 if (ctx->suspended)
245 return;
246
247 if (test_and_clear_bit(0, &ctx->irq_flags)) {
248 val = readl(ctx->regs + VIDINTCON0);
249
250 val &= ~VIDINTCON0_INT_ENABLE;
251 if (!ctx->i80_if)
252 val &= ~VIDINTCON0_INT_FRAME;
253
254 writel(val, ctx->regs + VIDINTCON0);
255 }
256}
257
258static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
259 struct drm_framebuffer *fb)
260{
261 unsigned long val;
262 int padding;
263
264 val = readl(ctx->regs + WINCON(win));
265 val &= ~WINCONx_BPPMODE_MASK;
266
267 switch (fb->format->format) {
268 case DRM_FORMAT_RGB565:
269 val |= WINCONx_BPPMODE_16BPP_565;
270 val |= WINCONx_BURSTLEN_16WORD;
271 break;
272 case DRM_FORMAT_XRGB8888:
273 val |= WINCONx_BPPMODE_24BPP_xRGB;
274 val |= WINCONx_BURSTLEN_16WORD;
275 break;
276 case DRM_FORMAT_XBGR8888:
277 val |= WINCONx_BPPMODE_24BPP_xBGR;
278 val |= WINCONx_BURSTLEN_16WORD;
279 break;
280 case DRM_FORMAT_RGBX8888:
281 val |= WINCONx_BPPMODE_24BPP_RGBx;
282 val |= WINCONx_BURSTLEN_16WORD;
283 break;
284 case DRM_FORMAT_BGRX8888:
285 val |= WINCONx_BPPMODE_24BPP_BGRx;
286 val |= WINCONx_BURSTLEN_16WORD;
287 break;
288 case DRM_FORMAT_ARGB8888:
289 val |= WINCONx_BPPMODE_32BPP_ARGB | WINCONx_BLD_PIX |
290 WINCONx_ALPHA_SEL;
291 val |= WINCONx_BURSTLEN_16WORD;
292 break;
293 case DRM_FORMAT_ABGR8888:
294 val |= WINCONx_BPPMODE_32BPP_ABGR | WINCONx_BLD_PIX |
295 WINCONx_ALPHA_SEL;
296 val |= WINCONx_BURSTLEN_16WORD;
297 break;
298 case DRM_FORMAT_RGBA8888:
299 val |= WINCONx_BPPMODE_32BPP_RGBA | WINCONx_BLD_PIX |
300 WINCONx_ALPHA_SEL;
301 val |= WINCONx_BURSTLEN_16WORD;
302 break;
303 case DRM_FORMAT_BGRA8888:
304 default:
305 val |= WINCONx_BPPMODE_32BPP_BGRA | WINCONx_BLD_PIX |
306 WINCONx_ALPHA_SEL;
307 val |= WINCONx_BURSTLEN_16WORD;
308 break;
309 }
310
311 DRM_DEV_DEBUG_KMS(ctx->dev, "cpp = %d\n", fb->format->cpp[0]);
312
313
314
315
316
317
318
319
320
321 padding = (fb->pitches[0] / fb->format->cpp[0]) - fb->width;
322 if (fb->width + padding < MIN_FB_WIDTH_FOR_16WORD_BURST) {
323 val &= ~WINCONx_BURSTLEN_MASK;
324 val |= WINCONx_BURSTLEN_8WORD;
325 }
326
327 writel(val, ctx->regs + WINCON(win));
328}
329
330static void decon_win_set_colkey(struct decon_context *ctx, unsigned int win)
331{
332 unsigned int keycon0 = 0, keycon1 = 0;
333
334 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
335 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
336
337 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
338
339 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
340 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
341}
342
343
344
345
346
347
348
349static void decon_shadow_protect_win(struct decon_context *ctx,
350 unsigned int win, bool protect)
351{
352 u32 bits, val;
353
354 bits = SHADOWCON_WINx_PROTECT(win);
355
356 val = readl(ctx->regs + SHADOWCON);
357 if (protect)
358 val |= bits;
359 else
360 val &= ~bits;
361 writel(val, ctx->regs + SHADOWCON);
362}
363
364static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
365{
366 struct decon_context *ctx = crtc->ctx;
367 int i;
368
369 if (ctx->suspended)
370 return;
371
372 for (i = 0; i < WINDOWS_NR; i++)
373 decon_shadow_protect_win(ctx, i, true);
374}
375
376static void decon_update_plane(struct exynos_drm_crtc *crtc,
377 struct exynos_drm_plane *plane)
378{
379 struct exynos_drm_plane_state *state =
380 to_exynos_plane_state(plane->base.state);
381 struct decon_context *ctx = crtc->ctx;
382 struct drm_framebuffer *fb = state->base.fb;
383 int padding;
384 unsigned long val, alpha;
385 unsigned int last_x;
386 unsigned int last_y;
387 unsigned int win = plane->index;
388 unsigned int cpp = fb->format->cpp[0];
389 unsigned int pitch = fb->pitches[0];
390
391 if (ctx->suspended)
392 return;
393
394
395
396
397
398
399
400
401
402
403
404
405 val = (unsigned long)exynos_drm_fb_dma_addr(fb, 0);
406 writel(val, ctx->regs + VIDW_BUF_START(win));
407
408 padding = (pitch / cpp) - fb->width;
409
410
411 writel(fb->width + padding, ctx->regs + VIDW_WHOLE_X(win));
412 writel(fb->height, ctx->regs + VIDW_WHOLE_Y(win));
413
414
415 writel(state->src.x, ctx->regs + VIDW_OFFSET_X(win));
416 writel(state->src.y, ctx->regs + VIDW_OFFSET_Y(win));
417
418 DRM_DEV_DEBUG_KMS(ctx->dev, "start addr = 0x%lx\n",
419 (unsigned long)val);
420 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
421 state->crtc.w, state->crtc.h);
422
423 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
424 VIDOSDxA_TOPLEFT_Y(state->crtc.y);
425 writel(val, ctx->regs + VIDOSD_A(win));
426
427 last_x = state->crtc.x + state->crtc.w;
428 if (last_x)
429 last_x--;
430 last_y = state->crtc.y + state->crtc.h;
431 if (last_y)
432 last_y--;
433
434 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y);
435
436 writel(val, ctx->regs + VIDOSD_B(win));
437
438 DRM_DEV_DEBUG_KMS(ctx->dev, "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
439 state->crtc.x, state->crtc.y, last_x, last_y);
440
441
442 alpha = VIDOSDxC_ALPHA0_R_F(0x0) |
443 VIDOSDxC_ALPHA0_G_F(0x0) |
444 VIDOSDxC_ALPHA0_B_F(0x0);
445
446 writel(alpha, ctx->regs + VIDOSD_C(win));
447
448 alpha = VIDOSDxD_ALPHA1_R_F(0xff) |
449 VIDOSDxD_ALPHA1_G_F(0xff) |
450 VIDOSDxD_ALPHA1_B_F(0xff);
451
452 writel(alpha, ctx->regs + VIDOSD_D(win));
453
454 decon_win_set_pixfmt(ctx, win, fb);
455
456
457 if (win != 0)
458 decon_win_set_colkey(ctx, win);
459
460
461 val = readl(ctx->regs + WINCON(win));
462 val |= WINCONx_TRIPLE_BUF_MODE;
463 val |= WINCONx_ENWIN;
464 writel(val, ctx->regs + WINCON(win));
465
466
467 decon_shadow_protect_win(ctx, win, false);
468
469 val = readl(ctx->regs + DECON_UPDATE);
470 val |= DECON_UPDATE_STANDALONE_F;
471 writel(val, ctx->regs + DECON_UPDATE);
472}
473
474static void decon_disable_plane(struct exynos_drm_crtc *crtc,
475 struct exynos_drm_plane *plane)
476{
477 struct decon_context *ctx = crtc->ctx;
478 unsigned int win = plane->index;
479 u32 val;
480
481 if (ctx->suspended)
482 return;
483
484
485 decon_shadow_protect_win(ctx, win, true);
486
487
488 val = readl(ctx->regs + WINCON(win));
489 val &= ~WINCONx_ENWIN;
490 writel(val, ctx->regs + WINCON(win));
491
492 val = readl(ctx->regs + DECON_UPDATE);
493 val |= DECON_UPDATE_STANDALONE_F;
494 writel(val, ctx->regs + DECON_UPDATE);
495}
496
497static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
498{
499 struct decon_context *ctx = crtc->ctx;
500 int i;
501
502 if (ctx->suspended)
503 return;
504
505 for (i = 0; i < WINDOWS_NR; i++)
506 decon_shadow_protect_win(ctx, i, false);
507 exynos_crtc_handle_event(crtc);
508}
509
510static void decon_init(struct decon_context *ctx)
511{
512 u32 val;
513
514 writel(VIDCON0_SWRESET, ctx->regs + VIDCON0);
515
516 val = VIDOUTCON0_DISP_IF_0_ON;
517 if (!ctx->i80_if)
518 val |= VIDOUTCON0_RGBIF;
519 writel(val, ctx->regs + VIDOUTCON0);
520
521 writel(VCLKCON0_CLKVALUP | VCLKCON0_VCLKFREE, ctx->regs + VCLKCON0);
522
523 if (!ctx->i80_if)
524 writel(VIDCON1_VCLK_HOLD, ctx->regs + VIDCON1(0));
525}
526
527static void decon_enable(struct exynos_drm_crtc *crtc)
528{
529 struct decon_context *ctx = crtc->ctx;
530
531 if (!ctx->suspended)
532 return;
533
534 pm_runtime_get_sync(ctx->dev);
535
536 decon_init(ctx);
537
538
539 if (test_and_clear_bit(0, &ctx->irq_flags))
540 decon_enable_vblank(ctx->crtc);
541
542 decon_commit(ctx->crtc);
543
544 ctx->suspended = false;
545}
546
547static void decon_disable(struct exynos_drm_crtc *crtc)
548{
549 struct decon_context *ctx = crtc->ctx;
550 int i;
551
552 if (ctx->suspended)
553 return;
554
555
556
557
558
559
560 for (i = 0; i < WINDOWS_NR; i++)
561 decon_disable_plane(crtc, &ctx->planes[i]);
562
563 pm_runtime_put_sync(ctx->dev);
564
565 ctx->suspended = true;
566}
567
568static const struct exynos_drm_crtc_ops decon_crtc_ops = {
569 .enable = decon_enable,
570 .disable = decon_disable,
571 .enable_vblank = decon_enable_vblank,
572 .disable_vblank = decon_disable_vblank,
573 .atomic_begin = decon_atomic_begin,
574 .update_plane = decon_update_plane,
575 .disable_plane = decon_disable_plane,
576 .atomic_flush = decon_atomic_flush,
577};
578
579
580static irqreturn_t decon_irq_handler(int irq, void *dev_id)
581{
582 struct decon_context *ctx = (struct decon_context *)dev_id;
583 u32 val, clear_bit;
584
585 val = readl(ctx->regs + VIDINTCON1);
586
587 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
588 if (val & clear_bit)
589 writel(clear_bit, ctx->regs + VIDINTCON1);
590
591
592 if (!ctx->drm_dev)
593 goto out;
594
595 if (!ctx->i80_if) {
596 drm_crtc_handle_vblank(&ctx->crtc->base);
597
598
599 if (atomic_read(&ctx->wait_vsync_event)) {
600 atomic_set(&ctx->wait_vsync_event, 0);
601 wake_up(&ctx->wait_vsync_queue);
602 }
603 }
604out:
605 return IRQ_HANDLED;
606}
607
608static int decon_bind(struct device *dev, struct device *master, void *data)
609{
610 struct decon_context *ctx = dev_get_drvdata(dev);
611 struct drm_device *drm_dev = data;
612 struct exynos_drm_plane *exynos_plane;
613 unsigned int i;
614 int ret;
615
616 ret = decon_ctx_initialize(ctx, drm_dev);
617 if (ret) {
618 DRM_DEV_ERROR(dev, "decon_ctx_initialize failed.\n");
619 return ret;
620 }
621
622 for (i = 0; i < WINDOWS_NR; i++) {
623 ctx->configs[i].pixel_formats = decon_formats;
624 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(decon_formats);
625 ctx->configs[i].zpos = i;
626 ctx->configs[i].type = decon_win_types[i];
627
628 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
629 &ctx->configs[i]);
630 if (ret)
631 return ret;
632 }
633
634 exynos_plane = &ctx->planes[DEFAULT_WIN];
635 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
636 EXYNOS_DISPLAY_TYPE_LCD, &decon_crtc_ops, ctx);
637 if (IS_ERR(ctx->crtc)) {
638 decon_ctx_remove(ctx);
639 return PTR_ERR(ctx->crtc);
640 }
641
642 if (ctx->encoder)
643 exynos_dpi_bind(drm_dev, ctx->encoder);
644
645 return 0;
646
647}
648
649static void decon_unbind(struct device *dev, struct device *master,
650 void *data)
651{
652 struct decon_context *ctx = dev_get_drvdata(dev);
653
654 decon_disable(ctx->crtc);
655
656 if (ctx->encoder)
657 exynos_dpi_remove(ctx->encoder);
658
659 decon_ctx_remove(ctx);
660}
661
662static const struct component_ops decon_component_ops = {
663 .bind = decon_bind,
664 .unbind = decon_unbind,
665};
666
667static int decon_probe(struct platform_device *pdev)
668{
669 struct device *dev = &pdev->dev;
670 struct decon_context *ctx;
671 struct device_node *i80_if_timings;
672 struct resource *res;
673 int ret;
674
675 if (!dev->of_node)
676 return -ENODEV;
677
678 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
679 if (!ctx)
680 return -ENOMEM;
681
682 ctx->dev = dev;
683 ctx->suspended = true;
684
685 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
686 if (i80_if_timings)
687 ctx->i80_if = true;
688 of_node_put(i80_if_timings);
689
690 ctx->regs = of_iomap(dev->of_node, 0);
691 if (!ctx->regs)
692 return -ENOMEM;
693
694 ctx->pclk = devm_clk_get(dev, "pclk_decon0");
695 if (IS_ERR(ctx->pclk)) {
696 dev_err(dev, "failed to get bus clock pclk\n");
697 ret = PTR_ERR(ctx->pclk);
698 goto err_iounmap;
699 }
700
701 ctx->aclk = devm_clk_get(dev, "aclk_decon0");
702 if (IS_ERR(ctx->aclk)) {
703 dev_err(dev, "failed to get bus clock aclk\n");
704 ret = PTR_ERR(ctx->aclk);
705 goto err_iounmap;
706 }
707
708 ctx->eclk = devm_clk_get(dev, "decon0_eclk");
709 if (IS_ERR(ctx->eclk)) {
710 dev_err(dev, "failed to get eclock\n");
711 ret = PTR_ERR(ctx->eclk);
712 goto err_iounmap;
713 }
714
715 ctx->vclk = devm_clk_get(dev, "decon0_vclk");
716 if (IS_ERR(ctx->vclk)) {
717 dev_err(dev, "failed to get vclock\n");
718 ret = PTR_ERR(ctx->vclk);
719 goto err_iounmap;
720 }
721
722 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
723 ctx->i80_if ? "lcd_sys" : "vsync");
724 if (!res) {
725 dev_err(dev, "irq request failed.\n");
726 ret = -ENXIO;
727 goto err_iounmap;
728 }
729
730 ret = devm_request_irq(dev, res->start, decon_irq_handler,
731 0, "drm_decon", ctx);
732 if (ret) {
733 dev_err(dev, "irq request failed.\n");
734 goto err_iounmap;
735 }
736
737 init_waitqueue_head(&ctx->wait_vsync_queue);
738 atomic_set(&ctx->wait_vsync_event, 0);
739
740 platform_set_drvdata(pdev, ctx);
741
742 ctx->encoder = exynos_dpi_probe(dev);
743 if (IS_ERR(ctx->encoder)) {
744 ret = PTR_ERR(ctx->encoder);
745 goto err_iounmap;
746 }
747
748 pm_runtime_enable(dev);
749
750 ret = component_add(dev, &decon_component_ops);
751 if (ret)
752 goto err_disable_pm_runtime;
753
754 return ret;
755
756err_disable_pm_runtime:
757 pm_runtime_disable(dev);
758
759err_iounmap:
760 iounmap(ctx->regs);
761
762 return ret;
763}
764
765static int decon_remove(struct platform_device *pdev)
766{
767 struct decon_context *ctx = dev_get_drvdata(&pdev->dev);
768
769 pm_runtime_disable(&pdev->dev);
770
771 iounmap(ctx->regs);
772
773 component_del(&pdev->dev, &decon_component_ops);
774
775 return 0;
776}
777
778#ifdef CONFIG_PM
779static int exynos7_decon_suspend(struct device *dev)
780{
781 struct decon_context *ctx = dev_get_drvdata(dev);
782
783 clk_disable_unprepare(ctx->vclk);
784 clk_disable_unprepare(ctx->eclk);
785 clk_disable_unprepare(ctx->aclk);
786 clk_disable_unprepare(ctx->pclk);
787
788 return 0;
789}
790
791static int exynos7_decon_resume(struct device *dev)
792{
793 struct decon_context *ctx = dev_get_drvdata(dev);
794 int ret;
795
796 ret = clk_prepare_enable(ctx->pclk);
797 if (ret < 0) {
798 DRM_DEV_ERROR(dev, "Failed to prepare_enable the pclk [%d]\n",
799 ret);
800 return ret;
801 }
802
803 ret = clk_prepare_enable(ctx->aclk);
804 if (ret < 0) {
805 DRM_DEV_ERROR(dev, "Failed to prepare_enable the aclk [%d]\n",
806 ret);
807 return ret;
808 }
809
810 ret = clk_prepare_enable(ctx->eclk);
811 if (ret < 0) {
812 DRM_DEV_ERROR(dev, "Failed to prepare_enable the eclk [%d]\n",
813 ret);
814 return ret;
815 }
816
817 ret = clk_prepare_enable(ctx->vclk);
818 if (ret < 0) {
819 DRM_DEV_ERROR(dev, "Failed to prepare_enable the vclk [%d]\n",
820 ret);
821 return ret;
822 }
823
824 return 0;
825}
826#endif
827
828static const struct dev_pm_ops exynos7_decon_pm_ops = {
829 SET_RUNTIME_PM_OPS(exynos7_decon_suspend, exynos7_decon_resume,
830 NULL)
831 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
832 pm_runtime_force_resume)
833};
834
835struct platform_driver decon_driver = {
836 .probe = decon_probe,
837 .remove = decon_remove,
838 .driver = {
839 .name = "exynos-decon",
840 .pm = &exynos7_decon_pm_ops,
841 .of_match_table = decon_driver_dt_match,
842 },
843};
844
