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8
9#include <drm/drmP.h>
10
11#include <linux/kernel.h>
12#include <linux/platform_device.h>
13#include <linux/clk.h>
14#include <linux/of.h>
15#include <linux/of_device.h>
16#include <linux/pm_runtime.h>
17#include <linux/component.h>
18#include <linux/mfd/syscon.h>
19#include <linux/regmap.h>
20
21#include <video/of_display_timing.h>
22#include <video/of_videomode.h>
23#include <video/samsung_fimd.h>
24#include <drm/exynos_drm.h>
25
26#include "exynos_drm_drv.h"
27#include "exynos_drm_fb.h"
28#include "exynos_drm_crtc.h"
29#include "exynos_drm_plane.h"
30
31
32
33
34
35
36
37
38#define MIN_FB_WIDTH_FOR_16WORD_BURST 128
39
40
41#define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
42#define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
43
44
45
46
47#define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
48
49#define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
50
51#define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
52#define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
53
54#define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
55#define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
56#define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
57#define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
58
59
60#define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
61
62#define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
63
64
65#define TRIGCON 0x1A4
66#define TRGMODE_ENABLE (1 << 0)
67#define SWTRGCMD_ENABLE (1 << 1)
68
69#define HWTRGEN_ENABLE (1 << 3)
70#define HWTRGMASK_ENABLE (1 << 4)
71
72#define HWTRIGEN_PER_ENABLE (1 << 31)
73
74
75#define VIDOUT_CON 0x000
76#define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
77
78
79#define I80IFCONFAx(x) (0x1B0 + (x) * 4)
80#define I80IFCONFBx(x) (0x1B8 + (x) * 4)
81#define LCD_CS_SETUP(x) ((x) << 16)
82#define LCD_WR_SETUP(x) ((x) << 12)
83#define LCD_WR_ACTIVE(x) ((x) << 8)
84#define LCD_WR_HOLD(x) ((x) << 4)
85#define I80IFEN_ENABLE (1 << 0)
86
87
88#define WINDOWS_NR 5
89
90
91#define I80_HW_TRG (1 << 1)
92
93struct fimd_driver_data {
94 unsigned int timing_base;
95 unsigned int lcdblk_offset;
96 unsigned int lcdblk_vt_shift;
97 unsigned int lcdblk_bypass_shift;
98 unsigned int lcdblk_mic_bypass_shift;
99 unsigned int trg_type;
100
101 unsigned int has_shadowcon:1;
102 unsigned int has_clksel:1;
103 unsigned int has_limited_fmt:1;
104 unsigned int has_vidoutcon:1;
105 unsigned int has_vtsel:1;
106 unsigned int has_mic_bypass:1;
107 unsigned int has_dp_clk:1;
108 unsigned int has_hw_trigger:1;
109 unsigned int has_trigger_per_te:1;
110};
111
112static struct fimd_driver_data s3c64xx_fimd_driver_data = {
113 .timing_base = 0x0,
114 .has_clksel = 1,
115 .has_limited_fmt = 1,
116};
117
118static struct fimd_driver_data s5pv210_fimd_driver_data = {
119 .timing_base = 0x0,
120 .has_shadowcon = 1,
121 .has_clksel = 1,
122};
123
124static struct fimd_driver_data exynos3_fimd_driver_data = {
125 .timing_base = 0x20000,
126 .lcdblk_offset = 0x210,
127 .lcdblk_bypass_shift = 1,
128 .has_shadowcon = 1,
129 .has_vidoutcon = 1,
130};
131
132static struct fimd_driver_data exynos4_fimd_driver_data = {
133 .timing_base = 0x0,
134 .lcdblk_offset = 0x210,
135 .lcdblk_vt_shift = 10,
136 .lcdblk_bypass_shift = 1,
137 .has_shadowcon = 1,
138 .has_vtsel = 1,
139};
140
141static struct fimd_driver_data exynos5_fimd_driver_data = {
142 .timing_base = 0x20000,
143 .lcdblk_offset = 0x214,
144 .lcdblk_vt_shift = 24,
145 .lcdblk_bypass_shift = 15,
146 .has_shadowcon = 1,
147 .has_vidoutcon = 1,
148 .has_vtsel = 1,
149 .has_dp_clk = 1,
150};
151
152static struct fimd_driver_data exynos5420_fimd_driver_data = {
153 .timing_base = 0x20000,
154 .lcdblk_offset = 0x214,
155 .lcdblk_vt_shift = 24,
156 .lcdblk_bypass_shift = 15,
157 .lcdblk_mic_bypass_shift = 11,
158 .has_shadowcon = 1,
159 .has_vidoutcon = 1,
160 .has_vtsel = 1,
161 .has_mic_bypass = 1,
162 .has_dp_clk = 1,
163};
164
165struct fimd_context {
166 struct device *dev;
167 struct drm_device *drm_dev;
168 struct exynos_drm_crtc *crtc;
169 struct exynos_drm_plane planes[WINDOWS_NR];
170 struct exynos_drm_plane_config configs[WINDOWS_NR];
171 struct clk *bus_clk;
172 struct clk *lcd_clk;
173 void __iomem *regs;
174 struct regmap *sysreg;
175 unsigned long irq_flags;
176 u32 vidcon0;
177 u32 vidcon1;
178 u32 vidout_con;
179 u32 i80ifcon;
180 bool i80_if;
181 bool suspended;
182 wait_queue_head_t wait_vsync_queue;
183 atomic_t wait_vsync_event;
184 atomic_t win_updated;
185 atomic_t triggering;
186 u32 clkdiv;
187
188 const struct fimd_driver_data *driver_data;
189 struct drm_encoder *encoder;
190 struct exynos_drm_clk dp_clk;
191};
192
193static const struct of_device_id fimd_driver_dt_match[] = {
194 { .compatible = "samsung,s3c6400-fimd",
195 .data = &s3c64xx_fimd_driver_data },
196 { .compatible = "samsung,s5pv210-fimd",
197 .data = &s5pv210_fimd_driver_data },
198 { .compatible = "samsung,exynos3250-fimd",
199 .data = &exynos3_fimd_driver_data },
200 { .compatible = "samsung,exynos4210-fimd",
201 .data = &exynos4_fimd_driver_data },
202 { .compatible = "samsung,exynos5250-fimd",
203 .data = &exynos5_fimd_driver_data },
204 { .compatible = "samsung,exynos5420-fimd",
205 .data = &exynos5420_fimd_driver_data },
206 {},
207};
208MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
209
210static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
211 DRM_PLANE_TYPE_PRIMARY,
212 DRM_PLANE_TYPE_OVERLAY,
213 DRM_PLANE_TYPE_OVERLAY,
214 DRM_PLANE_TYPE_OVERLAY,
215 DRM_PLANE_TYPE_CURSOR,
216};
217
218static const uint32_t fimd_formats[] = {
219 DRM_FORMAT_C8,
220 DRM_FORMAT_XRGB1555,
221 DRM_FORMAT_RGB565,
222 DRM_FORMAT_XRGB8888,
223 DRM_FORMAT_ARGB8888,
224};
225
226static const unsigned int capabilities[WINDOWS_NR] = {
227 0,
228 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
229 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
230 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
231 EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
232};
233
234static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
235 u32 val)
236{
237 val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
238 writel(val, ctx->regs + reg);
239}
240
241static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
242{
243 struct fimd_context *ctx = crtc->ctx;
244 u32 val;
245
246 if (ctx->suspended)
247 return -EPERM;
248
249 if (!test_and_set_bit(0, &ctx->irq_flags)) {
250 val = readl(ctx->regs + VIDINTCON0);
251
252 val |= VIDINTCON0_INT_ENABLE;
253
254 if (ctx->i80_if) {
255 val |= VIDINTCON0_INT_I80IFDONE;
256 val |= VIDINTCON0_INT_SYSMAINCON;
257 val &= ~VIDINTCON0_INT_SYSSUBCON;
258 } else {
259 val |= VIDINTCON0_INT_FRAME;
260
261 val &= ~VIDINTCON0_FRAMESEL0_MASK;
262 val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
263 val &= ~VIDINTCON0_FRAMESEL1_MASK;
264 val |= VIDINTCON0_FRAMESEL1_NONE;
265 }
266
267 writel(val, ctx->regs + VIDINTCON0);
268 }
269
270 return 0;
271}
272
273static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
274{
275 struct fimd_context *ctx = crtc->ctx;
276 u32 val;
277
278 if (ctx->suspended)
279 return;
280
281 if (test_and_clear_bit(0, &ctx->irq_flags)) {
282 val = readl(ctx->regs + VIDINTCON0);
283
284 val &= ~VIDINTCON0_INT_ENABLE;
285
286 if (ctx->i80_if) {
287 val &= ~VIDINTCON0_INT_I80IFDONE;
288 val &= ~VIDINTCON0_INT_SYSMAINCON;
289 val &= ~VIDINTCON0_INT_SYSSUBCON;
290 } else
291 val &= ~VIDINTCON0_INT_FRAME;
292
293 writel(val, ctx->regs + VIDINTCON0);
294 }
295}
296
297static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
298{
299 struct fimd_context *ctx = crtc->ctx;
300
301 if (ctx->suspended)
302 return;
303
304 atomic_set(&ctx->wait_vsync_event, 1);
305
306
307
308
309
310 if (!wait_event_timeout(ctx->wait_vsync_queue,
311 !atomic_read(&ctx->wait_vsync_event),
312 HZ/20))
313 DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
314}
315
316static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
317 bool enable)
318{
319 u32 val = readl(ctx->regs + WINCON(win));
320
321 if (enable)
322 val |= WINCONx_ENWIN;
323 else
324 val &= ~WINCONx_ENWIN;
325
326 writel(val, ctx->regs + WINCON(win));
327}
328
329static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
330 unsigned int win,
331 bool enable)
332{
333 u32 val = readl(ctx->regs + SHADOWCON);
334
335 if (enable)
336 val |= SHADOWCON_CHx_ENABLE(win);
337 else
338 val &= ~SHADOWCON_CHx_ENABLE(win);
339
340 writel(val, ctx->regs + SHADOWCON);
341}
342
343static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
344{
345 struct fimd_context *ctx = crtc->ctx;
346 unsigned int win, ch_enabled = 0;
347
348
349 pm_runtime_get_sync(ctx->dev);
350
351 clk_prepare_enable(ctx->bus_clk);
352 clk_prepare_enable(ctx->lcd_clk);
353
354
355 for (win = 0; win < WINDOWS_NR; win++) {
356 u32 val = readl(ctx->regs + WINCON(win));
357
358 if (val & WINCONx_ENWIN) {
359 fimd_enable_video_output(ctx, win, false);
360
361 if (ctx->driver_data->has_shadowcon)
362 fimd_enable_shadow_channel_path(ctx, win,
363 false);
364
365 ch_enabled = 1;
366 }
367 }
368
369
370 if (ch_enabled) {
371 ctx->suspended = false;
372
373 fimd_enable_vblank(ctx->crtc);
374 fimd_wait_for_vblank(ctx->crtc);
375 fimd_disable_vblank(ctx->crtc);
376
377 ctx->suspended = true;
378 }
379
380 clk_disable_unprepare(ctx->lcd_clk);
381 clk_disable_unprepare(ctx->bus_clk);
382
383 pm_runtime_put(ctx->dev);
384}
385
386
387static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
388 struct drm_crtc_state *state)
389{
390 struct drm_display_mode *mode = &state->adjusted_mode;
391 struct fimd_context *ctx = crtc->ctx;
392 unsigned long ideal_clk, lcd_rate;
393 u32 clkdiv;
394
395 if (mode->clock == 0) {
396 DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
397 return -EINVAL;
398 }
399
400 ideal_clk = mode->clock * 1000;
401
402 if (ctx->i80_if) {
403
404
405
406
407 ideal_clk *= 2;
408 }
409
410 lcd_rate = clk_get_rate(ctx->lcd_clk);
411 if (2 * lcd_rate < ideal_clk) {
412 DRM_DEV_ERROR(ctx->dev,
413 "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
414 lcd_rate, ideal_clk);
415 return -EINVAL;
416 }
417
418
419 clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
420 if (clkdiv >= 0x200) {
421 DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
422 ideal_clk);
423 return -EINVAL;
424 }
425
426 ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
427
428 return 0;
429}
430
431static void fimd_setup_trigger(struct fimd_context *ctx)
432{
433 void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
434 u32 trg_type = ctx->driver_data->trg_type;
435 u32 val = readl(timing_base + TRIGCON);
436
437 val &= ~(TRGMODE_ENABLE);
438
439 if (trg_type == I80_HW_TRG) {
440 if (ctx->driver_data->has_hw_trigger)
441 val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
442 if (ctx->driver_data->has_trigger_per_te)
443 val |= HWTRIGEN_PER_ENABLE;
444 } else {
445 val |= TRGMODE_ENABLE;
446 }
447
448 writel(val, timing_base + TRIGCON);
449}
450
451static void fimd_commit(struct exynos_drm_crtc *crtc)
452{
453 struct fimd_context *ctx = crtc->ctx;
454 struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
455 const struct fimd_driver_data *driver_data = ctx->driver_data;
456 void *timing_base = ctx->regs + driver_data->timing_base;
457 u32 val;
458
459 if (ctx->suspended)
460 return;
461
462
463 if (mode->htotal == 0 || mode->vtotal == 0)
464 return;
465
466 if (ctx->i80_if) {
467 val = ctx->i80ifcon | I80IFEN_ENABLE;
468 writel(val, timing_base + I80IFCONFAx(0));
469
470
471 writel(0, timing_base + I80IFCONFBx(0));
472
473
474 if (driver_data->has_vtsel && ctx->sysreg &&
475 regmap_update_bits(ctx->sysreg,
476 driver_data->lcdblk_offset,
477 0x3 << driver_data->lcdblk_vt_shift,
478 0x1 << driver_data->lcdblk_vt_shift)) {
479 DRM_DEV_ERROR(ctx->dev,
480 "Failed to update sysreg for I80 i/f.\n");
481 return;
482 }
483 } else {
484 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
485 u32 vidcon1;
486
487
488 vidcon1 = ctx->vidcon1;
489 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
490 vidcon1 |= VIDCON1_INV_VSYNC;
491 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
492 vidcon1 |= VIDCON1_INV_HSYNC;
493 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
494
495
496 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
497 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
498 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
499
500 val = VIDTCON0_VBPD(vbpd - 1) |
501 VIDTCON0_VFPD(vfpd - 1) |
502 VIDTCON0_VSPW(vsync_len - 1);
503 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
504
505
506 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
507 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
508 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
509
510 val = VIDTCON1_HBPD(hbpd - 1) |
511 VIDTCON1_HFPD(hfpd - 1) |
512 VIDTCON1_HSPW(hsync_len - 1);
513 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
514 }
515
516 if (driver_data->has_vidoutcon)
517 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
518
519
520 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
521 driver_data->lcdblk_offset,
522 0x1 << driver_data->lcdblk_bypass_shift,
523 0x1 << driver_data->lcdblk_bypass_shift)) {
524 DRM_DEV_ERROR(ctx->dev,
525 "Failed to update sysreg for bypass setting.\n");
526 return;
527 }
528
529
530
531
532 if (driver_data->has_mic_bypass && ctx->sysreg &&
533 regmap_update_bits(ctx->sysreg,
534 driver_data->lcdblk_offset,
535 0x1 << driver_data->lcdblk_mic_bypass_shift,
536 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
537 DRM_DEV_ERROR(ctx->dev,
538 "Failed to update sysreg for bypass mic.\n");
539 return;
540 }
541
542
543 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
544 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
545 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
546 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
547 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
548
549 fimd_setup_trigger(ctx);
550
551
552
553
554
555 val = ctx->vidcon0;
556 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
557
558 if (ctx->driver_data->has_clksel)
559 val |= VIDCON0_CLKSEL_LCD;
560
561 if (ctx->clkdiv > 1)
562 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
563
564 writel(val, ctx->regs + VIDCON0);
565}
566
567static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
568 unsigned int alpha, unsigned int pixel_alpha)
569{
570 u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
571 u32 val = 0;
572
573 switch (pixel_alpha) {
574 case DRM_MODE_BLEND_PIXEL_NONE:
575 case DRM_MODE_BLEND_COVERAGE:
576 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
577 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
578 break;
579 case DRM_MODE_BLEND_PREMULTI:
580 default:
581 if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
582 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
583 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
584 } else {
585 val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
586 val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
587 }
588 break;
589 }
590 fimd_set_bits(ctx, BLENDEQx(win), mask, val);
591}
592
593static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
594 unsigned int alpha, unsigned int pixel_alpha)
595{
596 u32 win_alpha_l = (alpha >> 8) & 0xf;
597 u32 win_alpha_h = alpha >> 12;
598 u32 val = 0;
599
600 switch (pixel_alpha) {
601 case DRM_MODE_BLEND_PIXEL_NONE:
602 break;
603 case DRM_MODE_BLEND_COVERAGE:
604 case DRM_MODE_BLEND_PREMULTI:
605 default:
606 val |= WINCON1_ALPHA_SEL;
607 val |= WINCON1_BLD_PIX;
608 val |= WINCON1_ALPHA_MUL;
609 break;
610 }
611 fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
612
613
614 val = VIDISD14C_ALPHA0_R(win_alpha_h) |
615 VIDISD14C_ALPHA0_G(win_alpha_h) |
616 VIDISD14C_ALPHA0_B(win_alpha_h) |
617 VIDISD14C_ALPHA1_R(0x0) |
618 VIDISD14C_ALPHA1_G(0x0) |
619 VIDISD14C_ALPHA1_B(0x0);
620 writel(val, ctx->regs + VIDOSD_C(win));
621
622 val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
623 VIDW_ALPHA_B(win_alpha_l);
624 writel(val, ctx->regs + VIDWnALPHA0(win));
625
626 val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
627 VIDW_ALPHA_B(0x0);
628 writel(val, ctx->regs + VIDWnALPHA1(win));
629
630 fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
631 BLENDCON_NEW_8BIT_ALPHA_VALUE);
632}
633
634static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
635 struct drm_framebuffer *fb, int width)
636{
637 struct exynos_drm_plane plane = ctx->planes[win];
638 struct exynos_drm_plane_state *state =
639 to_exynos_plane_state(plane.base.state);
640 uint32_t pixel_format = fb->format->format;
641 unsigned int alpha = state->base.alpha;
642 u32 val = WINCONx_ENWIN;
643 unsigned int pixel_alpha;
644
645 if (fb->format->has_alpha)
646 pixel_alpha = state->base.pixel_blend_mode;
647 else
648 pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
649
650
651
652
653
654 if (ctx->driver_data->has_limited_fmt && !win) {
655 if (pixel_format == DRM_FORMAT_ARGB8888)
656 pixel_format = DRM_FORMAT_XRGB8888;
657 }
658
659 switch (pixel_format) {
660 case DRM_FORMAT_C8:
661 val |= WINCON0_BPPMODE_8BPP_PALETTE;
662 val |= WINCONx_BURSTLEN_8WORD;
663 val |= WINCONx_BYTSWP;
664 break;
665 case DRM_FORMAT_XRGB1555:
666 val |= WINCON0_BPPMODE_16BPP_1555;
667 val |= WINCONx_HAWSWP;
668 val |= WINCONx_BURSTLEN_16WORD;
669 break;
670 case DRM_FORMAT_RGB565:
671 val |= WINCON0_BPPMODE_16BPP_565;
672 val |= WINCONx_HAWSWP;
673 val |= WINCONx_BURSTLEN_16WORD;
674 break;
675 case DRM_FORMAT_XRGB8888:
676 val |= WINCON0_BPPMODE_24BPP_888;
677 val |= WINCONx_WSWP;
678 val |= WINCONx_BURSTLEN_16WORD;
679 break;
680 case DRM_FORMAT_ARGB8888:
681 default:
682 val |= WINCON1_BPPMODE_25BPP_A1888;
683 val |= WINCONx_WSWP;
684 val |= WINCONx_BURSTLEN_16WORD;
685 break;
686 }
687
688
689
690
691
692
693
694
695
696 if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
697 val &= ~WINCONx_BURSTLEN_MASK;
698 val |= WINCONx_BURSTLEN_4WORD;
699 }
700 fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
701
702
703 if (win != 0) {
704 fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
705 fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
706 }
707}
708
709static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
710{
711 unsigned int keycon0 = 0, keycon1 = 0;
712
713 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
714 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
715
716 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
717
718 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
719 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
720}
721
722
723
724
725
726
727
728static void fimd_shadow_protect_win(struct fimd_context *ctx,
729 unsigned int win, bool protect)
730{
731 u32 reg, bits, val;
732
733
734
735
736
737
738
739
740
741
742
743 if (ctx->driver_data->has_shadowcon) {
744 reg = SHADOWCON;
745 bits = SHADOWCON_WINx_PROTECT(win);
746 } else {
747 reg = PRTCON;
748 bits = PRTCON_PROTECT;
749 }
750
751 val = readl(ctx->regs + reg);
752 if (protect)
753 val |= bits;
754 else
755 val &= ~bits;
756 writel(val, ctx->regs + reg);
757}
758
759static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
760{
761 struct fimd_context *ctx = crtc->ctx;
762 int i;
763
764 if (ctx->suspended)
765 return;
766
767 for (i = 0; i < WINDOWS_NR; i++)
768 fimd_shadow_protect_win(ctx, i, true);
769}
770
771static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
772{
773 struct fimd_context *ctx = crtc->ctx;
774 int i;
775
776 if (ctx->suspended)
777 return;
778
779 for (i = 0; i < WINDOWS_NR; i++)
780 fimd_shadow_protect_win(ctx, i, false);
781
782 exynos_crtc_handle_event(crtc);
783}
784
785static void fimd_update_plane(struct exynos_drm_crtc *crtc,
786 struct exynos_drm_plane *plane)
787{
788 struct exynos_drm_plane_state *state =
789 to_exynos_plane_state(plane->base.state);
790 struct fimd_context *ctx = crtc->ctx;
791 struct drm_framebuffer *fb = state->base.fb;
792 dma_addr_t dma_addr;
793 unsigned long val, size, offset;
794 unsigned int last_x, last_y, buf_offsize, line_size;
795 unsigned int win = plane->index;
796 unsigned int cpp = fb->format->cpp[0];
797 unsigned int pitch = fb->pitches[0];
798
799 if (ctx->suspended)
800 return;
801
802 offset = state->src.x * cpp;
803 offset += state->src.y * pitch;
804
805
806 dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
807 val = (unsigned long)dma_addr;
808 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
809
810
811 size = pitch * state->crtc.h;
812 val = (unsigned long)(dma_addr + size);
813 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
814
815 DRM_DEV_DEBUG_KMS(ctx->dev,
816 "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
817 (unsigned long)dma_addr, val, size);
818 DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
819 state->crtc.w, state->crtc.h);
820
821
822 buf_offsize = pitch - (state->crtc.w * cpp);
823 line_size = state->crtc.w * cpp;
824 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
825 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
826 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
827 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
828 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
829
830
831 val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
832 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
833 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
834 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
835 writel(val, ctx->regs + VIDOSD_A(win));
836
837 last_x = state->crtc.x + state->crtc.w;
838 if (last_x)
839 last_x--;
840 last_y = state->crtc.y + state->crtc.h;
841 if (last_y)
842 last_y--;
843
844 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
845 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
846
847 writel(val, ctx->regs + VIDOSD_B(win));
848
849 DRM_DEV_DEBUG_KMS(ctx->dev,
850 "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
851 state->crtc.x, state->crtc.y, last_x, last_y);
852
853
854 if (win != 3 && win != 4) {
855 u32 offset = VIDOSD_D(win);
856 if (win == 0)
857 offset = VIDOSD_C(win);
858 val = state->crtc.w * state->crtc.h;
859 writel(val, ctx->regs + offset);
860
861 DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
862 (unsigned int)val);
863 }
864
865 fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
866
867
868 if (win != 0)
869 fimd_win_set_colkey(ctx, win);
870
871 fimd_enable_video_output(ctx, win, true);
872
873 if (ctx->driver_data->has_shadowcon)
874 fimd_enable_shadow_channel_path(ctx, win, true);
875
876 if (ctx->i80_if)
877 atomic_set(&ctx->win_updated, 1);
878}
879
880static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
881 struct exynos_drm_plane *plane)
882{
883 struct fimd_context *ctx = crtc->ctx;
884 unsigned int win = plane->index;
885
886 if (ctx->suspended)
887 return;
888
889 fimd_enable_video_output(ctx, win, false);
890
891 if (ctx->driver_data->has_shadowcon)
892 fimd_enable_shadow_channel_path(ctx, win, false);
893}
894
895static void fimd_enable(struct exynos_drm_crtc *crtc)
896{
897 struct fimd_context *ctx = crtc->ctx;
898
899 if (!ctx->suspended)
900 return;
901
902 ctx->suspended = false;
903
904 pm_runtime_get_sync(ctx->dev);
905
906
907 if (test_and_clear_bit(0, &ctx->irq_flags))
908 fimd_enable_vblank(ctx->crtc);
909
910 fimd_commit(ctx->crtc);
911}
912
913static void fimd_disable(struct exynos_drm_crtc *crtc)
914{
915 struct fimd_context *ctx = crtc->ctx;
916 int i;
917
918 if (ctx->suspended)
919 return;
920
921
922
923
924
925
926 for (i = 0; i < WINDOWS_NR; i++)
927 fimd_disable_plane(crtc, &ctx->planes[i]);
928
929 fimd_enable_vblank(crtc);
930 fimd_wait_for_vblank(crtc);
931 fimd_disable_vblank(crtc);
932
933 writel(0, ctx->regs + VIDCON0);
934
935 pm_runtime_put_sync(ctx->dev);
936 ctx->suspended = true;
937}
938
939static void fimd_trigger(struct device *dev)
940{
941 struct fimd_context *ctx = dev_get_drvdata(dev);
942 const struct fimd_driver_data *driver_data = ctx->driver_data;
943 void *timing_base = ctx->regs + driver_data->timing_base;
944 u32 reg;
945
946
947
948
949
950 if (atomic_read(&ctx->triggering))
951 return;
952
953
954 atomic_set(&ctx->triggering, 1);
955
956 reg = readl(timing_base + TRIGCON);
957 reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
958 writel(reg, timing_base + TRIGCON);
959
960
961
962
963
964 if (!test_bit(0, &ctx->irq_flags))
965 atomic_set(&ctx->triggering, 0);
966}
967
968static void fimd_te_handler(struct exynos_drm_crtc *crtc)
969{
970 struct fimd_context *ctx = crtc->ctx;
971 u32 trg_type = ctx->driver_data->trg_type;
972
973
974 if (!ctx->drm_dev)
975 return;
976
977 if (trg_type == I80_HW_TRG)
978 goto out;
979
980
981
982
983
984 if (atomic_add_unless(&ctx->win_updated, -1, 0))
985 fimd_trigger(ctx->dev);
986
987out:
988
989 if (atomic_read(&ctx->wait_vsync_event)) {
990 atomic_set(&ctx->wait_vsync_event, 0);
991 wake_up(&ctx->wait_vsync_queue);
992 }
993
994 if (test_bit(0, &ctx->irq_flags))
995 drm_crtc_handle_vblank(&ctx->crtc->base);
996}
997
998static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
999{
1000 struct fimd_context *ctx = container_of(clk, struct fimd_context,
1001 dp_clk);
1002 u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
1003 writel(val, ctx->regs + DP_MIE_CLKCON);
1004}
1005
1006static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
1007 .enable = fimd_enable,
1008 .disable = fimd_disable,
1009 .enable_vblank = fimd_enable_vblank,
1010 .disable_vblank = fimd_disable_vblank,
1011 .atomic_begin = fimd_atomic_begin,
1012 .update_plane = fimd_update_plane,
1013 .disable_plane = fimd_disable_plane,
1014 .atomic_flush = fimd_atomic_flush,
1015 .atomic_check = fimd_atomic_check,
1016 .te_handler = fimd_te_handler,
1017};
1018
1019static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1020{
1021 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1022 u32 val, clear_bit;
1023
1024 val = readl(ctx->regs + VIDINTCON1);
1025
1026 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1027 if (val & clear_bit)
1028 writel(clear_bit, ctx->regs + VIDINTCON1);
1029
1030
1031 if (!ctx->drm_dev)
1032 goto out;
1033
1034 if (!ctx->i80_if)
1035 drm_crtc_handle_vblank(&ctx->crtc->base);
1036
1037 if (ctx->i80_if) {
1038
1039 atomic_set(&ctx->triggering, 0);
1040 } else {
1041
1042 if (atomic_read(&ctx->wait_vsync_event)) {
1043 atomic_set(&ctx->wait_vsync_event, 0);
1044 wake_up(&ctx->wait_vsync_queue);
1045 }
1046 }
1047
1048out:
1049 return IRQ_HANDLED;
1050}
1051
1052static int fimd_bind(struct device *dev, struct device *master, void *data)
1053{
1054 struct fimd_context *ctx = dev_get_drvdata(dev);
1055 struct drm_device *drm_dev = data;
1056 struct exynos_drm_plane *exynos_plane;
1057 unsigned int i;
1058 int ret;
1059
1060 ctx->drm_dev = drm_dev;
1061
1062 for (i = 0; i < WINDOWS_NR; i++) {
1063 ctx->configs[i].pixel_formats = fimd_formats;
1064 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
1065 ctx->configs[i].zpos = i;
1066 ctx->configs[i].type = fimd_win_types[i];
1067 ctx->configs[i].capabilities = capabilities[i];
1068 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
1069 &ctx->configs[i]);
1070 if (ret)
1071 return ret;
1072 }
1073
1074 exynos_plane = &ctx->planes[DEFAULT_WIN];
1075 ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1076 EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1077 if (IS_ERR(ctx->crtc))
1078 return PTR_ERR(ctx->crtc);
1079
1080 if (ctx->driver_data->has_dp_clk) {
1081 ctx->dp_clk.enable = fimd_dp_clock_enable;
1082 ctx->crtc->pipe_clk = &ctx->dp_clk;
1083 }
1084
1085 if (ctx->encoder)
1086 exynos_dpi_bind(drm_dev, ctx->encoder);
1087
1088 if (is_drm_iommu_supported(drm_dev))
1089 fimd_clear_channels(ctx->crtc);
1090
1091 return exynos_drm_register_dma(drm_dev, dev);
1092}
1093
1094static void fimd_unbind(struct device *dev, struct device *master,
1095 void *data)
1096{
1097 struct fimd_context *ctx = dev_get_drvdata(dev);
1098
1099 fimd_disable(ctx->crtc);
1100
1101 exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev);
1102
1103 if (ctx->encoder)
1104 exynos_dpi_remove(ctx->encoder);
1105}
1106
1107static const struct component_ops fimd_component_ops = {
1108 .bind = fimd_bind,
1109 .unbind = fimd_unbind,
1110};
1111
1112static int fimd_probe(struct platform_device *pdev)
1113{
1114 struct device *dev = &pdev->dev;
1115 struct fimd_context *ctx;
1116 struct device_node *i80_if_timings;
1117 struct resource *res;
1118 int ret;
1119
1120 if (!dev->of_node)
1121 return -ENODEV;
1122
1123 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1124 if (!ctx)
1125 return -ENOMEM;
1126
1127 ctx->dev = dev;
1128 ctx->suspended = true;
1129 ctx->driver_data = of_device_get_match_data(dev);
1130
1131 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1132 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1133 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1134 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1135
1136 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1137 if (i80_if_timings) {
1138 u32 val;
1139
1140 ctx->i80_if = true;
1141
1142 if (ctx->driver_data->has_vidoutcon)
1143 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1144 else
1145 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1146
1147
1148
1149
1150 ctx->vidcon0 |= VIDCON0_DSI_EN;
1151
1152 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1153 val = 0;
1154 ctx->i80ifcon = LCD_CS_SETUP(val);
1155 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1156 val = 0;
1157 ctx->i80ifcon |= LCD_WR_SETUP(val);
1158 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1159 val = 1;
1160 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1161 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1162 val = 0;
1163 ctx->i80ifcon |= LCD_WR_HOLD(val);
1164 }
1165 of_node_put(i80_if_timings);
1166
1167 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1168 "samsung,sysreg");
1169 if (IS_ERR(ctx->sysreg)) {
1170 dev_warn(dev, "failed to get system register.\n");
1171 ctx->sysreg = NULL;
1172 }
1173
1174 ctx->bus_clk = devm_clk_get(dev, "fimd");
1175 if (IS_ERR(ctx->bus_clk)) {
1176 dev_err(dev, "failed to get bus clock\n");
1177 return PTR_ERR(ctx->bus_clk);
1178 }
1179
1180 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1181 if (IS_ERR(ctx->lcd_clk)) {
1182 dev_err(dev, "failed to get lcd clock\n");
1183 return PTR_ERR(ctx->lcd_clk);
1184 }
1185
1186 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1187
1188 ctx->regs = devm_ioremap_resource(dev, res);
1189 if (IS_ERR(ctx->regs))
1190 return PTR_ERR(ctx->regs);
1191
1192 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1193 ctx->i80_if ? "lcd_sys" : "vsync");
1194 if (!res) {
1195 dev_err(dev, "irq request failed.\n");
1196 return -ENXIO;
1197 }
1198
1199 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1200 0, "drm_fimd", ctx);
1201 if (ret) {
1202 dev_err(dev, "irq request failed.\n");
1203 return ret;
1204 }
1205
1206 init_waitqueue_head(&ctx->wait_vsync_queue);
1207 atomic_set(&ctx->wait_vsync_event, 0);
1208
1209 platform_set_drvdata(pdev, ctx);
1210
1211 ctx->encoder = exynos_dpi_probe(dev);
1212 if (IS_ERR(ctx->encoder))
1213 return PTR_ERR(ctx->encoder);
1214
1215 pm_runtime_enable(dev);
1216
1217 ret = component_add(dev, &fimd_component_ops);
1218 if (ret)
1219 goto err_disable_pm_runtime;
1220
1221 return ret;
1222
1223err_disable_pm_runtime:
1224 pm_runtime_disable(dev);
1225
1226 return ret;
1227}
1228
1229static int fimd_remove(struct platform_device *pdev)
1230{
1231 pm_runtime_disable(&pdev->dev);
1232
1233 component_del(&pdev->dev, &fimd_component_ops);
1234
1235 return 0;
1236}
1237
1238#ifdef CONFIG_PM
1239static int exynos_fimd_suspend(struct device *dev)
1240{
1241 struct fimd_context *ctx = dev_get_drvdata(dev);
1242
1243 clk_disable_unprepare(ctx->lcd_clk);
1244 clk_disable_unprepare(ctx->bus_clk);
1245
1246 return 0;
1247}
1248
1249static int exynos_fimd_resume(struct device *dev)
1250{
1251 struct fimd_context *ctx = dev_get_drvdata(dev);
1252 int ret;
1253
1254 ret = clk_prepare_enable(ctx->bus_clk);
1255 if (ret < 0) {
1256 DRM_DEV_ERROR(dev,
1257 "Failed to prepare_enable the bus clk [%d]\n",
1258 ret);
1259 return ret;
1260 }
1261
1262 ret = clk_prepare_enable(ctx->lcd_clk);
1263 if (ret < 0) {
1264 DRM_DEV_ERROR(dev,
1265 "Failed to prepare_enable the lcd clk [%d]\n",
1266 ret);
1267 return ret;
1268 }
1269
1270 return 0;
1271}
1272#endif
1273
1274static const struct dev_pm_ops exynos_fimd_pm_ops = {
1275 SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1276 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1277 pm_runtime_force_resume)
1278};
1279
1280struct platform_driver fimd_driver = {
1281 .probe = fimd_probe,
1282 .remove = fimd_remove,
1283 .driver = {
1284 .name = "exynos4-fb",
1285 .owner = THIS_MODULE,
1286 .pm = &exynos_fimd_pm_ops,
1287 .of_match_table = fimd_driver_dt_match,
1288 },
1289};
1290
