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8
9#include <linux/i2c.h>
10
11#include <drm/drmP.h>
12#include "framebuffer.h"
13#include "psb_drv.h"
14#include "psb_intel_drv.h"
15#include "psb_intel_reg.h"
16#include "gma_display.h"
17#include "power.h"
18#include "cdv_device.h"
19
20static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
21 struct drm_crtc *crtc, int target,
22 int refclk, struct gma_clock_t *best_clock);
23
24
25#define CDV_LIMIT_SINGLE_LVDS_96 0
26#define CDV_LIMIT_SINGLE_LVDS_100 1
27#define CDV_LIMIT_DAC_HDMI_27 2
28#define CDV_LIMIT_DAC_HDMI_96 3
29#define CDV_LIMIT_DP_27 4
30#define CDV_LIMIT_DP_100 5
31
32static const struct gma_limit_t cdv_intel_limits[] = {
33 {
34 .dot = {.min = 20000, .max = 115500},
35 .vco = {.min = 1800000, .max = 3600000},
36 .n = {.min = 2, .max = 6},
37 .m = {.min = 60, .max = 160},
38 .m1 = {.min = 0, .max = 0},
39 .m2 = {.min = 58, .max = 158},
40 .p = {.min = 28, .max = 140},
41 .p1 = {.min = 2, .max = 10},
42 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
43 .find_pll = gma_find_best_pll,
44 },
45 {
46 .dot = {.min = 20000, .max = 115500},
47 .vco = {.min = 1800000, .max = 3600000},
48 .n = {.min = 2, .max = 6},
49 .m = {.min = 60, .max = 160},
50 .m1 = {.min = 0, .max = 0},
51 .m2 = {.min = 58, .max = 158},
52 .p = {.min = 28, .max = 140},
53 .p1 = {.min = 2, .max = 10},
54
55
56
57 .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
58 .find_pll = gma_find_best_pll,
59 },
60 {
61 .dot = {.min = 20000, .max = 400000},
62 .vco = {.min = 1809000, .max = 3564000},
63 .n = {.min = 1, .max = 1},
64 .m = {.min = 67, .max = 132},
65 .m1 = {.min = 0, .max = 0},
66 .m2 = {.min = 65, .max = 130},
67 .p = {.min = 5, .max = 90},
68 .p1 = {.min = 1, .max = 9},
69 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
70 .find_pll = gma_find_best_pll,
71 },
72 {
73 .dot = {.min = 20000, .max = 400000},
74 .vco = {.min = 1800000, .max = 3600000},
75 .n = {.min = 2, .max = 6},
76 .m = {.min = 60, .max = 160},
77 .m1 = {.min = 0, .max = 0},
78 .m2 = {.min = 58, .max = 158},
79 .p = {.min = 5, .max = 100},
80 .p1 = {.min = 1, .max = 10},
81 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
82 .find_pll = gma_find_best_pll,
83 },
84 {
85 .dot = {.min = 160000, .max = 272000},
86 .vco = {.min = 1809000, .max = 3564000},
87 .n = {.min = 1, .max = 1},
88 .m = {.min = 67, .max = 132},
89 .m1 = {.min = 0, .max = 0},
90 .m2 = {.min = 65, .max = 130},
91 .p = {.min = 5, .max = 90},
92 .p1 = {.min = 1, .max = 9},
93 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
94 .find_pll = cdv_intel_find_dp_pll,
95 },
96 {
97 .dot = {.min = 160000, .max = 272000},
98 .vco = {.min = 1800000, .max = 3600000},
99 .n = {.min = 2, .max = 6},
100 .m = {.min = 60, .max = 164},
101 .m1 = {.min = 0, .max = 0},
102 .m2 = {.min = 58, .max = 162},
103 .p = {.min = 5, .max = 100},
104 .p1 = {.min = 1, .max = 10},
105 .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 10},
106 .find_pll = cdv_intel_find_dp_pll,
107 }
108};
109
110#define _wait_for(COND, MS, W) ({ \
111 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
112 int ret__ = 0; \
113 while (!(COND)) { \
114 if (time_after(jiffies, timeout__)) { \
115 ret__ = -ETIMEDOUT; \
116 break; \
117 } \
118 if (W && !in_dbg_master()) \
119 msleep(W); \
120 } \
121 ret__; \
122})
123
124#define wait_for(COND, MS) _wait_for(COND, MS, 1)
125
126
127int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
128{
129 int ret;
130
131 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
132 if (ret) {
133 DRM_ERROR("timeout waiting for SB to idle before read\n");
134 return ret;
135 }
136
137 REG_WRITE(SB_ADDR, reg);
138 REG_WRITE(SB_PCKT,
139 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
140 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
141 SET_FIELD(0xf, SB_BYTE_ENABLE));
142
143 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
144 if (ret) {
145 DRM_ERROR("timeout waiting for SB to idle after read\n");
146 return ret;
147 }
148
149 *val = REG_READ(SB_DATA);
150
151 return 0;
152}
153
154int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
155{
156 int ret;
157 static bool dpio_debug = true;
158 u32 temp;
159
160 if (dpio_debug) {
161 if (cdv_sb_read(dev, reg, &temp) == 0)
162 DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
163 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
164 }
165
166 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
167 if (ret) {
168 DRM_ERROR("timeout waiting for SB to idle before write\n");
169 return ret;
170 }
171
172 REG_WRITE(SB_ADDR, reg);
173 REG_WRITE(SB_DATA, val);
174 REG_WRITE(SB_PCKT,
175 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
176 SET_FIELD(SB_DEST_DPLL, SB_DEST) |
177 SET_FIELD(0xf, SB_BYTE_ENABLE));
178
179 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
180 if (ret) {
181 DRM_ERROR("timeout waiting for SB to idle after write\n");
182 return ret;
183 }
184
185 if (dpio_debug) {
186 if (cdv_sb_read(dev, reg, &temp) == 0)
187 DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
188 }
189
190 return 0;
191}
192
193
194
195
196void cdv_sb_reset(struct drm_device *dev)
197{
198
199 REG_WRITE(DPIO_CFG, 0);
200 REG_READ(DPIO_CFG);
201 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
202}
203
204
205
206
207
208
209static int
210cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
211 struct gma_clock_t *clock, bool is_lvds, u32 ddi_select)
212{
213 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
214 int pipe = gma_crtc->pipe;
215 u32 m, n_vco, p;
216 int ret = 0;
217 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
218 int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
219 u32 ref_value;
220 u32 lane_reg, lane_value;
221
222 cdv_sb_reset(dev);
223
224 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
225
226 udelay(100);
227
228
229 ref_value = 0x68A701;
230
231 cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248 ret = cdv_sb_read(dev, ref_sfr, &ref_value);
249 if (ret)
250 return ret;
251 ref_value &= ~(REF_CLK_MASK);
252
253
254 if (pipe == 1 && !is_lvds && !(ddi_select & DP_MASK)) {
255 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
256 ref_value |= REF_CLK_DPLLA;
257 } else {
258 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
259 ref_value |= REF_CLK_DPLL;
260 }
261 ret = cdv_sb_write(dev, ref_sfr, ref_value);
262 if (ret)
263 return ret;
264
265 ret = cdv_sb_read(dev, SB_M(pipe), &m);
266 if (ret)
267 return ret;
268 m &= ~SB_M_DIVIDER_MASK;
269 m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
270 ret = cdv_sb_write(dev, SB_M(pipe), m);
271 if (ret)
272 return ret;
273
274 ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
275 if (ret)
276 return ret;
277
278
279 n_vco &= 0xFFFF;
280 n_vco |= 0x107;
281 n_vco &= ~(SB_N_VCO_SEL_MASK |
282 SB_N_DIVIDER_MASK |
283 SB_N_CB_TUNE_MASK);
284
285 n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
286
287 if (clock->vco < 2250000) {
288 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
289 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
290 } else if (clock->vco < 2750000) {
291 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
292 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
293 } else if (clock->vco < 3300000) {
294 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
295 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
296 } else {
297 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
298 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
299 }
300
301 ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
302 if (ret)
303 return ret;
304
305 ret = cdv_sb_read(dev, SB_P(pipe), &p);
306 if (ret)
307 return ret;
308 p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
309 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
310 switch (clock->p2) {
311 case 5:
312 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
313 break;
314 case 10:
315 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
316 break;
317 case 14:
318 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
319 break;
320 case 7:
321 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
322 break;
323 default:
324 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
325 return -EINVAL;
326 }
327 ret = cdv_sb_write(dev, SB_P(pipe), p);
328 if (ret)
329 return ret;
330
331 if (ddi_select) {
332 if ((ddi_select & DDI_MASK) == DDI0_SELECT) {
333 lane_reg = PSB_LANE0;
334 cdv_sb_read(dev, lane_reg, &lane_value);
335 lane_value &= ~(LANE_PLL_MASK);
336 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
337 cdv_sb_write(dev, lane_reg, lane_value);
338
339 lane_reg = PSB_LANE1;
340 cdv_sb_read(dev, lane_reg, &lane_value);
341 lane_value &= ~(LANE_PLL_MASK);
342 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
343 cdv_sb_write(dev, lane_reg, lane_value);
344 } else {
345 lane_reg = PSB_LANE2;
346 cdv_sb_read(dev, lane_reg, &lane_value);
347 lane_value &= ~(LANE_PLL_MASK);
348 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
349 cdv_sb_write(dev, lane_reg, lane_value);
350
351 lane_reg = PSB_LANE3;
352 cdv_sb_read(dev, lane_reg, &lane_value);
353 lane_value &= ~(LANE_PLL_MASK);
354 lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
355 cdv_sb_write(dev, lane_reg, lane_value);
356 }
357 }
358 return 0;
359}
360
361static const struct gma_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
362 int refclk)
363{
364 const struct gma_limit_t *limit;
365 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
366
367
368
369
370 if (refclk == 96000)
371 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
372 else
373 limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
374 } else if (gma_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
375 gma_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
376 if (refclk == 27000)
377 limit = &cdv_intel_limits[CDV_LIMIT_DP_27];
378 else
379 limit = &cdv_intel_limits[CDV_LIMIT_DP_100];
380 } else {
381 if (refclk == 27000)
382 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
383 else
384 limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
385 }
386 return limit;
387}
388
389
390static void cdv_intel_clock(int refclk, struct gma_clock_t *clock)
391{
392 clock->m = clock->m2 + 2;
393 clock->p = clock->p1 * clock->p2;
394 clock->vco = (refclk * clock->m) / clock->n;
395 clock->dot = clock->vco / clock->p;
396}
397
398static bool cdv_intel_find_dp_pll(const struct gma_limit_t *limit,
399 struct drm_crtc *crtc, int target,
400 int refclk,
401 struct gma_clock_t *best_clock)
402{
403 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
404 struct gma_clock_t clock;
405
406 switch (refclk) {
407 case 27000:
408 if (target < 200000) {
409 clock.p1 = 2;
410 clock.p2 = 10;
411 clock.n = 1;
412 clock.m1 = 0;
413 clock.m2 = 118;
414 } else {
415 clock.p1 = 1;
416 clock.p2 = 10;
417 clock.n = 1;
418 clock.m1 = 0;
419 clock.m2 = 98;
420 }
421 break;
422
423 case 100000:
424 if (target < 200000) {
425 clock.p1 = 2;
426 clock.p2 = 10;
427 clock.n = 5;
428 clock.m1 = 0;
429 clock.m2 = 160;
430 } else {
431 clock.p1 = 1;
432 clock.p2 = 10;
433 clock.n = 5;
434 clock.m1 = 0;
435 clock.m2 = 133;
436 }
437 break;
438
439 default:
440 return false;
441 }
442
443 gma_crtc->clock_funcs->clock(refclk, &clock);
444 memcpy(best_clock, &clock, sizeof(struct gma_clock_t));
445 return true;
446}
447
448#define FIFO_PIPEA (1 << 0)
449#define FIFO_PIPEB (1 << 1)
450
451static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
452{
453 struct drm_crtc *crtc;
454 struct drm_psb_private *dev_priv = dev->dev_private;
455 struct gma_crtc *gma_crtc = NULL;
456
457 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
458 gma_crtc = to_gma_crtc(crtc);
459
460 if (crtc->primary->fb == NULL || !gma_crtc->active)
461 return false;
462 return true;
463}
464
465void cdv_disable_sr(struct drm_device *dev)
466{
467 if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
468
469
470 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
471 REG_READ(FW_BLC_SELF);
472
473 gma_wait_for_vblank(dev);
474
475
476
477
478 REG_WRITE(OV_OVADD, 0);
479 REG_READ(OV_OVADD);
480
481 gma_wait_for_vblank(dev);
482 }
483
484}
485
486void cdv_update_wm(struct drm_device *dev, struct drm_crtc *crtc)
487{
488 struct drm_psb_private *dev_priv = dev->dev_private;
489 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
490
491
492 if (cdv_intel_pipe_enabled(dev, 0) ^ cdv_intel_pipe_enabled(dev, 1)) {
493 u32 fw;
494
495 fw = REG_READ(DSPFW1);
496 fw &= ~DSP_FIFO_SR_WM_MASK;
497 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
498 fw &= ~CURSOR_B_FIFO_WM_MASK;
499 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
500 REG_WRITE(DSPFW1, fw);
501
502 fw = REG_READ(DSPFW2);
503 fw &= ~CURSOR_A_FIFO_WM_MASK;
504 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
505 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
506 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
507 REG_WRITE(DSPFW2, fw);
508
509 REG_WRITE(DSPFW3, 0x36000000);
510
511
512
513
514 if (gma_crtc->pipe == 1 &&
515 gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
516 REG_WRITE(DSPFW5, 0x00040330);
517 } else {
518 fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
519 (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
520 (3 << CURSOR_B_FIFO_WM1_SHIFT) |
521 (4 << CURSOR_FIFO_SR_WM1_SHIFT);
522 REG_WRITE(DSPFW5, fw);
523 }
524
525 REG_WRITE(DSPFW6, 0x10);
526
527 gma_wait_for_vblank(dev);
528
529
530 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
531 REG_READ(FW_BLC_SELF);
532 gma_wait_for_vblank(dev);
533
534 } else {
535
536
537 REG_WRITE(DSPFW1, 0x3f880808);
538 REG_WRITE(DSPFW2, 0x0b020202);
539 REG_WRITE(DSPFW3, 0x24000000);
540 REG_WRITE(DSPFW4, 0x08030202);
541 REG_WRITE(DSPFW5, 0x01010101);
542 REG_WRITE(DSPFW6, 0x1d0);
543
544 gma_wait_for_vblank(dev);
545
546 dev_priv->ops->disable_sr(dev);
547 }
548}
549
550
551
552
553
554static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
555{
556 u32 pfit_control;
557
558 pfit_control = REG_READ(PFIT_CONTROL);
559
560
561 if ((pfit_control & PFIT_ENABLE) == 0)
562 return -1;
563 return (pfit_control >> 29) & 0x3;
564}
565
566static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
567 struct drm_display_mode *mode,
568 struct drm_display_mode *adjusted_mode,
569 int x, int y,
570 struct drm_framebuffer *old_fb)
571{
572 struct drm_device *dev = crtc->dev;
573 struct drm_psb_private *dev_priv = dev->dev_private;
574 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
575 int pipe = gma_crtc->pipe;
576 const struct psb_offset *map = &dev_priv->regmap[pipe];
577 int refclk;
578 struct gma_clock_t clock;
579 u32 dpll = 0, dspcntr, pipeconf;
580 bool ok;
581 bool is_crt = false, is_lvds = false, is_tv = false;
582 bool is_hdmi = false, is_dp = false;
583 struct drm_mode_config *mode_config = &dev->mode_config;
584 struct drm_connector *connector;
585 const struct gma_limit_t *limit;
586 u32 ddi_select = 0;
587 bool is_edp = false;
588
589 list_for_each_entry(connector, &mode_config->connector_list, head) {
590 struct gma_encoder *gma_encoder =
591 gma_attached_encoder(connector);
592
593 if (!connector->encoder
594 || connector->encoder->crtc != crtc)
595 continue;
596
597 ddi_select = gma_encoder->ddi_select;
598 switch (gma_encoder->type) {
599 case INTEL_OUTPUT_LVDS:
600 is_lvds = true;
601 break;
602 case INTEL_OUTPUT_TVOUT:
603 is_tv = true;
604 break;
605 case INTEL_OUTPUT_ANALOG:
606 is_crt = true;
607 break;
608 case INTEL_OUTPUT_HDMI:
609 is_hdmi = true;
610 break;
611 case INTEL_OUTPUT_DISPLAYPORT:
612 is_dp = true;
613 break;
614 case INTEL_OUTPUT_EDP:
615 is_edp = true;
616 break;
617 default:
618 DRM_ERROR("invalid output type.\n");
619 return 0;
620 }
621 }
622
623 if (dev_priv->dplla_96mhz)
624
625 refclk = 96000;
626 else
627
628 refclk = 27000;
629 if (is_dp || is_edp) {
630
631
632
633
634
635
636
637
638 if (pipe == 0)
639 refclk = 27000;
640 else
641 refclk = 100000;
642 }
643
644 if (is_lvds && dev_priv->lvds_use_ssc) {
645 refclk = dev_priv->lvds_ssc_freq * 1000;
646 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
647 }
648
649 drm_mode_debug_printmodeline(adjusted_mode);
650
651 limit = gma_crtc->clock_funcs->limit(crtc, refclk);
652
653 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
654 &clock);
655 if (!ok) {
656 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
657 adjusted_mode->clock, clock.dot);
658 return 0;
659 }
660
661 dpll = DPLL_VGA_MODE_DIS;
662 if (is_tv) {
663
664
665 dpll |= 3;
666 }
667
668
669 if (is_dp || is_edp) {
670 cdv_intel_dp_set_m_n(crtc, mode, adjusted_mode);
671 } else {
672 REG_WRITE(PIPE_GMCH_DATA_M(pipe), 0);
673 REG_WRITE(PIPE_GMCH_DATA_N(pipe), 0);
674 REG_WRITE(PIPE_DP_LINK_M(pipe), 0);
675 REG_WRITE(PIPE_DP_LINK_N(pipe), 0);
676 }
677
678 dpll |= DPLL_SYNCLOCK_ENABLE;
679
680
681
682
683
684
685
686 pipeconf = REG_READ(map->conf);
687
688 pipeconf &= ~(PIPE_BPC_MASK);
689 if (is_edp) {
690 switch (dev_priv->edp.bpp) {
691 case 24:
692 pipeconf |= PIPE_8BPC;
693 break;
694 case 18:
695 pipeconf |= PIPE_6BPC;
696 break;
697 case 30:
698 pipeconf |= PIPE_10BPC;
699 break;
700 default:
701 pipeconf |= PIPE_8BPC;
702 break;
703 }
704 } else if (is_lvds) {
705
706 if ((REG_READ(LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
707 pipeconf |= PIPE_8BPC;
708 else
709 pipeconf |= PIPE_6BPC;
710 } else
711 pipeconf |= PIPE_8BPC;
712
713
714 dspcntr = DISPPLANE_GAMMA_ENABLE;
715
716 if (pipe == 0)
717 dspcntr |= DISPPLANE_SEL_PIPE_A;
718 else
719 dspcntr |= DISPPLANE_SEL_PIPE_B;
720
721 dspcntr |= DISPLAY_PLANE_ENABLE;
722 pipeconf |= PIPEACONF_ENABLE;
723
724 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
725 REG_READ(map->dpll);
726
727 cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds, ddi_select);
728
729 udelay(150);
730
731
732
733
734
735
736 if (is_lvds) {
737 u32 lvds = REG_READ(LVDS);
738
739 lvds |=
740 LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
741 LVDS_PIPEB_SELECT;
742
743
744
745
746 if (clock.p2 == 7)
747 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
748 else
749 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
750
751
752
753
754
755
756 REG_WRITE(LVDS, lvds);
757 REG_READ(LVDS);
758 }
759
760 dpll |= DPLL_VCO_ENABLE;
761
762
763 if (cdv_intel_panel_fitter_pipe(dev) == pipe)
764 REG_WRITE(PFIT_CONTROL, 0);
765
766 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
767 drm_mode_debug_printmodeline(mode);
768
769 REG_WRITE(map->dpll,
770 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
771 REG_READ(map->dpll);
772
773 udelay(150);
774
775 if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
776 dev_err(dev->dev, "Failed to get DPLL lock\n");
777 return -EBUSY;
778 }
779
780 {
781 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
782 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
783 }
784
785 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
786 ((adjusted_mode->crtc_htotal - 1) << 16));
787 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
788 ((adjusted_mode->crtc_hblank_end - 1) << 16));
789 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
790 ((adjusted_mode->crtc_hsync_end - 1) << 16));
791 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
792 ((adjusted_mode->crtc_vtotal - 1) << 16));
793 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
794 ((adjusted_mode->crtc_vblank_end - 1) << 16));
795 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
796 ((adjusted_mode->crtc_vsync_end - 1) << 16));
797
798
799
800 REG_WRITE(map->size,
801 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
802 REG_WRITE(map->pos, 0);
803 REG_WRITE(map->src,
804 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
805 REG_WRITE(map->conf, pipeconf);
806 REG_READ(map->conf);
807
808 gma_wait_for_vblank(dev);
809
810 REG_WRITE(map->cntr, dspcntr);
811
812
813 {
814 const struct drm_crtc_helper_funcs *crtc_funcs =
815 crtc->helper_private;
816 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
817 }
818
819 gma_wait_for_vblank(dev);
820
821 return 0;
822}
823
824
825
826
827
828static void i8xx_clock(int refclk, struct gma_clock_t *clock)
829{
830 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
831 clock->p = clock->p1 * clock->p2;
832 clock->vco = refclk * clock->m / (clock->n + 2);
833 clock->dot = clock->vco / clock->p;
834}
835
836
837static int cdv_intel_crtc_clock_get(struct drm_device *dev,
838 struct drm_crtc *crtc)
839{
840 struct drm_psb_private *dev_priv = dev->dev_private;
841 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
842 int pipe = gma_crtc->pipe;
843 const struct psb_offset *map = &dev_priv->regmap[pipe];
844 u32 dpll;
845 u32 fp;
846 struct gma_clock_t clock;
847 bool is_lvds;
848 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
849
850 if (gma_power_begin(dev, false)) {
851 dpll = REG_READ(map->dpll);
852 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
853 fp = REG_READ(map->fp0);
854 else
855 fp = REG_READ(map->fp1);
856 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
857 gma_power_end(dev);
858 } else {
859 dpll = p->dpll;
860 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
861 fp = p->fp0;
862 else
863 fp = p->fp1;
864
865 is_lvds = (pipe == 1) &&
866 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
867 }
868
869 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
870 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
871 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
872
873 if (is_lvds) {
874 clock.p1 =
875 ffs((dpll &
876 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
877 DPLL_FPA01_P1_POST_DIV_SHIFT);
878 if (clock.p1 == 0) {
879 clock.p1 = 4;
880 dev_err(dev->dev, "PLL %d\n", dpll);
881 }
882 clock.p2 = 14;
883
884 if ((dpll & PLL_REF_INPUT_MASK) ==
885 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
886
887 i8xx_clock(66000, &clock);
888 } else
889 i8xx_clock(48000, &clock);
890 } else {
891 if (dpll & PLL_P1_DIVIDE_BY_TWO)
892 clock.p1 = 2;
893 else {
894 clock.p1 =
895 ((dpll &
896 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
897 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
898 }
899 if (dpll & PLL_P2_DIVIDE_BY_4)
900 clock.p2 = 4;
901 else
902 clock.p2 = 2;
903
904 i8xx_clock(48000, &clock);
905 }
906
907
908
909
910
911
912 return clock.dot;
913}
914
915
916struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
917 struct drm_crtc *crtc)
918{
919 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
920 int pipe = gma_crtc->pipe;
921 struct drm_psb_private *dev_priv = dev->dev_private;
922 struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
923 const struct psb_offset *map = &dev_priv->regmap[pipe];
924 struct drm_display_mode *mode;
925 int htot;
926 int hsync;
927 int vtot;
928 int vsync;
929
930 if (gma_power_begin(dev, false)) {
931 htot = REG_READ(map->htotal);
932 hsync = REG_READ(map->hsync);
933 vtot = REG_READ(map->vtotal);
934 vsync = REG_READ(map->vsync);
935 gma_power_end(dev);
936 } else {
937 htot = p->htotal;
938 hsync = p->hsync;
939 vtot = p->vtotal;
940 vsync = p->vsync;
941 }
942
943 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
944 if (!mode)
945 return NULL;
946
947 mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
948 mode->hdisplay = (htot & 0xffff) + 1;
949 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
950 mode->hsync_start = (hsync & 0xffff) + 1;
951 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
952 mode->vdisplay = (vtot & 0xffff) + 1;
953 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
954 mode->vsync_start = (vsync & 0xffff) + 1;
955 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
956
957 drm_mode_set_name(mode);
958 drm_mode_set_crtcinfo(mode, 0);
959
960 return mode;
961}
962
963const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
964 .dpms = gma_crtc_dpms,
965 .mode_set = cdv_intel_crtc_mode_set,
966 .mode_set_base = gma_pipe_set_base,
967 .prepare = gma_crtc_prepare,
968 .commit = gma_crtc_commit,
969 .disable = gma_crtc_disable,
970};
971
972const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
973 .cursor_set = gma_crtc_cursor_set,
974 .cursor_move = gma_crtc_cursor_move,
975 .gamma_set = gma_crtc_gamma_set,
976 .set_config = gma_crtc_set_config,
977 .destroy = gma_crtc_destroy,
978};
979
980const struct gma_clock_funcs cdv_clock_funcs = {
981 .clock = cdv_intel_clock,
982 .limit = cdv_intel_limit,
983 .pll_is_valid = gma_pll_is_valid,
984};
985