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23#ifndef _INTEL_GUC_FWIF_H
24#define _INTEL_GUC_FWIF_H
25
26#define GUC_CLIENT_PRIORITY_KMD_HIGH 0
27#define GUC_CLIENT_PRIORITY_HIGH 1
28#define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
29#define GUC_CLIENT_PRIORITY_NORMAL 3
30#define GUC_CLIENT_PRIORITY_NUM 4
31
32#define GUC_MAX_STAGE_DESCRIPTORS 1024
33#define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS
34
35#define GUC_RENDER_ENGINE 0
36#define GUC_VIDEO_ENGINE 1
37#define GUC_BLITTER_ENGINE 2
38#define GUC_VIDEOENHANCE_ENGINE 3
39#define GUC_VIDEO_ENGINE2 4
40#define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
41
42#define GUC_DOORBELL_INVALID 256
43
44#define GUC_DB_SIZE (PAGE_SIZE)
45#define GUC_WQ_SIZE (PAGE_SIZE * 2)
46
47
48#define WQ_STATUS_ACTIVE 1
49#define WQ_STATUS_SUSPENDED 2
50#define WQ_STATUS_CMD_ERROR 3
51#define WQ_STATUS_ENGINE_ID_NOT_USED 4
52#define WQ_STATUS_SUSPENDED_FROM_RESET 5
53#define WQ_TYPE_SHIFT 0
54#define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT)
55#define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT)
56#define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT)
57#define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT)
58#define WQ_TARGET_SHIFT 10
59#define WQ_LEN_SHIFT 16
60#define WQ_NO_WCFLUSH_WAIT (1 << 27)
61#define WQ_PRESENT_WORKLOAD (1 << 28)
62
63#define WQ_RING_TAIL_SHIFT 20
64#define WQ_RING_TAIL_MAX 0x7FF
65#define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT)
66
67#define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
68#define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
69#define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
70#define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
71#define GUC_STAGE_DESC_ATTR_RESET BIT(4)
72#define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
73#define GUC_STAGE_DESC_ATTR_PCH BIT(6)
74#define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
75
76
77#define GUC_CTL_CTXINFO 0
78#define GUC_CTL_CTXNUM_IN16_SHIFT 0
79#define GUC_CTL_BASE_ADDR_SHIFT 12
80
81#define GUC_CTL_ARAT_HIGH 1
82#define GUC_CTL_ARAT_LOW 2
83
84#define GUC_CTL_DEVICE_INFO 3
85
86#define GUC_CTL_LOG_PARAMS 4
87#define GUC_LOG_VALID (1 << 0)
88#define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1)
89#define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3)
90#define GUC_LOG_CRASH_SHIFT 4
91#define GUC_LOG_CRASH_MASK (0x1 << GUC_LOG_CRASH_SHIFT)
92#define GUC_LOG_DPC_SHIFT 6
93#define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT)
94#define GUC_LOG_ISR_SHIFT 9
95#define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT)
96#define GUC_LOG_BUF_ADDR_SHIFT 12
97
98#define GUC_CTL_PAGE_FAULT_CONTROL 5
99
100#define GUC_CTL_WA 6
101#define GUC_CTL_WA_UK_BY_DRIVER (1 << 3)
102
103#define GUC_CTL_FEATURE 7
104#define GUC_CTL_VCS2_ENABLED (1 << 0)
105#define GUC_CTL_KERNEL_SUBMISSIONS (1 << 1)
106#define GUC_CTL_FEATURE2 (1 << 2)
107#define GUC_CTL_POWER_GATING (1 << 3)
108#define GUC_CTL_DISABLE_SCHEDULER (1 << 4)
109#define GUC_CTL_PREEMPTION_LOG (1 << 5)
110#define GUC_CTL_ENABLE_SLPC (1 << 7)
111#define GUC_CTL_RESET_ON_PREMPT_FAILURE (1 << 8)
112
113#define GUC_CTL_DEBUG 8
114#define GUC_LOG_VERBOSITY_SHIFT 0
115#define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
116#define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
117#define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
118#define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
119
120#define GUC_LOG_VERBOSITY_MIN 0
121#define GUC_LOG_VERBOSITY_MAX 3
122#define GUC_LOG_VERBOSITY_MASK 0x0000000f
123#define GUC_LOG_DESTINATION_MASK (3 << 4)
124#define GUC_LOG_DISABLED (1 << 6)
125#define GUC_PROFILE_ENABLED (1 << 7)
126#define GUC_WQ_TRACK_ENABLED (1 << 8)
127#define GUC_ADS_ENABLED (1 << 9)
128#define GUC_LOG_DEFAULT_DISABLED (1 << 10)
129#define GUC_ADS_ADDR_SHIFT 11
130#define GUC_ADS_ADDR_MASK 0xfffff800
131
132#define GUC_CTL_RSRVD 9
133
134#define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2)
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178struct uc_css_header {
179 u32 module_type;
180
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182 u32 header_size_dw;
183 u32 header_version;
184 u32 module_id;
185 u32 module_vendor;
186 union {
187 struct {
188 u8 day;
189 u8 month;
190 u16 year;
191 };
192 u32 date;
193 };
194 u32 size_dw;
195 u32 key_size_dw;
196 u32 modulus_size_dw;
197 u32 exponent_size_dw;
198 union {
199 struct {
200 u8 hour;
201 u8 min;
202 u16 sec;
203 };
204 u32 time;
205 };
206
207 char username[8];
208 char buildnumber[12];
209 union {
210 struct {
211 u32 branch_client_version;
212 u32 sw_version;
213 } guc;
214 struct {
215 u32 sw_version;
216 u32 reserved;
217 } huc;
218 };
219 u32 prod_preprod_fw;
220 u32 reserved[12];
221 u32 header_info;
222} __packed;
223
224
225struct guc_wq_item {
226 u32 header;
227 u32 context_desc;
228 u32 submit_element_info;
229 u32 fence_id;
230} __packed;
231
232struct guc_process_desc {
233 u32 stage_id;
234 u64 db_base_addr;
235 u32 head;
236 u32 tail;
237 u32 error_offset;
238 u64 wq_base_addr;
239 u32 wq_size_bytes;
240 u32 wq_status;
241 u32 engine_presence;
242 u32 priority;
243 u32 reserved[30];
244} __packed;
245
246
247#define GUC_ELC_CTXID_OFFSET 0
248#define GUC_ELC_ENGINE_OFFSET 29
249
250
251struct guc_execlist_context {
252 u32 context_desc;
253 u32 context_id;
254 u32 ring_status;
255 u32 ring_lrca;
256 u32 ring_begin;
257 u32 ring_end;
258 u32 ring_next_free_location;
259 u32 ring_current_tail_pointer_value;
260 u8 engine_state_submit_value;
261 u8 engine_state_wait_value;
262 u16 pagefault_count;
263 u16 engine_submit_queue_count;
264} __packed;
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275struct guc_stage_desc {
276 u32 sched_common_area;
277 u32 stage_id;
278 u32 pas_id;
279 u8 engines_used;
280 u64 db_trigger_cpu;
281 u32 db_trigger_uk;
282 u64 db_trigger_phy;
283 u16 db_id;
284
285 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM];
286
287 u8 attribute;
288
289 u32 priority;
290
291 u32 wq_sampled_tail_offset;
292 u32 wq_total_submit_enqueues;
293
294 u32 process_desc;
295 u32 wq_addr;
296 u32 wq_size;
297
298 u32 engine_presence;
299
300 u8 engine_suspended;
301
302 u8 reserved0[3];
303 u64 reserved1[1];
304
305 u64 desc_private;
306} __packed;
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364struct guc_ct_buffer_desc {
365 u32 addr;
366 u64 host_private;
367 u32 size;
368 u32 head;
369 u32 tail;
370 u32 is_in_error;
371 u32 fence;
372 u32 status;
373 u32 owner;
374 u32 owner_sub_id;
375 u32 reserved[5];
376} __packed;
377
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379#define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u
380#define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u
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393#define GUC_CT_MSG_LEN_SHIFT 0
394#define GUC_CT_MSG_LEN_MASK 0x1F
395#define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8)
396#define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9)
397#define GUC_CT_MSG_SEND_STATUS (1 << 10)
398#define GUC_CT_MSG_ACTION_SHIFT 16
399#define GUC_CT_MSG_ACTION_MASK 0xFFFF
400
401#define GUC_FORCEWAKE_RENDER (1 << 0)
402#define GUC_FORCEWAKE_MEDIA (1 << 1)
403
404#define GUC_POWER_UNSPECIFIED 0
405#define GUC_POWER_D0 1
406#define GUC_POWER_D1 2
407#define GUC_POWER_D2 3
408#define GUC_POWER_D3 4
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412
413#define POLICY_RESET_ENGINE (1<<0)
414
415#define POLICY_PREEMPT_TO_IDLE (1<<1)
416
417#define POLICY_MAX_NUM_WI 15
418#define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
419#define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000
420#define POLICY_DEFAULT_PREEMPTION_TIME_US 500000
421#define POLICY_DEFAULT_FAULT_TIME_US 250000
422
423struct guc_policy {
424
425 u32 execution_quantum;
426 u32 reserved1;
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430 u32 preemption_time;
431
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434 u32 fault_time;
435
436 u32 policy_flags;
437 u32 reserved[2];
438} __packed;
439
440struct guc_policies {
441 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINES_NUM];
442
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446 u32 dpc_promote_time;
447
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449 u32 is_valid;
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453 u32 max_num_work_items;
454
455 u32 reserved[19];
456} __packed;
457
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460#define GUC_REGSET_FLAGS_NONE 0x0
461#define GUC_REGSET_POWERCYCLE 0x1
462#define GUC_REGSET_MASKED 0x2
463#define GUC_REGSET_ENGINERESET 0x4
464#define GUC_REGSET_SAVE_DEFAULT_VALUE 0x8
465#define GUC_REGSET_SAVE_CURRENT_VALUE 0x10
466
467#define GUC_REGSET_MAX_REGISTERS 25
468#define GUC_MMIO_WHITE_LIST_START 0x24d0
469#define GUC_MMIO_WHITE_LIST_MAX 12
470#define GUC_S3_SAVE_SPACE_PAGES 10
471
472struct guc_mmio_regset {
473 struct __packed {
474 u32 offset;
475 u32 value;
476 u32 flags;
477 } registers[GUC_REGSET_MAX_REGISTERS];
478
479 u32 values_valid;
480 u32 number_of_registers;
481} __packed;
482
483
484struct mmio_white_list {
485 u32 mmio_start;
486 u32 offsets[GUC_MMIO_WHITE_LIST_MAX];
487 u32 count;
488} __packed;
489
490struct guc_mmio_reg_state {
491 struct guc_mmio_regset global_reg;
492 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINES_NUM];
493 struct mmio_white_list white_list[GUC_MAX_ENGINES_NUM];
494} __packed;
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498struct guc_ads {
499 u32 reg_state_addr;
500 u32 reg_state_buffer;
501 u32 golden_context_lrca;
502 u32 scheduler_policies;
503 u32 reserved0[3];
504 u32 eng_state_size[GUC_MAX_ENGINES_NUM];
505 u32 reserved2[4];
506} __packed;
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510enum guc_log_buffer_type {
511 GUC_ISR_LOG_BUFFER,
512 GUC_DPC_LOG_BUFFER,
513 GUC_CRASH_DUMP_LOG_BUFFER,
514 GUC_MAX_LOG_BUFFER
515};
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536struct guc_log_buffer_state {
537 u32 marker[2];
538 u32 read_ptr;
539 u32 write_ptr;
540 u32 size;
541 u32 sampled_write_ptr;
542 union {
543 struct {
544 u32 flush_to_file:1;
545 u32 buffer_full_cnt:4;
546 u32 reserved:27;
547 };
548 u32 flags;
549 };
550 u32 version;
551} __packed;
552
553struct guc_ctx_report {
554 u32 report_return_status;
555 u32 reserved1[64];
556 u32 affected_count;
557 u32 reserved2[2];
558} __packed;
559
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561struct guc_shared_ctx_data {
562 u32 addr_of_last_preempted_data_low;
563 u32 addr_of_last_preempted_data_high;
564 u32 addr_of_last_preempted_data_high_tmp;
565 u32 padding;
566 u32 is_mapped_to_proxy;
567 u32 proxy_ctx_id;
568 u32 engine_reset_ctx_id;
569 u32 media_reset_count;
570 u32 reserved1[8];
571 u32 uk_last_ctx_switch_reason;
572 u32 was_reset;
573 u32 lrca_gpu_addr;
574 u64 execlist_ctx;
575 u32 reserved2[66];
576 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
577} __packed;
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620#define GUC_MAX_MMIO_MSG_LEN 8
621
622#define INTEL_GUC_MSG_TYPE_SHIFT 28
623#define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT)
624#define INTEL_GUC_MSG_DATA_SHIFT 16
625#define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT)
626#define INTEL_GUC_MSG_CODE_SHIFT 0
627#define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT)
628
629#define __INTEL_GUC_MSG_GET(T, m) \
630 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT)
631#define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m)
632#define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m)
633#define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m)
634
635enum intel_guc_msg_type {
636 INTEL_GUC_MSG_TYPE_REQUEST = 0x0,
637 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF,
638};
639
640#define __INTEL_GUC_MSG_TYPE_IS(T, m) \
641 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T)
642#define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m)
643#define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m)
644
645enum intel_guc_action {
646 INTEL_GUC_ACTION_DEFAULT = 0x0,
647 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2,
648 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3,
649 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x6,
650 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10,
651 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20,
652 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30,
653 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302,
654 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501,
655 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502,
656 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003,
657 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000,
658 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505,
659 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506,
660 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x0E000,
661 INTEL_GUC_ACTION_LIMIT
662};
663
664enum intel_guc_preempt_options {
665 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4,
666 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8,
667};
668
669enum intel_guc_report_status {
670 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0,
671 INTEL_GUC_REPORT_STATUS_ACKED = 0x1,
672 INTEL_GUC_REPORT_STATUS_ERROR = 0x2,
673 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4,
674};
675
676enum intel_guc_sleep_state_status {
677 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x0,
678 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x1,
679 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x2
680#define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000
681};
682
683#define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0)
684#define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4
685#define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT)
686#define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8)
687
688enum intel_guc_response_status {
689 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0,
690 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000,
691};
692
693#define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \
694 (typecheck(u32, (m)) && \
695 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \
696 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \
697 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT)))
698
699
700enum intel_guc_recv_message {
701 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
702 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3)
703};
704
705#endif
706