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29#include <linux/delay.h>
30#include <linux/export.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33
34#include <drm/drm_atomic_helper.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
37#include <drm/i915_drm.h>
38
39#include "i915_drv.h"
40#include "intel_connector.h"
41#include "intel_drv.h"
42#include "intel_hdmi.h"
43#include "intel_panel.h"
44#include "intel_sdvo.h"
45#include "intel_sdvo_regs.h"
46
47#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
48#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
49#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
50#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
51
52#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
53 SDVO_TV_MASK)
54
55#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
56#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
57#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
58#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
59#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
60
61
62static const char * const tv_format_names[] = {
63 "NTSC_M" , "NTSC_J" , "NTSC_443",
64 "PAL_B" , "PAL_D" , "PAL_G" ,
65 "PAL_H" , "PAL_I" , "PAL_M" ,
66 "PAL_N" , "PAL_NC" , "PAL_60" ,
67 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
68 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
69 "SECAM_60"
70};
71
72#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
73
74struct intel_sdvo {
75 struct intel_encoder base;
76
77 struct i2c_adapter *i2c;
78 u8 slave_addr;
79
80 struct i2c_adapter ddc;
81
82
83 i915_reg_t sdvo_reg;
84
85
86 u16 controlled_output;
87
88
89
90
91
92 struct intel_sdvo_caps caps;
93
94
95 int pixel_clock_min, pixel_clock_max;
96
97
98
99
100
101 u16 attached_output;
102
103
104
105
106 u16 hotplug_active;
107
108 enum port port;
109
110 bool has_hdmi_monitor;
111 bool has_hdmi_audio;
112
113
114 u8 ddc_bus;
115
116
117
118
119 u8 dtd_sdvo_flags;
120};
121
122struct intel_sdvo_connector {
123 struct intel_connector base;
124
125
126 u16 output_flag;
127
128
129 u8 tv_format_supported[TV_FORMAT_NUM];
130 int format_supported_num;
131 struct drm_property *tv_format;
132
133
134 struct drm_property *left;
135 struct drm_property *right;
136 struct drm_property *top;
137 struct drm_property *bottom;
138 struct drm_property *hpos;
139 struct drm_property *vpos;
140 struct drm_property *contrast;
141 struct drm_property *saturation;
142 struct drm_property *hue;
143 struct drm_property *sharpness;
144 struct drm_property *flicker_filter;
145 struct drm_property *flicker_filter_adaptive;
146 struct drm_property *flicker_filter_2d;
147 struct drm_property *tv_chroma_filter;
148 struct drm_property *tv_luma_filter;
149 struct drm_property *dot_crawl;
150
151
152 struct drm_property *brightness;
153
154
155 u32 max_hscan, max_vscan;
156
157
158
159
160 bool is_hdmi;
161};
162
163struct intel_sdvo_connector_state {
164
165 struct intel_digital_connector_state base;
166
167 struct {
168 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
169 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
170 unsigned chroma_filter, luma_filter, dot_crawl;
171 } tv;
172};
173
174static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
175{
176 return container_of(encoder, struct intel_sdvo, base);
177}
178
179static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
180{
181 return to_sdvo(intel_attached_encoder(connector));
182}
183
184static struct intel_sdvo_connector *
185to_intel_sdvo_connector(struct drm_connector *connector)
186{
187 return container_of(connector, struct intel_sdvo_connector, base.base);
188}
189
190#define to_intel_sdvo_connector_state(conn_state) \
191 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
192
193static bool
194intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags);
195static bool
196intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
197 struct intel_sdvo_connector *intel_sdvo_connector,
198 int type);
199static bool
200intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
201 struct intel_sdvo_connector *intel_sdvo_connector);
202
203
204
205
206
207
208static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
209{
210 struct drm_device *dev = intel_sdvo->base.base.dev;
211 struct drm_i915_private *dev_priv = to_i915(dev);
212 u32 bval = val, cval = val;
213 int i;
214
215 if (HAS_PCH_SPLIT(dev_priv)) {
216 I915_WRITE(intel_sdvo->sdvo_reg, val);
217 POSTING_READ(intel_sdvo->sdvo_reg);
218
219
220
221
222 if (HAS_PCH_IBX(dev_priv)) {
223 I915_WRITE(intel_sdvo->sdvo_reg, val);
224 POSTING_READ(intel_sdvo->sdvo_reg);
225 }
226 return;
227 }
228
229 if (intel_sdvo->port == PORT_B)
230 cval = I915_READ(GEN3_SDVOC);
231 else
232 bval = I915_READ(GEN3_SDVOB);
233
234
235
236
237
238
239 for (i = 0; i < 2; i++) {
240 I915_WRITE(GEN3_SDVOB, bval);
241 POSTING_READ(GEN3_SDVOB);
242
243 I915_WRITE(GEN3_SDVOC, cval);
244 POSTING_READ(GEN3_SDVOC);
245 }
246}
247
248static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
249{
250 struct i2c_msg msgs[] = {
251 {
252 .addr = intel_sdvo->slave_addr,
253 .flags = 0,
254 .len = 1,
255 .buf = &addr,
256 },
257 {
258 .addr = intel_sdvo->slave_addr,
259 .flags = I2C_M_RD,
260 .len = 1,
261 .buf = ch,
262 }
263 };
264 int ret;
265
266 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
267 return true;
268
269 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
270 return false;
271}
272
273#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
274
275static const struct _sdvo_cmd_name {
276 u8 cmd;
277 const char *name;
278} __attribute__ ((packed)) sdvo_cmd_names[] = {
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
322
323
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
368
369
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
390};
391
392#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
393
394static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
395 const void *args, int args_len)
396{
397 int i, pos = 0;
398#define BUF_LEN 256
399 char buffer[BUF_LEN];
400
401#define BUF_PRINT(args...) \
402 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
403
404
405 for (i = 0; i < args_len; i++) {
406 BUF_PRINT("%02X ", ((u8 *)args)[i]);
407 }
408 for (; i < 8; i++) {
409 BUF_PRINT(" ");
410 }
411 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
412 if (cmd == sdvo_cmd_names[i].cmd) {
413 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
414 break;
415 }
416 }
417 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
418 BUF_PRINT("(%02X)", cmd);
419 }
420 BUG_ON(pos >= BUF_LEN - 1);
421#undef BUF_PRINT
422#undef BUF_LEN
423
424 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
425}
426
427static const char * const cmd_status_names[] = {
428 "Power on",
429 "Success",
430 "Not supported",
431 "Invalid arg",
432 "Pending",
433 "Target not specified",
434 "Scaling not supported"
435};
436
437static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
438 const void *args, int args_len,
439 bool unlocked)
440{
441 u8 *buf, status;
442 struct i2c_msg *msgs;
443 int i, ret = true;
444
445
446 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
447 if (!buf)
448 return false;
449
450 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
451 if (!msgs) {
452 kfree(buf);
453 return false;
454 }
455
456 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
457
458 for (i = 0; i < args_len; i++) {
459 msgs[i].addr = intel_sdvo->slave_addr;
460 msgs[i].flags = 0;
461 msgs[i].len = 2;
462 msgs[i].buf = buf + 2 *i;
463 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
464 buf[2*i + 1] = ((u8*)args)[i];
465 }
466 msgs[i].addr = intel_sdvo->slave_addr;
467 msgs[i].flags = 0;
468 msgs[i].len = 2;
469 msgs[i].buf = buf + 2*i;
470 buf[2*i + 0] = SDVO_I2C_OPCODE;
471 buf[2*i + 1] = cmd;
472
473
474 status = SDVO_I2C_CMD_STATUS;
475 msgs[i+1].addr = intel_sdvo->slave_addr;
476 msgs[i+1].flags = 0;
477 msgs[i+1].len = 1;
478 msgs[i+1].buf = &status;
479
480 msgs[i+2].addr = intel_sdvo->slave_addr;
481 msgs[i+2].flags = I2C_M_RD;
482 msgs[i+2].len = 1;
483 msgs[i+2].buf = &status;
484
485 if (unlocked)
486 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
487 else
488 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
489 if (ret < 0) {
490 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
491 ret = false;
492 goto out;
493 }
494 if (ret != i+3) {
495
496 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
497 ret = false;
498 }
499
500out:
501 kfree(msgs);
502 kfree(buf);
503 return ret;
504}
505
506static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
507 const void *args, int args_len)
508{
509 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
510}
511
512static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
513 void *response, int response_len)
514{
515 u8 retry = 15;
516 u8 status;
517 int i, pos = 0;
518#define BUF_LEN 256
519 char buffer[BUF_LEN];
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539 if (!intel_sdvo_read_byte(intel_sdvo,
540 SDVO_I2C_CMD_STATUS,
541 &status))
542 goto log_fail;
543
544 while ((status == SDVO_CMD_STATUS_PENDING ||
545 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
546 if (retry < 10)
547 msleep(15);
548 else
549 udelay(15);
550
551 if (!intel_sdvo_read_byte(intel_sdvo,
552 SDVO_I2C_CMD_STATUS,
553 &status))
554 goto log_fail;
555 }
556
557#define BUF_PRINT(args...) \
558 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
559
560 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
561 BUF_PRINT("(%s)", cmd_status_names[status]);
562 else
563 BUF_PRINT("(??? %d)", status);
564
565 if (status != SDVO_CMD_STATUS_SUCCESS)
566 goto log_fail;
567
568
569 for (i = 0; i < response_len; i++) {
570 if (!intel_sdvo_read_byte(intel_sdvo,
571 SDVO_I2C_RETURN_0 + i,
572 &((u8 *)response)[i]))
573 goto log_fail;
574 BUF_PRINT(" %02X", ((u8 *)response)[i]);
575 }
576 BUG_ON(pos >= BUF_LEN - 1);
577#undef BUF_PRINT
578#undef BUF_LEN
579
580 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
581 return true;
582
583log_fail:
584 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
585 return false;
586}
587
588static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
589{
590 if (adjusted_mode->crtc_clock >= 100000)
591 return 1;
592 else if (adjusted_mode->crtc_clock >= 50000)
593 return 2;
594 else
595 return 4;
596}
597
598static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
599 u8 ddc_bus)
600{
601
602 return __intel_sdvo_write_cmd(intel_sdvo,
603 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
604 &ddc_bus, 1, false);
605}
606
607static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
608{
609 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
610 return false;
611
612 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
613}
614
615static bool
616intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
617{
618 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
619 return false;
620
621 return intel_sdvo_read_response(intel_sdvo, value, len);
622}
623
624static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
625{
626 struct intel_sdvo_set_target_input_args targets = {0};
627 return intel_sdvo_set_value(intel_sdvo,
628 SDVO_CMD_SET_TARGET_INPUT,
629 &targets, sizeof(targets));
630}
631
632
633
634
635
636
637
638static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
639{
640 struct intel_sdvo_get_trained_inputs_response response;
641
642 BUILD_BUG_ON(sizeof(response) != 1);
643 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
644 &response, sizeof(response)))
645 return false;
646
647 *input_1 = response.input0_trained;
648 *input_2 = response.input1_trained;
649 return true;
650}
651
652static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
653 u16 outputs)
654{
655 return intel_sdvo_set_value(intel_sdvo,
656 SDVO_CMD_SET_ACTIVE_OUTPUTS,
657 &outputs, sizeof(outputs));
658}
659
660static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
661 u16 *outputs)
662{
663 return intel_sdvo_get_value(intel_sdvo,
664 SDVO_CMD_GET_ACTIVE_OUTPUTS,
665 outputs, sizeof(*outputs));
666}
667
668static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
669 int mode)
670{
671 u8 state = SDVO_ENCODER_STATE_ON;
672
673 switch (mode) {
674 case DRM_MODE_DPMS_ON:
675 state = SDVO_ENCODER_STATE_ON;
676 break;
677 case DRM_MODE_DPMS_STANDBY:
678 state = SDVO_ENCODER_STATE_STANDBY;
679 break;
680 case DRM_MODE_DPMS_SUSPEND:
681 state = SDVO_ENCODER_STATE_SUSPEND;
682 break;
683 case DRM_MODE_DPMS_OFF:
684 state = SDVO_ENCODER_STATE_OFF;
685 break;
686 }
687
688 return intel_sdvo_set_value(intel_sdvo,
689 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
690}
691
692static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
693 int *clock_min,
694 int *clock_max)
695{
696 struct intel_sdvo_pixel_clock_range clocks;
697
698 BUILD_BUG_ON(sizeof(clocks) != 4);
699 if (!intel_sdvo_get_value(intel_sdvo,
700 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
701 &clocks, sizeof(clocks)))
702 return false;
703
704
705 *clock_min = clocks.min * 10;
706 *clock_max = clocks.max * 10;
707 return true;
708}
709
710static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
711 u16 outputs)
712{
713 return intel_sdvo_set_value(intel_sdvo,
714 SDVO_CMD_SET_TARGET_OUTPUT,
715 &outputs, sizeof(outputs));
716}
717
718static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
719 struct intel_sdvo_dtd *dtd)
720{
721 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
722 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
723}
724
725static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
726 struct intel_sdvo_dtd *dtd)
727{
728 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
729 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
730}
731
732static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
733 struct intel_sdvo_dtd *dtd)
734{
735 return intel_sdvo_set_timing(intel_sdvo,
736 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
737}
738
739static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
740 struct intel_sdvo_dtd *dtd)
741{
742 return intel_sdvo_set_timing(intel_sdvo,
743 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
744}
745
746static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
747 struct intel_sdvo_dtd *dtd)
748{
749 return intel_sdvo_get_timing(intel_sdvo,
750 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
751}
752
753static bool
754intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
755 struct intel_sdvo_connector *intel_sdvo_connector,
756 u16 clock,
757 u16 width,
758 u16 height)
759{
760 struct intel_sdvo_preferred_input_timing_args args;
761
762 memset(&args, 0, sizeof(args));
763 args.clock = clock;
764 args.width = width;
765 args.height = height;
766 args.interlace = 0;
767
768 if (IS_LVDS(intel_sdvo_connector)) {
769 const struct drm_display_mode *fixed_mode =
770 intel_sdvo_connector->base.panel.fixed_mode;
771
772 if (fixed_mode->hdisplay != width ||
773 fixed_mode->vdisplay != height)
774 args.scaled = 1;
775 }
776
777 return intel_sdvo_set_value(intel_sdvo,
778 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
779 &args, sizeof(args));
780}
781
782static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
783 struct intel_sdvo_dtd *dtd)
784{
785 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
786 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
787 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
788 &dtd->part1, sizeof(dtd->part1)) &&
789 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
790 &dtd->part2, sizeof(dtd->part2));
791}
792
793static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
794{
795 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
796}
797
798static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
799 const struct drm_display_mode *mode)
800{
801 u16 width, height;
802 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
803 u16 h_sync_offset, v_sync_offset;
804 int mode_clock;
805
806 memset(dtd, 0, sizeof(*dtd));
807
808 width = mode->hdisplay;
809 height = mode->vdisplay;
810
811
812 h_blank_len = mode->htotal - mode->hdisplay;
813 h_sync_len = mode->hsync_end - mode->hsync_start;
814
815 v_blank_len = mode->vtotal - mode->vdisplay;
816 v_sync_len = mode->vsync_end - mode->vsync_start;
817
818 h_sync_offset = mode->hsync_start - mode->hdisplay;
819 v_sync_offset = mode->vsync_start - mode->vdisplay;
820
821 mode_clock = mode->clock;
822 mode_clock /= 10;
823 dtd->part1.clock = mode_clock;
824
825 dtd->part1.h_active = width & 0xff;
826 dtd->part1.h_blank = h_blank_len & 0xff;
827 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
828 ((h_blank_len >> 8) & 0xf);
829 dtd->part1.v_active = height & 0xff;
830 dtd->part1.v_blank = v_blank_len & 0xff;
831 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
832 ((v_blank_len >> 8) & 0xf);
833
834 dtd->part2.h_sync_off = h_sync_offset & 0xff;
835 dtd->part2.h_sync_width = h_sync_len & 0xff;
836 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
837 (v_sync_len & 0xf);
838 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
839 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
840 ((v_sync_len & 0x30) >> 4);
841
842 dtd->part2.dtd_flags = 0x18;
843 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
844 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
845 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
846 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
847 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
848 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
849
850 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
851}
852
853static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
854 const struct intel_sdvo_dtd *dtd)
855{
856 struct drm_display_mode mode = {};
857
858 mode.hdisplay = dtd->part1.h_active;
859 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
860 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
861 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
862 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
863 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
864 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
865 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
866
867 mode.vdisplay = dtd->part1.v_active;
868 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
869 mode.vsync_start = mode.vdisplay;
870 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
871 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
872 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
873 mode.vsync_end = mode.vsync_start +
874 (dtd->part2.v_sync_off_width & 0xf);
875 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
876 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
877 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
878
879 mode.clock = dtd->part1.clock * 10;
880
881 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
882 mode.flags |= DRM_MODE_FLAG_INTERLACE;
883 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
884 mode.flags |= DRM_MODE_FLAG_PHSYNC;
885 else
886 mode.flags |= DRM_MODE_FLAG_NHSYNC;
887 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
888 mode.flags |= DRM_MODE_FLAG_PVSYNC;
889 else
890 mode.flags |= DRM_MODE_FLAG_NVSYNC;
891
892 drm_mode_set_crtcinfo(&mode, 0);
893
894 drm_mode_copy(pmode, &mode);
895}
896
897static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
898{
899 struct intel_sdvo_encode encode;
900
901 BUILD_BUG_ON(sizeof(encode) != 2);
902 return intel_sdvo_get_value(intel_sdvo,
903 SDVO_CMD_GET_SUPP_ENCODE,
904 &encode, sizeof(encode));
905}
906
907static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
908 u8 mode)
909{
910 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
911}
912
913static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
914 u8 mode)
915{
916 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
917}
918
919static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
920 u8 audio_state)
921{
922 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
923 &audio_state, 1);
924}
925
926#if 0
927static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
928{
929 int i, j;
930 u8 set_buf_index[2];
931 u8 av_split;
932 u8 buf_size;
933 u8 buf[48];
934 u8 *pos;
935
936 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
937
938 for (i = 0; i <= av_split; i++) {
939 set_buf_index[0] = i; set_buf_index[1] = 0;
940 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
941 set_buf_index, 2);
942 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
943 intel_sdvo_read_response(encoder, &buf_size, 1);
944
945 pos = buf;
946 for (j = 0; j <= buf_size; j += 8) {
947 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
948 NULL, 0);
949 intel_sdvo_read_response(encoder, pos, 8);
950 pos += 8;
951 }
952 }
953}
954#endif
955
956static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
957 unsigned int if_index, u8 tx_rate,
958 const u8 *data, unsigned int length)
959{
960 u8 set_buf_index[2] = { if_index, 0 };
961 u8 hbuf_size, tmp[8];
962 int i;
963
964 if (!intel_sdvo_set_value(intel_sdvo,
965 SDVO_CMD_SET_HBUF_INDEX,
966 set_buf_index, 2))
967 return false;
968
969 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
970 &hbuf_size, 1))
971 return false;
972
973
974 hbuf_size++;
975
976 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
977 if_index, length, hbuf_size);
978
979 for (i = 0; i < hbuf_size; i += 8) {
980 memset(tmp, 0, 8);
981 if (i < length)
982 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
983
984 if (!intel_sdvo_set_value(intel_sdvo,
985 SDVO_CMD_SET_HBUF_DATA,
986 tmp, 8))
987 return false;
988 }
989
990 return intel_sdvo_set_value(intel_sdvo,
991 SDVO_CMD_SET_HBUF_TXRATE,
992 &tx_rate, 1);
993}
994
995static ssize_t intel_sdvo_read_infoframe(struct intel_sdvo *intel_sdvo,
996 unsigned int if_index,
997 u8 *data, unsigned int length)
998{
999 u8 set_buf_index[2] = { if_index, 0 };
1000 u8 hbuf_size, tx_rate, av_split;
1001 int i;
1002
1003 if (!intel_sdvo_get_value(intel_sdvo,
1004 SDVO_CMD_GET_HBUF_AV_SPLIT,
1005 &av_split, 1))
1006 return -ENXIO;
1007
1008 if (av_split < if_index)
1009 return 0;
1010
1011 if (!intel_sdvo_get_value(intel_sdvo,
1012 SDVO_CMD_GET_HBUF_TXRATE,
1013 &tx_rate, 1))
1014 return -ENXIO;
1015
1016 if (tx_rate == SDVO_HBUF_TX_DISABLED)
1017 return 0;
1018
1019 if (!intel_sdvo_set_value(intel_sdvo,
1020 SDVO_CMD_SET_HBUF_INDEX,
1021 set_buf_index, 2))
1022 return -ENXIO;
1023
1024 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
1025 &hbuf_size, 1))
1026 return -ENXIO;
1027
1028
1029 hbuf_size++;
1030
1031 DRM_DEBUG_KMS("reading sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
1032 if_index, length, hbuf_size);
1033
1034 hbuf_size = min_t(unsigned int, length, hbuf_size);
1035
1036 for (i = 0; i < hbuf_size; i += 8) {
1037 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HBUF_DATA, NULL, 0))
1038 return -ENXIO;
1039 if (!intel_sdvo_read_response(intel_sdvo, &data[i],
1040 min_t(unsigned int, 8, hbuf_size - i)))
1041 return -ENXIO;
1042 }
1043
1044 return hbuf_size;
1045}
1046
1047static bool intel_sdvo_compute_avi_infoframe(struct intel_sdvo *intel_sdvo,
1048 struct intel_crtc_state *crtc_state,
1049 struct drm_connector_state *conn_state)
1050{
1051 struct hdmi_avi_infoframe *frame = &crtc_state->infoframes.avi.avi;
1052 const struct drm_display_mode *adjusted_mode =
1053 &crtc_state->base.adjusted_mode;
1054 int ret;
1055
1056 if (!crtc_state->has_hdmi_sink)
1057 return true;
1058
1059 crtc_state->infoframes.enable |=
1060 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1061
1062 ret = drm_hdmi_avi_infoframe_from_display_mode(frame,
1063 conn_state->connector,
1064 adjusted_mode);
1065 if (ret)
1066 return false;
1067
1068 drm_hdmi_avi_infoframe_quant_range(frame,
1069 conn_state->connector,
1070 adjusted_mode,
1071 crtc_state->limited_color_range ?
1072 HDMI_QUANTIZATION_RANGE_LIMITED :
1073 HDMI_QUANTIZATION_RANGE_FULL);
1074
1075 ret = hdmi_avi_infoframe_check(frame);
1076 if (WARN_ON(ret))
1077 return false;
1078
1079 return true;
1080}
1081
1082static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
1083 const struct intel_crtc_state *crtc_state)
1084{
1085 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1086 const union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1087 ssize_t len;
1088
1089 if ((crtc_state->infoframes.enable &
1090 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI)) == 0)
1091 return true;
1092
1093 if (WARN_ON(frame->any.type != HDMI_INFOFRAME_TYPE_AVI))
1094 return false;
1095
1096 len = hdmi_infoframe_pack_only(frame, sdvo_data, sizeof(sdvo_data));
1097 if (WARN_ON(len < 0))
1098 return false;
1099
1100 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1101 SDVO_HBUF_TX_VSYNC,
1102 sdvo_data, sizeof(sdvo_data));
1103}
1104
1105static void intel_sdvo_get_avi_infoframe(struct intel_sdvo *intel_sdvo,
1106 struct intel_crtc_state *crtc_state)
1107{
1108 u8 sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
1109 union hdmi_infoframe *frame = &crtc_state->infoframes.avi;
1110 ssize_t len;
1111 int ret;
1112
1113 if (!crtc_state->has_hdmi_sink)
1114 return;
1115
1116 len = intel_sdvo_read_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1117 sdvo_data, sizeof(sdvo_data));
1118 if (len < 0) {
1119 DRM_DEBUG_KMS("failed to read AVI infoframe\n");
1120 return;
1121 } else if (len == 0) {
1122 return;
1123 }
1124
1125 crtc_state->infoframes.enable |=
1126 intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI);
1127
1128 ret = hdmi_infoframe_unpack(frame, sdvo_data, sizeof(sdvo_data));
1129 if (ret) {
1130 DRM_DEBUG_KMS("Failed to unpack AVI infoframe\n");
1131 return;
1132 }
1133
1134 if (frame->any.type != HDMI_INFOFRAME_TYPE_AVI)
1135 DRM_DEBUG_KMS("Found the wrong infoframe type 0x%x (expected 0x%02x)\n",
1136 frame->any.type, HDMI_INFOFRAME_TYPE_AVI);
1137}
1138
1139static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
1140 const struct drm_connector_state *conn_state)
1141{
1142 struct intel_sdvo_tv_format format;
1143 u32 format_map;
1144
1145 format_map = 1 << conn_state->tv.mode;
1146 memset(&format, 0, sizeof(format));
1147 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
1148
1149 BUILD_BUG_ON(sizeof(format) != 6);
1150 return intel_sdvo_set_value(intel_sdvo,
1151 SDVO_CMD_SET_TV_FORMAT,
1152 &format, sizeof(format));
1153}
1154
1155static bool
1156intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1157 const struct drm_display_mode *mode)
1158{
1159 struct intel_sdvo_dtd output_dtd;
1160
1161 if (!intel_sdvo_set_target_output(intel_sdvo,
1162 intel_sdvo->attached_output))
1163 return false;
1164
1165 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1166 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1167 return false;
1168
1169 return true;
1170}
1171
1172
1173
1174
1175
1176static bool
1177intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
1178 struct intel_sdvo_connector *intel_sdvo_connector,
1179 const struct drm_display_mode *mode,
1180 struct drm_display_mode *adjusted_mode)
1181{
1182 struct intel_sdvo_dtd input_dtd;
1183
1184
1185 if (!intel_sdvo_set_target_input(intel_sdvo))
1186 return false;
1187
1188 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1189 intel_sdvo_connector,
1190 mode->clock / 10,
1191 mode->hdisplay,
1192 mode->vdisplay))
1193 return false;
1194
1195 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
1196 &input_dtd))
1197 return false;
1198
1199 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1200 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
1201
1202 return true;
1203}
1204
1205static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
1206{
1207 unsigned dotclock = pipe_config->port_clock;
1208 struct dpll *clock = &pipe_config->dpll;
1209
1210
1211
1212
1213
1214 if (dotclock >= 100000 && dotclock < 140500) {
1215 clock->p1 = 2;
1216 clock->p2 = 10;
1217 clock->n = 3;
1218 clock->m1 = 16;
1219 clock->m2 = 8;
1220 } else if (dotclock >= 140500 && dotclock <= 200000) {
1221 clock->p1 = 1;
1222 clock->p2 = 10;
1223 clock->n = 6;
1224 clock->m1 = 12;
1225 clock->m2 = 8;
1226 } else {
1227 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1228 }
1229
1230 pipe_config->clock_set = true;
1231}
1232
1233static int intel_sdvo_compute_config(struct intel_encoder *encoder,
1234 struct intel_crtc_state *pipe_config,
1235 struct drm_connector_state *conn_state)
1236{
1237 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1238 struct intel_sdvo_connector_state *intel_sdvo_state =
1239 to_intel_sdvo_connector_state(conn_state);
1240 struct intel_sdvo_connector *intel_sdvo_connector =
1241 to_intel_sdvo_connector(conn_state->connector);
1242 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1243 struct drm_display_mode *mode = &pipe_config->base.mode;
1244
1245 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1246 pipe_config->pipe_bpp = 8*3;
1247 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1248
1249 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
1250 pipe_config->has_pch_encoder = true;
1251
1252
1253
1254
1255
1256
1257
1258 if (IS_TV(intel_sdvo_connector)) {
1259 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1260 return -EINVAL;
1261
1262 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1263 intel_sdvo_connector,
1264 mode,
1265 adjusted_mode);
1266 pipe_config->sdvo_tv_clock = true;
1267 } else if (IS_LVDS(intel_sdvo_connector)) {
1268 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
1269 intel_sdvo_connector->base.panel.fixed_mode))
1270 return -EINVAL;
1271
1272 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1273 intel_sdvo_connector,
1274 mode,
1275 adjusted_mode);
1276 }
1277
1278 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
1279 return -EINVAL;
1280
1281
1282
1283
1284
1285 pipe_config->pixel_multiplier =
1286 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1287
1288 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
1289 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1290
1291 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1292 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
1293 pipe_config->has_audio = true;
1294
1295 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1296
1297
1298
1299
1300
1301
1302 if (pipe_config->has_hdmi_sink &&
1303 drm_match_cea_mode(adjusted_mode) > 1)
1304 pipe_config->limited_color_range = true;
1305 } else {
1306 if (pipe_config->has_hdmi_sink &&
1307 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
1308 pipe_config->limited_color_range = true;
1309 }
1310
1311
1312 if (IS_TV(intel_sdvo_connector))
1313 i9xx_adjust_sdvo_tv_clock(pipe_config);
1314
1315
1316 if (intel_sdvo_connector->is_hdmi)
1317 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1318
1319 if (!intel_sdvo_compute_avi_infoframe(intel_sdvo,
1320 pipe_config, conn_state)) {
1321 DRM_DEBUG_KMS("bad AVI infoframe\n");
1322 return -EINVAL;
1323 }
1324
1325 return 0;
1326}
1327
1328#define UPDATE_PROPERTY(input, NAME) \
1329 do { \
1330 val = input; \
1331 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1332 } while (0)
1333
1334static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
1335 const struct intel_sdvo_connector_state *sdvo_state)
1336{
1337 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
1338 struct intel_sdvo_connector *intel_sdvo_conn =
1339 to_intel_sdvo_connector(conn_state->connector);
1340 u16 val;
1341
1342 if (intel_sdvo_conn->left)
1343 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1344
1345 if (intel_sdvo_conn->top)
1346 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1347
1348 if (intel_sdvo_conn->hpos)
1349 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1350
1351 if (intel_sdvo_conn->vpos)
1352 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1353
1354 if (intel_sdvo_conn->saturation)
1355 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1356
1357 if (intel_sdvo_conn->contrast)
1358 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1359
1360 if (intel_sdvo_conn->hue)
1361 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1362
1363 if (intel_sdvo_conn->brightness)
1364 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1365
1366 if (intel_sdvo_conn->sharpness)
1367 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1368
1369 if (intel_sdvo_conn->flicker_filter)
1370 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1371
1372 if (intel_sdvo_conn->flicker_filter_2d)
1373 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1374
1375 if (intel_sdvo_conn->flicker_filter_adaptive)
1376 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1377
1378 if (intel_sdvo_conn->tv_chroma_filter)
1379 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1380
1381 if (intel_sdvo_conn->tv_luma_filter)
1382 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1383
1384 if (intel_sdvo_conn->dot_crawl)
1385 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1386
1387#undef UPDATE_PROPERTY
1388}
1389
1390static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1391 const struct intel_crtc_state *crtc_state,
1392 const struct drm_connector_state *conn_state)
1393{
1394 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
1395 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1396 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1397 const struct intel_sdvo_connector_state *sdvo_state =
1398 to_intel_sdvo_connector_state(conn_state);
1399 const struct intel_sdvo_connector *intel_sdvo_connector =
1400 to_intel_sdvo_connector(conn_state->connector);
1401 const struct drm_display_mode *mode = &crtc_state->base.mode;
1402 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
1403 u32 sdvox;
1404 struct intel_sdvo_in_out_map in_out;
1405 struct intel_sdvo_dtd input_dtd, output_dtd;
1406 int rate;
1407
1408 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1409
1410
1411
1412
1413
1414
1415
1416
1417 in_out.in0 = intel_sdvo->attached_output;
1418 in_out.in1 = 0;
1419
1420 intel_sdvo_set_value(intel_sdvo,
1421 SDVO_CMD_SET_IN_OUT_MAP,
1422 &in_out, sizeof(in_out));
1423
1424
1425 if (!intel_sdvo_set_target_output(intel_sdvo,
1426 intel_sdvo->attached_output))
1427 return;
1428
1429
1430 if (IS_LVDS(intel_sdvo_connector))
1431 intel_sdvo_get_dtd_from_mode(&output_dtd,
1432 intel_sdvo_connector->base.panel.fixed_mode);
1433 else
1434 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1435 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1436 DRM_INFO("Setting output timings on %s failed\n",
1437 SDVO_NAME(intel_sdvo));
1438
1439
1440 if (!intel_sdvo_set_target_input(intel_sdvo))
1441 return;
1442
1443 if (crtc_state->has_hdmi_sink) {
1444 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1445 intel_sdvo_set_colorimetry(intel_sdvo,
1446 SDVO_COLORIMETRY_RGB256);
1447 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
1448 } else
1449 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
1450
1451 if (IS_TV(intel_sdvo_connector) &&
1452 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
1453 return;
1454
1455 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1456
1457 if (IS_TV(intel_sdvo_connector) || IS_LVDS(intel_sdvo_connector))
1458 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
1459 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1460 DRM_INFO("Setting input timings on %s failed\n",
1461 SDVO_NAME(intel_sdvo));
1462
1463 switch (crtc_state->pixel_multiplier) {
1464 default:
1465 WARN(1, "unknown pixel multiplier specified\n");
1466
1467 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1468 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1469 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
1470 }
1471 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1472 return;
1473
1474
1475 if (INTEL_GEN(dev_priv) >= 4) {
1476
1477
1478 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
1479 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
1480 sdvox |= HDMI_COLOR_RANGE_16_235;
1481 if (INTEL_GEN(dev_priv) < 5)
1482 sdvox |= SDVO_BORDER_ENABLE;
1483 } else {
1484 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1485 if (intel_sdvo->port == PORT_B)
1486 sdvox &= SDVOB_PRESERVE_MASK;
1487 else
1488 sdvox &= SDVOC_PRESERVE_MASK;
1489 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1490 }
1491
1492 if (HAS_PCH_CPT(dev_priv))
1493 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
1494 else
1495 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
1496
1497 if (INTEL_GEN(dev_priv) >= 4) {
1498
1499 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
1500 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
1501
1502 } else {
1503 sdvox |= (crtc_state->pixel_multiplier - 1)
1504 << SDVO_PORT_MULTIPLY_SHIFT;
1505 }
1506
1507 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1508 INTEL_GEN(dev_priv) < 5)
1509 sdvox |= SDVO_STALL_SELECT;
1510 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
1511}
1512
1513static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
1514{
1515 struct intel_sdvo_connector *intel_sdvo_connector =
1516 to_intel_sdvo_connector(&connector->base);
1517 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1518 u16 active_outputs = 0;
1519
1520 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1521
1522 return active_outputs & intel_sdvo_connector->output_flag;
1523}
1524
1525bool intel_sdvo_port_enabled(struct drm_i915_private *dev_priv,
1526 i915_reg_t sdvo_reg, enum pipe *pipe)
1527{
1528 u32 val;
1529
1530 val = I915_READ(sdvo_reg);
1531
1532
1533 if (HAS_PCH_CPT(dev_priv))
1534 *pipe = (val & SDVO_PIPE_SEL_MASK_CPT) >> SDVO_PIPE_SEL_SHIFT_CPT;
1535 else if (IS_CHERRYVIEW(dev_priv))
1536 *pipe = (val & SDVO_PIPE_SEL_MASK_CHV) >> SDVO_PIPE_SEL_SHIFT_CHV;
1537 else
1538 *pipe = (val & SDVO_PIPE_SEL_MASK) >> SDVO_PIPE_SEL_SHIFT;
1539
1540 return val & SDVO_ENABLE;
1541}
1542
1543static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1544 enum pipe *pipe)
1545{
1546 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1547 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1548 u16 active_outputs = 0;
1549 bool ret;
1550
1551 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1552
1553 ret = intel_sdvo_port_enabled(dev_priv, intel_sdvo->sdvo_reg, pipe);
1554
1555 return ret || active_outputs;
1556}
1557
1558static void intel_sdvo_get_config(struct intel_encoder *encoder,
1559 struct intel_crtc_state *pipe_config)
1560{
1561 struct drm_device *dev = encoder->base.dev;
1562 struct drm_i915_private *dev_priv = to_i915(dev);
1563 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1564 struct intel_sdvo_dtd dtd;
1565 int encoder_pixel_multiplier = 0;
1566 int dotclock;
1567 u32 flags = 0, sdvox;
1568 u8 val;
1569 bool ret;
1570
1571 pipe_config->output_types |= BIT(INTEL_OUTPUT_SDVO);
1572
1573 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1574
1575 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1576 if (!ret) {
1577
1578
1579
1580
1581 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1582 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1583 } else {
1584 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1585 flags |= DRM_MODE_FLAG_PHSYNC;
1586 else
1587 flags |= DRM_MODE_FLAG_NHSYNC;
1588
1589 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1590 flags |= DRM_MODE_FLAG_PVSYNC;
1591 else
1592 flags |= DRM_MODE_FLAG_NVSYNC;
1593 }
1594
1595 pipe_config->base.adjusted_mode.flags |= flags;
1596
1597
1598
1599
1600
1601
1602
1603
1604 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
1605 pipe_config->pixel_multiplier =
1606 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1607 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1608 }
1609
1610 dotclock = pipe_config->port_clock;
1611
1612 if (pipe_config->pixel_multiplier)
1613 dotclock /= pipe_config->pixel_multiplier;
1614
1615 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
1616
1617
1618 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1619 &val, 1)) {
1620 switch (val) {
1621 case SDVO_CLOCK_RATE_MULT_1X:
1622 encoder_pixel_multiplier = 1;
1623 break;
1624 case SDVO_CLOCK_RATE_MULT_2X:
1625 encoder_pixel_multiplier = 2;
1626 break;
1627 case SDVO_CLOCK_RATE_MULT_4X:
1628 encoder_pixel_multiplier = 4;
1629 break;
1630 }
1631 }
1632
1633 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1634 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1635 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
1636
1637 if (sdvox & HDMI_COLOR_RANGE_16_235)
1638 pipe_config->limited_color_range = true;
1639
1640 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1641 &val, 1)) {
1642 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1643
1644 if ((val & mask) == mask)
1645 pipe_config->has_audio = true;
1646 }
1647
1648 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1649 &val, 1)) {
1650 if (val == SDVO_ENCODE_HDMI)
1651 pipe_config->has_hdmi_sink = true;
1652 }
1653
1654 intel_sdvo_get_avi_infoframe(intel_sdvo, pipe_config);
1655}
1656
1657static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1658{
1659 intel_sdvo_set_audio_state(intel_sdvo, 0);
1660}
1661
1662static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1663 const struct intel_crtc_state *crtc_state,
1664 const struct drm_connector_state *conn_state)
1665{
1666 const struct drm_display_mode *adjusted_mode =
1667 &crtc_state->base.adjusted_mode;
1668 struct drm_connector *connector = conn_state->connector;
1669 u8 *eld = connector->eld;
1670
1671 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1672
1673 intel_sdvo_set_audio_state(intel_sdvo, 0);
1674
1675 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1676 SDVO_HBUF_TX_DISABLED,
1677 eld, drm_eld_size(eld));
1678
1679 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1680 SDVO_AUDIO_PRESENCE_DETECT);
1681}
1682
1683static void intel_disable_sdvo(struct intel_encoder *encoder,
1684 const struct intel_crtc_state *old_crtc_state,
1685 const struct drm_connector_state *conn_state)
1686{
1687 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1688 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1689 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1690 u32 temp;
1691
1692 if (old_crtc_state->has_audio)
1693 intel_sdvo_disable_audio(intel_sdvo);
1694
1695 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1696 if (0)
1697 intel_sdvo_set_encoder_power_state(intel_sdvo,
1698 DRM_MODE_DPMS_OFF);
1699
1700 temp = I915_READ(intel_sdvo->sdvo_reg);
1701
1702 temp &= ~SDVO_ENABLE;
1703 intel_sdvo_write_sdvox(intel_sdvo, temp);
1704
1705
1706
1707
1708
1709
1710 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1711
1712
1713
1714
1715 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1716 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1717
1718 temp &= ~SDVO_PIPE_SEL_MASK;
1719 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A);
1720 intel_sdvo_write_sdvox(intel_sdvo, temp);
1721
1722 temp &= ~SDVO_ENABLE;
1723 intel_sdvo_write_sdvox(intel_sdvo, temp);
1724
1725 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1726 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1727 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1728 }
1729}
1730
1731static void pch_disable_sdvo(struct intel_encoder *encoder,
1732 const struct intel_crtc_state *old_crtc_state,
1733 const struct drm_connector_state *old_conn_state)
1734{
1735}
1736
1737static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1738 const struct intel_crtc_state *old_crtc_state,
1739 const struct drm_connector_state *old_conn_state)
1740{
1741 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
1742}
1743
1744static void intel_enable_sdvo(struct intel_encoder *encoder,
1745 const struct intel_crtc_state *pipe_config,
1746 const struct drm_connector_state *conn_state)
1747{
1748 struct drm_device *dev = encoder->base.dev;
1749 struct drm_i915_private *dev_priv = to_i915(dev);
1750 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1751 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1752 u32 temp;
1753 bool input1, input2;
1754 int i;
1755 bool success;
1756
1757 temp = I915_READ(intel_sdvo->sdvo_reg);
1758 temp |= SDVO_ENABLE;
1759 intel_sdvo_write_sdvox(intel_sdvo, temp);
1760
1761 for (i = 0; i < 2; i++)
1762 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
1763
1764 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1765
1766
1767
1768
1769
1770
1771 if (success && !input1) {
1772 DRM_DEBUG_KMS("First %s output reported failure to "
1773 "sync\n", SDVO_NAME(intel_sdvo));
1774 }
1775
1776 if (0)
1777 intel_sdvo_set_encoder_power_state(intel_sdvo,
1778 DRM_MODE_DPMS_ON);
1779 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1780
1781 if (pipe_config->has_audio)
1782 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
1783}
1784
1785static enum drm_mode_status
1786intel_sdvo_mode_valid(struct drm_connector *connector,
1787 struct drm_display_mode *mode)
1788{
1789 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1790 struct intel_sdvo_connector *intel_sdvo_connector =
1791 to_intel_sdvo_connector(connector);
1792 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1793
1794 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1795 return MODE_NO_DBLESCAN;
1796
1797 if (intel_sdvo->pixel_clock_min > mode->clock)
1798 return MODE_CLOCK_LOW;
1799
1800 if (intel_sdvo->pixel_clock_max < mode->clock)
1801 return MODE_CLOCK_HIGH;
1802
1803 if (mode->clock > max_dotclk)
1804 return MODE_CLOCK_HIGH;
1805
1806 if (IS_LVDS(intel_sdvo_connector)) {
1807 const struct drm_display_mode *fixed_mode =
1808 intel_sdvo_connector->base.panel.fixed_mode;
1809
1810 if (mode->hdisplay > fixed_mode->hdisplay)
1811 return MODE_PANEL;
1812
1813 if (mode->vdisplay > fixed_mode->vdisplay)
1814 return MODE_PANEL;
1815 }
1816
1817 return MODE_OK;
1818}
1819
1820static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
1821{
1822 BUILD_BUG_ON(sizeof(*caps) != 8);
1823 if (!intel_sdvo_get_value(intel_sdvo,
1824 SDVO_CMD_GET_DEVICE_CAPS,
1825 caps, sizeof(*caps)))
1826 return false;
1827
1828 DRM_DEBUG_KMS("SDVO capabilities:\n"
1829 " vendor_id: %d\n"
1830 " device_id: %d\n"
1831 " device_rev_id: %d\n"
1832 " sdvo_version_major: %d\n"
1833 " sdvo_version_minor: %d\n"
1834 " sdvo_inputs_mask: %d\n"
1835 " smooth_scaling: %d\n"
1836 " sharp_scaling: %d\n"
1837 " up_scaling: %d\n"
1838 " down_scaling: %d\n"
1839 " stall_support: %d\n"
1840 " output_flags: %d\n",
1841 caps->vendor_id,
1842 caps->device_id,
1843 caps->device_rev_id,
1844 caps->sdvo_version_major,
1845 caps->sdvo_version_minor,
1846 caps->sdvo_inputs_mask,
1847 caps->smooth_scaling,
1848 caps->sharp_scaling,
1849 caps->up_scaling,
1850 caps->down_scaling,
1851 caps->stall_support,
1852 caps->output_flags);
1853
1854 return true;
1855}
1856
1857static u16 intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
1858{
1859 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
1860 u16 hotplug;
1861
1862 if (!I915_HAS_HOTPLUG(dev_priv))
1863 return 0;
1864
1865
1866
1867
1868
1869 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1870 return 0;
1871
1872 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1873 &hotplug, sizeof(hotplug)))
1874 return 0;
1875
1876 return hotplug;
1877}
1878
1879static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
1880{
1881 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1882
1883 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1884 &intel_sdvo->hotplug_active, 2);
1885}
1886
1887static bool intel_sdvo_hotplug(struct intel_encoder *encoder,
1888 struct intel_connector *connector)
1889{
1890 intel_sdvo_enable_hotplug(encoder);
1891
1892 return intel_encoder_hotplug(encoder, connector);
1893}
1894
1895static bool
1896intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
1897{
1898
1899 return hweight16(intel_sdvo->caps.output_flags) > 1;
1900}
1901
1902static struct edid *
1903intel_sdvo_get_edid(struct drm_connector *connector)
1904{
1905 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1906 return drm_get_edid(connector, &sdvo->ddc);
1907}
1908
1909
1910static struct edid *
1911intel_sdvo_get_analog_edid(struct drm_connector *connector)
1912{
1913 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1914
1915 return drm_get_edid(connector,
1916 intel_gmbus_get_adapter(dev_priv,
1917 dev_priv->vbt.crt_ddc_pin));
1918}
1919
1920static enum drm_connector_status
1921intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
1922{
1923 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1924 struct intel_sdvo_connector *intel_sdvo_connector =
1925 to_intel_sdvo_connector(connector);
1926 enum drm_connector_status status;
1927 struct edid *edid;
1928
1929 edid = intel_sdvo_get_edid(connector);
1930
1931 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
1932 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
1933
1934
1935
1936
1937
1938 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1939 intel_sdvo->ddc_bus = ddc;
1940 edid = intel_sdvo_get_edid(connector);
1941 if (edid)
1942 break;
1943 }
1944
1945
1946
1947
1948 if (edid == NULL)
1949 intel_sdvo->ddc_bus = saved_ddc;
1950 }
1951
1952
1953
1954
1955
1956 if (edid == NULL)
1957 edid = intel_sdvo_get_analog_edid(connector);
1958
1959 status = connector_status_unknown;
1960 if (edid != NULL) {
1961
1962 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1963 status = connector_status_connected;
1964 if (intel_sdvo_connector->is_hdmi) {
1965 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1966 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1967 }
1968 } else
1969 status = connector_status_disconnected;
1970 kfree(edid);
1971 }
1972
1973 return status;
1974}
1975
1976static bool
1977intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1978 struct edid *edid)
1979{
1980 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1981 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1982
1983 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1984 connector_is_digital, monitor_is_digital);
1985 return connector_is_digital == monitor_is_digital;
1986}
1987
1988static enum drm_connector_status
1989intel_sdvo_detect(struct drm_connector *connector, bool force)
1990{
1991 u16 response;
1992 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1993 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1994 enum drm_connector_status ret;
1995
1996 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1997 connector->base.id, connector->name);
1998
1999 if (!intel_sdvo_get_value(intel_sdvo,
2000 SDVO_CMD_GET_ATTACHED_DISPLAYS,
2001 &response, 2))
2002 return connector_status_unknown;
2003
2004 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
2005 response & 0xff, response >> 8,
2006 intel_sdvo_connector->output_flag);
2007
2008 if (response == 0)
2009 return connector_status_disconnected;
2010
2011 intel_sdvo->attached_output = response;
2012
2013 intel_sdvo->has_hdmi_monitor = false;
2014 intel_sdvo->has_hdmi_audio = false;
2015
2016 if ((intel_sdvo_connector->output_flag & response) == 0)
2017 ret = connector_status_disconnected;
2018 else if (IS_TMDS(intel_sdvo_connector))
2019 ret = intel_sdvo_tmds_sink_detect(connector);
2020 else {
2021 struct edid *edid;
2022
2023
2024 edid = intel_sdvo_get_edid(connector);
2025 if (edid == NULL)
2026 edid = intel_sdvo_get_analog_edid(connector);
2027 if (edid != NULL) {
2028 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
2029 edid))
2030 ret = connector_status_connected;
2031 else
2032 ret = connector_status_disconnected;
2033
2034 kfree(edid);
2035 } else
2036 ret = connector_status_connected;
2037 }
2038
2039 return ret;
2040}
2041
2042static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
2043{
2044 struct edid *edid;
2045
2046 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2047 connector->base.id, connector->name);
2048
2049
2050 edid = intel_sdvo_get_edid(connector);
2051
2052
2053
2054
2055
2056
2057
2058 if (edid == NULL)
2059 edid = intel_sdvo_get_analog_edid(connector);
2060
2061 if (edid != NULL) {
2062 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
2063 edid)) {
2064 drm_connector_update_edid_property(connector, edid);
2065 drm_add_edid_modes(connector, edid);
2066 }
2067
2068 kfree(edid);
2069 }
2070}
2071
2072
2073
2074
2075
2076
2077static const struct drm_display_mode sdvo_tv_modes[] = {
2078 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
2079 416, 0, 200, 201, 232, 233, 0,
2080 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2081 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
2082 416, 0, 240, 241, 272, 273, 0,
2083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2084 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
2085 496, 0, 300, 301, 332, 333, 0,
2086 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2087 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
2088 736, 0, 350, 351, 382, 383, 0,
2089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2090 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
2091 736, 0, 400, 401, 432, 433, 0,
2092 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2093 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
2094 736, 0, 480, 481, 512, 513, 0,
2095 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2096 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
2097 800, 0, 480, 481, 512, 513, 0,
2098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2099 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
2100 800, 0, 576, 577, 608, 609, 0,
2101 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2102 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
2103 816, 0, 350, 351, 382, 383, 0,
2104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2105 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
2106 816, 0, 400, 401, 432, 433, 0,
2107 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2108 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
2109 816, 0, 480, 481, 512, 513, 0,
2110 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2111 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
2112 816, 0, 540, 541, 572, 573, 0,
2113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2114 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
2115 816, 0, 576, 577, 608, 609, 0,
2116 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2117 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
2118 864, 0, 576, 577, 608, 609, 0,
2119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2120 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
2121 896, 0, 600, 601, 632, 633, 0,
2122 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2123 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
2124 928, 0, 624, 625, 656, 657, 0,
2125 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2126 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
2127 1016, 0, 766, 767, 798, 799, 0,
2128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2129 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
2130 1120, 0, 768, 769, 800, 801, 0,
2131 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2132 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
2133 1376, 0, 1024, 1025, 1056, 1057, 0,
2134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
2135};
2136
2137static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
2138{
2139 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2140 const struct drm_connector_state *conn_state = connector->state;
2141 struct intel_sdvo_sdtv_resolution_request tv_res;
2142 u32 reply = 0, format_map = 0;
2143 int i;
2144
2145 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2146 connector->base.id, connector->name);
2147
2148
2149
2150
2151
2152 format_map = 1 << conn_state->tv.mode;
2153 memcpy(&tv_res, &format_map,
2154 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
2155
2156 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2157 return;
2158
2159 BUILD_BUG_ON(sizeof(tv_res) != 3);
2160 if (!intel_sdvo_write_cmd(intel_sdvo,
2161 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
2162 &tv_res, sizeof(tv_res)))
2163 return;
2164 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
2165 return;
2166
2167 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
2168 if (reply & (1 << i)) {
2169 struct drm_display_mode *nmode;
2170 nmode = drm_mode_duplicate(connector->dev,
2171 &sdvo_tv_modes[i]);
2172 if (nmode)
2173 drm_mode_probed_add(connector, nmode);
2174 }
2175}
2176
2177static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2178{
2179 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2180 struct drm_i915_private *dev_priv = to_i915(connector->dev);
2181 struct drm_display_mode *newmode;
2182
2183 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
2184 connector->base.id, connector->name);
2185
2186
2187
2188
2189
2190 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
2191 newmode = drm_mode_duplicate(connector->dev,
2192 dev_priv->vbt.sdvo_lvds_vbt_mode);
2193 if (newmode != NULL) {
2194
2195 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2196 DRM_MODE_TYPE_DRIVER);
2197 drm_mode_probed_add(connector, newmode);
2198 }
2199 }
2200
2201
2202
2203
2204
2205
2206 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2207}
2208
2209static int intel_sdvo_get_modes(struct drm_connector *connector)
2210{
2211 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2212
2213 if (IS_TV(intel_sdvo_connector))
2214 intel_sdvo_get_tv_modes(connector);
2215 else if (IS_LVDS(intel_sdvo_connector))
2216 intel_sdvo_get_lvds_modes(connector);
2217 else
2218 intel_sdvo_get_ddc_modes(connector);
2219
2220 return !list_empty(&connector->probed_modes);
2221}
2222
2223static int
2224intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2225 const struct drm_connector_state *state,
2226 struct drm_property *property,
2227 u64 *val)
2228{
2229 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2230 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
2231
2232 if (property == intel_sdvo_connector->tv_format) {
2233 int i;
2234
2235 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2236 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2237 *val = i;
2238
2239 return 0;
2240 }
2241
2242 WARN_ON(1);
2243 *val = 0;
2244 } else if (property == intel_sdvo_connector->top ||
2245 property == intel_sdvo_connector->bottom)
2246 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2247 else if (property == intel_sdvo_connector->left ||
2248 property == intel_sdvo_connector->right)
2249 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2250 else if (property == intel_sdvo_connector->hpos)
2251 *val = sdvo_state->tv.hpos;
2252 else if (property == intel_sdvo_connector->vpos)
2253 *val = sdvo_state->tv.vpos;
2254 else if (property == intel_sdvo_connector->saturation)
2255 *val = state->tv.saturation;
2256 else if (property == intel_sdvo_connector->contrast)
2257 *val = state->tv.contrast;
2258 else if (property == intel_sdvo_connector->hue)
2259 *val = state->tv.hue;
2260 else if (property == intel_sdvo_connector->brightness)
2261 *val = state->tv.brightness;
2262 else if (property == intel_sdvo_connector->sharpness)
2263 *val = sdvo_state->tv.sharpness;
2264 else if (property == intel_sdvo_connector->flicker_filter)
2265 *val = sdvo_state->tv.flicker_filter;
2266 else if (property == intel_sdvo_connector->flicker_filter_2d)
2267 *val = sdvo_state->tv.flicker_filter_2d;
2268 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2269 *val = sdvo_state->tv.flicker_filter_adaptive;
2270 else if (property == intel_sdvo_connector->tv_chroma_filter)
2271 *val = sdvo_state->tv.chroma_filter;
2272 else if (property == intel_sdvo_connector->tv_luma_filter)
2273 *val = sdvo_state->tv.luma_filter;
2274 else if (property == intel_sdvo_connector->dot_crawl)
2275 *val = sdvo_state->tv.dot_crawl;
2276 else
2277 return intel_digital_connector_atomic_get_property(connector, state, property, val);
2278
2279 return 0;
2280}
2281
2282static int
2283intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2284 struct drm_connector_state *state,
2285 struct drm_property *property,
2286 u64 val)
2287{
2288 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2289 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
2290
2291 if (property == intel_sdvo_connector->tv_format) {
2292 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
2293
2294 if (state->crtc) {
2295 struct drm_crtc_state *crtc_state =
2296 drm_atomic_get_new_crtc_state(state->state, state->crtc);
2297
2298 crtc_state->connectors_changed = true;
2299 }
2300 } else if (property == intel_sdvo_connector->top ||
2301 property == intel_sdvo_connector->bottom)
2302
2303 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2304 else if (property == intel_sdvo_connector->left ||
2305 property == intel_sdvo_connector->right)
2306
2307 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2308 else if (property == intel_sdvo_connector->hpos)
2309 sdvo_state->tv.hpos = val;
2310 else if (property == intel_sdvo_connector->vpos)
2311 sdvo_state->tv.vpos = val;
2312 else if (property == intel_sdvo_connector->saturation)
2313 state->tv.saturation = val;
2314 else if (property == intel_sdvo_connector->contrast)
2315 state->tv.contrast = val;
2316 else if (property == intel_sdvo_connector->hue)
2317 state->tv.hue = val;
2318 else if (property == intel_sdvo_connector->brightness)
2319 state->tv.brightness = val;
2320 else if (property == intel_sdvo_connector->sharpness)
2321 sdvo_state->tv.sharpness = val;
2322 else if (property == intel_sdvo_connector->flicker_filter)
2323 sdvo_state->tv.flicker_filter = val;
2324 else if (property == intel_sdvo_connector->flicker_filter_2d)
2325 sdvo_state->tv.flicker_filter_2d = val;
2326 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2327 sdvo_state->tv.flicker_filter_adaptive = val;
2328 else if (property == intel_sdvo_connector->tv_chroma_filter)
2329 sdvo_state->tv.chroma_filter = val;
2330 else if (property == intel_sdvo_connector->tv_luma_filter)
2331 sdvo_state->tv.luma_filter = val;
2332 else if (property == intel_sdvo_connector->dot_crawl)
2333 sdvo_state->tv.dot_crawl = val;
2334 else
2335 return intel_digital_connector_atomic_set_property(connector, state, property, val);
2336
2337 return 0;
2338}
2339
2340static int
2341intel_sdvo_connector_register(struct drm_connector *connector)
2342{
2343 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2344 int ret;
2345
2346 ret = intel_connector_register(connector);
2347 if (ret)
2348 return ret;
2349
2350 return sysfs_create_link(&connector->kdev->kobj,
2351 &sdvo->ddc.dev.kobj,
2352 sdvo->ddc.dev.kobj.name);
2353}
2354
2355static void
2356intel_sdvo_connector_unregister(struct drm_connector *connector)
2357{
2358 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2359
2360 sysfs_remove_link(&connector->kdev->kobj,
2361 sdvo->ddc.dev.kobj.name);
2362 intel_connector_unregister(connector);
2363}
2364
2365static struct drm_connector_state *
2366intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2367{
2368 struct intel_sdvo_connector_state *state;
2369
2370 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2371 if (!state)
2372 return NULL;
2373
2374 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2375 return &state->base.base;
2376}
2377
2378static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2379 .detect = intel_sdvo_detect,
2380 .fill_modes = drm_helper_probe_single_connector_modes,
2381 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2382 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
2383 .late_register = intel_sdvo_connector_register,
2384 .early_unregister = intel_sdvo_connector_unregister,
2385 .destroy = intel_connector_destroy,
2386 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
2387 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
2388};
2389
2390static int intel_sdvo_atomic_check(struct drm_connector *conn,
2391 struct drm_connector_state *new_conn_state)
2392{
2393 struct drm_atomic_state *state = new_conn_state->state;
2394 struct drm_connector_state *old_conn_state =
2395 drm_atomic_get_old_connector_state(state, conn);
2396 struct intel_sdvo_connector_state *old_state =
2397 to_intel_sdvo_connector_state(old_conn_state);
2398 struct intel_sdvo_connector_state *new_state =
2399 to_intel_sdvo_connector_state(new_conn_state);
2400
2401 if (new_conn_state->crtc &&
2402 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2403 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2404 struct drm_crtc_state *crtc_state =
2405 drm_atomic_get_new_crtc_state(new_conn_state->state,
2406 new_conn_state->crtc);
2407
2408 crtc_state->connectors_changed = true;
2409 }
2410
2411 return intel_digital_connector_atomic_check(conn, new_conn_state);
2412}
2413
2414static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2415 .get_modes = intel_sdvo_get_modes,
2416 .mode_valid = intel_sdvo_mode_valid,
2417 .atomic_check = intel_sdvo_atomic_check,
2418};
2419
2420static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2421{
2422 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
2423
2424 i2c_del_adapter(&intel_sdvo->ddc);
2425 intel_encoder_destroy(encoder);
2426}
2427
2428static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2429 .destroy = intel_sdvo_enc_destroy,
2430};
2431
2432static void
2433intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2434{
2435 u16 mask = 0;
2436 unsigned int num_bits;
2437
2438
2439
2440
2441
2442 switch (sdvo->controlled_output) {
2443 case SDVO_OUTPUT_LVDS1:
2444 mask |= SDVO_OUTPUT_LVDS1;
2445
2446 case SDVO_OUTPUT_LVDS0:
2447 mask |= SDVO_OUTPUT_LVDS0;
2448
2449 case SDVO_OUTPUT_TMDS1:
2450 mask |= SDVO_OUTPUT_TMDS1;
2451
2452 case SDVO_OUTPUT_TMDS0:
2453 mask |= SDVO_OUTPUT_TMDS0;
2454
2455 case SDVO_OUTPUT_RGB1:
2456 mask |= SDVO_OUTPUT_RGB1;
2457
2458 case SDVO_OUTPUT_RGB0:
2459 mask |= SDVO_OUTPUT_RGB0;
2460 break;
2461 }
2462
2463
2464 mask &= sdvo->caps.output_flags;
2465 num_bits = hweight16(mask);
2466
2467 if (num_bits > 3)
2468 num_bits = 3;
2469
2470
2471 sdvo->ddc_bus = 1 << num_bits;
2472}
2473
2474
2475
2476
2477
2478
2479
2480
2481static void
2482intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
2483 struct intel_sdvo *sdvo)
2484{
2485 struct sdvo_device_mapping *mapping;
2486
2487 if (sdvo->port == PORT_B)
2488 mapping = &dev_priv->vbt.sdvo_mappings[0];
2489 else
2490 mapping = &dev_priv->vbt.sdvo_mappings[1];
2491
2492 if (mapping->initialized)
2493 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2494 else
2495 intel_sdvo_guess_ddc_bus(sdvo);
2496}
2497
2498static void
2499intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2500 struct intel_sdvo *sdvo)
2501{
2502 struct sdvo_device_mapping *mapping;
2503 u8 pin;
2504
2505 if (sdvo->port == PORT_B)
2506 mapping = &dev_priv->vbt.sdvo_mappings[0];
2507 else
2508 mapping = &dev_priv->vbt.sdvo_mappings[1];
2509
2510 if (mapping->initialized &&
2511 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
2512 pin = mapping->i2c_pin;
2513 else
2514 pin = GMBUS_PIN_DPB;
2515
2516 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2517
2518
2519
2520
2521
2522
2523 intel_gmbus_force_bit(sdvo->i2c, true);
2524}
2525
2526
2527static void
2528intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2529{
2530 intel_gmbus_force_bit(sdvo->i2c, false);
2531}
2532
2533static bool
2534intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
2535{
2536 return intel_sdvo_check_supp_encode(intel_sdvo);
2537}
2538
2539static u8
2540intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2541 struct intel_sdvo *sdvo)
2542{
2543 struct sdvo_device_mapping *my_mapping, *other_mapping;
2544
2545 if (sdvo->port == PORT_B) {
2546 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2547 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
2548 } else {
2549 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2550 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
2551 }
2552
2553
2554 if (my_mapping->slave_addr)
2555 return my_mapping->slave_addr;
2556
2557
2558
2559
2560
2561 if (other_mapping->slave_addr) {
2562 if (other_mapping->slave_addr == 0x70)
2563 return 0x72;
2564 else
2565 return 0x70;
2566 }
2567
2568
2569
2570
2571
2572 if (sdvo->port == PORT_B)
2573 return 0x70;
2574 else
2575 return 0x72;
2576}
2577
2578static int
2579intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2580 struct intel_sdvo *encoder)
2581{
2582 struct drm_connector *drm_connector;
2583 int ret;
2584
2585 drm_connector = &connector->base.base;
2586 ret = drm_connector_init(encoder->base.base.dev,
2587 drm_connector,
2588 &intel_sdvo_connector_funcs,
2589 connector->base.base.connector_type);
2590 if (ret < 0)
2591 return ret;
2592
2593 drm_connector_helper_add(drm_connector,
2594 &intel_sdvo_connector_helper_funcs);
2595
2596 connector->base.base.interlace_allowed = 1;
2597 connector->base.base.doublescan_allowed = 0;
2598 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
2599 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
2600
2601 intel_connector_attach_encoder(&connector->base, &encoder->base);
2602
2603 return 0;
2604}
2605
2606static void
2607intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2608 struct intel_sdvo_connector *connector)
2609{
2610 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
2611
2612 intel_attach_force_audio_property(&connector->base.base);
2613 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
2614 intel_attach_broadcast_rgb_property(&connector->base.base);
2615 }
2616 intel_attach_aspect_ratio_property(&connector->base.base);
2617 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
2618}
2619
2620static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2621{
2622 struct intel_sdvo_connector *sdvo_connector;
2623 struct intel_sdvo_connector_state *conn_state;
2624
2625 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2626 if (!sdvo_connector)
2627 return NULL;
2628
2629 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2630 if (!conn_state) {
2631 kfree(sdvo_connector);
2632 return NULL;
2633 }
2634
2635 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2636 &conn_state->base.base);
2637
2638 return sdvo_connector;
2639}
2640
2641static bool
2642intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
2643{
2644 struct drm_encoder *encoder = &intel_sdvo->base.base;
2645 struct drm_connector *connector;
2646 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2647 struct intel_connector *intel_connector;
2648 struct intel_sdvo_connector *intel_sdvo_connector;
2649
2650 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2651
2652 intel_sdvo_connector = intel_sdvo_connector_alloc();
2653 if (!intel_sdvo_connector)
2654 return false;
2655
2656 if (device == 0) {
2657 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
2658 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
2659 } else if (device == 1) {
2660 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
2661 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
2662 }
2663
2664 intel_connector = &intel_sdvo_connector->base;
2665 connector = &intel_connector->base;
2666 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2667 intel_sdvo_connector->output_flag) {
2668 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
2669
2670
2671
2672
2673 intel_encoder->hotplug = intel_sdvo_hotplug;
2674 intel_sdvo_enable_hotplug(intel_encoder);
2675 } else {
2676 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
2677 }
2678 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2679 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2680
2681 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
2682 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2683 intel_sdvo_connector->is_hdmi = true;
2684 }
2685
2686 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2687 kfree(intel_sdvo_connector);
2688 return false;
2689 }
2690
2691 if (intel_sdvo_connector->is_hdmi)
2692 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
2693
2694 return true;
2695}
2696
2697static bool
2698intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
2699{
2700 struct drm_encoder *encoder = &intel_sdvo->base.base;
2701 struct drm_connector *connector;
2702 struct intel_connector *intel_connector;
2703 struct intel_sdvo_connector *intel_sdvo_connector;
2704
2705 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2706
2707 intel_sdvo_connector = intel_sdvo_connector_alloc();
2708 if (!intel_sdvo_connector)
2709 return false;
2710
2711 intel_connector = &intel_sdvo_connector->base;
2712 connector = &intel_connector->base;
2713 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2714 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2715
2716 intel_sdvo->controlled_output |= type;
2717 intel_sdvo_connector->output_flag = type;
2718
2719 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2720 kfree(intel_sdvo_connector);
2721 return false;
2722 }
2723
2724 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
2725 goto err;
2726
2727 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2728 goto err;
2729
2730 return true;
2731
2732err:
2733 intel_connector_destroy(connector);
2734 return false;
2735}
2736
2737static bool
2738intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
2739{
2740 struct drm_encoder *encoder = &intel_sdvo->base.base;
2741 struct drm_connector *connector;
2742 struct intel_connector *intel_connector;
2743 struct intel_sdvo_connector *intel_sdvo_connector;
2744
2745 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2746
2747 intel_sdvo_connector = intel_sdvo_connector_alloc();
2748 if (!intel_sdvo_connector)
2749 return false;
2750
2751 intel_connector = &intel_sdvo_connector->base;
2752 connector = &intel_connector->base;
2753 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
2754 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2755 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2756
2757 if (device == 0) {
2758 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2759 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2760 } else if (device == 1) {
2761 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2762 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2763 }
2764
2765 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2766 kfree(intel_sdvo_connector);
2767 return false;
2768 }
2769
2770 return true;
2771}
2772
2773static bool
2774intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
2775{
2776 struct drm_encoder *encoder = &intel_sdvo->base.base;
2777 struct drm_connector *connector;
2778 struct intel_connector *intel_connector;
2779 struct intel_sdvo_connector *intel_sdvo_connector;
2780 struct drm_display_mode *mode;
2781
2782 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2783
2784 intel_sdvo_connector = intel_sdvo_connector_alloc();
2785 if (!intel_sdvo_connector)
2786 return false;
2787
2788 intel_connector = &intel_sdvo_connector->base;
2789 connector = &intel_connector->base;
2790 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2791 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2792
2793 if (device == 0) {
2794 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2795 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2796 } else if (device == 1) {
2797 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2798 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2799 }
2800
2801 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2802 kfree(intel_sdvo_connector);
2803 return false;
2804 }
2805
2806 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
2807 goto err;
2808
2809 intel_sdvo_get_lvds_modes(connector);
2810
2811 list_for_each_entry(mode, &connector->probed_modes, head) {
2812 if (mode->type & DRM_MODE_TYPE_PREFERRED) {
2813 struct drm_display_mode *fixed_mode =
2814 drm_mode_duplicate(connector->dev, mode);
2815
2816 intel_panel_init(&intel_connector->panel,
2817 fixed_mode, NULL);
2818 break;
2819 }
2820 }
2821
2822 if (!intel_connector->panel.fixed_mode)
2823 goto err;
2824
2825 return true;
2826
2827err:
2828 intel_connector_destroy(connector);
2829 return false;
2830}
2831
2832static bool
2833intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, u16 flags)
2834{
2835
2836
2837 if (flags & SDVO_OUTPUT_TMDS0)
2838 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
2839 return false;
2840
2841 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
2842 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
2843 return false;
2844
2845
2846 if (flags & SDVO_OUTPUT_SVID0)
2847 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
2848 return false;
2849
2850 if (flags & SDVO_OUTPUT_CVBS0)
2851 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
2852 return false;
2853
2854 if (flags & SDVO_OUTPUT_YPRPB0)
2855 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2856 return false;
2857
2858 if (flags & SDVO_OUTPUT_RGB0)
2859 if (!intel_sdvo_analog_init(intel_sdvo, 0))
2860 return false;
2861
2862 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
2863 if (!intel_sdvo_analog_init(intel_sdvo, 1))
2864 return false;
2865
2866 if (flags & SDVO_OUTPUT_LVDS0)
2867 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
2868 return false;
2869
2870 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
2871 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
2872 return false;
2873
2874 if ((flags & SDVO_OUTPUT_MASK) == 0) {
2875 unsigned char bytes[2];
2876
2877 intel_sdvo->controlled_output = 0;
2878 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
2879 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2880 SDVO_NAME(intel_sdvo),
2881 bytes[0], bytes[1]);
2882 return false;
2883 }
2884 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2885
2886 return true;
2887}
2888
2889static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2890{
2891 struct drm_device *dev = intel_sdvo->base.base.dev;
2892 struct drm_connector *connector, *tmp;
2893
2894 list_for_each_entry_safe(connector, tmp,
2895 &dev->mode_config.connector_list, head) {
2896 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2897 drm_connector_unregister(connector);
2898 intel_connector_destroy(connector);
2899 }
2900 }
2901}
2902
2903static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2904 struct intel_sdvo_connector *intel_sdvo_connector,
2905 int type)
2906{
2907 struct drm_device *dev = intel_sdvo->base.base.dev;
2908 struct intel_sdvo_tv_format format;
2909 u32 format_map, i;
2910
2911 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2912 return false;
2913
2914 BUILD_BUG_ON(sizeof(format) != 6);
2915 if (!intel_sdvo_get_value(intel_sdvo,
2916 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2917 &format, sizeof(format)))
2918 return false;
2919
2920 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
2921
2922 if (format_map == 0)
2923 return false;
2924
2925 intel_sdvo_connector->format_supported_num = 0;
2926 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2927 if (format_map & (1 << i))
2928 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
2929
2930
2931 intel_sdvo_connector->tv_format =
2932 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2933 "mode", intel_sdvo_connector->format_supported_num);
2934 if (!intel_sdvo_connector->tv_format)
2935 return false;
2936
2937 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2938 drm_property_add_enum(intel_sdvo_connector->tv_format, i,
2939 tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
2940
2941 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
2942 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2943 intel_sdvo_connector->tv_format, 0);
2944 return true;
2945
2946}
2947
2948#define _ENHANCEMENT(state_assignment, name, NAME) do { \
2949 if (enhancements.name) { \
2950 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2951 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2952 return false; \
2953 intel_sdvo_connector->name = \
2954 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
2955 if (!intel_sdvo_connector->name) return false; \
2956 state_assignment = response; \
2957 drm_object_attach_property(&connector->base, \
2958 intel_sdvo_connector->name, 0); \
2959 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2960 data_value[0], data_value[1], response); \
2961 } \
2962} while (0)
2963
2964#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2965
2966static bool
2967intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2968 struct intel_sdvo_connector *intel_sdvo_connector,
2969 struct intel_sdvo_enhancements_reply enhancements)
2970{
2971 struct drm_device *dev = intel_sdvo->base.base.dev;
2972 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2973 struct drm_connector_state *conn_state = connector->state;
2974 struct intel_sdvo_connector_state *sdvo_state =
2975 to_intel_sdvo_connector_state(conn_state);
2976 u16 response, data_value[2];
2977
2978
2979 if (enhancements.overscan_h) {
2980 if (!intel_sdvo_get_value(intel_sdvo,
2981 SDVO_CMD_GET_MAX_OVERSCAN_H,
2982 &data_value, 4))
2983 return false;
2984
2985 if (!intel_sdvo_get_value(intel_sdvo,
2986 SDVO_CMD_GET_OVERSCAN_H,
2987 &response, 2))
2988 return false;
2989
2990 sdvo_state->tv.overscan_h = response;
2991
2992 intel_sdvo_connector->max_hscan = data_value[0];
2993 intel_sdvo_connector->left =
2994 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
2995 if (!intel_sdvo_connector->left)
2996 return false;
2997
2998 drm_object_attach_property(&connector->base,
2999 intel_sdvo_connector->left, 0);
3000
3001 intel_sdvo_connector->right =
3002 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
3003 if (!intel_sdvo_connector->right)
3004 return false;
3005
3006 drm_object_attach_property(&connector->base,
3007 intel_sdvo_connector->right, 0);
3008 DRM_DEBUG_KMS("h_overscan: max %d, "
3009 "default %d, current %d\n",
3010 data_value[0], data_value[1], response);
3011 }
3012
3013 if (enhancements.overscan_v) {
3014 if (!intel_sdvo_get_value(intel_sdvo,
3015 SDVO_CMD_GET_MAX_OVERSCAN_V,
3016 &data_value, 4))
3017 return false;
3018
3019 if (!intel_sdvo_get_value(intel_sdvo,
3020 SDVO_CMD_GET_OVERSCAN_V,
3021 &response, 2))
3022 return false;
3023
3024 sdvo_state->tv.overscan_v = response;
3025
3026 intel_sdvo_connector->max_vscan = data_value[0];
3027 intel_sdvo_connector->top =
3028 drm_property_create_range(dev, 0,
3029 "top_margin", 0, data_value[0]);
3030 if (!intel_sdvo_connector->top)
3031 return false;
3032
3033 drm_object_attach_property(&connector->base,
3034 intel_sdvo_connector->top, 0);
3035
3036 intel_sdvo_connector->bottom =
3037 drm_property_create_range(dev, 0,
3038 "bottom_margin", 0, data_value[0]);
3039 if (!intel_sdvo_connector->bottom)
3040 return false;
3041
3042 drm_object_attach_property(&connector->base,
3043 intel_sdvo_connector->bottom, 0);
3044 DRM_DEBUG_KMS("v_overscan: max %d, "
3045 "default %d, current %d\n",
3046 data_value[0], data_value[1], response);
3047 }
3048
3049 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
3050 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
3051 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
3052 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
3053 ENHANCEMENT(&conn_state->tv, hue, HUE);
3054 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
3055 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
3056 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
3057 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
3058 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
3059 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
3060 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
3061
3062 if (enhancements.dot_crawl) {
3063 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
3064 return false;
3065
3066 sdvo_state->tv.dot_crawl = response & 0x1;
3067 intel_sdvo_connector->dot_crawl =
3068 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
3069 if (!intel_sdvo_connector->dot_crawl)
3070 return false;
3071
3072 drm_object_attach_property(&connector->base,
3073 intel_sdvo_connector->dot_crawl, 0);
3074 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
3075 }
3076
3077 return true;
3078}
3079
3080static bool
3081intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
3082 struct intel_sdvo_connector *intel_sdvo_connector,
3083 struct intel_sdvo_enhancements_reply enhancements)
3084{
3085 struct drm_device *dev = intel_sdvo->base.base.dev;
3086 struct drm_connector *connector = &intel_sdvo_connector->base.base;
3087 u16 response, data_value[2];
3088
3089 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
3090
3091 return true;
3092}
3093#undef ENHANCEMENT
3094#undef _ENHANCEMENT
3095
3096static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
3097 struct intel_sdvo_connector *intel_sdvo_connector)
3098{
3099 union {
3100 struct intel_sdvo_enhancements_reply reply;
3101 u16 response;
3102 } enhancements;
3103
3104 BUILD_BUG_ON(sizeof(enhancements) != 2);
3105
3106 if (!intel_sdvo_get_value(intel_sdvo,
3107 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
3108 &enhancements, sizeof(enhancements)) ||
3109 enhancements.response == 0) {
3110 DRM_DEBUG_KMS("No enhancement is supported\n");
3111 return true;
3112 }
3113
3114 if (IS_TV(intel_sdvo_connector))
3115 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3116 else if (IS_LVDS(intel_sdvo_connector))
3117 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
3118 else
3119 return true;
3120}
3121
3122static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
3123 struct i2c_msg *msgs,
3124 int num)
3125{
3126 struct intel_sdvo *sdvo = adapter->algo_data;
3127
3128 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
3129 return -EIO;
3130
3131 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
3132}
3133
3134static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
3135{
3136 struct intel_sdvo *sdvo = adapter->algo_data;
3137 return sdvo->i2c->algo->functionality(sdvo->i2c);
3138}
3139
3140static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
3141 .master_xfer = intel_sdvo_ddc_proxy_xfer,
3142 .functionality = intel_sdvo_ddc_proxy_func
3143};
3144
3145static void proxy_lock_bus(struct i2c_adapter *adapter,
3146 unsigned int flags)
3147{
3148 struct intel_sdvo *sdvo = adapter->algo_data;
3149 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3150}
3151
3152static int proxy_trylock_bus(struct i2c_adapter *adapter,
3153 unsigned int flags)
3154{
3155 struct intel_sdvo *sdvo = adapter->algo_data;
3156 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3157}
3158
3159static void proxy_unlock_bus(struct i2c_adapter *adapter,
3160 unsigned int flags)
3161{
3162 struct intel_sdvo *sdvo = adapter->algo_data;
3163 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3164}
3165
3166static const struct i2c_lock_operations proxy_lock_ops = {
3167 .lock_bus = proxy_lock_bus,
3168 .trylock_bus = proxy_trylock_bus,
3169 .unlock_bus = proxy_unlock_bus,
3170};
3171
3172static bool
3173intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
3174 struct drm_i915_private *dev_priv)
3175{
3176 struct pci_dev *pdev = dev_priv->drm.pdev;
3177
3178 sdvo->ddc.owner = THIS_MODULE;
3179 sdvo->ddc.class = I2C_CLASS_DDC;
3180 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
3181 sdvo->ddc.dev.parent = &pdev->dev;
3182 sdvo->ddc.algo_data = sdvo;
3183 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
3184 sdvo->ddc.lock_ops = &proxy_lock_ops;
3185
3186 return i2c_add_adapter(&sdvo->ddc) == 0;
3187}
3188
3189static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3190 enum port port)
3191{
3192 if (HAS_PCH_SPLIT(dev_priv))
3193 WARN_ON(port != PORT_B);
3194 else
3195 WARN_ON(port != PORT_B && port != PORT_C);
3196}
3197
3198bool intel_sdvo_init(struct drm_i915_private *dev_priv,
3199 i915_reg_t sdvo_reg, enum port port)
3200{
3201 struct intel_encoder *intel_encoder;
3202 struct intel_sdvo *intel_sdvo;
3203 int i;
3204
3205 assert_sdvo_port_valid(dev_priv, port);
3206
3207 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
3208 if (!intel_sdvo)
3209 return false;
3210
3211 intel_sdvo->sdvo_reg = sdvo_reg;
3212 intel_sdvo->port = port;
3213 intel_sdvo->slave_addr =
3214 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
3215 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
3216 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
3217 goto err_i2c_bus;
3218
3219
3220 intel_encoder = &intel_sdvo->base;
3221 intel_encoder->type = INTEL_OUTPUT_SDVO;
3222 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
3223 intel_encoder->port = port;
3224 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3225 &intel_sdvo_enc_funcs, 0,
3226 "SDVO %c", port_name(port));
3227
3228
3229 for (i = 0; i < 0x40; i++) {
3230 u8 byte;
3231
3232 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
3233 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3234 SDVO_NAME(intel_sdvo));
3235 goto err;
3236 }
3237 }
3238
3239 intel_encoder->compute_config = intel_sdvo_compute_config;
3240 if (HAS_PCH_SPLIT(dev_priv)) {
3241 intel_encoder->disable = pch_disable_sdvo;
3242 intel_encoder->post_disable = pch_post_disable_sdvo;
3243 } else {
3244 intel_encoder->disable = intel_disable_sdvo;
3245 }
3246 intel_encoder->pre_enable = intel_sdvo_pre_enable;
3247 intel_encoder->enable = intel_enable_sdvo;
3248 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
3249 intel_encoder->get_config = intel_sdvo_get_config;
3250
3251
3252 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
3253 goto err;
3254
3255 if (intel_sdvo_output_setup(intel_sdvo,
3256 intel_sdvo->caps.output_flags) != true) {
3257 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3258 SDVO_NAME(intel_sdvo));
3259
3260 goto err_output;
3261 }
3262
3263
3264
3265
3266
3267 if (intel_sdvo->hotplug_active) {
3268 if (intel_sdvo->port == PORT_B)
3269 intel_encoder->hpd_pin = HPD_SDVO_B;
3270 else
3271 intel_encoder->hpd_pin = HPD_SDVO_C;
3272 }
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282 intel_sdvo->base.cloneable = 0;
3283
3284 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
3285
3286
3287 if (!intel_sdvo_set_target_input(intel_sdvo))
3288 goto err_output;
3289
3290 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3291 &intel_sdvo->pixel_clock_min,
3292 &intel_sdvo->pixel_clock_max))
3293 goto err_output;
3294
3295 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
3296 "clock range %dMHz - %dMHz, "
3297 "input 1: %c, input 2: %c, "
3298 "output 1: %c, output 2: %c\n",
3299 SDVO_NAME(intel_sdvo),
3300 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3301 intel_sdvo->caps.device_rev_id,
3302 intel_sdvo->pixel_clock_min / 1000,
3303 intel_sdvo->pixel_clock_max / 1000,
3304 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3305 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
3306
3307 intel_sdvo->caps.output_flags &
3308 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
3309 intel_sdvo->caps.output_flags &
3310 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
3311 return true;
3312
3313err_output:
3314 intel_sdvo_output_cleanup(intel_sdvo);
3315
3316err:
3317 drm_encoder_cleanup(&intel_encoder->base);
3318 i2c_del_adapter(&intel_sdvo->ddc);
3319err_i2c_bus:
3320 intel_sdvo_unselect_i2c_bus(intel_sdvo);
3321 kfree(intel_sdvo);
3322
3323 return false;
3324}
3325