1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 4 */ 5 6#ifndef __MESON_REGISTERS_H 7#define __MESON_REGISTERS_H 8 9/* Shift all registers by 2 */ 10#define _REG(reg) ((reg) << 2) 11 12#define writel_bits_relaxed(mask, val, addr) \ 13 writel_relaxed((readl_relaxed(addr) & ~(mask)) | (val), addr) 14 15/* vpp2 */ 16#define VPP2_DUMMY_DATA 0x1900 17#define VPP2_LINE_IN_LENGTH 0x1901 18#define VPP2_PIC_IN_HEIGHT 0x1902 19#define VPP2_SCALE_COEF_IDX 0x1903 20#define VPP2_SCALE_COEF 0x1904 21#define VPP2_VSC_REGION12_STARTP 0x1905 22#define VPP2_VSC_REGION34_STARTP 0x1906 23#define VPP2_VSC_REGION4_ENDP 0x1907 24#define VPP2_VSC_START_PHASE_STEP 0x1908 25#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 26#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 27#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 28#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 29#define VPP2_VSC_PHASE_CTRL 0x190d 30#define VPP2_VSC_INI_PHASE 0x190e 31#define VPP2_HSC_REGION12_STARTP 0x1910 32#define VPP2_HSC_REGION34_STARTP 0x1911 33#define VPP2_HSC_REGION4_ENDP 0x1912 34#define VPP2_HSC_START_PHASE_STEP 0x1913 35#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 36#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 37#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 38#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 39#define VPP2_HSC_PHASE_CTRL 0x1918 40#define VPP2_SC_MISC 0x1919 41#define VPP2_PREBLEND_VD1_H_START_END 0x191a 42#define VPP2_PREBLEND_VD1_V_START_END 0x191b 43#define VPP2_POSTBLEND_VD1_H_START_END 0x191c 44#define VPP2_POSTBLEND_VD1_V_START_END 0x191d 45#define VPP2_PREBLEND_H_SIZE 0x1920 46#define VPP2_POSTBLEND_H_SIZE 0x1921 47#define VPP2_HOLD_LINES 0x1922 48#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 49#define VPP2_PREBLEND_CURRENT_XY 0x1924 50#define VPP2_POSTBLEND_CURRENT_XY 0x1925 51#define VPP2_MISC 0x1926 52#define VPP2_OFIFO_SIZE 0x1927 53#define VPP2_FIFO_STATUS 0x1928 54#define VPP2_SMOKE_CTRL 0x1929 55#define VPP2_SMOKE1_VAL 0x192a 56#define VPP2_SMOKE2_VAL 0x192b 57#define VPP2_SMOKE1_H_START_END 0x192d 58#define VPP2_SMOKE1_V_START_END 0x192e 59#define VPP2_SMOKE2_H_START_END 0x192f 60#define VPP2_SMOKE2_V_START_END 0x1930 61#define VPP2_SCO_FIFO_CTRL 0x1933 62#define VPP2_HSC_PHASE_CTRL1 0x1934 63#define VPP2_HSC_INI_PAT_CTRL 0x1935 64#define VPP2_VADJ_CTRL 0x1940 65#define VPP2_VADJ1_Y 0x1941 66#define VPP2_VADJ1_MA_MB 0x1942 67#define VPP2_VADJ1_MC_MD 0x1943 68#define VPP2_VADJ2_Y 0x1944 69#define VPP2_VADJ2_MA_MB 0x1945 70#define VPP2_VADJ2_MC_MD 0x1946 71#define VPP2_MATRIX_PROBE_COLOR 0x195c 72#define VPP2_MATRIX_HL_COLOR 0x195d 73#define VPP2_MATRIX_PROBE_POS 0x195e 74#define VPP2_MATRIX_CTRL 0x195f 75#define VPP2_MATRIX_COEF00_01 0x1960 76#define VPP2_MATRIX_COEF02_10 0x1961 77#define VPP2_MATRIX_COEF11_12 0x1962 78#define VPP2_MATRIX_COEF20_21 0x1963 79#define VPP2_MATRIX_COEF22 0x1964 80#define VPP2_MATRIX_OFFSET0_1 0x1965 81#define VPP2_MATRIX_OFFSET2 0x1966 82#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 83#define VPP2_MATRIX_PRE_OFFSET2 0x1968 84#define VPP2_DUMMY_DATA1 0x1969 85#define VPP2_GAINOFF_CTRL0 0x196a 86#define VPP2_GAINOFF_CTRL1 0x196b 87#define VPP2_GAINOFF_CTRL2 0x196c 88#define VPP2_GAINOFF_CTRL3 0x196d 89#define VPP2_GAINOFF_CTRL4 0x196e 90#define VPP2_CHROMA_ADDR_PORT 0x1970 91#define VPP2_CHROMA_DATA_PORT 0x1971 92#define VPP2_GCLK_CTRL0 0x1972 93#define VPP2_GCLK_CTRL1 0x1973 94#define VPP2_SC_GCLK_CTRL 0x1974 95#define VPP2_MISC1 0x1976 96#define VPP2_DNLP_CTRL_00 0x1981 97#define VPP2_DNLP_CTRL_01 0x1982 98#define VPP2_DNLP_CTRL_02 0x1983 99#define VPP2_DNLP_CTRL_03 0x1984 100#define VPP2_DNLP_CTRL_04 0x1985 101#define VPP2_DNLP_CTRL_05 0x1986 102#define VPP2_DNLP_CTRL_06 0x1987 103#define VPP2_DNLP_CTRL_07 0x1988 104#define VPP2_DNLP_CTRL_08 0x1989 105#define VPP2_DNLP_CTRL_09 0x198a 106#define VPP2_DNLP_CTRL_10 0x198b 107#define VPP2_DNLP_CTRL_11 0x198c 108#define VPP2_DNLP_CTRL_12 0x198d 109#define VPP2_DNLP_CTRL_13 0x198e 110#define VPP2_DNLP_CTRL_14 0x198f 111#define VPP2_DNLP_CTRL_15 0x1990 112#define VPP2_VE_ENABLE_CTRL 0x19a1 113#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 114#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 115#define VPP2_VE_H_V_SIZE 0x19a4 116#define VPP2_VDO_MEAS_CTRL 0x19a8 117#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 118#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 119#define VPP2_OSD_VSC_PHASE_STEP 0x19c0 120#define VPP2_OSD_VSC_INI_PHASE 0x19c1 121#define VPP2_OSD_VSC_CTRL0 0x19c2 122#define VPP2_OSD_HSC_PHASE_STEP 0x19c3 123#define VPP2_OSD_HSC_INI_PHASE 0x19c4 124#define VPP2_OSD_HSC_CTRL0 0x19c5 125#define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 126#define VPP2_OSD_SC_DUMMY_DATA 0x19c7 127#define VPP2_OSD_SC_CTRL0 0x19c8 128#define VPP2_OSD_SCI_WH_M1 0x19c9 129#define VPP2_OSD_SCO_H_START_END 0x19ca 130#define VPP2_OSD_SCO_V_START_END 0x19cb 131#define VPP2_OSD_SCALE_COEF_IDX 0x19cc 132#define VPP2_OSD_SCALE_COEF 0x19cd 133#define VPP2_INT_LINE_NUM 0x19ce 134 135/* viu */ 136#define VIU_ADDR_START 0x1a00 137#define VIU_ADDR_END 0x1aff 138#define VIU_SW_RESET 0x1a01 139#define VIU_MISC_CTRL0 0x1a06 140#define VIU_MISC_CTRL1 0x1a07 141#define D2D3_INTF_LENGTH 0x1a08 142#define D2D3_INTF_CTRL0 0x1a09 143#define VIU_OSD1_CTRL_STAT 0x1a10 144#define VIU_OSD1_CTRL_STAT2 0x1a2d 145#define VIU_OSD1_COLOR_ADDR 0x1a11 146#define VIU_OSD1_COLOR 0x1a12 147#define VIU_OSD1_TCOLOR_AG0 0x1a17 148#define VIU_OSD1_TCOLOR_AG1 0x1a18 149#define VIU_OSD1_TCOLOR_AG2 0x1a19 150#define VIU_OSD1_TCOLOR_AG3 0x1a1a 151#define VIU_OSD1_BLK0_CFG_W0 0x1a1b 152#define VIU_OSD1_BLK1_CFG_W0 0x1a1f 153#define VIU_OSD1_BLK2_CFG_W0 0x1a23 154#define VIU_OSD1_BLK3_CFG_W0 0x1a27 155#define VIU_OSD1_BLK0_CFG_W1 0x1a1c 156#define VIU_OSD1_BLK1_CFG_W1 0x1a20 157#define VIU_OSD1_BLK2_CFG_W1 0x1a24 158#define VIU_OSD1_BLK3_CFG_W1 0x1a28 159#define VIU_OSD1_BLK0_CFG_W2 0x1a1d 160#define VIU_OSD1_BLK1_CFG_W2 0x1a21 161#define VIU_OSD1_BLK2_CFG_W2 0x1a25 162#define VIU_OSD1_BLK3_CFG_W2 0x1a29 163#define VIU_OSD1_BLK0_CFG_W3 0x1a1e 164#define VIU_OSD1_BLK1_CFG_W3 0x1a22 165#define VIU_OSD1_BLK2_CFG_W3 0x1a26 166#define VIU_OSD1_BLK3_CFG_W3 0x1a2a 167#define VIU_OSD1_BLK0_CFG_W4 0x1a13 168#define VIU_OSD1_BLK1_CFG_W4 0x1a14 169#define VIU_OSD1_BLK2_CFG_W4 0x1a15 170#define VIU_OSD1_BLK3_CFG_W4 0x1a16 171#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 172#define VIU_OSD1_TEST_RDDATA 0x1a2c 173#define VIU_OSD1_PROT_CTRL 0x1a2e 174#define VIU_OSD2_CTRL_STAT 0x1a30 175#define VIU_OSD2_CTRL_STAT2 0x1a4d 176#define VIU_OSD2_COLOR_ADDR 0x1a31 177#define VIU_OSD2_COLOR 0x1a32 178#define VIU_OSD2_HL1_H_START_END 0x1a33 179#define VIU_OSD2_HL1_V_START_END 0x1a34 180#define VIU_OSD2_HL2_H_START_END 0x1a35 181#define VIU_OSD2_HL2_V_START_END 0x1a36 182#define VIU_OSD2_TCOLOR_AG0 0x1a37 183#define VIU_OSD2_TCOLOR_AG1 0x1a38 184#define VIU_OSD2_TCOLOR_AG2 0x1a39 185#define VIU_OSD2_TCOLOR_AG3 0x1a3a 186#define VIU_OSD2_BLK0_CFG_W0 0x1a3b 187#define VIU_OSD2_BLK1_CFG_W0 0x1a3f 188#define VIU_OSD2_BLK2_CFG_W0 0x1a43 189#define VIU_OSD2_BLK3_CFG_W0 0x1a47 190#define VIU_OSD2_BLK0_CFG_W1 0x1a3c 191#define VIU_OSD2_BLK1_CFG_W1 0x1a40 192#define VIU_OSD2_BLK2_CFG_W1 0x1a44 193#define VIU_OSD2_BLK3_CFG_W1 0x1a48 194#define VIU_OSD2_BLK0_CFG_W2 0x1a3d 195#define VIU_OSD2_BLK1_CFG_W2 0x1a41 196#define VIU_OSD2_BLK2_CFG_W2 0x1a45 197#define VIU_OSD2_BLK3_CFG_W2 0x1a49 198#define VIU_OSD2_BLK0_CFG_W3 0x1a3e 199#define VIU_OSD2_BLK1_CFG_W3 0x1a42 200#define VIU_OSD2_BLK2_CFG_W3 0x1a46 201#define VIU_OSD2_BLK3_CFG_W3 0x1a4a 202#define VIU_OSD2_BLK0_CFG_W4 0x1a64 203#define VIU_OSD2_BLK1_CFG_W4 0x1a65 204#define VIU_OSD2_BLK2_CFG_W4 0x1a66 205#define VIU_OSD2_BLK3_CFG_W4 0x1a67 206#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 207#define VIU_OSD2_TEST_RDDATA 0x1a4c 208#define VIU_OSD2_PROT_CTRL 0x1a4e 209#define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd 210#define VIU_OSD2_DIMM_CTRL 0x1acf 211 212#define VIU_OSD3_CTRL_STAT 0x3d80 213#define VIU_OSD3_CTRL_STAT2 0x3d81 214#define VIU_OSD3_COLOR_ADDR 0x3d82 215#define VIU_OSD3_COLOR 0x3d83 216#define VIU_OSD3_TCOLOR_AG0 0x3d84 217#define VIU_OSD3_TCOLOR_AG1 0x3d85 218#define VIU_OSD3_TCOLOR_AG2 0x3d86 219#define VIU_OSD3_TCOLOR_AG3 0x3d87 220#define VIU_OSD3_BLK0_CFG_W0 0x3d88 221#define VIU_OSD3_BLK0_CFG_W1 0x3d8c 222#define VIU_OSD3_BLK0_CFG_W2 0x3d90 223#define VIU_OSD3_BLK0_CFG_W3 0x3d94 224#define VIU_OSD3_BLK0_CFG_W4 0x3d98 225#define VIU_OSD3_BLK1_CFG_W4 0x3d99 226#define VIU_OSD3_BLK2_CFG_W4 0x3d9a 227#define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c 228#define VIU_OSD3_TEST_RDDATA 0x3d9d 229#define VIU_OSD3_PROT_CTRL 0x3d9e 230#define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f 231#define VIU_OSD3_DIMM_CTRL 0x3da0 232 233#define VD1_IF0_GEN_REG 0x1a50 234#define VD1_IF0_CANVAS0 0x1a51 235#define VD1_IF0_CANVAS1 0x1a52 236#define VD1_IF0_LUMA_X0 0x1a53 237#define VD1_IF0_LUMA_Y0 0x1a54 238#define VD1_IF0_CHROMA_X0 0x1a55 239#define VD1_IF0_CHROMA_Y0 0x1a56 240#define VD1_IF0_LUMA_X1 0x1a57 241#define VD1_IF0_LUMA_Y1 0x1a58 242#define VD1_IF0_CHROMA_X1 0x1a59 243#define VD1_IF0_CHROMA_Y1 0x1a5a 244#define VD1_IF0_RPT_LOOP 0x1a5b 245#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 246#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 247#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 248#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 249#define VD1_IF0_LUMA_PSEL 0x1a60 250#define VD1_IF0_CHROMA_PSEL 0x1a61 251#define VD1_IF0_DUMMY_PIXEL 0x1a62 252#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 253#define VD1_IF0_RANGE_MAP_Y 0x1a6a 254#define VD1_IF0_RANGE_MAP_CB 0x1a6b 255#define VD1_IF0_RANGE_MAP_CR 0x1a6c 256#define VD1_IF0_GEN_REG2 0x1a6d 257#define VD1_IF0_PROT_CNTL 0x1a6e 258#define VIU_VD1_FMT_CTRL 0x1a68 259#define VIU_VD1_FMT_W 0x1a69 260#define VD2_IF0_GEN_REG 0x1a70 261#define VD2_IF0_CANVAS0 0x1a71 262#define VD2_IF0_CANVAS1 0x1a72 263#define VD2_IF0_LUMA_X0 0x1a73 264#define VD2_IF0_LUMA_Y0 0x1a74 265#define VD2_IF0_CHROMA_X0 0x1a75 266#define VD2_IF0_CHROMA_Y0 0x1a76 267#define VD2_IF0_LUMA_X1 0x1a77 268#define VD2_IF0_LUMA_Y1 0x1a78 269#define VD2_IF0_CHROMA_X1 0x1a79 270#define VD2_IF0_CHROMA_Y1 0x1a7a 271#define VD2_IF0_RPT_LOOP 0x1a7b 272#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 273#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 274#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 275#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 276#define VD2_IF0_LUMA_PSEL 0x1a80 277#define VD2_IF0_CHROMA_PSEL 0x1a81 278#define VD2_IF0_DUMMY_PIXEL 0x1a82 279#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 280#define VD2_IF0_RANGE_MAP_Y 0x1a8a 281#define VD2_IF0_RANGE_MAP_CB 0x1a8b 282#define VD2_IF0_RANGE_MAP_CR 0x1a8c 283#define VD2_IF0_GEN_REG2 0x1a8d 284#define VD2_IF0_PROT_CNTL 0x1a8e 285#define VIU_VD2_FMT_CTRL 0x1a88 286#define VIU_VD2_FMT_W 0x1a89 287 288/* VIU Matrix Registers */ 289#define VIU_OSD1_MATRIX_CTRL 0x1a90 290#define VIU_OSD1_MATRIX_COEF00_01 0x1a91 291#define VIU_OSD1_MATRIX_COEF02_10 0x1a92 292#define VIU_OSD1_MATRIX_COEF11_12 0x1a93 293#define VIU_OSD1_MATRIX_COEF20_21 0x1a94 294#define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 295#define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 296#define VIU_OSD1_MATRIX_OFFSET2 0x1a97 297#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 298#define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 299#define VIU_OSD1_MATRIX_COEF22_30 0x1a9d 300#define VIU_OSD1_MATRIX_COEF31_32 0x1a9e 301#define VIU_OSD1_MATRIX_COEF40_41 0x1a9f 302#define VD1_IF0_GEN_REG3 0x1aa7 303 304#define VIU_OSD_BLENDO_H_START_END 0x1aa9 305#define VIU_OSD_BLENDO_V_START_END 0x1aaa 306#define VIU_OSD_BLEND_GEN_CTRL0 0x1aab 307#define VIU_OSD_BLEND_GEN_CTRL1 0x1aac 308#define VIU_OSD_BLEND_DUMMY_DATA 0x1aad 309#define VIU_OSD_BLEND_CURRENT_XY 0x1aae 310 311#define VIU_OSD2_MATRIX_CTRL 0x1ab0 312#define VIU_OSD2_MATRIX_COEF00_01 0x1ab1 313#define VIU_OSD2_MATRIX_COEF02_10 0x1ab2 314#define VIU_OSD2_MATRIX_COEF11_12 0x1ab3 315#define VIU_OSD2_MATRIX_COEF20_21 0x1ab4 316#define VIU_OSD2_MATRIX_COEF22 0x1ab5 317#define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6 318#define VIU_OSD2_MATRIX_OFFSET2 0x1ab7 319#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8 320#define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9 321#define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba 322#define VIU_OSD2_MATRIX_HL_COLOR 0x1abb 323#define VIU_OSD2_MATRIX_PROBE_POS 0x1abc 324#define VIU_OSD1_EOTF_CTL 0x1ad4 325#define VIU_OSD1_EOTF_COEF00_01 0x1ad5 326#define VIU_OSD1_EOTF_COEF02_10 0x1ad6 327#define VIU_OSD1_EOTF_COEF11_12 0x1ad7 328#define VIU_OSD1_EOTF_COEF20_21 0x1ad8 329#define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 330#define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada 331#define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb 332#define VIU_OSD1_OETF_CTL 0x1adc 333#define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add 334#define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade 335#define AFBC_ENABLE 0x1ae0 336 337/* vpp */ 338#define VPP_DUMMY_DATA 0x1d00 339#define VPP_LINE_IN_LENGTH 0x1d01 340#define VPP_PIC_IN_HEIGHT 0x1d02 341#define VPP_SCALE_COEF_IDX 0x1d03 342#define VPP_SCALE_COEF 0x1d04 343#define VPP_VSC_REGION12_STARTP 0x1d05 344#define VPP_VSC_REGION34_STARTP 0x1d06 345#define VPP_VSC_REGION4_ENDP 0x1d07 346#define VPP_VSC_START_PHASE_STEP 0x1d08 347#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 348#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 349#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 350#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 351#define VPP_VSC_PHASE_CTRL 0x1d0d 352#define VPP_VSC_INI_PHASE 0x1d0e 353#define VPP_HSC_REGION12_STARTP 0x1d10 354#define VPP_HSC_REGION34_STARTP 0x1d11 355#define VPP_HSC_REGION4_ENDP 0x1d12 356#define VPP_HSC_START_PHASE_STEP 0x1d13 357#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 358#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 359#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 360#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 361#define VPP_HSC_PHASE_CTRL 0x1d18 362#define VPP_SC_MISC 0x1d19 363#define VPP_PREBLEND_VD1_H_START_END 0x1d1a 364#define VPP_PREBLEND_VD1_V_START_END 0x1d1b 365#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 366#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 367#define VPP_BLEND_VD2_H_START_END 0x1d1e 368#define VPP_BLEND_VD2_V_START_END 0x1d1f 369#define VPP_PREBLEND_H_SIZE 0x1d20 370#define VPP_POSTBLEND_H_SIZE 0x1d21 371#define VPP_HOLD_LINES 0x1d22 372#define VPP_BLEND_ONECOLOR_CTRL 0x1d23 373#define VPP_PREBLEND_CURRENT_XY 0x1d24 374#define VPP_POSTBLEND_CURRENT_XY 0x1d25 375#define VPP_MISC 0x1d26 376#define VPP_PREBLEND_ENABLE BIT(6) 377#define VPP_POSTBLEND_ENABLE BIT(7) 378#define VPP_OSD2_ALPHA_PREMULT BIT(8) 379#define VPP_OSD1_ALPHA_PREMULT BIT(9) 380#define VPP_VD1_POSTBLEND BIT(10) 381#define VPP_VD2_POSTBLEND BIT(11) 382#define VPP_OSD1_POSTBLEND BIT(12) 383#define VPP_OSD2_POSTBLEND BIT(13) 384#define VPP_VD1_PREBLEND BIT(14) 385#define VPP_VD2_PREBLEND BIT(15) 386#define VPP_OSD1_PREBLEND BIT(16) 387#define VPP_OSD2_PREBLEND BIT(17) 388#define VPP_COLOR_MNG_ENABLE BIT(28) 389#define VPP_OFIFO_SIZE 0x1d27 390#define VPP_FIFO_STATUS 0x1d28 391#define VPP_SMOKE_CTRL 0x1d29 392#define VPP_SMOKE1_VAL 0x1d2a 393#define VPP_SMOKE2_VAL 0x1d2b 394#define VPP_SMOKE3_VAL 0x1d2c 395#define VPP_SMOKE1_H_START_END 0x1d2d 396#define VPP_SMOKE1_V_START_END 0x1d2e 397#define VPP_SMOKE2_H_START_END 0x1d2f 398#define VPP_SMOKE2_V_START_END 0x1d30 399#define VPP_SMOKE3_H_START_END 0x1d31 400#define VPP_SMOKE3_V_START_END 0x1d32 401#define VPP_SCO_FIFO_CTRL 0x1d33 402#define VPP_HSC_PHASE_CTRL1 0x1d34 403#define VPP_HSC_INI_PAT_CTRL 0x1d35 404#define VPP_VADJ_CTRL 0x1d40 405#define VPP_VADJ1_Y 0x1d41 406#define VPP_VADJ1_MA_MB 0x1d42 407#define VPP_VADJ1_MC_MD 0x1d43 408#define VPP_VADJ2_Y 0x1d44 409#define VPP_VADJ2_MA_MB 0x1d45 410#define VPP_VADJ2_MC_MD 0x1d46 411#define VPP_HSHARP_CTRL 0x1d50 412#define VPP_HSHARP_LUMA_THRESH01 0x1d51 413#define VPP_HSHARP_LUMA_THRESH23 0x1d52 414#define VPP_HSHARP_CHROMA_THRESH01 0x1d53 415#define VPP_HSHARP_CHROMA_THRESH23 0x1d54 416#define VPP_HSHARP_LUMA_GAIN 0x1d55 417#define VPP_HSHARP_CHROMA_GAIN 0x1d56 418#define VPP_MATRIX_PROBE_COLOR 0x1d5c 419#define VPP_MATRIX_HL_COLOR 0x1d5d 420#define VPP_MATRIX_PROBE_POS 0x1d5e 421#define VPP_MATRIX_CTRL 0x1d5f 422#define VPP_MATRIX_COEF00_01 0x1d60 423#define VPP_MATRIX_COEF02_10 0x1d61 424#define VPP_MATRIX_COEF11_12 0x1d62 425#define VPP_MATRIX_COEF20_21 0x1d63 426#define VPP_MATRIX_COEF22 0x1d64 427#define VPP_MATRIX_OFFSET0_1 0x1d65 428#define VPP_MATRIX_OFFSET2 0x1d66 429#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 430#define VPP_MATRIX_PRE_OFFSET2 0x1d68 431#define VPP_DUMMY_DATA1 0x1d69 432#define VPP_GAINOFF_CTRL0 0x1d6a 433#define VPP_GAINOFF_CTRL1 0x1d6b 434#define VPP_GAINOFF_CTRL2 0x1d6c 435#define VPP_GAINOFF_CTRL3 0x1d6d 436#define VPP_GAINOFF_CTRL4 0x1d6e 437#define VPP_CHROMA_ADDR_PORT 0x1d70 438#define VPP_CHROMA_DATA_PORT 0x1d71 439#define VPP_GCLK_CTRL0 0x1d72 440#define VPP_GCLK_CTRL1 0x1d73 441#define VPP_SC_GCLK_CTRL 0x1d74 442#define VPP_MISC1 0x1d76 443#define VPP_BLACKEXT_CTRL 0x1d80 444#define VPP_DNLP_CTRL_00 0x1d81 445#define VPP_DNLP_CTRL_01 0x1d82 446#define VPP_DNLP_CTRL_02 0x1d83 447#define VPP_DNLP_CTRL_03 0x1d84 448#define VPP_DNLP_CTRL_04 0x1d85 449#define VPP_DNLP_CTRL_05 0x1d86 450#define VPP_DNLP_CTRL_06 0x1d87 451#define VPP_DNLP_CTRL_07 0x1d88 452#define VPP_DNLP_CTRL_08 0x1d89 453#define VPP_DNLP_CTRL_09 0x1d8a 454#define VPP_DNLP_CTRL_10 0x1d8b 455#define VPP_DNLP_CTRL_11 0x1d8c 456#define VPP_DNLP_CTRL_12 0x1d8d 457#define VPP_DNLP_CTRL_13 0x1d8e 458#define VPP_DNLP_CTRL_14 0x1d8f 459#define VPP_DNLP_CTRL_15 0x1d90 460#define VPP_PEAKING_HGAIN 0x1d91 461#define VPP_PEAKING_VGAIN 0x1d92 462#define VPP_PEAKING_NLP_1 0x1d93 463#define VPP_DOLBY_CTRL 0x1d93 464#define VPP_PEAKING_NLP_2 0x1d94 465#define VPP_PEAKING_NLP_3 0x1d95 466#define VPP_PEAKING_NLP_4 0x1d96 467#define VPP_PEAKING_NLP_5 0x1d97 468#define VPP_SHARP_LIMIT 0x1d98 469#define VPP_VLTI_CTRL 0x1d99 470#define VPP_HLTI_CTRL 0x1d9a 471#define VPP_CTI_CTRL 0x1d9b 472#define VPP_BLUE_STRETCH_1 0x1d9c 473#define VPP_BLUE_STRETCH_2 0x1d9d 474#define VPP_BLUE_STRETCH_3 0x1d9e 475#define VPP_CCORING_CTRL 0x1da0 476#define VPP_VE_ENABLE_CTRL 0x1da1 477#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 478#define VPP_VE_DEMO_CENTER_BAR 0x1da3 479#define VPP_VE_H_V_SIZE 0x1da4 480#define VPP_VDO_MEAS_CTRL 0x1da8 481#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 482#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 483#define VPP_INPUT_CTRL 0x1dab 484#define VPP_CTI_CTRL2 0x1dac 485#define VPP_PEAKING_SAT_THD1 0x1dad 486#define VPP_PEAKING_SAT_THD2 0x1dae 487#define VPP_PEAKING_SAT_THD3 0x1daf 488#define VPP_PEAKING_SAT_THD4 0x1db0 489#define VPP_PEAKING_SAT_THD5 0x1db1 490#define VPP_PEAKING_SAT_THD6 0x1db2 491#define VPP_PEAKING_SAT_THD7 0x1db3 492#define VPP_PEAKING_SAT_THD8 0x1db4 493#define VPP_PEAKING_SAT_THD9 0x1db5 494#define VPP_PEAKING_GAIN_ADD1 0x1db6 495#define VPP_PEAKING_GAIN_ADD2 0x1db7 496#define VPP_PEAKING_DNLP 0x1db8 497#define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 498#define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 499#define VPP_FRONT_HLTI_CTRL 0x1dbb 500#define VPP_FRONT_CTI_CTRL 0x1dbc 501#define VPP_FRONT_CTI_CTRL2 0x1dbd 502#define VPP_OSD_VSC_PHASE_STEP 0x1dc0 503#define VPP_OSD_VSC_INI_PHASE 0x1dc1 504#define VPP_OSD_VSC_CTRL0 0x1dc2 505#define VPP_OSD_HSC_PHASE_STEP 0x1dc3 506#define VPP_OSD_HSC_INI_PHASE 0x1dc4 507#define VPP_OSD_HSC_CTRL0 0x1dc5 508#define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 509#define VPP_OSD_SC_DUMMY_DATA 0x1dc7 510#define VPP_OSD_SC_CTRL0 0x1dc8 511#define VPP_OSD_SCI_WH_M1 0x1dc9 512#define VPP_OSD_SCO_H_START_END 0x1dca 513#define VPP_OSD_SCO_V_START_END 0x1dcb 514#define VPP_OSD_SCALE_COEF_IDX 0x1dcc 515#define VPP_OSD_SCALE_COEF 0x1dcd 516#define VPP_INT_LINE_NUM 0x1dce 517 518#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60 519#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61 520#define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62 521#define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63 522#define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64 523#define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65 524#define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66 525#define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67 526#define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68 527#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69 528#define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a 529#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b 530#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c 531#define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d 532 533#define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70 534#define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71 535#define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72 536#define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73 537#define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74 538#define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75 539#define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76 540#define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77 541#define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78 542#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79 543#define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a 544#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b 545#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c 546#define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d 547 548#define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0 549#define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1 550#define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2 551#define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3 552#define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4 553#define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5 554#define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6 555#define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7 556#define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8 557#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9 558#define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba 559#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb 560#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc 561#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd 562 563/* osd2 scaler */ 564#define OSD2_VSC_PHASE_STEP 0x3d00 565#define OSD2_VSC_INI_PHASE 0x3d01 566#define OSD2_VSC_CTRL0 0x3d02 567#define OSD2_HSC_PHASE_STEP 0x3d03 568#define OSD2_HSC_INI_PHASE 0x3d04 569#define OSD2_HSC_CTRL0 0x3d05 570#define OSD2_HSC_INI_PAT_CTRL 0x3d06 571#define OSD2_SC_DUMMY_DATA 0x3d07 572#define OSD2_SC_CTRL0 0x3d08 573#define OSD2_SCI_WH_M1 0x3d09 574#define OSD2_SCO_H_START_END 0x3d0a 575#define OSD2_SCO_V_START_END 0x3d0b 576#define OSD2_SCALE_COEF_IDX 0x3d18 577#define OSD2_SCALE_COEF 0x3d19 578 579/* osd34 scaler */ 580#define OSD34_SCALE_COEF_IDX 0x3d1e 581#define OSD34_SCALE_COEF 0x3d1f 582#define OSD34_VSC_PHASE_STEP 0x3d20 583#define OSD34_VSC_INI_PHASE 0x3d21 584#define OSD34_VSC_CTRL0 0x3d22 585#define OSD34_HSC_PHASE_STEP 0x3d23 586#define OSD34_HSC_INI_PHASE 0x3d24 587#define OSD34_HSC_CTRL0 0x3d25 588#define OSD34_HSC_INI_PAT_CTRL 0x3d26 589#define OSD34_SC_DUMMY_DATA 0x3d27 590#define OSD34_SC_CTRL0 0x3d28 591#define OSD34_SCI_WH_M1 0x3d29 592#define OSD34_SCO_H_START_END 0x3d2a 593#define OSD34_SCO_V_START_END 0x3d2b 594/* viu2 */ 595#define VIU2_ADDR_START 0x1e00 596#define VIU2_ADDR_END 0x1eff 597#define VIU2_SW_RESET 0x1e01 598#define VIU2_OSD1_CTRL_STAT 0x1e10 599#define VIU2_OSD1_CTRL_STAT2 0x1e2d 600#define VIU2_OSD1_COLOR_ADDR 0x1e11 601#define VIU2_OSD1_COLOR 0x1e12 602#define VIU2_OSD1_TCOLOR_AG0 0x1e17 603#define VIU2_OSD1_TCOLOR_AG1 0x1e18 604#define VIU2_OSD1_TCOLOR_AG2 0x1e19 605#define VIU2_OSD1_TCOLOR_AG3 0x1e1a 606#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 607#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 608#define VIU2_OSD1_BLK2_CFG_W0 0x1e23 609#define VIU2_OSD1_BLK3_CFG_W0 0x1e27 610#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 611#define VIU2_OSD1_BLK1_CFG_W1 0x1e20 612#define VIU2_OSD1_BLK2_CFG_W1 0x1e24 613#define VIU2_OSD1_BLK3_CFG_W1 0x1e28 614#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 615#define VIU2_OSD1_BLK1_CFG_W2 0x1e21 616#define VIU2_OSD1_BLK2_CFG_W2 0x1e25 617#define VIU2_OSD1_BLK3_CFG_W2 0x1e29 618#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 619#define VIU2_OSD1_BLK1_CFG_W3 0x1e22 620#define VIU2_OSD1_BLK2_CFG_W3 0x1e26 621#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 622#define VIU2_OSD1_BLK0_CFG_W4 0x1e13 623#define VIU2_OSD1_BLK1_CFG_W4 0x1e14 624#define VIU2_OSD1_BLK2_CFG_W4 0x1e15 625#define VIU2_OSD1_BLK3_CFG_W4 0x1e16 626#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 627#define VIU2_OSD1_TEST_RDDATA 0x1e2c 628#define VIU2_OSD1_PROT_CTRL 0x1e2e 629#define VIU2_OSD2_CTRL_STAT 0x1e30 630#define VIU2_OSD2_CTRL_STAT2 0x1e4d 631#define VIU2_OSD2_COLOR_ADDR 0x1e31 632#define VIU2_OSD2_COLOR 0x1e32 633#define VIU2_OSD2_HL1_H_START_END 0x1e33 634#define VIU2_OSD2_HL1_V_START_END 0x1e34 635#define VIU2_OSD2_HL2_H_START_END 0x1e35 636#define VIU2_OSD2_HL2_V_START_END 0x1e36 637#define VIU2_OSD2_TCOLOR_AG0 0x1e37 638#define VIU2_OSD2_TCOLOR_AG1 0x1e38 639#define VIU2_OSD2_TCOLOR_AG2 0x1e39 640#define VIU2_OSD2_TCOLOR_AG3 0x1e3a 641#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 642#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 643#define VIU2_OSD2_BLK2_CFG_W0 0x1e43 644#define VIU2_OSD2_BLK3_CFG_W0 0x1e47 645#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 646#define VIU2_OSD2_BLK1_CFG_W1 0x1e40 647#define VIU2_OSD2_BLK2_CFG_W1 0x1e44 648#define VIU2_OSD2_BLK3_CFG_W1 0x1e48 649#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 650#define VIU2_OSD2_BLK1_CFG_W2 0x1e41 651#define VIU2_OSD2_BLK2_CFG_W2 0x1e45 652#define VIU2_OSD2_BLK3_CFG_W2 0x1e49 653#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 654#define VIU2_OSD2_BLK1_CFG_W3 0x1e42 655#define VIU2_OSD2_BLK2_CFG_W3 0x1e46 656#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 657#define VIU2_OSD2_BLK0_CFG_W4 0x1e64 658#define VIU2_OSD2_BLK1_CFG_W4 0x1e65 659#define VIU2_OSD2_BLK2_CFG_W4 0x1e66 660#define VIU2_OSD2_BLK3_CFG_W4 0x1e67 661#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 662#define VIU2_OSD2_TEST_RDDATA 0x1e4c 663#define VIU2_OSD2_PROT_CTRL 0x1e4e 664#define VIU2_VD1_IF0_GEN_REG 0x1e50 665#define VIU2_VD1_IF0_CANVAS0 0x1e51 666#define VIU2_VD1_IF0_CANVAS1 0x1e52 667#define VIU2_VD1_IF0_LUMA_X0 0x1e53 668#define VIU2_VD1_IF0_LUMA_Y0 0x1e54 669#define VIU2_VD1_IF0_CHROMA_X0 0x1e55 670#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 671#define VIU2_VD1_IF0_LUMA_X1 0x1e57 672#define VIU2_VD1_IF0_LUMA_Y1 0x1e58 673#define VIU2_VD1_IF0_CHROMA_X1 0x1e59 674#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 675#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 676#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 677#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 678#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 679#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 680#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 681#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 682#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 683#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 684#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 685#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 686#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 687#define VIU2_VD1_IF0_GEN_REG2 0x1e6d 688#define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 689#define VIU2_VD1_FMT_CTRL 0x1e68 690#define VIU2_VD1_FMT_W 0x1e69 691 692/* encode */ 693#define ENCP_VFIFO2VD_CTL 0x1b58 694#define ENCP_VFIFO2VD_PIXEL_START 0x1b59 695#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 696#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 697#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 698#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 699#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 700#define VENC_SYNC_ROUTE 0x1b60 701#define VENC_VIDEO_EXSRC 0x1b61 702#define VENC_DVI_SETTING 0x1b62 703#define VENC_C656_CTRL 0x1b63 704#define VENC_UPSAMPLE_CTRL0 0x1b64 705#define VENC_UPSAMPLE_CTRL1 0x1b65 706#define VENC_UPSAMPLE_CTRL2 0x1b66 707#define TCON_INVERT_CTL 0x1b67 708#define VENC_VIDEO_PROG_MODE 0x1b68 709#define VENC_ENCI_LINE 0x1b69 710#define VENC_ENCI_PIXEL 0x1b6a 711#define VENC_ENCP_LINE 0x1b6b 712#define VENC_ENCP_PIXEL 0x1b6c 713#define VENC_STATA 0x1b6d 714#define VENC_INTCTRL 0x1b6e 715#define VENC_INTFLAG 0x1b6f 716#define VENC_VIDEO_TST_EN 0x1b70 717#define VENC_VIDEO_TST_MDSEL 0x1b71 718#define VENC_VIDEO_TST_Y 0x1b72 719#define VENC_VIDEO_TST_CB 0x1b73 720#define VENC_VIDEO_TST_CR 0x1b74 721#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 722#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 723#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 724#define VENC_VDAC_DACSEL0 0x1b78 725#define VENC_VDAC_DACSEL1 0x1b79 726#define VENC_VDAC_DACSEL2 0x1b7a 727#define VENC_VDAC_DACSEL3 0x1b7b 728#define VENC_VDAC_DACSEL4 0x1b7c 729#define VENC_VDAC_DACSEL5 0x1b7d 730#define VENC_VDAC_SETTING 0x1b7e 731#define VENC_VDAC_TST_VAL 0x1b7f 732#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 733#define VENC_VDAC_DAC0_OFFSET 0x1bf1 734#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 735#define VENC_VDAC_DAC1_OFFSET 0x1bf3 736#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 737#define VENC_VDAC_DAC2_OFFSET 0x1bf5 738#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 739#define VENC_VDAC_DAC3_OFFSET 0x1bf7 740#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 741#define VENC_VDAC_DAC4_OFFSET 0x1bf9 742#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 743#define VENC_VDAC_DAC5_OFFSET 0x1bfb 744#define VENC_VDAC_FIFO_CTRL 0x1bfc 745#define ENCL_TCON_INVERT_CTL 0x1bfd 746#define ENCP_VIDEO_EN 0x1b80 747#define ENCP_VIDEO_SYNC_MODE 0x1b81 748#define ENCP_MACV_EN 0x1b82 749#define ENCP_VIDEO_Y_SCL 0x1b83 750#define ENCP_VIDEO_PB_SCL 0x1b84 751#define ENCP_VIDEO_PR_SCL 0x1b85 752#define ENCP_VIDEO_SYNC_SCL 0x1b86 753#define ENCP_VIDEO_MACV_SCL 0x1b87 754#define ENCP_VIDEO_Y_OFFST 0x1b88 755#define ENCP_VIDEO_PB_OFFST 0x1b89 756#define ENCP_VIDEO_PR_OFFST 0x1b8a 757#define ENCP_VIDEO_SYNC_OFFST 0x1b8b 758#define ENCP_VIDEO_MACV_OFFST 0x1b8c 759#define ENCP_VIDEO_MODE 0x1b8d 760#define ENCP_VIDEO_MODE_ADV 0x1b8e 761#define ENCP_DBG_PX_RST 0x1b90 762#define ENCP_DBG_LN_RST 0x1b91 763#define ENCP_DBG_PX_INT 0x1b92 764#define ENCP_DBG_LN_INT 0x1b93 765#define ENCP_VIDEO_YFP1_HTIME 0x1b94 766#define ENCP_VIDEO_YFP2_HTIME 0x1b95 767#define ENCP_VIDEO_YC_DLY 0x1b96 768#define ENCP_VIDEO_MAX_PXCNT 0x1b97 769#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 770#define ENCP_VIDEO_HSPULS_END 0x1b99 771#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 772#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 773#define ENCP_VIDEO_VSPULS_END 0x1b9c 774#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 775#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 776#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 777#define ENCP_VIDEO_EQPULS_END 0x1ba0 778#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 779#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 780#define ENCP_VIDEO_HAVON_END 0x1ba3 781#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 782#define ENCP_VIDEO_VAVON_ELINE 0x1baf 783#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 784#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 785#define ENCP_VIDEO_HSO_END 0x1ba8 786#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 787#define ENCP_VIDEO_VSO_END 0x1baa 788#define ENCP_VIDEO_VSO_BLINE 0x1bab 789#define ENCP_VIDEO_VSO_ELINE 0x1bac 790#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 791#define ENCP_VIDEO_MAX_LNCNT 0x1bae 792#define ENCP_VIDEO_SY_VAL 0x1bb0 793#define ENCP_VIDEO_SY2_VAL 0x1bb1 794#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 795#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 796#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 797#define ENCP_VIDEO_HOFFST 0x1bb5 798#define ENCP_VIDEO_VOFFST 0x1bb6 799#define ENCP_VIDEO_RGB_CTRL 0x1bb7 800#define ENCP_VIDEO_FILT_CTRL 0x1bb8 801#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 802#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 803#define ENCP_VIDEO_MATRIX_CB 0x1bbb 804#define ENCP_VIDEO_MATRIX_CR 0x1bbc 805#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 806#define ENCP_MACV_BLANKY_VAL 0x1bc0 807#define ENCP_MACV_MAXY_VAL 0x1bc1 808#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 809#define ENCP_MACV_PSSYNC_STRT 0x1bc3 810#define ENCP_MACV_AGC_STRT 0x1bc4 811#define ENCP_MACV_AGC_END 0x1bc5 812#define ENCP_MACV_WAVE_END 0x1bc6 813#define ENCP_MACV_STRTLINE 0x1bc7 814#define ENCP_MACV_ENDLINE 0x1bc8 815#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 816#define ENCP_MACV_TS_CNT_MAX_H 0x1bca 817#define ENCP_MACV_TIME_DOWN 0x1bcb 818#define ENCP_MACV_TIME_LO 0x1bcc 819#define ENCP_MACV_TIME_UP 0x1bcd 820#define ENCP_MACV_TIME_RST 0x1bce 821#define ENCP_VBI_CTRL 0x1bd0 822#define ENCP_VBI_SETTING 0x1bd1 823#define ENCP_VBI_BEGIN 0x1bd2 824#define ENCP_VBI_WIDTH 0x1bd3 825#define ENCP_VBI_HVAL 0x1bd4 826#define ENCP_VBI_DATA0 0x1bd5 827#define ENCP_VBI_DATA1 0x1bd6 828#define C656_HS_ST 0x1be0 829#define C656_HS_ED 0x1be1 830#define C656_VS_LNST_E 0x1be2 831#define C656_VS_LNST_O 0x1be3 832#define C656_VS_LNED_E 0x1be4 833#define C656_VS_LNED_O 0x1be5 834#define C656_FS_LNST 0x1be6 835#define C656_FS_LNED 0x1be7 836#define ENCI_VIDEO_MODE 0x1b00 837#define ENCI_VIDEO_MODE_ADV 0x1b01 838#define ENCI_VIDEO_FSC_ADJ 0x1b02 839#define ENCI_VIDEO_BRIGHT 0x1b03 840#define ENCI_VIDEO_CONT 0x1b04 841#define ENCI_VIDEO_SAT 0x1b05 842#define ENCI_VIDEO_HUE 0x1b06 843#define ENCI_VIDEO_SCH 0x1b07 844#define ENCI_SYNC_MODE 0x1b08 845#define ENCI_SYNC_CTRL 0x1b09 846#define ENCI_SYNC_HSO_BEGIN 0x1b0a 847#define ENCI_SYNC_HSO_END 0x1b0b 848#define ENCI_SYNC_VSO_EVN 0x1b0c 849#define ENCI_SYNC_VSO_ODD 0x1b0d 850#define ENCI_SYNC_VSO_EVNLN 0x1b0e 851#define ENCI_SYNC_VSO_ODDLN 0x1b0f 852#define ENCI_SYNC_HOFFST 0x1b10 853#define ENCI_SYNC_VOFFST 0x1b11 854#define ENCI_SYNC_ADJ 0x1b12 855#define ENCI_RGB_SETTING 0x1b13 856#define ENCI_DE_H_BEGIN 0x1b16 857#define ENCI_DE_H_END 0x1b17 858#define ENCI_DE_V_BEGIN_EVEN 0x1b18 859#define ENCI_DE_V_END_EVEN 0x1b19 860#define ENCI_DE_V_BEGIN_ODD 0x1b1a 861#define ENCI_DE_V_END_ODD 0x1b1b 862#define ENCI_VBI_SETTING 0x1b20 863#define ENCI_VBI_CCDT_EVN 0x1b21 864#define ENCI_VBI_CCDT_ODD 0x1b22 865#define ENCI_VBI_CC525_LN 0x1b23 866#define ENCI_VBI_CC625_LN 0x1b24 867#define ENCI_VBI_WSSDT 0x1b25 868#define ENCI_VBI_WSS_LN 0x1b26 869#define ENCI_VBI_CGMSDT_L 0x1b27 870#define ENCI_VBI_CGMSDT_H 0x1b28 871#define ENCI_VBI_CGMS_LN 0x1b29 872#define ENCI_VBI_TTX_HTIME 0x1b2a 873#define ENCI_VBI_TTX_LN 0x1b2b 874#define ENCI_VBI_TTXDT0 0x1b2c 875#define ENCI_VBI_TTXDT1 0x1b2d 876#define ENCI_VBI_TTXDT2 0x1b2e 877#define ENCI_VBI_TTXDT3 0x1b2f 878#define ENCI_MACV_N0 0x1b30 879#define ENCI_MACV_N1 0x1b31 880#define ENCI_MACV_N2 0x1b32 881#define ENCI_MACV_N3 0x1b33 882#define ENCI_MACV_N4 0x1b34 883#define ENCI_MACV_N5 0x1b35 884#define ENCI_MACV_N6 0x1b36 885#define ENCI_MACV_N7 0x1b37 886#define ENCI_MACV_N8 0x1b38 887#define ENCI_MACV_N9 0x1b39 888#define ENCI_MACV_N10 0x1b3a 889#define ENCI_MACV_N11 0x1b3b 890#define ENCI_MACV_N12 0x1b3c 891#define ENCI_MACV_N13 0x1b3d 892#define ENCI_MACV_N14 0x1b3e 893#define ENCI_MACV_N15 0x1b3f 894#define ENCI_MACV_N16 0x1b40 895#define ENCI_MACV_N17 0x1b41 896#define ENCI_MACV_N18 0x1b42 897#define ENCI_MACV_N19 0x1b43 898#define ENCI_MACV_N20 0x1b44 899#define ENCI_MACV_N21 0x1b45 900#define ENCI_MACV_N22 0x1b46 901#define ENCI_DBG_PX_RST 0x1b48 902#define ENCI_DBG_FLDLN_RST 0x1b49 903#define ENCI_DBG_PX_INT 0x1b4a 904#define ENCI_DBG_FLDLN_INT 0x1b4b 905#define ENCI_DBG_MAXPX 0x1b4c 906#define ENCI_DBG_MAXLN 0x1b4d 907#define ENCI_MACV_MAX_AMP 0x1b50 908#define ENCI_MACV_PULSE_LO 0x1b51 909#define ENCI_MACV_PULSE_HI 0x1b52 910#define ENCI_MACV_BKP_MAX 0x1b53 911#define ENCI_CFILT_CTRL 0x1b54 912#define ENCI_CFILT7 0x1b55 913#define ENCI_YC_DELAY 0x1b56 914#define ENCI_VIDEO_EN 0x1b57 915#define ENCI_DVI_HSO_BEGIN 0x1c00 916#define ENCI_DVI_HSO_END 0x1c01 917#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 918#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 919#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 920#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 921#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 922#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 923#define ENCI_DVI_VSO_END_EVN 0x1c08 924#define ENCI_DVI_VSO_END_ODD 0x1c09 925#define ENCI_CFILT_CTRL2 0x1c0a 926#define ENCI_DACSEL_0 0x1c0b 927#define ENCI_DACSEL_1 0x1c0c 928#define ENCP_DACSEL_0 0x1c0d 929#define ENCP_DACSEL_1 0x1c0e 930#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 931#define ENCI_TST_EN 0x1c10 932#define ENCI_TST_MDSEL 0x1c11 933#define ENCI_TST_Y 0x1c12 934#define ENCI_TST_CB 0x1c13 935#define ENCI_TST_CR 0x1c14 936#define ENCI_TST_CLRBAR_STRT 0x1c15 937#define ENCI_TST_CLRBAR_WIDTH 0x1c16 938#define ENCI_TST_VDCNT_STSET 0x1c17 939#define ENCI_VFIFO2VD_CTL 0x1c18 940#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 941#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 942#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 943#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 944#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 945#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 946#define ENCI_VFIFO2VD_CTL2 0x1c1f 947#define ENCT_VFIFO2VD_CTL 0x1c20 948#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 949#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 950#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 951#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 952#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 953#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 954#define ENCT_VFIFO2VD_CTL2 0x1c27 955#define ENCT_TST_EN 0x1c28 956#define ENCT_TST_MDSEL 0x1c29 957#define ENCT_TST_Y 0x1c2a 958#define ENCT_TST_CB 0x1c2b 959#define ENCT_TST_CR 0x1c2c 960#define ENCT_TST_CLRBAR_STRT 0x1c2d 961#define ENCT_TST_CLRBAR_WIDTH 0x1c2e 962#define ENCT_TST_VDCNT_STSET 0x1c2f 963#define ENCP_DVI_HSO_BEGIN 0x1c30 964#define ENCP_DVI_HSO_END 0x1c31 965#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 966#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 967#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 968#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 969#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 970#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 971#define ENCP_DVI_VSO_END_EVN 0x1c38 972#define ENCP_DVI_VSO_END_ODD 0x1c39 973#define ENCP_DE_H_BEGIN 0x1c3a 974#define ENCP_DE_H_END 0x1c3b 975#define ENCP_DE_V_BEGIN_EVEN 0x1c3c 976#define ENCP_DE_V_END_EVEN 0x1c3d 977#define ENCP_DE_V_BEGIN_ODD 0x1c3e 978#define ENCP_DE_V_END_ODD 0x1c3f 979#define ENCI_SYNC_LINE_LENGTH 0x1c40 980#define ENCI_SYNC_PIXEL_EN 0x1c41 981#define ENCI_SYNC_TO_LINE_EN 0x1c42 982#define ENCI_SYNC_TO_PIXEL 0x1c43 983#define ENCP_SYNC_LINE_LENGTH 0x1c44 984#define ENCP_SYNC_PIXEL_EN 0x1c45 985#define ENCP_SYNC_TO_LINE_EN 0x1c46 986#define ENCP_SYNC_TO_PIXEL 0x1c47 987#define ENCT_SYNC_LINE_LENGTH 0x1c48 988#define ENCT_SYNC_PIXEL_EN 0x1c49 989#define ENCT_SYNC_TO_LINE_EN 0x1c4a 990#define ENCT_SYNC_TO_PIXEL 0x1c4b 991#define ENCL_SYNC_LINE_LENGTH 0x1c4c 992#define ENCL_SYNC_PIXEL_EN 0x1c4d 993#define ENCL_SYNC_TO_LINE_EN 0x1c4e 994#define ENCL_SYNC_TO_PIXEL 0x1c4f 995#define ENCP_VFIFO2VD_CTL2 0x1c50 996#define VENC_DVI_SETTING_MORE 0x1c51 997#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 998#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 999#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 1000#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
1001#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 1002#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 1003#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 1004#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 1005#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 1006#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 1007#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 1008#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 1009#define ENCT_VIDEO_EN 0x1c60 1010#define ENCT_VIDEO_Y_SCL 0x1c61 1011#define ENCT_VIDEO_PB_SCL 0x1c62 1012#define ENCT_VIDEO_PR_SCL 0x1c63 1013#define ENCT_VIDEO_Y_OFFST 0x1c64 1014#define ENCT_VIDEO_PB_OFFST 0x1c65 1015#define ENCT_VIDEO_PR_OFFST 0x1c66 1016#define ENCT_VIDEO_MODE 0x1c67 1017#define ENCT_VIDEO_MODE_ADV 0x1c68 1018#define ENCT_DBG_PX_RST 0x1c69 1019#define ENCT_DBG_LN_RST 0x1c6a 1020#define ENCT_DBG_PX_INT 0x1c6b 1021#define ENCT_DBG_LN_INT 0x1c6c 1022#define ENCT_VIDEO_YFP1_HTIME 0x1c6d 1023#define ENCT_VIDEO_YFP2_HTIME 0x1c6e 1024#define ENCT_VIDEO_YC_DLY 0x1c6f 1025#define ENCT_VIDEO_MAX_PXCNT 0x1c70 1026#define ENCT_VIDEO_HAVON_END 0x1c71 1027#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 1028#define ENCT_VIDEO_VAVON_ELINE 0x1c73 1029#define ENCT_VIDEO_VAVON_BLINE 0x1c74 1030#define ENCT_VIDEO_HSO_BEGIN 0x1c75 1031#define ENCT_VIDEO_HSO_END 0x1c76 1032#define ENCT_VIDEO_VSO_BEGIN 0x1c77 1033#define ENCT_VIDEO_VSO_END 0x1c78 1034#define ENCT_VIDEO_VSO_BLINE 0x1c79 1035#define ENCT_VIDEO_VSO_ELINE 0x1c7a 1036#define ENCT_VIDEO_MAX_LNCNT 0x1c7b 1037#define ENCT_VIDEO_BLANKY_VAL 0x1c7c 1038#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 1039#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 1040#define ENCT_VIDEO_HOFFST 0x1c7f 1041#define ENCT_VIDEO_VOFFST 0x1c80 1042#define ENCT_VIDEO_RGB_CTRL 0x1c81 1043#define ENCT_VIDEO_FILT_CTRL 0x1c82 1044#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 1045#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 1046#define ENCT_VIDEO_MATRIX_CB 0x1c85 1047#define ENCT_VIDEO_MATRIX_CR 0x1c86 1048#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 1049#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 1050#define ENCT_DACSEL_0 0x1c89 1051#define ENCT_DACSEL_1 0x1c8a 1052#define ENCL_VFIFO2VD_CTL 0x1c90 1053#define ENCL_VFIFO2VD_PIXEL_START 0x1c91 1054#define ENCL_VFIFO2VD_PIXEL_END 0x1c92 1055#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 1056#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 1057#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 1058#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 1059#define ENCL_VFIFO2VD_CTL2 0x1c97 1060#define ENCL_TST_EN 0x1c98 1061#define ENCL_TST_MDSEL 0x1c99 1062#define ENCL_TST_Y 0x1c9a 1063#define ENCL_TST_CB 0x1c9b 1064#define ENCL_TST_CR 0x1c9c 1065#define ENCL_TST_CLRBAR_STRT 0x1c9d 1066#define ENCL_TST_CLRBAR_WIDTH 0x1c9e 1067#define ENCL_TST_VDCNT_STSET 0x1c9f 1068#define ENCL_VIDEO_EN 0x1ca0 1069#define ENCL_VIDEO_Y_SCL 0x1ca1 1070#define ENCL_VIDEO_PB_SCL 0x1ca2 1071#define ENCL_VIDEO_PR_SCL 0x1ca3 1072#define ENCL_VIDEO_Y_OFFST 0x1ca4 1073#define ENCL_VIDEO_PB_OFFST 0x1ca5 1074#define ENCL_VIDEO_PR_OFFST 0x1ca6 1075#define ENCL_VIDEO_MODE 0x1ca7 1076#define ENCL_VIDEO_MODE_ADV 0x1ca8 1077#define ENCL_DBG_PX_RST 0x1ca9 1078#define ENCL_DBG_LN_RST 0x1caa 1079#define ENCL_DBG_PX_INT 0x1cab 1080#define ENCL_DBG_LN_INT 0x1cac 1081#define ENCL_VIDEO_YFP1_HTIME 0x1cad 1082#define ENCL_VIDEO_YFP2_HTIME 0x1cae 1083#define ENCL_VIDEO_YC_DLY 0x1caf 1084#define ENCL_VIDEO_MAX_PXCNT 0x1cb0 1085#define ENCL_VIDEO_HAVON_END 0x1cb1 1086#define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 1087#define ENCL_VIDEO_VAVON_ELINE 0x1cb3 1088#define ENCL_VIDEO_VAVON_BLINE 0x1cb4 1089#define ENCL_VIDEO_HSO_BEGIN 0x1cb5 1090#define ENCL_VIDEO_HSO_END 0x1cb6 1091#define ENCL_VIDEO_VSO_BEGIN 0x1cb7 1092#define ENCL_VIDEO_VSO_END 0x1cb8 1093#define ENCL_VIDEO_VSO_BLINE 0x1cb9 1094#define ENCL_VIDEO_VSO_ELINE 0x1cba 1095#define ENCL_VIDEO_MAX_LNCNT 0x1cbb 1096#define ENCL_VIDEO_BLANKY_VAL 0x1cbc 1097#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 1098#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 1099#define ENCL_VIDEO_HOFFST 0x1cbf 1100#define ENCL_VIDEO_VOFFST 0x1cc0 1101#define ENCL_VIDEO_RGB_CTRL 0x1cc1 1102#define ENCL_VIDEO_FILT_CTRL 0x1cc2 1103#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 1104#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 1105#define ENCL_VIDEO_MATRIX_CB 0x1cc5 1106#define ENCL_VIDEO_MATRIX_CR 0x1cc6 1107#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 1108#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 1109#define ENCL_DACSEL_0 0x1cc9 1110#define ENCL_DACSEL_1 0x1cca 1111#define RDMA_AHB_START_ADDR_MAN 0x1100 1112#define RDMA_AHB_END_ADDR_MAN 0x1101 1113#define RDMA_AHB_START_ADDR_1 0x1102 1114#define RDMA_AHB_END_ADDR_1 0x1103 1115#define RDMA_AHB_START_ADDR_2 0x1104 1116#define RDMA_AHB_END_ADDR_2 0x1105 1117#define RDMA_AHB_START_ADDR_3 0x1106 1118#define RDMA_AHB_END_ADDR_3 0x1107 1119#define RDMA_AHB_START_ADDR_4 0x1108 1120#define RDMA_AHB_END_ADDR_4 0x1109 1121#define RDMA_AHB_START_ADDR_5 0x110a 1122#define RDMA_AHB_END_ADDR_5 0x110b 1123#define RDMA_AHB_START_ADDR_6 0x110c 1124#define RDMA_AHB_END_ADDR_6 0x110d 1125#define RDMA_AHB_START_ADDR_7 0x110e 1126#define RDMA_AHB_END_ADDR_7 0x110f 1127#define RDMA_ACCESS_AUTO 0x1110 1128#define RDMA_ACCESS_AUTO2 0x1111 1129#define RDMA_ACCESS_AUTO3 0x1112 1130#define RDMA_ACCESS_MAN 0x1113 1131#define RDMA_CTRL 0x1114 1132#define RDMA_STATUS 0x1115 1133#define RDMA_STATUS2 0x1116 1134#define RDMA_STATUS3 0x1117 1135#define L_GAMMA_CNTL_PORT 0x1400 1136#define L_GAMMA_DATA_PORT 0x1401 1137#define L_GAMMA_ADDR_PORT 0x1402 1138#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 1139#define L_RGB_BASE_ADDR 0x1405 1140#define L_RGB_COEFF_ADDR 0x1406 1141#define L_POL_CNTL_ADDR 0x1407 1142#define L_DITH_CNTL_ADDR 0x1408 1143#define L_GAMMA_PROBE_CTRL 0x1409 1144#define L_GAMMA_PROBE_COLOR_L 0x140a 1145#define L_GAMMA_PROBE_COLOR_H 0x140b 1146#define L_GAMMA_PROBE_HL_COLOR 0x140c 1147#define L_GAMMA_PROBE_POS_X 0x140d 1148#define L_GAMMA_PROBE_POS_Y 0x140e 1149#define L_STH1_HS_ADDR 0x1410 1150#define L_STH1_HE_ADDR 0x1411 1151#define L_STH1_VS_ADDR 0x1412 1152#define L_STH1_VE_ADDR 0x1413 1153#define L_STH2_HS_ADDR 0x1414 1154#define L_STH2_HE_ADDR 0x1415 1155#define L_STH2_VS_ADDR 0x1416 1156#define L_STH2_VE_ADDR 0x1417 1157#define L_OEH_HS_ADDR 0x1418 1158#define L_OEH_HE_ADDR 0x1419 1159#define L_OEH_VS_ADDR 0x141a 1160#define L_OEH_VE_ADDR 0x141b 1161#define L_VCOM_HSWITCH_ADDR 0x141c 1162#define L_VCOM_VS_ADDR 0x141d 1163#define L_VCOM_VE_ADDR 0x141e 1164#define L_CPV1_HS_ADDR 0x141f 1165#define L_CPV1_HE_ADDR 0x1420 1166#define L_CPV1_VS_ADDR 0x1421 1167#define L_CPV1_VE_ADDR 0x1422 1168#define L_CPV2_HS_ADDR 0x1423 1169#define L_CPV2_HE_ADDR 0x1424 1170#define L_CPV2_VS_ADDR 0x1425 1171#define L_CPV2_VE_ADDR 0x1426 1172#define L_STV1_HS_ADDR 0x1427 1173#define L_STV1_HE_ADDR 0x1428 1174#define L_STV1_VS_ADDR 0x1429 1175#define L_STV1_VE_ADDR 0x142a 1176#define L_STV2_HS_ADDR 0x142b 1177#define L_STV2_HE_ADDR 0x142c 1178#define L_STV2_VS_ADDR 0x142d 1179#define L_STV2_VE_ADDR 0x142e 1180#define L_OEV1_HS_ADDR 0x142f 1181#define L_OEV1_HE_ADDR 0x1430 1182#define L_OEV1_VS_ADDR 0x1431 1183#define L_OEV1_VE_ADDR 0x1432 1184#define L_OEV2_HS_ADDR 0x1433 1185#define L_OEV2_HE_ADDR 0x1434 1186#define L_OEV2_VS_ADDR 0x1435 1187#define L_OEV2_VE_ADDR 0x1436 1188#define L_OEV3_HS_ADDR 0x1437 1189#define L_OEV3_HE_ADDR 0x1438 1190#define L_OEV3_VS_ADDR 0x1439 1191#define L_OEV3_VE_ADDR 0x143a 1192#define L_LCD_PWR_ADDR 0x143b 1193#define L_LCD_PWM0_LO_ADDR 0x143c 1194#define L_LCD_PWM0_HI_ADDR 0x143d 1195#define L_LCD_PWM1_LO_ADDR 0x143e 1196#define L_LCD_PWM1_HI_ADDR 0x143f 1197#define L_INV_CNT_ADDR 0x1440 1198#define L_TCON_MISC_SEL_ADDR 0x1441 1199#define L_DUAL_PORT_CNTL_ADDR 0x1442 1200#define MLVDS_CLK_CTL1_HI 0x1443 1201#define MLVDS_CLK_CTL1_LO 0x1444 1202#define L_TCON_DOUBLE_CTL 0x1449 1203#define L_TCON_PATTERN_HI 0x144a 1204#define L_TCON_PATTERN_LO 0x144b 1205#define LDIM_BL_ADDR_PORT 0x144e 1206#define LDIM_BL_DATA_PORT 0x144f 1207#define L_DE_HS_ADDR 0x1451 1208#define L_DE_HE_ADDR 0x1452 1209#define L_DE_VS_ADDR 0x1453 1210#define L_DE_VE_ADDR 0x1454 1211#define L_HSYNC_HS_ADDR 0x1455 1212#define L_HSYNC_HE_ADDR 0x1456 1213#define L_HSYNC_VS_ADDR 0x1457 1214#define L_HSYNC_VE_ADDR 0x1458 1215#define L_VSYNC_HS_ADDR 0x1459 1216#define L_VSYNC_HE_ADDR 0x145a 1217#define L_VSYNC_VS_ADDR 0x145b 1218#define L_VSYNC_VE_ADDR 0x145c 1219#define L_LCD_MCU_CTL 0x145d 1220#define DUAL_MLVDS_CTL 0x1460 1221#define DUAL_MLVDS_LINE_START 0x1461 1222#define DUAL_MLVDS_LINE_END 0x1462 1223#define DUAL_MLVDS_PIXEL_W_START_L 0x1463 1224#define DUAL_MLVDS_PIXEL_W_END_L 0x1464 1225#define DUAL_MLVDS_PIXEL_W_START_R 0x1465 1226#define DUAL_MLVDS_PIXEL_W_END_R 0x1466 1227#define DUAL_MLVDS_PIXEL_R_START_L 0x1467 1228#define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 1229#define DUAL_MLVDS_PIXEL_R_START_R 0x1469 1230#define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 1231#define V_INVERSION_PIXEL 0x1470 1232#define V_INVERSION_LINE 0x1471 1233#define V_INVERSION_CONTROL 0x1472 1234#define MLVDS2_CONTROL 0x1474 1235#define MLVDS2_CONFIG_HI 0x1475 1236#define MLVDS2_CONFIG_LO 0x1476 1237#define MLVDS2_DUAL_GATE_WR_START 0x1477 1238#define MLVDS2_DUAL_GATE_WR_END 0x1478 1239#define MLVDS2_DUAL_GATE_RD_START 0x1479 1240#define MLVDS2_DUAL_GATE_RD_END 0x147a 1241#define MLVDS2_SECOND_RESET_CTL 0x147b 1242#define MLVDS2_DUAL_GATE_CTL_HI 0x147c 1243#define MLVDS2_DUAL_GATE_CTL_LO 0x147d 1244#define MLVDS2_RESET_CONFIG_HI 0x147e 1245#define MLVDS2_RESET_CONFIG_LO 0x147f 1246#define GAMMA_CNTL_PORT 0x1480 1247#define GAMMA_DATA_PORT 0x1481 1248#define GAMMA_ADDR_PORT 0x1482 1249#define GAMMA_VCOM_HSWITCH_ADDR 0x1483 1250#define RGB_BASE_ADDR 0x1485 1251#define RGB_COEFF_ADDR 0x1486 1252#define POL_CNTL_ADDR 0x1487 1253#define DITH_CNTL_ADDR 0x1488 1254#define GAMMA_PROBE_CTRL 0x1489 1255#define GAMMA_PROBE_COLOR_L 0x148a 1256#define GAMMA_PROBE_COLOR_H 0x148b 1257#define GAMMA_PROBE_HL_COLOR 0x148c 1258#define GAMMA_PROBE_POS_X 0x148d 1259#define GAMMA_PROBE_POS_Y 0x148e 1260#define STH1_HS_ADDR 0x1490 1261#define STH1_HE_ADDR 0x1491 1262#define STH1_VS_ADDR 0x1492 1263#define STH1_VE_ADDR 0x1493 1264#define STH2_HS_ADDR 0x1494 1265#define STH2_HE_ADDR 0x1495 1266#define STH2_VS_ADDR 0x1496 1267#define STH2_VE_ADDR 0x1497 1268#define OEH_HS_ADDR 0x1498 1269#define OEH_HE_ADDR 0x1499 1270#define OEH_VS_ADDR 0x149a 1271#define OEH_VE_ADDR 0x149b 1272#define VCOM_HSWITCH_ADDR 0x149c 1273#define VCOM_VS_ADDR 0x149d 1274#define VCOM_VE_ADDR 0x149e 1275#define CPV1_HS_ADDR 0x149f 1276#define CPV1_HE_ADDR 0x14a0 1277#define CPV1_VS_ADDR 0x14a1 1278#define CPV1_VE_ADDR 0x14a2 1279#define CPV2_HS_ADDR 0x14a3 1280#define CPV2_HE_ADDR 0x14a4 1281#define CPV2_VS_ADDR 0x14a5 1282#define CPV2_VE_ADDR 0x14a6 1283#define STV1_HS_ADDR 0x14a7 1284#define STV1_HE_ADDR 0x14a8 1285#define STV1_VS_ADDR 0x14a9 1286#define STV1_VE_ADDR 0x14aa 1287#define STV2_HS_ADDR 0x14ab 1288#define STV2_HE_ADDR 0x14ac 1289#define STV2_VS_ADDR 0x14ad 1290#define STV2_VE_ADDR 0x14ae 1291#define OEV1_HS_ADDR 0x14af 1292#define OEV1_HE_ADDR 0x14b0 1293#define OEV1_VS_ADDR 0x14b1 1294#define OEV1_VE_ADDR 0x14b2 1295#define OEV2_HS_ADDR 0x14b3 1296#define OEV2_HE_ADDR 0x14b4 1297#define OEV2_VS_ADDR 0x14b5 1298#define OEV2_VE_ADDR 0x14b6 1299#define OEV3_HS_ADDR 0x14b7 1300#define OEV3_HE_ADDR 0x14b8 1301#define OEV3_VS_ADDR 0x14b9 1302#define OEV3_VE_ADDR 0x14ba 1303#define LCD_PWR_ADDR 0x14bb 1304#define LCD_PWM0_LO_ADDR 0x14bc 1305#define LCD_PWM0_HI_ADDR 0x14bd 1306#define LCD_PWM1_LO_ADDR 0x14be 1307#define LCD_PWM1_HI_ADDR 0x14bf 1308#define INV_CNT_ADDR 0x14c0 1309#define TCON_MISC_SEL_ADDR 0x14c1 1310#define DUAL_PORT_CNTL_ADDR 0x14c2 1311#define MLVDS_CONTROL 0x14c3 1312#define MLVDS_RESET_PATTERN_HI 0x14c4 1313#define MLVDS_RESET_PATTERN_LO 0x14c5 1314#define MLVDS_RESET_PATTERN_EXT 0x14c6 1315#define MLVDS_CONFIG_HI 0x14c7 1316#define MLVDS_CONFIG_LO 0x14c8 1317#define TCON_DOUBLE_CTL 0x14c9 1318#define TCON_PATTERN_HI 0x14ca 1319#define TCON_PATTERN_LO 0x14cb 1320#define TCON_CONTROL_HI 0x14cc 1321#define TCON_CONTROL_LO 0x14cd 1322#define LVDS_BLANK_DATA_HI 0x14ce 1323#define LVDS_BLANK_DATA_LO 0x14cf 1324#define LVDS_PACK_CNTL_ADDR 0x14d0 1325#define DE_HS_ADDR 0x14d1 1326#define DE_HE_ADDR 0x14d2 1327#define DE_VS_ADDR 0x14d3 1328#define DE_VE_ADDR 0x14d4 1329#define HSYNC_HS_ADDR 0x14d5 1330#define HSYNC_HE_ADDR 0x14d6 1331#define HSYNC_VS_ADDR 0x14d7 1332#define HSYNC_VE_ADDR 0x14d8 1333#define VSYNC_HS_ADDR 0x14d9 1334#define VSYNC_HE_ADDR 0x14da 1335#define VSYNC_VS_ADDR 0x14db 1336#define VSYNC_VE_ADDR 0x14dc 1337#define LCD_MCU_CTL 0x14dd 1338#define LCD_MCU_DATA_0 0x14de 1339#define LCD_MCU_DATA_1 0x14df 1340#define LVDS_GEN_CNTL 0x14e0 1341#define LVDS_PHY_CNTL0 0x14e1 1342#define LVDS_PHY_CNTL1 0x14e2 1343#define LVDS_PHY_CNTL2 0x14e3 1344#define LVDS_PHY_CNTL3 0x14e4 1345#define LVDS_PHY_CNTL4 0x14e5 1346#define LVDS_PHY_CNTL5 0x14e6 1347#define LVDS_SRG_TEST 0x14e8 1348#define LVDS_BIST_MUX0 0x14e9 1349#define LVDS_BIST_MUX1 0x14ea 1350#define LVDS_BIST_FIXED0 0x14eb 1351#define LVDS_BIST_FIXED1 0x14ec 1352#define LVDS_BIST_CNTL0 0x14ed 1353#define LVDS_CLKB_CLKA 0x14ee 1354#define LVDS_PHY_CLK_CNTL 0x14ef 1355#define LVDS_SER_EN 0x14f0 1356#define LVDS_PHY_CNTL6 0x14f1 1357#define LVDS_PHY_CNTL7 0x14f2 1358#define LVDS_PHY_CNTL8 0x14f3 1359#define MLVDS_CLK_CTL0_HI 0x14f4 1360#define MLVDS_CLK_CTL0_LO 0x14f5 1361#define MLVDS_DUAL_GATE_WR_START 0x14f6 1362#define MLVDS_DUAL_GATE_WR_END 0x14f7 1363#define MLVDS_DUAL_GATE_RD_START 0x14f8 1364#define MLVDS_DUAL_GATE_RD_END 0x14f9 1365#define MLVDS_SECOND_RESET_CTL 0x14fa 1366#define MLVDS_DUAL_GATE_CTL_HI 0x14fb 1367#define MLVDS_DUAL_GATE_CTL_LO 0x14fc 1368#define MLVDS_RESET_CONFIG_HI 0x14fd 1369#define MLVDS_RESET_CONFIG_LO 0x14fe 1370#define VPU_OSD1_MMC_CTRL 0x2701 1371#define VPU_OSD2_MMC_CTRL 0x2702 1372#define VPU_VD1_MMC_CTRL 0x2703 1373#define VPU_VD2_MMC_CTRL 0x2704 1374#define VPU_DI_IF1_MMC_CTRL 0x2705 1375#define VPU_DI_MEM_MMC_CTRL 0x2706 1376#define VPU_DI_INP_MMC_CTRL 0x2707 1377#define VPU_DI_MTNRD_MMC_CTRL 0x2708 1378#define VPU_DI_CHAN2_MMC_CTRL 0x2709 1379#define VPU_DI_MTNWR_MMC_CTRL 0x270a 1380#define VPU_DI_NRWR_MMC_CTRL 0x270b 1381#define VPU_DI_DIWR_MMC_CTRL 0x270c 1382#define VPU_VDIN0_MMC_CTRL 0x270d 1383#define VPU_VDIN1_MMC_CTRL 0x270e 1384#define VPU_BT656_MMC_CTRL 0x270f 1385#define VPU_TVD3D_MMC_CTRL 0x2710 1386#define VPU_TVDVBI_MMC_CTRL 0x2711 1387#define VPU_TVDVBI_VSLATCH_ADDR 0x2712 1388#define VPU_TVDVBI_WRRSP_ADDR 0x2713 1389#define VPU_VDIN_PRE_ARB_CTRL 0x2714 1390#define VPU_VDISP_PRE_ARB_CTRL 0x2715 1391#define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 1392#define VPU_OSD3_MMC_CTRL 0x2717 1393#define VPU_OSD4_MMC_CTRL 0x2718 1394#define VPU_VD3_MMC_CTRL 0x2719 1395#define VPU_VIU_VENC_MUX_CTRL 0x271a 1396#define VIU1_SEL_VENC_MASK 0x3 1397#define VIU1_SEL_VENC_ENCL 0 1398#define VIU1_SEL_VENC_ENCI 1 1399#define VIU1_SEL_VENC_ENCP 2 1400#define VIU1_SEL_VENC_ENCT 3 1401#define VIU2_SEL_VENC_MASK 0xc 1402#define VIU2_SEL_VENC_ENCL 0 1403#define VIU2_SEL_VENC_ENCI (1 << 2) 1404#define VIU2_SEL_VENC_ENCP (2 << 2) 1405#define VIU2_SEL_VENC_ENCT (3 << 2) 1406#define VPU_HDMI_SETTING 0x271b 1407#define ENCI_INFO_READ 0x271c 1408#define ENCP_INFO_READ 0x271d 1409#define ENCT_INFO_READ 0x271e 1410#define ENCL_INFO_READ 0x271f 1411#define VPU_SW_RESET 0x2720 1412#define VPU_D2D3_MMC_CTRL 0x2721 1413#define VPU_CONT_MMC_CTRL 0x2722 1414#define VPU_CLK_GATE 0x2723 1415#define VPU_RDMA_MMC_CTRL 0x2724 1416#define VPU_MEM_PD_REG0 0x2725 1417#define VPU_MEM_PD_REG1 0x2726 1418#define VPU_HDMI_DATA_OVR 0x2727 1419#define VPU_PROT1_MMC_CTRL 0x2728 1420#define VPU_PROT2_MMC_CTRL 0x2729 1421#define VPU_PROT3_MMC_CTRL 0x272a 1422#define VPU_ARB4_V1_MMC_CTRL 0x272b 1423#define VPU_ARB4_V2_MMC_CTRL 0x272c 1424#define VPU_VPU_PWM_V0 0x2730 1425#define VPU_VPU_PWM_V1 0x2731 1426#define VPU_VPU_PWM_V2 0x2732 1427#define VPU_VPU_PWM_V3 0x2733 1428#define VPU_VPU_PWM_H0 0x2734 1429#define VPU_VPU_PWM_H1 0x2735 1430#define VPU_VPU_PWM_H2 0x2736 1431#define VPU_VPU_PWM_H3 0x2737 1432#define VPU_MISC_CTRL 0x2740 1433#define VPU_ISP_GCLK_CTRL0 0x2741 1434#define VPU_ISP_GCLK_CTRL1 0x2742 1435#define VPU_HDMI_FMT_CTRL 0x2743 1436#define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743 1437#define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744 1438#define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745 1439 1440#define VPU_PROT1_CLK_GATE 0x2750 1441#define VPU_PROT1_GEN_CNTL 0x2751 1442#define VPU_PROT1_X_START_END 0x2752 1443#define VPU_PROT1_Y_START_END 0x2753 1444#define VPU_PROT1_Y_LEN_STEP 0x2754 1445#define VPU_PROT1_RPT_LOOP 0x2755 1446#define VPU_PROT1_RPT_PAT 0x2756 1447#define VPU_PROT1_DDR 0x2757 1448#define VPU_PROT1_RBUF_ROOM 0x2758 1449#define VPU_PROT1_STAT_0 0x2759 1450#define VPU_PROT1_STAT_1 0x275a 1451#define VPU_PROT1_STAT_2 0x275b 1452#define VPU_PROT1_REQ_ONOFF 0x275c 1453#define VPU_PROT2_CLK_GATE 0x2760 1454#define VPU_PROT2_GEN_CNTL 0x2761 1455#define VPU_PROT2_X_START_END 0x2762 1456#define VPU_PROT2_Y_START_END 0x2763 1457#define VPU_PROT2_Y_LEN_STEP 0x2764 1458#define VPU_PROT2_RPT_LOOP 0x2765 1459#define VPU_PROT2_RPT_PAT 0x2766 1460#define VPU_PROT2_DDR 0x2767 1461#define VPU_PROT2_RBUF_ROOM 0x2768 1462#define VPU_PROT2_STAT_0 0x2769 1463#define VPU_PROT2_STAT_1 0x276a 1464#define VPU_PROT2_STAT_2 0x276b 1465#define VPU_PROT2_REQ_ONOFF 0x276c 1466#define VPU_PROT3_CLK_GATE 0x2770 1467#define VPU_PROT3_GEN_CNTL 0x2771 1468#define VPU_PROT3_X_START_END 0x2772 1469#define VPU_PROT3_Y_START_END 0x2773 1470#define VPU_PROT3_Y_LEN_STEP 0x2774 1471#define VPU_PROT3_RPT_LOOP 0x2775 1472#define VPU_PROT3_RPT_PAT 0x2776 1473#define VPU_PROT3_DDR 0x2777 1474#define VPU_PROT3_RBUF_ROOM 0x2778 1475#define VPU_PROT3_STAT_0 0x2779 1476#define VPU_PROT3_STAT_1 0x277a 1477#define VPU_PROT3_STAT_2 0x277b 1478#define VPU_PROT3_REQ_ONOFF 0x277c 1479#define VPU_RDARB_MODE_L1C1 0x2790 1480#define VPU_RDARB_MODE_L1C2 0x2799 1481#define VPU_RDARB_MODE_L2C1 0x279d 1482#define VPU_WRARB_MODE_L2C1 0x27a2 1483 1484/* osd super scale */ 1485#define OSDSR_HV_SIZEIN 0x3130 1486#define OSDSR_CTRL_MODE 0x3131 1487#define OSDSR_ABIC_HCOEF 0x3132 1488#define OSDSR_YBIC_HCOEF 0x3133 1489#define OSDSR_CBIC_HCOEF 0x3134 1490#define OSDSR_ABIC_VCOEF 0x3135 1491#define OSDSR_YBIC_VCOEF 0x3136 1492#define OSDSR_CBIC_VCOEF 0x3137 1493#define OSDSR_VAR_PARA 0x3138 1494#define OSDSR_CONST_PARA 0x3139 1495#define OSDSR_RKE_EXTWIN 0x313a 1496#define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b 1497#define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c 1498#define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d 1499#define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e 1500#define OSDSR_UK_BST_GAIN 0x313f 1501#define OSDSR_HVBLEND_TH 0x3140 1502#define OSDSR_DEMO_WIND_TB 0x3141 1503#define OSDSR_DEMO_WIND_LR 0x3142 1504#define OSDSR_INT_BLANK_NUM 0x3143 1505#define OSDSR_FRM_END_STAT 0x3144 1506#define OSDSR_ABIC_HCOEF0 0x3145 1507#define OSDSR_YBIC_HCOEF0 0x3146 1508#define OSDSR_CBIC_HCOEF0 0x3147 1509#define OSDSR_ABIC_VCOEF0 0x3148 1510#define OSDSR_YBIC_VCOEF0 0x3149 1511#define OSDSR_CBIC_VCOEF0 0x314a 1512 1513/* osd afbcd on gxtvbb */ 1514#define OSD1_AFBCD_ENABLE 0x31a0 1515#define OSD1_AFBCD_MODE 0x31a1 1516#define OSD1_AFBCD_SIZE_IN 0x31a2 1517#define OSD1_AFBCD_HDR_PTR 0x31a3 1518#define OSD1_AFBCD_FRAME_PTR 0x31a4 1519#define OSD1_AFBCD_CHROMA_PTR 0x31a5 1520#define OSD1_AFBCD_CONV_CTRL 0x31a6 1521#define OSD1_AFBCD_STATUS 0x31a8 1522#define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9 1523#define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa 1524#define VIU_MISC_CTRL1 0x1a07 1525 1526/* add for gxm and 962e dv core2 */ 1527#define DOLBY_CORE2A_SWAP_CTRL1 0x3434 1528#define DOLBY_CORE2A_SWAP_CTRL2 0x3435 1529 1530/* osd afbc on g12a */ 1531#define VPU_MAFBC_BLOCK_ID 0x3a00 1532#define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01 1533#define VPU_MAFBC_IRQ_CLEAR 0x3a02 1534#define VPU_MAFBC_IRQ_MASK 0x3a03 1535#define VPU_MAFBC_IRQ_STATUS 0x3a04 1536#define VPU_MAFBC_COMMAND 0x3a05 1537#define VPU_MAFBC_STATUS 0x3a06 1538#define VPU_MAFBC_SURFACE_CFG 0x3a07 1539 1540/* osd afbc on g12a */ 1541#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10 1542#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11 1543#define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12 1544#define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13 1545#define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14 1546#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15 1547#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16 1548#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17 1549#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18 1550#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19 1551#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a 1552#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b 1553#define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c 1554 1555#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30 1556#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31 1557#define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32 1558#define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33 1559#define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34 1560#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35 1561#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36 1562#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37 1563#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38 1564#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39 1565#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a 1566#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b 1567#define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c 1568 1569#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50 1570#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51 1571#define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52 1572#define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53 1573#define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54 1574#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55 1575#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56 1576#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57 1577#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58 1578#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59 1579#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a 1580#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b 1581#define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c 1582 1583#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70 1584#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71 1585#define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72 1586#define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73 1587#define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74 1588#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75 1589#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76 1590#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77 1591#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78 1592#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79 1593#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a 1594#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b 1595#define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c 1596 1597#define DOLBY_PATH_CTRL 0x1a0c 1598#define OSD_PATH_MISC_CTRL 0x1a0e 1599#define MALI_AFBCD_TOP_CTRL 0x1a0f 1600 1601#define VIU_OSD_BLEND_CTRL 0x39b0 1602#define VIU_OSD_BLEND_CTRL1 0x39c0 1603#define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1 1604#define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2 1605#define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3 1606#define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4 1607#define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5 1608#define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6 1609#define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7 1610#define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8 1611#define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9 1612#define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba 1613#define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb 1614#define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc 1615#define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf 1616 1617#define VPP_OUT_H_V_SIZE 0x1da5 1618 1619#define VPP_VD2_HDR_IN_SIZE 0x1df0 1620#define VPP_OSD1_IN_SIZE 0x1df1 1621#define VPP_GCLK_CTRL2 0x1df2 1622#define VD2_PPS_DUMMY_DATA 0x1df4 1623#define VPP_OSD1_BLD_H_SCOPE 0x1df5 1624#define VPP_OSD1_BLD_V_SCOPE 0x1df6 1625#define VPP_OSD2_BLD_H_SCOPE 0x1df7 1626#define VPP_OSD2_BLD_V_SCOPE 0x1df8 1627#define VPP_WRBAK_CTRL 0x1df9 1628#define VPP_SLEEP_CTRL 0x1dfa 1629#define VD1_BLEND_SRC_CTRL 0x1dfb 1630#define VD2_BLEND_SRC_CTRL 0x1dfc 1631#define OSD1_BLEND_SRC_CTRL 0x1dfd 1632#define OSD2_BLEND_SRC_CTRL 0x1dfe 1633 1634#define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968 1635#define VPP_POST_BLEND_DUMMY_ALPHA 0x3969 1636#define VPP_RDARB_MODE 0x3978 1637#define VPP_RDARB_REQEN_SLV 0x3979 1638#define VPU_RDARB_MODE_L2C1 0x279d 1639 1640#endif /* __MESON_REGISTERS_H */ 1641