1
2
3
4
5#if !defined(_DPU_TRACE_H_) || defined(TRACE_HEADER_MULTI_READ)
6#define _DPU_TRACE_H_
7
8#include <linux/stringify.h>
9#include <linux/types.h>
10#include <linux/tracepoint.h>
11
12#include <drm/drm_rect.h>
13#include "dpu_crtc.h"
14#include "dpu_encoder_phys.h"
15#include "dpu_hw_mdss.h"
16#include "dpu_hw_vbif.h"
17#include "dpu_plane.h"
18
19#undef TRACE_SYSTEM
20#define TRACE_SYSTEM dpu
21#undef TRACE_INCLUDE_FILE
22#define TRACE_INCLUDE_FILE dpu_trace
23
24TRACE_EVENT(dpu_perf_set_qos_luts,
25 TP_PROTO(u32 pnum, u32 fmt, bool rt, u32 fl,
26 u32 lut, u32 lut_usage),
27 TP_ARGS(pnum, fmt, rt, fl, lut, lut_usage),
28 TP_STRUCT__entry(
29 __field(u32, pnum)
30 __field(u32, fmt)
31 __field(bool, rt)
32 __field(u32, fl)
33 __field(u64, lut)
34 __field(u32, lut_usage)
35 ),
36 TP_fast_assign(
37 __entry->pnum = pnum;
38 __entry->fmt = fmt;
39 __entry->rt = rt;
40 __entry->fl = fl;
41 __entry->lut = lut;
42 __entry->lut_usage = lut_usage;
43 ),
44 TP_printk("pnum=%d fmt=%x rt=%d fl=%d lut=0x%llx lut_usage=%d",
45 __entry->pnum, __entry->fmt,
46 __entry->rt, __entry->fl,
47 __entry->lut, __entry->lut_usage)
48);
49
50TRACE_EVENT(dpu_perf_set_danger_luts,
51 TP_PROTO(u32 pnum, u32 fmt, u32 mode, u32 danger_lut,
52 u32 safe_lut),
53 TP_ARGS(pnum, fmt, mode, danger_lut, safe_lut),
54 TP_STRUCT__entry(
55 __field(u32, pnum)
56 __field(u32, fmt)
57 __field(u32, mode)
58 __field(u32, danger_lut)
59 __field(u32, safe_lut)
60 ),
61 TP_fast_assign(
62 __entry->pnum = pnum;
63 __entry->fmt = fmt;
64 __entry->mode = mode;
65 __entry->danger_lut = danger_lut;
66 __entry->safe_lut = safe_lut;
67 ),
68 TP_printk("pnum=%d fmt=%x mode=%d luts[0x%x, 0x%x]",
69 __entry->pnum, __entry->fmt,
70 __entry->mode, __entry->danger_lut,
71 __entry->safe_lut)
72);
73
74TRACE_EVENT(dpu_perf_set_ot,
75 TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx),
76 TP_ARGS(pnum, xin_id, rd_lim, vbif_idx),
77 TP_STRUCT__entry(
78 __field(u32, pnum)
79 __field(u32, xin_id)
80 __field(u32, rd_lim)
81 __field(u32, vbif_idx)
82 ),
83 TP_fast_assign(
84 __entry->pnum = pnum;
85 __entry->xin_id = xin_id;
86 __entry->rd_lim = rd_lim;
87 __entry->vbif_idx = vbif_idx;
88 ),
89 TP_printk("pnum:%d xin_id:%d ot:%d vbif:%d",
90 __entry->pnum, __entry->xin_id, __entry->rd_lim,
91 __entry->vbif_idx)
92)
93
94TRACE_EVENT(dpu_cmd_release_bw,
95 TP_PROTO(u32 crtc_id),
96 TP_ARGS(crtc_id),
97 TP_STRUCT__entry(
98 __field(u32, crtc_id)
99 ),
100 TP_fast_assign(
101 __entry->crtc_id = crtc_id;
102 ),
103 TP_printk("crtc:%d", __entry->crtc_id)
104);
105
106TRACE_EVENT(tracing_mark_write,
107 TP_PROTO(int pid, const char *name, bool trace_begin),
108 TP_ARGS(pid, name, trace_begin),
109 TP_STRUCT__entry(
110 __field(int, pid)
111 __string(trace_name, name)
112 __field(bool, trace_begin)
113 ),
114 TP_fast_assign(
115 __entry->pid = pid;
116 __assign_str(trace_name, name);
117 __entry->trace_begin = trace_begin;
118 ),
119 TP_printk("%s|%d|%s", __entry->trace_begin ? "B" : "E",
120 __entry->pid, __get_str(trace_name))
121)
122
123TRACE_EVENT(dpu_trace_counter,
124 TP_PROTO(int pid, char *name, int value),
125 TP_ARGS(pid, name, value),
126 TP_STRUCT__entry(
127 __field(int, pid)
128 __string(counter_name, name)
129 __field(int, value)
130 ),
131 TP_fast_assign(
132 __entry->pid = current->tgid;
133 __assign_str(counter_name, name);
134 __entry->value = value;
135 ),
136 TP_printk("%d|%s|%d", __entry->pid,
137 __get_str(counter_name), __entry->value)
138)
139
140TRACE_EVENT(dpu_perf_crtc_update,
141 TP_PROTO(u32 crtc, u64 bw_ctl_mnoc, u64 bw_ctl_llcc,
142 u64 bw_ctl_ebi, u32 core_clk_rate,
143 bool stop_req, u32 update_bus, u32 update_clk),
144 TP_ARGS(crtc, bw_ctl_mnoc, bw_ctl_llcc, bw_ctl_ebi, core_clk_rate,
145 stop_req, update_bus, update_clk),
146 TP_STRUCT__entry(
147 __field(u32, crtc)
148 __field(u64, bw_ctl_mnoc)
149 __field(u64, bw_ctl_llcc)
150 __field(u64, bw_ctl_ebi)
151 __field(u32, core_clk_rate)
152 __field(bool, stop_req)
153 __field(u32, update_bus)
154 __field(u32, update_clk)
155 ),
156 TP_fast_assign(
157 __entry->crtc = crtc;
158 __entry->bw_ctl_mnoc = bw_ctl_mnoc;
159 __entry->bw_ctl_llcc = bw_ctl_llcc;
160 __entry->bw_ctl_ebi = bw_ctl_ebi;
161 __entry->core_clk_rate = core_clk_rate;
162 __entry->stop_req = stop_req;
163 __entry->update_bus = update_bus;
164 __entry->update_clk = update_clk;
165 ),
166 TP_printk(
167 "crtc=%d bw_mnoc=%llu bw_llcc=%llu bw_ebi=%llu clk_rate=%u stop_req=%d u_bus=%d u_clk=%d",
168 __entry->crtc,
169 __entry->bw_ctl_mnoc,
170 __entry->bw_ctl_llcc,
171 __entry->bw_ctl_ebi,
172 __entry->core_clk_rate,
173 __entry->stop_req,
174 __entry->update_bus,
175 __entry->update_clk)
176);
177
178DECLARE_EVENT_CLASS(dpu_enc_irq_template,
179 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
180 int irq_idx),
181 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx),
182 TP_STRUCT__entry(
183 __field( uint32_t, drm_id )
184 __field( enum dpu_intr_idx, intr_idx )
185 __field( int, hw_idx )
186 __field( int, irq_idx )
187 ),
188 TP_fast_assign(
189 __entry->drm_id = drm_id;
190 __entry->intr_idx = intr_idx;
191 __entry->hw_idx = hw_idx;
192 __entry->irq_idx = irq_idx;
193 ),
194 TP_printk("id=%u, intr=%d, hw=%d, irq=%d",
195 __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
196 __entry->irq_idx)
197);
198DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_register_success,
199 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
200 int irq_idx),
201 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
202);
203DEFINE_EVENT(dpu_enc_irq_template, dpu_enc_irq_unregister_success,
204 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
205 int irq_idx),
206 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx)
207);
208
209TRACE_EVENT(dpu_enc_irq_wait_success,
210 TP_PROTO(uint32_t drm_id, enum dpu_intr_idx intr_idx, int hw_idx,
211 int irq_idx, enum dpu_pingpong pp_idx, int atomic_cnt),
212 TP_ARGS(drm_id, intr_idx, hw_idx, irq_idx, pp_idx, atomic_cnt),
213 TP_STRUCT__entry(
214 __field( uint32_t, drm_id )
215 __field( enum dpu_intr_idx, intr_idx )
216 __field( int, hw_idx )
217 __field( int, irq_idx )
218 __field( enum dpu_pingpong, pp_idx )
219 __field( int, atomic_cnt )
220 ),
221 TP_fast_assign(
222 __entry->drm_id = drm_id;
223 __entry->intr_idx = intr_idx;
224 __entry->hw_idx = hw_idx;
225 __entry->irq_idx = irq_idx;
226 __entry->pp_idx = pp_idx;
227 __entry->atomic_cnt = atomic_cnt;
228 ),
229 TP_printk("id=%u, intr=%d, hw=%d, irq=%d, pp=%d, atomic_cnt=%d",
230 __entry->drm_id, __entry->intr_idx, __entry->hw_idx,
231 __entry->irq_idx, __entry->pp_idx, __entry->atomic_cnt)
232);
233
234DECLARE_EVENT_CLASS(dpu_drm_obj_template,
235 TP_PROTO(uint32_t drm_id),
236 TP_ARGS(drm_id),
237 TP_STRUCT__entry(
238 __field( uint32_t, drm_id )
239 ),
240 TP_fast_assign(
241 __entry->drm_id = drm_id;
242 ),
243 TP_printk("id=%u", __entry->drm_id)
244);
245DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_atomic_check,
246 TP_PROTO(uint32_t drm_id),
247 TP_ARGS(drm_id)
248);
249DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_mode_set,
250 TP_PROTO(uint32_t drm_id),
251 TP_ARGS(drm_id)
252);
253DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_disable,
254 TP_PROTO(uint32_t drm_id),
255 TP_ARGS(drm_id)
256);
257DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_kickoff,
258 TP_PROTO(uint32_t drm_id),
259 TP_ARGS(drm_id)
260);
261DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff,
262 TP_PROTO(uint32_t drm_id),
263 TP_ARGS(drm_id)
264);
265DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_prepare_kickoff_reset,
266 TP_PROTO(uint32_t drm_id),
267 TP_ARGS(drm_id)
268);
269DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_flip,
270 TP_PROTO(uint32_t drm_id),
271 TP_ARGS(drm_id)
272);
273DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_vblank_cb,
274 TP_PROTO(uint32_t drm_id),
275 TP_ARGS(drm_id)
276);
277DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_complete_commit,
278 TP_PROTO(uint32_t drm_id),
279 TP_ARGS(drm_id)
280);
281DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_enc_enable,
282 TP_PROTO(uint32_t drm_id),
283 TP_ARGS(drm_id)
284);
285DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_commit,
286 TP_PROTO(uint32_t drm_id),
287 TP_ARGS(drm_id)
288);
289DEFINE_EVENT(dpu_drm_obj_template, dpu_kms_wait_for_commit_done,
290 TP_PROTO(uint32_t drm_id),
291 TP_ARGS(drm_id)
292);
293DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume,
294 TP_PROTO(uint32_t drm_id),
295 TP_ARGS(drm_id)
296);
297
298TRACE_EVENT(dpu_enc_enable,
299 TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay),
300 TP_ARGS(drm_id, hdisplay, vdisplay),
301 TP_STRUCT__entry(
302 __field( uint32_t, drm_id )
303 __field( int, hdisplay )
304 __field( int, vdisplay )
305 ),
306 TP_fast_assign(
307 __entry->drm_id = drm_id;
308 __entry->hdisplay = hdisplay;
309 __entry->vdisplay = vdisplay;
310 ),
311 TP_printk("id=%u, mode=%dx%d",
312 __entry->drm_id, __entry->hdisplay, __entry->vdisplay)
313);
314
315DECLARE_EVENT_CLASS(dpu_enc_keyval_template,
316 TP_PROTO(uint32_t drm_id, int val),
317 TP_ARGS(drm_id, val),
318 TP_STRUCT__entry(
319 __field( uint32_t, drm_id )
320 __field( int, val )
321 ),
322 TP_fast_assign(
323 __entry->drm_id = drm_id;
324 __entry->val = val;
325 ),
326 TP_printk("id=%u, val=%d", __entry->drm_id, __entry->val)
327);
328DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_underrun_cb,
329 TP_PROTO(uint32_t drm_id, int count),
330 TP_ARGS(drm_id, count)
331);
332DEFINE_EVENT(dpu_enc_keyval_template, dpu_enc_trigger_start,
333 TP_PROTO(uint32_t drm_id, int ctl_idx),
334 TP_ARGS(drm_id, ctl_idx)
335);
336
337TRACE_EVENT(dpu_enc_atomic_check_flags,
338 TP_PROTO(uint32_t drm_id, unsigned int flags, int private_flags),
339 TP_ARGS(drm_id, flags, private_flags),
340 TP_STRUCT__entry(
341 __field( uint32_t, drm_id )
342 __field( unsigned int, flags )
343 __field( int, private_flags )
344 ),
345 TP_fast_assign(
346 __entry->drm_id = drm_id;
347 __entry->flags = flags;
348 __entry->private_flags = private_flags;
349 ),
350 TP_printk("id=%u, flags=%u, private_flags=%d",
351 __entry->drm_id, __entry->flags, __entry->private_flags)
352);
353
354DECLARE_EVENT_CLASS(dpu_enc_id_enable_template,
355 TP_PROTO(uint32_t drm_id, bool enable),
356 TP_ARGS(drm_id, enable),
357 TP_STRUCT__entry(
358 __field( uint32_t, drm_id )
359 __field( bool, enable )
360 ),
361 TP_fast_assign(
362 __entry->drm_id = drm_id;
363 __entry->enable = enable;
364 ),
365 TP_printk("id=%u, enable=%s",
366 __entry->drm_id, __entry->enable ? "true" : "false")
367);
368DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper,
369 TP_PROTO(uint32_t drm_id, bool enable),
370 TP_ARGS(drm_id, enable)
371);
372DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb,
373 TP_PROTO(uint32_t drm_id, bool enable),
374 TP_ARGS(drm_id, enable)
375);
376DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_frame_event_cb,
377 TP_PROTO(uint32_t drm_id, bool enable),
378 TP_ARGS(drm_id, enable)
379);
380DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_phys_cmd_connect_te,
381 TP_PROTO(uint32_t drm_id, bool enable),
382 TP_ARGS(drm_id, enable)
383);
384
385TRACE_EVENT(dpu_enc_rc,
386 TP_PROTO(uint32_t drm_id, u32 sw_event, bool idle_pc_supported,
387 int rc_state, const char *stage),
388 TP_ARGS(drm_id, sw_event, idle_pc_supported, rc_state, stage),
389 TP_STRUCT__entry(
390 __field( uint32_t, drm_id )
391 __field( u32, sw_event )
392 __field( bool, idle_pc_supported )
393 __field( int, rc_state )
394 __string( stage_str, stage )
395 ),
396 TP_fast_assign(
397 __entry->drm_id = drm_id;
398 __entry->sw_event = sw_event;
399 __entry->idle_pc_supported = idle_pc_supported;
400 __entry->rc_state = rc_state;
401 __assign_str(stage_str, stage);
402 ),
403 TP_printk("%s: id:%u, sw_event:%d, idle_pc_supported:%s, rc_state:%d\n",
404 __get_str(stage_str), __entry->drm_id, __entry->sw_event,
405 __entry->idle_pc_supported ? "true" : "false",
406 __entry->rc_state)
407);
408
409TRACE_EVENT(dpu_enc_frame_done_cb_not_busy,
410 TP_PROTO(uint32_t drm_id, u32 event, enum dpu_intf intf_idx),
411 TP_ARGS(drm_id, event, intf_idx),
412 TP_STRUCT__entry(
413 __field( uint32_t, drm_id )
414 __field( u32, event )
415 __field( enum dpu_intf, intf_idx )
416 ),
417 TP_fast_assign(
418 __entry->drm_id = drm_id;
419 __entry->event = event;
420 __entry->intf_idx = intf_idx;
421 ),
422 TP_printk("id=%u, event=%u, intf=%d", __entry->drm_id, __entry->event,
423 __entry->intf_idx)
424);
425
426TRACE_EVENT(dpu_enc_frame_done_cb,
427 TP_PROTO(uint32_t drm_id, unsigned int idx,
428 unsigned long frame_busy_mask),
429 TP_ARGS(drm_id, idx, frame_busy_mask),
430 TP_STRUCT__entry(
431 __field( uint32_t, drm_id )
432 __field( unsigned int, idx )
433 __field( unsigned long, frame_busy_mask )
434 ),
435 TP_fast_assign(
436 __entry->drm_id = drm_id;
437 __entry->idx = idx;
438 __entry->frame_busy_mask = frame_busy_mask;
439 ),
440 TP_printk("id=%u, idx=%u, frame_busy_mask=%lx", __entry->drm_id,
441 __entry->idx, __entry->frame_busy_mask)
442);
443
444TRACE_EVENT(dpu_enc_trigger_flush,
445 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx,
446 int pending_kickoff_cnt, int ctl_idx, u32 extra_flush_bits,
447 u32 pending_flush_ret),
448 TP_ARGS(drm_id, intf_idx, pending_kickoff_cnt, ctl_idx,
449 extra_flush_bits, pending_flush_ret),
450 TP_STRUCT__entry(
451 __field( uint32_t, drm_id )
452 __field( enum dpu_intf, intf_idx )
453 __field( int, pending_kickoff_cnt )
454 __field( int, ctl_idx )
455 __field( u32, extra_flush_bits )
456 __field( u32, pending_flush_ret )
457 ),
458 TP_fast_assign(
459 __entry->drm_id = drm_id;
460 __entry->intf_idx = intf_idx;
461 __entry->pending_kickoff_cnt = pending_kickoff_cnt;
462 __entry->ctl_idx = ctl_idx;
463 __entry->extra_flush_bits = extra_flush_bits;
464 __entry->pending_flush_ret = pending_flush_ret;
465 ),
466 TP_printk("id=%u, intf_idx=%d, pending_kickoff_cnt=%d ctl_idx=%d "
467 "extra_flush_bits=0x%x pending_flush_ret=0x%x",
468 __entry->drm_id, __entry->intf_idx,
469 __entry->pending_kickoff_cnt, __entry->ctl_idx,
470 __entry->extra_flush_bits, __entry->pending_flush_ret)
471);
472
473DECLARE_EVENT_CLASS(dpu_enc_ktime_template,
474 TP_PROTO(uint32_t drm_id, ktime_t time),
475 TP_ARGS(drm_id, time),
476 TP_STRUCT__entry(
477 __field( uint32_t, drm_id )
478 __field( ktime_t, time )
479 ),
480 TP_fast_assign(
481 __entry->drm_id = drm_id;
482 __entry->time = time;
483 ),
484 TP_printk("id=%u, time=%lld", __entry->drm_id,
485 ktime_to_ms(__entry->time))
486);
487DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_vsync_event_work,
488 TP_PROTO(uint32_t drm_id, ktime_t time),
489 TP_ARGS(drm_id, time)
490);
491DEFINE_EVENT(dpu_enc_ktime_template, dpu_enc_early_kickoff,
492 TP_PROTO(uint32_t drm_id, ktime_t time),
493 TP_ARGS(drm_id, time)
494);
495
496DECLARE_EVENT_CLASS(dpu_id_event_template,
497 TP_PROTO(uint32_t drm_id, u32 event),
498 TP_ARGS(drm_id, event),
499 TP_STRUCT__entry(
500 __field( uint32_t, drm_id )
501 __field( u32, event )
502 ),
503 TP_fast_assign(
504 __entry->drm_id = drm_id;
505 __entry->event = event;
506 ),
507 TP_printk("id=%u, event=%u", __entry->drm_id, __entry->event)
508);
509DEFINE_EVENT(dpu_id_event_template, dpu_enc_frame_done_timeout,
510 TP_PROTO(uint32_t drm_id, u32 event),
511 TP_ARGS(drm_id, event)
512);
513DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_cb,
514 TP_PROTO(uint32_t drm_id, u32 event),
515 TP_ARGS(drm_id, event)
516);
517DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_done,
518 TP_PROTO(uint32_t drm_id, u32 event),
519 TP_ARGS(drm_id, event)
520);
521DEFINE_EVENT(dpu_id_event_template, dpu_crtc_frame_event_more_pending,
522 TP_PROTO(uint32_t drm_id, u32 event),
523 TP_ARGS(drm_id, event)
524);
525
526TRACE_EVENT(dpu_enc_wait_event_timeout,
527 TP_PROTO(uint32_t drm_id, int32_t hw_id, int rc, s64 time,
528 s64 expected_time, int atomic_cnt),
529 TP_ARGS(drm_id, hw_id, rc, time, expected_time, atomic_cnt),
530 TP_STRUCT__entry(
531 __field( uint32_t, drm_id )
532 __field( int32_t, hw_id )
533 __field( int, rc )
534 __field( s64, time )
535 __field( s64, expected_time )
536 __field( int, atomic_cnt )
537 ),
538 TP_fast_assign(
539 __entry->drm_id = drm_id;
540 __entry->hw_id = hw_id;
541 __entry->rc = rc;
542 __entry->time = time;
543 __entry->expected_time = expected_time;
544 __entry->atomic_cnt = atomic_cnt;
545 ),
546 TP_printk("id=%u, hw_id=%d, rc=%d, time=%lld, expected=%lld cnt=%d",
547 __entry->drm_id, __entry->hw_id, __entry->rc, __entry->time,
548 __entry->expected_time, __entry->atomic_cnt)
549);
550
551TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl,
552 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable,
553 int refcnt),
554 TP_ARGS(drm_id, pp, enable, refcnt),
555 TP_STRUCT__entry(
556 __field( uint32_t, drm_id )
557 __field( enum dpu_pingpong, pp )
558 __field( bool, enable )
559 __field( int, refcnt )
560 ),
561 TP_fast_assign(
562 __entry->drm_id = drm_id;
563 __entry->pp = pp;
564 __entry->enable = enable;
565 __entry->refcnt = refcnt;
566 ),
567 TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id,
568 __entry->pp, __entry->enable ? "true" : "false",
569 __entry->refcnt)
570);
571
572TRACE_EVENT(dpu_enc_phys_cmd_pp_tx_done,
573 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int new_count,
574 u32 event),
575 TP_ARGS(drm_id, pp, new_count, event),
576 TP_STRUCT__entry(
577 __field( uint32_t, drm_id )
578 __field( enum dpu_pingpong, pp )
579 __field( int, new_count )
580 __field( u32, event )
581 ),
582 TP_fast_assign(
583 __entry->drm_id = drm_id;
584 __entry->pp = pp;
585 __entry->new_count = new_count;
586 __entry->event = event;
587 ),
588 TP_printk("id=%u, pp=%d, new_count=%d, event=%u", __entry->drm_id,
589 __entry->pp, __entry->new_count, __entry->event)
590);
591
592TRACE_EVENT(dpu_enc_phys_cmd_pdone_timeout,
593 TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int timeout_count,
594 int kickoff_count, u32 event),
595 TP_ARGS(drm_id, pp, timeout_count, kickoff_count, event),
596 TP_STRUCT__entry(
597 __field( uint32_t, drm_id )
598 __field( enum dpu_pingpong, pp )
599 __field( int, timeout_count )
600 __field( int, kickoff_count )
601 __field( u32, event )
602 ),
603 TP_fast_assign(
604 __entry->drm_id = drm_id;
605 __entry->pp = pp;
606 __entry->timeout_count = timeout_count;
607 __entry->kickoff_count = kickoff_count;
608 __entry->event = event;
609 ),
610 TP_printk("id=%u, pp=%d, timeout_count=%d, kickoff_count=%d, event=%u",
611 __entry->drm_id, __entry->pp, __entry->timeout_count,
612 __entry->kickoff_count, __entry->event)
613);
614
615TRACE_EVENT(dpu_enc_phys_vid_post_kickoff,
616 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx),
617 TP_ARGS(drm_id, intf_idx),
618 TP_STRUCT__entry(
619 __field( uint32_t, drm_id )
620 __field( enum dpu_intf, intf_idx )
621 ),
622 TP_fast_assign(
623 __entry->drm_id = drm_id;
624 __entry->intf_idx = intf_idx;
625 ),
626 TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx)
627);
628
629TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl,
630 TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable,
631 int refcnt),
632 TP_ARGS(drm_id, intf_idx, enable, refcnt),
633 TP_STRUCT__entry(
634 __field( uint32_t, drm_id )
635 __field( enum dpu_intf, intf_idx )
636 __field( bool, enable )
637 __field( int, refcnt )
638 ),
639 TP_fast_assign(
640 __entry->drm_id = drm_id;
641 __entry->intf_idx = intf_idx;
642 __entry->enable = enable;
643 __entry->refcnt = refcnt;
644 ),
645 TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id,
646 __entry->intf_idx, __entry->enable ? "true" : "false",
647 __entry->drm_id)
648);
649
650TRACE_EVENT(dpu_crtc_setup_mixer,
651 TP_PROTO(uint32_t crtc_id, uint32_t plane_id,
652 struct drm_plane_state *state, struct dpu_plane_state *pstate,
653 uint32_t stage_idx, enum dpu_sspp sspp, uint32_t pixel_format,
654 uint64_t modifier),
655 TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
656 pixel_format, modifier),
657 TP_STRUCT__entry(
658 __field( uint32_t, crtc_id )
659 __field( uint32_t, plane_id )
660 __field( uint32_t, fb_id )
661 __field_struct( struct drm_rect, src_rect )
662 __field_struct( struct drm_rect, dst_rect )
663 __field( uint32_t, stage_idx )
664 __field( enum dpu_stage, stage )
665 __field( enum dpu_sspp, sspp )
666 __field( uint32_t, multirect_idx )
667 __field( uint32_t, multirect_mode )
668 __field( uint32_t, pixel_format )
669 __field( uint64_t, modifier )
670 ),
671 TP_fast_assign(
672 __entry->crtc_id = crtc_id;
673 __entry->plane_id = plane_id;
674 __entry->fb_id = state ? state->fb->base.id : 0;
675 __entry->src_rect = drm_plane_state_src(state);
676 __entry->dst_rect = drm_plane_state_dest(state);
677 __entry->stage_idx = stage_idx;
678 __entry->stage = pstate->stage;
679 __entry->sspp = sspp;
680 __entry->multirect_idx = pstate->multirect_index;
681 __entry->multirect_mode = pstate->multirect_mode;
682 __entry->pixel_format = pixel_format;
683 __entry->modifier = modifier;
684 ),
685 TP_printk("crtc_id:%u plane_id:%u fb_id:%u src:" DRM_RECT_FP_FMT
686 " dst:" DRM_RECT_FMT " stage_idx:%u stage:%d, sspp:%d "
687 "multirect_index:%d multirect_mode:%u pix_format:%u "
688 "modifier:%llu",
689 __entry->crtc_id, __entry->plane_id, __entry->fb_id,
690 DRM_RECT_FP_ARG(&__entry->src_rect),
691 DRM_RECT_ARG(&__entry->dst_rect),
692 __entry->stage_idx, __entry->stage, __entry->sspp,
693 __entry->multirect_idx, __entry->multirect_mode,
694 __entry->pixel_format, __entry->modifier)
695);
696
697TRACE_EVENT(dpu_crtc_setup_lm_bounds,
698 TP_PROTO(uint32_t drm_id, int mixer, struct drm_rect *bounds),
699 TP_ARGS(drm_id, mixer, bounds),
700 TP_STRUCT__entry(
701 __field( uint32_t, drm_id )
702 __field( int, mixer )
703 __field_struct( struct drm_rect, bounds )
704 ),
705 TP_fast_assign(
706 __entry->drm_id = drm_id;
707 __entry->mixer = mixer;
708 __entry->bounds = *bounds;
709 ),
710 TP_printk("id:%u mixer:%d bounds:" DRM_RECT_FMT, __entry->drm_id,
711 __entry->mixer, DRM_RECT_ARG(&__entry->bounds))
712);
713
714TRACE_EVENT(dpu_crtc_vblank_enable,
715 TP_PROTO(uint32_t drm_id, uint32_t enc_id, bool enable,
716 struct dpu_crtc *crtc),
717 TP_ARGS(drm_id, enc_id, enable, crtc),
718 TP_STRUCT__entry(
719 __field( uint32_t, drm_id )
720 __field( uint32_t, enc_id )
721 __field( bool, enable )
722 __field( bool, enabled )
723 ),
724 TP_fast_assign(
725 __entry->drm_id = drm_id;
726 __entry->enc_id = enc_id;
727 __entry->enable = enable;
728 __entry->enabled = crtc->enabled;
729 ),
730 TP_printk("id:%u encoder:%u enable:%s state{enabled:%s}",
731 __entry->drm_id, __entry->enc_id,
732 __entry->enable ? "true" : "false",
733 __entry->enabled ? "true" : "false")
734);
735
736DECLARE_EVENT_CLASS(dpu_crtc_enable_template,
737 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
738 TP_ARGS(drm_id, enable, crtc),
739 TP_STRUCT__entry(
740 __field( uint32_t, drm_id )
741 __field( bool, enable )
742 __field( bool, enabled )
743 ),
744 TP_fast_assign(
745 __entry->drm_id = drm_id;
746 __entry->enable = enable;
747 __entry->enabled = crtc->enabled;
748 ),
749 TP_printk("id:%u enable:%s state{enabled:%s}",
750 __entry->drm_id, __entry->enable ? "true" : "false",
751 __entry->enabled ? "true" : "false")
752);
753DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_enable,
754 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
755 TP_ARGS(drm_id, enable, crtc)
756);
757DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_disable,
758 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
759 TP_ARGS(drm_id, enable, crtc)
760);
761DEFINE_EVENT(dpu_crtc_enable_template, dpu_crtc_vblank,
762 TP_PROTO(uint32_t drm_id, bool enable, struct dpu_crtc *crtc),
763 TP_ARGS(drm_id, enable, crtc)
764);
765
766TRACE_EVENT(dpu_crtc_disable_frame_pending,
767 TP_PROTO(uint32_t drm_id, int frame_pending),
768 TP_ARGS(drm_id, frame_pending),
769 TP_STRUCT__entry(
770 __field( uint32_t, drm_id )
771 __field( int, frame_pending )
772 ),
773 TP_fast_assign(
774 __entry->drm_id = drm_id;
775 __entry->frame_pending = frame_pending;
776 ),
777 TP_printk("id:%u frame_pending:%d", __entry->drm_id,
778 __entry->frame_pending)
779);
780
781TRACE_EVENT(dpu_plane_set_scanout,
782 TP_PROTO(enum dpu_sspp index, struct dpu_hw_fmt_layout *layout,
783 enum dpu_sspp_multirect_index multirect_index),
784 TP_ARGS(index, layout, multirect_index),
785 TP_STRUCT__entry(
786 __field( enum dpu_sspp, index )
787 __field_struct( struct dpu_hw_fmt_layout, layout )
788 __field( enum dpu_sspp_multirect_index, multirect_index)
789 ),
790 TP_fast_assign(
791 __entry->index = index;
792 __entry->layout = *layout;
793 __entry->multirect_index = multirect_index;
794 ),
795 TP_printk("index:%d layout:{%ux%u @ [%u/%u, %u/%u, %u/%u, %u/%u]} "
796 "multirect_index:%d", __entry->index, __entry->layout.width,
797 __entry->layout.height, __entry->layout.plane_addr[0],
798 __entry->layout.plane_size[0],
799 __entry->layout.plane_addr[1],
800 __entry->layout.plane_size[1],
801 __entry->layout.plane_addr[2],
802 __entry->layout.plane_size[2],
803 __entry->layout.plane_addr[3],
804 __entry->layout.plane_size[3], __entry->multirect_index)
805);
806
807TRACE_EVENT(dpu_plane_disable,
808 TP_PROTO(uint32_t drm_id, bool is_virtual, uint32_t multirect_mode),
809 TP_ARGS(drm_id, is_virtual, multirect_mode),
810 TP_STRUCT__entry(
811 __field( uint32_t, drm_id )
812 __field( bool, is_virtual )
813 __field( uint32_t, multirect_mode )
814 ),
815 TP_fast_assign(
816 __entry->drm_id = drm_id;
817 __entry->is_virtual = is_virtual;
818 __entry->multirect_mode = multirect_mode;
819 ),
820 TP_printk("id:%u is_virtual:%s multirect_mode:%u", __entry->drm_id,
821 __entry->is_virtual ? "true" : "false",
822 __entry->multirect_mode)
823);
824
825DECLARE_EVENT_CLASS(dpu_rm_iter_template,
826 TP_PROTO(uint32_t id, uint32_t enc_id),
827 TP_ARGS(id, enc_id),
828 TP_STRUCT__entry(
829 __field( uint32_t, id )
830 __field( uint32_t, enc_id )
831 ),
832 TP_fast_assign(
833 __entry->id = id;
834 __entry->enc_id = enc_id;
835 ),
836 TP_printk("id:%d enc_id:%u", __entry->id, __entry->enc_id)
837);
838DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_intf,
839 TP_PROTO(uint32_t id, uint32_t enc_id),
840 TP_ARGS(id, enc_id)
841);
842DEFINE_EVENT(dpu_rm_iter_template, dpu_rm_reserve_ctls,
843 TP_PROTO(uint32_t id, uint32_t enc_id),
844 TP_ARGS(id, enc_id)
845);
846
847TRACE_EVENT(dpu_rm_reserve_lms,
848 TP_PROTO(uint32_t id, uint32_t enc_id, uint32_t pp_id),
849 TP_ARGS(id, enc_id, pp_id),
850 TP_STRUCT__entry(
851 __field( uint32_t, id )
852 __field( uint32_t, enc_id )
853 __field( uint32_t, pp_id )
854 ),
855 TP_fast_assign(
856 __entry->id = id;
857 __entry->enc_id = enc_id;
858 __entry->pp_id = pp_id;
859 ),
860 TP_printk("id:%d enc_id:%u pp_id:%u", __entry->id,
861 __entry->enc_id, __entry->pp_id)
862);
863
864TRACE_EVENT(dpu_vbif_wait_xin_halt_fail,
865 TP_PROTO(enum dpu_vbif index, u32 xin_id),
866 TP_ARGS(index, xin_id),
867 TP_STRUCT__entry(
868 __field( enum dpu_vbif, index )
869 __field( u32, xin_id )
870 ),
871 TP_fast_assign(
872 __entry->index = index;
873 __entry->xin_id = xin_id;
874 ),
875 TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id)
876);
877
878TRACE_EVENT(dpu_pp_connect_ext_te,
879 TP_PROTO(enum dpu_pingpong pp, u32 cfg),
880 TP_ARGS(pp, cfg),
881 TP_STRUCT__entry(
882 __field( enum dpu_pingpong, pp )
883 __field( u32, cfg )
884 ),
885 TP_fast_assign(
886 __entry->pp = pp;
887 __entry->cfg = cfg;
888 ),
889 TP_printk("pp:%d cfg:%u", __entry->pp, __entry->cfg)
890);
891
892DECLARE_EVENT_CLASS(dpu_core_irq_idx_cnt_template,
893 TP_PROTO(int irq_idx, int enable_count),
894 TP_ARGS(irq_idx, enable_count),
895 TP_STRUCT__entry(
896 __field( int, irq_idx )
897 __field( int, enable_count )
898 ),
899 TP_fast_assign(
900 __entry->irq_idx = irq_idx;
901 __entry->enable_count = enable_count;
902 ),
903 TP_printk("irq_idx:%d enable_count:%u", __entry->irq_idx,
904 __entry->enable_count)
905);
906DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_enable_idx,
907 TP_PROTO(int irq_idx, int enable_count),
908 TP_ARGS(irq_idx, enable_count)
909);
910DEFINE_EVENT(dpu_core_irq_idx_cnt_template, dpu_core_irq_disable_idx,
911 TP_PROTO(int irq_idx, int enable_count),
912 TP_ARGS(irq_idx, enable_count)
913);
914
915DECLARE_EVENT_CLASS(dpu_core_irq_callback_template,
916 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
917 TP_ARGS(irq_idx, callback),
918 TP_STRUCT__entry(
919 __field( int, irq_idx )
920 __field( struct dpu_irq_callback *, callback)
921 ),
922 TP_fast_assign(
923 __entry->irq_idx = irq_idx;
924 __entry->callback = callback;
925 ),
926 TP_printk("irq_idx:%d callback:%pK", __entry->irq_idx,
927 __entry->callback)
928);
929DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_register_callback,
930 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
931 TP_ARGS(irq_idx, callback)
932);
933DEFINE_EVENT(dpu_core_irq_callback_template, dpu_core_irq_unregister_callback,
934 TP_PROTO(int irq_idx, struct dpu_irq_callback *callback),
935 TP_ARGS(irq_idx, callback)
936);
937
938TRACE_EVENT(dpu_core_perf_update_clk,
939 TP_PROTO(struct drm_device *dev, bool stop_req, u64 clk_rate),
940 TP_ARGS(dev, stop_req, clk_rate),
941 TP_STRUCT__entry(
942 __string( dev_name, dev->unique )
943 __field( bool, stop_req )
944 __field( u64, clk_rate )
945 ),
946 TP_fast_assign(
947 __assign_str(dev_name, dev->unique);
948 __entry->stop_req = stop_req;
949 __entry->clk_rate = clk_rate;
950 ),
951 TP_printk("dev:%s stop_req:%s clk_rate:%llu", __get_str(dev_name),
952 __entry->stop_req ? "true" : "false", __entry->clk_rate)
953);
954
955TRACE_EVENT(dpu_hw_ctl_update_pending_flush,
956 TP_PROTO(u32 new_bits, u32 pending_mask),
957 TP_ARGS(new_bits, pending_mask),
958 TP_STRUCT__entry(
959 __field( u32, new_bits )
960 __field( u32, pending_mask )
961 ),
962 TP_fast_assign(
963 __entry->new_bits = new_bits;
964 __entry->pending_mask = pending_mask;
965 ),
966 TP_printk("new=%x existing=%x", __entry->new_bits,
967 __entry->pending_mask)
968);
969
970DECLARE_EVENT_CLASS(dpu_hw_ctl_pending_flush_template,
971 TP_PROTO(u32 pending_mask, u32 ctl_flush),
972 TP_ARGS(pending_mask, ctl_flush),
973 TP_STRUCT__entry(
974 __field( u32, pending_mask )
975 __field( u32, ctl_flush )
976 ),
977 TP_fast_assign(
978 __entry->pending_mask = pending_mask;
979 __entry->ctl_flush = ctl_flush;
980 ),
981 TP_printk("pending_mask=%x CTL_FLUSH=%x", __entry->pending_mask,
982 __entry->ctl_flush)
983);
984DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_clear_pending_flush,
985 TP_PROTO(u32 pending_mask, u32 ctl_flush),
986 TP_ARGS(pending_mask, ctl_flush)
987);
988DEFINE_EVENT(dpu_hw_ctl_pending_flush_template,
989 dpu_hw_ctl_trigger_pending_flush,
990 TP_PROTO(u32 pending_mask, u32 ctl_flush),
991 TP_ARGS(pending_mask, ctl_flush)
992);
993DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_prepare,
994 TP_PROTO(u32 pending_mask, u32 ctl_flush),
995 TP_ARGS(pending_mask, ctl_flush)
996);
997DEFINE_EVENT(dpu_hw_ctl_pending_flush_template, dpu_hw_ctl_trigger_start,
998 TP_PROTO(u32 pending_mask, u32 ctl_flush),
999 TP_ARGS(pending_mask, ctl_flush)
1000);
1001
1002#define DPU_ATRACE_END(name) trace_tracing_mark_write(current->tgid, name, 0)
1003#define DPU_ATRACE_BEGIN(name) trace_tracing_mark_write(current->tgid, name, 1)
1004#define DPU_ATRACE_FUNC() DPU_ATRACE_BEGIN(__func__)
1005
1006#define DPU_ATRACE_INT(name, value) \
1007 trace_dpu_trace_counter(current->tgid, name, value)
1008
1009#endif
1010
1011
1012#undef TRACE_INCLUDE_PATH
1013#define TRACE_INCLUDE_PATH .
1014#include <trace/define_trace.h>
1015
