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6
7#include <drm/drm.h>
8#include <drm/drmP.h>
9#include <drm/drm_atomic.h>
10#include <drm/drm_atomic_uapi.h>
11#include <drm/drm_crtc.h>
12#include <drm/drm_flip_work.h>
13#include <drm/drm_gem_framebuffer_helper.h>
14#include <drm/drm_plane_helper.h>
15#include <drm/drm_probe_helper.h>
16#ifdef CONFIG_DRM_ANALOGIX_DP
17#include <drm/bridge/analogix_dp.h>
18#endif
19
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/clk.h>
24#include <linux/iopoll.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/pm_runtime.h>
28#include <linux/component.h>
29#include <linux/overflow.h>
30
31#include <linux/reset.h>
32#include <linux/delay.h>
33
34#include "rockchip_drm_drv.h"
35#include "rockchip_drm_gem.h"
36#include "rockchip_drm_fb.h"
37#include "rockchip_drm_psr.h"
38#include "rockchip_drm_vop.h"
39#include "rockchip_rgb.h"
40
41#define VOP_WIN_SET(vop, win, name, v) \
42 vop_reg_set(vop, &win->phy->name, win->base, ~0, v, #name)
43#define VOP_SCL_SET(vop, win, name, v) \
44 vop_reg_set(vop, &win->phy->scl->name, win->base, ~0, v, #name)
45#define VOP_SCL_SET_EXT(vop, win, name, v) \
46 vop_reg_set(vop, &win->phy->scl->ext->name, \
47 win->base, ~0, v, #name)
48
49#define VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, name, v) \
50 do { \
51 if (win_yuv2yuv && win_yuv2yuv->name.mask) \
52 vop_reg_set(vop, &win_yuv2yuv->name, 0, ~0, v, #name); \
53 } while (0)
54
55#define VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop, win_yuv2yuv, name, v) \
56 do { \
57 if (win_yuv2yuv && win_yuv2yuv->phy->name.mask) \
58 vop_reg_set(vop, &win_yuv2yuv->phy->name, win_yuv2yuv->base, ~0, v, #name); \
59 } while (0)
60
61#define VOP_INTR_SET_MASK(vop, name, mask, v) \
62 vop_reg_set(vop, &vop->data->intr->name, 0, mask, v, #name)
63
64#define VOP_REG_SET(vop, group, name, v) \
65 vop_reg_set(vop, &vop->data->group->name, 0, ~0, v, #name)
66
67#define VOP_INTR_SET_TYPE(vop, name, type, v) \
68 do { \
69 int i, reg = 0, mask = 0; \
70 for (i = 0; i < vop->data->intr->nintrs; i++) { \
71 if (vop->data->intr->intrs[i] & type) { \
72 reg |= (v) << i; \
73 mask |= 1 << i; \
74 } \
75 } \
76 VOP_INTR_SET_MASK(vop, name, mask, reg); \
77 } while (0)
78#define VOP_INTR_GET_TYPE(vop, name, type) \
79 vop_get_intr_type(vop, &vop->data->intr->name, type)
80
81#define VOP_WIN_GET(vop, win, name) \
82 vop_read_reg(vop, win->offset, win->phy->name)
83
84#define VOP_WIN_HAS_REG(win, name) \
85 (!!(win->phy->name.mask))
86
87#define VOP_WIN_GET_YRGBADDR(vop, win) \
88 vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
89
90#define VOP_WIN_TO_INDEX(vop_win) \
91 ((vop_win) - (vop_win)->vop->win)
92
93#define to_vop(x) container_of(x, struct vop, crtc)
94#define to_vop_win(x) container_of(x, struct vop_win, base)
95
96
97
98
99
100
101static const uint32_t bt601_yuv2rgb[] = {
102 0x4A8, 0x0, 0x662,
103 0x4A8, 0x1E6F, 0x1CBF,
104 0x4A8, 0x812, 0x0,
105 0x321168, 0x0877CF, 0x2EB127
106};
107
108enum vop_pending {
109 VOP_PENDING_FB_UNREF,
110};
111
112struct vop_win {
113 struct drm_plane base;
114 const struct vop_win_data *data;
115 const struct vop_win_yuv2yuv_data *yuv2yuv_data;
116 struct vop *vop;
117};
118
119struct rockchip_rgb;
120struct vop {
121 struct drm_crtc crtc;
122 struct device *dev;
123 struct drm_device *drm_dev;
124 bool is_enabled;
125
126 struct completion dsp_hold_completion;
127
128
129 struct drm_pending_vblank_event *event;
130
131 struct drm_flip_work fb_unref_work;
132 unsigned long pending;
133
134 struct completion line_flag_completion;
135
136 const struct vop_data *data;
137
138 uint32_t *regsbak;
139 void __iomem *regs;
140
141
142 uint32_t len;
143
144
145 spinlock_t reg_lock;
146
147 spinlock_t irq_lock;
148
149 struct mutex vop_lock;
150
151 unsigned int irq;
152
153
154 struct clk *hclk;
155
156 struct clk *dclk;
157
158 struct clk *aclk;
159
160
161 struct reset_control *dclk_rst;
162
163
164 struct rockchip_rgb *rgb;
165
166 struct vop_win win[];
167};
168
169static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
170{
171 writel(v, vop->regs + offset);
172 vop->regsbak[offset >> 2] = v;
173}
174
175static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
176{
177 return readl(vop->regs + offset);
178}
179
180static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
181 const struct vop_reg *reg)
182{
183 return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
184}
185
186static void vop_reg_set(struct vop *vop, const struct vop_reg *reg,
187 uint32_t _offset, uint32_t _mask, uint32_t v,
188 const char *reg_name)
189{
190 int offset, mask, shift;
191
192 if (!reg || !reg->mask) {
193 DRM_DEV_DEBUG(vop->dev, "Warning: not support %s\n", reg_name);
194 return;
195 }
196
197 offset = reg->offset + _offset;
198 mask = reg->mask & _mask;
199 shift = reg->shift;
200
201 if (reg->write_mask) {
202 v = ((v << shift) & 0xffff) | (mask << (shift + 16));
203 } else {
204 uint32_t cached_val = vop->regsbak[offset >> 2];
205
206 v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
207 vop->regsbak[offset >> 2] = v;
208 }
209
210 if (reg->relaxed)
211 writel_relaxed(v, vop->regs + offset);
212 else
213 writel(v, vop->regs + offset);
214}
215
216static inline uint32_t vop_get_intr_type(struct vop *vop,
217 const struct vop_reg *reg, int type)
218{
219 uint32_t i, ret = 0;
220 uint32_t regs = vop_read_reg(vop, 0, reg);
221
222 for (i = 0; i < vop->data->intr->nintrs; i++) {
223 if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
224 ret |= vop->data->intr->intrs[i];
225 }
226
227 return ret;
228}
229
230static inline void vop_cfg_done(struct vop *vop)
231{
232 VOP_REG_SET(vop, common, cfg_done, 1);
233}
234
235static bool has_rb_swapped(uint32_t format)
236{
237 switch (format) {
238 case DRM_FORMAT_XBGR8888:
239 case DRM_FORMAT_ABGR8888:
240 case DRM_FORMAT_BGR888:
241 case DRM_FORMAT_BGR565:
242 return true;
243 default:
244 return false;
245 }
246}
247
248static enum vop_data_format vop_convert_format(uint32_t format)
249{
250 switch (format) {
251 case DRM_FORMAT_XRGB8888:
252 case DRM_FORMAT_ARGB8888:
253 case DRM_FORMAT_XBGR8888:
254 case DRM_FORMAT_ABGR8888:
255 return VOP_FMT_ARGB8888;
256 case DRM_FORMAT_RGB888:
257 case DRM_FORMAT_BGR888:
258 return VOP_FMT_RGB888;
259 case DRM_FORMAT_RGB565:
260 case DRM_FORMAT_BGR565:
261 return VOP_FMT_RGB565;
262 case DRM_FORMAT_NV12:
263 return VOP_FMT_YUV420SP;
264 case DRM_FORMAT_NV16:
265 return VOP_FMT_YUV422SP;
266 case DRM_FORMAT_NV24:
267 return VOP_FMT_YUV444SP;
268 default:
269 DRM_ERROR("unsupported format[%08x]\n", format);
270 return -EINVAL;
271 }
272}
273
274static uint16_t scl_vop_cal_scale(enum scale_mode mode, uint32_t src,
275 uint32_t dst, bool is_horizontal,
276 int vsu_mode, int *vskiplines)
277{
278 uint16_t val = 1 << SCL_FT_DEFAULT_FIXPOINT_SHIFT;
279
280 if (vskiplines)
281 *vskiplines = 0;
282
283 if (is_horizontal) {
284 if (mode == SCALE_UP)
285 val = GET_SCL_FT_BIC(src, dst);
286 else if (mode == SCALE_DOWN)
287 val = GET_SCL_FT_BILI_DN(src, dst);
288 } else {
289 if (mode == SCALE_UP) {
290 if (vsu_mode == SCALE_UP_BIL)
291 val = GET_SCL_FT_BILI_UP(src, dst);
292 else
293 val = GET_SCL_FT_BIC(src, dst);
294 } else if (mode == SCALE_DOWN) {
295 if (vskiplines) {
296 *vskiplines = scl_get_vskiplines(src, dst);
297 val = scl_get_bili_dn_vskip(src, dst,
298 *vskiplines);
299 } else {
300 val = GET_SCL_FT_BILI_DN(src, dst);
301 }
302 }
303 }
304
305 return val;
306}
307
308static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
309 uint32_t src_w, uint32_t src_h, uint32_t dst_w,
310 uint32_t dst_h, uint32_t pixel_format)
311{
312 uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
313 uint16_t cbcr_hor_scl_mode = SCALE_NONE;
314 uint16_t cbcr_ver_scl_mode = SCALE_NONE;
315 int hsub = drm_format_horz_chroma_subsampling(pixel_format);
316 int vsub = drm_format_vert_chroma_subsampling(pixel_format);
317 const struct drm_format_info *info;
318 bool is_yuv = false;
319 uint16_t cbcr_src_w = src_w / hsub;
320 uint16_t cbcr_src_h = src_h / vsub;
321 uint16_t vsu_mode;
322 uint16_t lb_mode;
323 uint32_t val;
324 int vskiplines;
325
326 info = drm_format_info(pixel_format);
327
328 if (info->is_yuv)
329 is_yuv = true;
330
331 if (dst_w > 3840) {
332 DRM_DEV_ERROR(vop->dev, "Maximum dst width (3840) exceeded\n");
333 return;
334 }
335
336 if (!win->phy->scl->ext) {
337 VOP_SCL_SET(vop, win, scale_yrgb_x,
338 scl_cal_scale2(src_w, dst_w));
339 VOP_SCL_SET(vop, win, scale_yrgb_y,
340 scl_cal_scale2(src_h, dst_h));
341 if (is_yuv) {
342 VOP_SCL_SET(vop, win, scale_cbcr_x,
343 scl_cal_scale2(cbcr_src_w, dst_w));
344 VOP_SCL_SET(vop, win, scale_cbcr_y,
345 scl_cal_scale2(cbcr_src_h, dst_h));
346 }
347 return;
348 }
349
350 yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
351 yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
352
353 if (is_yuv) {
354 cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
355 cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
356 if (cbcr_hor_scl_mode == SCALE_DOWN)
357 lb_mode = scl_vop_cal_lb_mode(dst_w, true);
358 else
359 lb_mode = scl_vop_cal_lb_mode(cbcr_src_w, true);
360 } else {
361 if (yrgb_hor_scl_mode == SCALE_DOWN)
362 lb_mode = scl_vop_cal_lb_mode(dst_w, false);
363 else
364 lb_mode = scl_vop_cal_lb_mode(src_w, false);
365 }
366
367 VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
368 if (lb_mode == LB_RGB_3840X2) {
369 if (yrgb_ver_scl_mode != SCALE_NONE) {
370 DRM_DEV_ERROR(vop->dev, "not allow yrgb ver scale\n");
371 return;
372 }
373 if (cbcr_ver_scl_mode != SCALE_NONE) {
374 DRM_DEV_ERROR(vop->dev, "not allow cbcr ver scale\n");
375 return;
376 }
377 vsu_mode = SCALE_UP_BIL;
378 } else if (lb_mode == LB_RGB_2560X4) {
379 vsu_mode = SCALE_UP_BIL;
380 } else {
381 vsu_mode = SCALE_UP_BIC;
382 }
383
384 val = scl_vop_cal_scale(yrgb_hor_scl_mode, src_w, dst_w,
385 true, 0, NULL);
386 VOP_SCL_SET(vop, win, scale_yrgb_x, val);
387 val = scl_vop_cal_scale(yrgb_ver_scl_mode, src_h, dst_h,
388 false, vsu_mode, &vskiplines);
389 VOP_SCL_SET(vop, win, scale_yrgb_y, val);
390
391 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
392 VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
393
394 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
395 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
396 VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
397 VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
398 VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
399 if (is_yuv) {
400 val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
401 dst_w, true, 0, NULL);
402 VOP_SCL_SET(vop, win, scale_cbcr_x, val);
403 val = scl_vop_cal_scale(cbcr_ver_scl_mode, cbcr_src_h,
404 dst_h, false, vsu_mode, &vskiplines);
405 VOP_SCL_SET(vop, win, scale_cbcr_y, val);
406
407 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
408 VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
409 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
410 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
411 VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
412 VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
413 VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
414 }
415}
416
417static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
418{
419 unsigned long flags;
420
421 if (WARN_ON(!vop->is_enabled))
422 return;
423
424 spin_lock_irqsave(&vop->irq_lock, flags);
425
426 VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
427 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
428
429 spin_unlock_irqrestore(&vop->irq_lock, flags);
430}
431
432static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
433{
434 unsigned long flags;
435
436 if (WARN_ON(!vop->is_enabled))
437 return;
438
439 spin_lock_irqsave(&vop->irq_lock, flags);
440
441 VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
442
443 spin_unlock_irqrestore(&vop->irq_lock, flags);
444}
445
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448
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466
467
468static bool vop_line_flag_irq_is_enabled(struct vop *vop)
469{
470 uint32_t line_flag_irq;
471 unsigned long flags;
472
473 spin_lock_irqsave(&vop->irq_lock, flags);
474
475 line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
476
477 spin_unlock_irqrestore(&vop->irq_lock, flags);
478
479 return !!line_flag_irq;
480}
481
482static void vop_line_flag_irq_enable(struct vop *vop)
483{
484 unsigned long flags;
485
486 if (WARN_ON(!vop->is_enabled))
487 return;
488
489 spin_lock_irqsave(&vop->irq_lock, flags);
490
491 VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
492 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
493
494 spin_unlock_irqrestore(&vop->irq_lock, flags);
495}
496
497static void vop_line_flag_irq_disable(struct vop *vop)
498{
499 unsigned long flags;
500
501 if (WARN_ON(!vop->is_enabled))
502 return;
503
504 spin_lock_irqsave(&vop->irq_lock, flags);
505
506 VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
507
508 spin_unlock_irqrestore(&vop->irq_lock, flags);
509}
510
511static int vop_core_clks_enable(struct vop *vop)
512{
513 int ret;
514
515 ret = clk_enable(vop->hclk);
516 if (ret < 0)
517 return ret;
518
519 ret = clk_enable(vop->aclk);
520 if (ret < 0)
521 goto err_disable_hclk;
522
523 return 0;
524
525err_disable_hclk:
526 clk_disable(vop->hclk);
527 return ret;
528}
529
530static void vop_core_clks_disable(struct vop *vop)
531{
532 clk_disable(vop->aclk);
533 clk_disable(vop->hclk);
534}
535
536static void vop_win_disable(struct vop *vop, const struct vop_win_data *win)
537{
538 if (win->phy->scl && win->phy->scl->ext) {
539 VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
540 VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
541 VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
542 VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
543 }
544
545 VOP_WIN_SET(vop, win, enable, 0);
546}
547
548static int vop_enable(struct drm_crtc *crtc)
549{
550 struct vop *vop = to_vop(crtc);
551 int ret, i;
552
553 ret = pm_runtime_get_sync(vop->dev);
554 if (ret < 0) {
555 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
556 return ret;
557 }
558
559 ret = vop_core_clks_enable(vop);
560 if (WARN_ON(ret < 0))
561 goto err_put_pm_runtime;
562
563 ret = clk_enable(vop->dclk);
564 if (WARN_ON(ret < 0))
565 goto err_disable_core;
566
567
568
569
570
571
572
573 ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
574 if (ret) {
575 DRM_DEV_ERROR(vop->dev,
576 "failed to attach dma mapping, %d\n", ret);
577 goto err_disable_dclk;
578 }
579
580 spin_lock(&vop->reg_lock);
581 for (i = 0; i < vop->len; i += 4)
582 writel_relaxed(vop->regsbak[i / 4], vop->regs + i);
583
584
585
586
587
588
589 for (i = 0; i < vop->data->win_size; i++) {
590 struct vop_win *vop_win = &vop->win[i];
591 const struct vop_win_data *win = vop_win->data;
592
593 vop_win_disable(vop, win);
594 }
595 spin_unlock(&vop->reg_lock);
596
597 vop_cfg_done(vop);
598
599
600
601
602 vop->is_enabled = true;
603
604 spin_lock(&vop->reg_lock);
605
606 VOP_REG_SET(vop, common, standby, 1);
607
608 spin_unlock(&vop->reg_lock);
609
610 drm_crtc_vblank_on(crtc);
611
612 return 0;
613
614err_disable_dclk:
615 clk_disable(vop->dclk);
616err_disable_core:
617 vop_core_clks_disable(vop);
618err_put_pm_runtime:
619 pm_runtime_put_sync(vop->dev);
620 return ret;
621}
622
623static void vop_crtc_atomic_disable(struct drm_crtc *crtc,
624 struct drm_crtc_state *old_state)
625{
626 struct vop *vop = to_vop(crtc);
627
628 WARN_ON(vop->event);
629
630 mutex_lock(&vop->vop_lock);
631 drm_crtc_vblank_off(crtc);
632
633
634
635
636
637
638
639
640 reinit_completion(&vop->dsp_hold_completion);
641 vop_dsp_hold_valid_irq_enable(vop);
642
643 spin_lock(&vop->reg_lock);
644
645 VOP_REG_SET(vop, common, standby, 1);
646
647 spin_unlock(&vop->reg_lock);
648
649 wait_for_completion(&vop->dsp_hold_completion);
650
651 vop_dsp_hold_valid_irq_disable(vop);
652
653 vop->is_enabled = false;
654
655
656
657
658 rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
659
660 clk_disable(vop->dclk);
661 vop_core_clks_disable(vop);
662 pm_runtime_put(vop->dev);
663 mutex_unlock(&vop->vop_lock);
664
665 if (crtc->state->event && !crtc->state->active) {
666 spin_lock_irq(&crtc->dev->event_lock);
667 drm_crtc_send_vblank_event(crtc, crtc->state->event);
668 spin_unlock_irq(&crtc->dev->event_lock);
669
670 crtc->state->event = NULL;
671 }
672}
673
674static void vop_plane_destroy(struct drm_plane *plane)
675{
676 drm_plane_cleanup(plane);
677}
678
679static int vop_plane_atomic_check(struct drm_plane *plane,
680 struct drm_plane_state *state)
681{
682 struct drm_crtc *crtc = state->crtc;
683 struct drm_crtc_state *crtc_state;
684 struct drm_framebuffer *fb = state->fb;
685 struct vop_win *vop_win = to_vop_win(plane);
686 const struct vop_win_data *win = vop_win->data;
687 int ret;
688 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
689 DRM_PLANE_HELPER_NO_SCALING;
690 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
691 DRM_PLANE_HELPER_NO_SCALING;
692
693 if (!crtc || !fb)
694 return 0;
695
696 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc);
697 if (WARN_ON(!crtc_state))
698 return -EINVAL;
699
700 ret = drm_atomic_helper_check_plane_state(state, crtc_state,
701 min_scale, max_scale,
702 true, true);
703 if (ret)
704 return ret;
705
706 if (!state->visible)
707 return 0;
708
709 ret = vop_convert_format(fb->format->format);
710 if (ret < 0)
711 return ret;
712
713
714
715
716
717 if (fb->format->is_yuv && ((state->src.x1 >> 16) % 2)) {
718 DRM_ERROR("Invalid Source: Yuv format not support odd xpos\n");
719 return -EINVAL;
720 }
721
722 if (fb->format->is_yuv && state->rotation & DRM_MODE_REFLECT_Y) {
723 DRM_ERROR("Invalid Source: Yuv format does not support this rotation\n");
724 return -EINVAL;
725 }
726
727 return 0;
728}
729
730static void vop_plane_atomic_disable(struct drm_plane *plane,
731 struct drm_plane_state *old_state)
732{
733 struct vop_win *vop_win = to_vop_win(plane);
734 const struct vop_win_data *win = vop_win->data;
735 struct vop *vop = to_vop(old_state->crtc);
736
737 if (!old_state->crtc)
738 return;
739
740 spin_lock(&vop->reg_lock);
741
742 vop_win_disable(vop, win);
743
744 spin_unlock(&vop->reg_lock);
745}
746
747static void vop_plane_atomic_update(struct drm_plane *plane,
748 struct drm_plane_state *old_state)
749{
750 struct drm_plane_state *state = plane->state;
751 struct drm_crtc *crtc = state->crtc;
752 struct vop_win *vop_win = to_vop_win(plane);
753 const struct vop_win_data *win = vop_win->data;
754 const struct vop_win_yuv2yuv_data *win_yuv2yuv = vop_win->yuv2yuv_data;
755 struct vop *vop = to_vop(state->crtc);
756 struct drm_framebuffer *fb = state->fb;
757 unsigned int actual_w, actual_h;
758 unsigned int dsp_stx, dsp_sty;
759 uint32_t act_info, dsp_info, dsp_st;
760 struct drm_rect *src = &state->src;
761 struct drm_rect *dest = &state->dst;
762 struct drm_gem_object *obj, *uv_obj;
763 struct rockchip_gem_object *rk_obj, *rk_uv_obj;
764 unsigned long offset;
765 dma_addr_t dma_addr;
766 uint32_t val;
767 bool rb_swap;
768 int win_index = VOP_WIN_TO_INDEX(vop_win);
769 int format;
770 int is_yuv = fb->format->is_yuv;
771 int i;
772
773
774
775
776 if (WARN_ON(!crtc))
777 return;
778
779 if (WARN_ON(!vop->is_enabled))
780 return;
781
782 if (!state->visible) {
783 vop_plane_atomic_disable(plane, old_state);
784 return;
785 }
786
787 obj = fb->obj[0];
788 rk_obj = to_rockchip_obj(obj);
789
790 actual_w = drm_rect_width(src) >> 16;
791 actual_h = drm_rect_height(src) >> 16;
792 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
793
794 dsp_info = (drm_rect_height(dest) - 1) << 16;
795 dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
796
797 dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
798 dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
799 dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
800
801 offset = (src->x1 >> 16) * fb->format->cpp[0];
802 offset += (src->y1 >> 16) * fb->pitches[0];
803 dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
804
805
806
807
808
809 if (state->rotation & DRM_MODE_REFLECT_Y)
810 dma_addr += (actual_h - 1) * fb->pitches[0];
811
812 format = vop_convert_format(fb->format->format);
813
814 spin_lock(&vop->reg_lock);
815
816 VOP_WIN_SET(vop, win, format, format);
817 VOP_WIN_SET(vop, win, yrgb_vir, DIV_ROUND_UP(fb->pitches[0], 4));
818 VOP_WIN_SET(vop, win, yrgb_mst, dma_addr);
819 VOP_WIN_YUV2YUV_SET(vop, win_yuv2yuv, y2r_en, is_yuv);
820 VOP_WIN_SET(vop, win, y_mir_en,
821 (state->rotation & DRM_MODE_REFLECT_Y) ? 1 : 0);
822 VOP_WIN_SET(vop, win, x_mir_en,
823 (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
824
825 if (is_yuv) {
826 int hsub = drm_format_horz_chroma_subsampling(fb->format->format);
827 int vsub = drm_format_vert_chroma_subsampling(fb->format->format);
828 int bpp = fb->format->cpp[1];
829
830 uv_obj = fb->obj[1];
831 rk_uv_obj = to_rockchip_obj(uv_obj);
832
833 offset = (src->x1 >> 16) * bpp / hsub;
834 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
835
836 dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
837 VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
838 VOP_WIN_SET(vop, win, uv_mst, dma_addr);
839
840 for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
841 VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
842 win_yuv2yuv,
843 y2r_coefficients[i],
844 bt601_yuv2rgb[i]);
845 }
846 }
847
848 if (win->phy->scl)
849 scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
850 drm_rect_width(dest), drm_rect_height(dest),
851 fb->format->format);
852
853 VOP_WIN_SET(vop, win, act_info, act_info);
854 VOP_WIN_SET(vop, win, dsp_info, dsp_info);
855 VOP_WIN_SET(vop, win, dsp_st, dsp_st);
856
857 rb_swap = has_rb_swapped(fb->format->format);
858 VOP_WIN_SET(vop, win, rb_swap, rb_swap);
859
860
861
862
863
864
865
866
867 if (fb->format->has_alpha && win_index > 0) {
868 VOP_WIN_SET(vop, win, dst_alpha_ctl,
869 DST_FACTOR_M0(ALPHA_SRC_INVERSE));
870 val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
871 SRC_ALPHA_M0(ALPHA_STRAIGHT) |
872 SRC_BLEND_M0(ALPHA_PER_PIX) |
873 SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
874 SRC_FACTOR_M0(ALPHA_ONE);
875 VOP_WIN_SET(vop, win, src_alpha_ctl, val);
876 } else {
877 VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
878 }
879
880 VOP_WIN_SET(vop, win, enable, 1);
881 spin_unlock(&vop->reg_lock);
882}
883
884static int vop_plane_atomic_async_check(struct drm_plane *plane,
885 struct drm_plane_state *state)
886{
887 struct vop_win *vop_win = to_vop_win(plane);
888 const struct vop_win_data *win = vop_win->data;
889 int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
890 DRM_PLANE_HELPER_NO_SCALING;
891 int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
892 DRM_PLANE_HELPER_NO_SCALING;
893 struct drm_crtc_state *crtc_state;
894
895 if (plane != state->crtc->cursor)
896 return -EINVAL;
897
898 if (!plane->state)
899 return -EINVAL;
900
901 if (!plane->state->fb)
902 return -EINVAL;
903
904 if (state->state)
905 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
906 state->crtc);
907 else
908 crtc_state = plane->crtc->state;
909
910 return drm_atomic_helper_check_plane_state(plane->state, crtc_state,
911 min_scale, max_scale,
912 true, true);
913}
914
915static void vop_plane_atomic_async_update(struct drm_plane *plane,
916 struct drm_plane_state *new_state)
917{
918 struct vop *vop = to_vop(plane->state->crtc);
919 struct drm_framebuffer *old_fb = plane->state->fb;
920
921 plane->state->crtc_x = new_state->crtc_x;
922 plane->state->crtc_y = new_state->crtc_y;
923 plane->state->crtc_h = new_state->crtc_h;
924 plane->state->crtc_w = new_state->crtc_w;
925 plane->state->src_x = new_state->src_x;
926 plane->state->src_y = new_state->src_y;
927 plane->state->src_h = new_state->src_h;
928 plane->state->src_w = new_state->src_w;
929 swap(plane->state->fb, new_state->fb);
930
931 if (vop->is_enabled) {
932 rockchip_drm_psr_inhibit_get_state(new_state->state);
933 vop_plane_atomic_update(plane, plane->state);
934 spin_lock(&vop->reg_lock);
935 vop_cfg_done(vop);
936 spin_unlock(&vop->reg_lock);
937 rockchip_drm_psr_inhibit_put_state(new_state->state);
938
939
940
941
942
943
944
945
946
947 if (old_fb && plane->state->fb != old_fb) {
948 drm_framebuffer_get(old_fb);
949 WARN_ON(drm_crtc_vblank_get(plane->state->crtc) != 0);
950 drm_flip_work_queue(&vop->fb_unref_work, old_fb);
951 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
952 }
953 }
954}
955
956static const struct drm_plane_helper_funcs plane_helper_funcs = {
957 .atomic_check = vop_plane_atomic_check,
958 .atomic_update = vop_plane_atomic_update,
959 .atomic_disable = vop_plane_atomic_disable,
960 .atomic_async_check = vop_plane_atomic_async_check,
961 .atomic_async_update = vop_plane_atomic_async_update,
962 .prepare_fb = drm_gem_fb_prepare_fb,
963};
964
965static const struct drm_plane_funcs vop_plane_funcs = {
966 .update_plane = drm_atomic_helper_update_plane,
967 .disable_plane = drm_atomic_helper_disable_plane,
968 .destroy = vop_plane_destroy,
969 .reset = drm_atomic_helper_plane_reset,
970 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
971 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
972};
973
974static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
975{
976 struct vop *vop = to_vop(crtc);
977 unsigned long flags;
978
979 if (WARN_ON(!vop->is_enabled))
980 return -EPERM;
981
982 spin_lock_irqsave(&vop->irq_lock, flags);
983
984 VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
985 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
986
987 spin_unlock_irqrestore(&vop->irq_lock, flags);
988
989 return 0;
990}
991
992static void vop_crtc_disable_vblank(struct drm_crtc *crtc)
993{
994 struct vop *vop = to_vop(crtc);
995 unsigned long flags;
996
997 if (WARN_ON(!vop->is_enabled))
998 return;
999
1000 spin_lock_irqsave(&vop->irq_lock, flags);
1001
1002 VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
1003
1004 spin_unlock_irqrestore(&vop->irq_lock, flags);
1005}
1006
1007static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
1008 const struct drm_display_mode *mode,
1009 struct drm_display_mode *adjusted_mode)
1010{
1011 struct vop *vop = to_vop(crtc);
1012
1013 adjusted_mode->clock =
1014 clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
1015
1016 return true;
1017}
1018
1019static void vop_crtc_atomic_enable(struct drm_crtc *crtc,
1020 struct drm_crtc_state *old_state)
1021{
1022 struct vop *vop = to_vop(crtc);
1023 const struct vop_data *vop_data = vop->data;
1024 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
1025 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1026 u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
1027 u16 hdisplay = adjusted_mode->hdisplay;
1028 u16 htotal = adjusted_mode->htotal;
1029 u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
1030 u16 hact_end = hact_st + hdisplay;
1031 u16 vdisplay = adjusted_mode->vdisplay;
1032 u16 vtotal = adjusted_mode->vtotal;
1033 u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
1034 u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
1035 u16 vact_end = vact_st + vdisplay;
1036 uint32_t pin_pol, val;
1037 int dither_bpc = s->output_bpc ? s->output_bpc : 10;
1038 int ret;
1039
1040 mutex_lock(&vop->vop_lock);
1041
1042 WARN_ON(vop->event);
1043
1044 ret = vop_enable(crtc);
1045 if (ret) {
1046 mutex_unlock(&vop->vop_lock);
1047 DRM_DEV_ERROR(vop->dev, "Failed to enable vop (%d)\n", ret);
1048 return;
1049 }
1050
1051 pin_pol = BIT(DCLK_INVERT);
1052 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) ?
1053 BIT(HSYNC_POSITIVE) : 0;
1054 pin_pol |= (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) ?
1055 BIT(VSYNC_POSITIVE) : 0;
1056 VOP_REG_SET(vop, output, pin_pol, pin_pol);
1057 VOP_REG_SET(vop, output, mipi_dual_channel_en, 0);
1058
1059 switch (s->output_type) {
1060 case DRM_MODE_CONNECTOR_LVDS:
1061 VOP_REG_SET(vop, output, rgb_en, 1);
1062 VOP_REG_SET(vop, output, rgb_pin_pol, pin_pol);
1063 break;
1064 case DRM_MODE_CONNECTOR_eDP:
1065 VOP_REG_SET(vop, output, edp_pin_pol, pin_pol);
1066 VOP_REG_SET(vop, output, edp_en, 1);
1067 break;
1068 case DRM_MODE_CONNECTOR_HDMIA:
1069 VOP_REG_SET(vop, output, hdmi_pin_pol, pin_pol);
1070 VOP_REG_SET(vop, output, hdmi_en, 1);
1071 break;
1072 case DRM_MODE_CONNECTOR_DSI:
1073 VOP_REG_SET(vop, output, mipi_pin_pol, pin_pol);
1074 VOP_REG_SET(vop, output, mipi_en, 1);
1075 VOP_REG_SET(vop, output, mipi_dual_channel_en,
1076 !!(s->output_flags & ROCKCHIP_OUTPUT_DSI_DUAL));
1077 break;
1078 case DRM_MODE_CONNECTOR_DisplayPort:
1079 pin_pol &= ~BIT(DCLK_INVERT);
1080 VOP_REG_SET(vop, output, dp_pin_pol, pin_pol);
1081 VOP_REG_SET(vop, output, dp_en, 1);
1082 break;
1083 default:
1084 DRM_DEV_ERROR(vop->dev, "unsupported connector_type [%d]\n",
1085 s->output_type);
1086 }
1087
1088
1089
1090
1091 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1092 !(vop_data->feature & VOP_FEATURE_OUTPUT_RGB10))
1093 s->output_mode = ROCKCHIP_OUT_MODE_P888;
1094
1095 if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA && dither_bpc <= 8)
1096 VOP_REG_SET(vop, common, pre_dither_down, 1);
1097 else
1098 VOP_REG_SET(vop, common, pre_dither_down, 0);
1099
1100 if (dither_bpc == 6) {
1101 VOP_REG_SET(vop, common, dither_down_sel, DITHER_DOWN_ALLEGRO);
1102 VOP_REG_SET(vop, common, dither_down_mode, RGB888_TO_RGB666);
1103 VOP_REG_SET(vop, common, dither_down_en, 1);
1104 } else {
1105 VOP_REG_SET(vop, common, dither_down_en, 0);
1106 }
1107
1108 VOP_REG_SET(vop, common, out_mode, s->output_mode);
1109
1110 VOP_REG_SET(vop, modeset, htotal_pw, (htotal << 16) | hsync_len);
1111 val = hact_st << 16;
1112 val |= hact_end;
1113 VOP_REG_SET(vop, modeset, hact_st_end, val);
1114 VOP_REG_SET(vop, modeset, hpost_st_end, val);
1115
1116 VOP_REG_SET(vop, modeset, vtotal_pw, (vtotal << 16) | vsync_len);
1117 val = vact_st << 16;
1118 val |= vact_end;
1119 VOP_REG_SET(vop, modeset, vact_st_end, val);
1120 VOP_REG_SET(vop, modeset, vpost_st_end, val);
1121
1122 VOP_REG_SET(vop, intr, line_flag_num[0], vact_end);
1123
1124 clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
1125
1126 VOP_REG_SET(vop, common, standby, 0);
1127 mutex_unlock(&vop->vop_lock);
1128}
1129
1130static bool vop_fs_irq_is_pending(struct vop *vop)
1131{
1132 return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
1133}
1134
1135static void vop_wait_for_irq_handler(struct vop *vop)
1136{
1137 bool pending;
1138 int ret;
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148 ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
1149 !pending, 0, 10 * 1000);
1150 if (ret)
1151 DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
1152
1153 synchronize_irq(vop->irq);
1154}
1155
1156static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
1157 struct drm_crtc_state *old_crtc_state)
1158{
1159 struct drm_atomic_state *old_state = old_crtc_state->state;
1160 struct drm_plane_state *old_plane_state, *new_plane_state;
1161 struct vop *vop = to_vop(crtc);
1162 struct drm_plane *plane;
1163 int i;
1164
1165 if (WARN_ON(!vop->is_enabled))
1166 return;
1167
1168 spin_lock(&vop->reg_lock);
1169
1170 vop_cfg_done(vop);
1171
1172 spin_unlock(&vop->reg_lock);
1173
1174
1175
1176
1177
1178
1179 vop_wait_for_irq_handler(vop);
1180
1181 spin_lock_irq(&crtc->dev->event_lock);
1182 if (crtc->state->event) {
1183 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1184 WARN_ON(vop->event);
1185
1186 vop->event = crtc->state->event;
1187 crtc->state->event = NULL;
1188 }
1189 spin_unlock_irq(&crtc->dev->event_lock);
1190
1191 for_each_oldnew_plane_in_state(old_state, plane, old_plane_state,
1192 new_plane_state, i) {
1193 if (!old_plane_state->fb)
1194 continue;
1195
1196 if (old_plane_state->fb == new_plane_state->fb)
1197 continue;
1198
1199 drm_framebuffer_get(old_plane_state->fb);
1200 WARN_ON(drm_crtc_vblank_get(crtc) != 0);
1201 drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
1202 set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
1203 }
1204}
1205
1206static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
1207 .mode_fixup = vop_crtc_mode_fixup,
1208 .atomic_flush = vop_crtc_atomic_flush,
1209 .atomic_enable = vop_crtc_atomic_enable,
1210 .atomic_disable = vop_crtc_atomic_disable,
1211};
1212
1213static void vop_crtc_destroy(struct drm_crtc *crtc)
1214{
1215 drm_crtc_cleanup(crtc);
1216}
1217
1218static void vop_crtc_reset(struct drm_crtc *crtc)
1219{
1220 if (crtc->state)
1221 __drm_atomic_helper_crtc_destroy_state(crtc->state);
1222 kfree(crtc->state);
1223
1224 crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
1225 if (crtc->state)
1226 crtc->state->crtc = crtc;
1227}
1228
1229static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
1230{
1231 struct rockchip_crtc_state *rockchip_state;
1232
1233 rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
1234 if (!rockchip_state)
1235 return NULL;
1236
1237 __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
1238 return &rockchip_state->base;
1239}
1240
1241static void vop_crtc_destroy_state(struct drm_crtc *crtc,
1242 struct drm_crtc_state *state)
1243{
1244 struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
1245
1246 __drm_atomic_helper_crtc_destroy_state(&s->base);
1247 kfree(s);
1248}
1249
1250#ifdef CONFIG_DRM_ANALOGIX_DP
1251static struct drm_connector *vop_get_edp_connector(struct vop *vop)
1252{
1253 struct drm_connector *connector;
1254 struct drm_connector_list_iter conn_iter;
1255
1256 drm_connector_list_iter_begin(vop->drm_dev, &conn_iter);
1257 drm_for_each_connector_iter(connector, &conn_iter) {
1258 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1259 drm_connector_list_iter_end(&conn_iter);
1260 return connector;
1261 }
1262 }
1263 drm_connector_list_iter_end(&conn_iter);
1264
1265 return NULL;
1266}
1267
1268static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1269 const char *source_name)
1270{
1271 struct vop *vop = to_vop(crtc);
1272 struct drm_connector *connector;
1273 int ret;
1274
1275 connector = vop_get_edp_connector(vop);
1276 if (!connector)
1277 return -EINVAL;
1278
1279 if (source_name && strcmp(source_name, "auto") == 0)
1280 ret = analogix_dp_start_crc(connector);
1281 else if (!source_name)
1282 ret = analogix_dp_stop_crc(connector);
1283 else
1284 ret = -EINVAL;
1285
1286 return ret;
1287}
1288
1289static int
1290vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1291 size_t *values_cnt)
1292{
1293 if (source_name && strcmp(source_name, "auto") != 0)
1294 return -EINVAL;
1295
1296 *values_cnt = 3;
1297 return 0;
1298}
1299
1300#else
1301static int vop_crtc_set_crc_source(struct drm_crtc *crtc,
1302 const char *source_name)
1303{
1304 return -ENODEV;
1305}
1306
1307static int
1308vop_crtc_verify_crc_source(struct drm_crtc *crtc, const char *source_name,
1309 size_t *values_cnt)
1310{
1311 return -ENODEV;
1312}
1313#endif
1314
1315static const struct drm_crtc_funcs vop_crtc_funcs = {
1316 .set_config = drm_atomic_helper_set_config,
1317 .page_flip = drm_atomic_helper_page_flip,
1318 .destroy = vop_crtc_destroy,
1319 .reset = vop_crtc_reset,
1320 .atomic_duplicate_state = vop_crtc_duplicate_state,
1321 .atomic_destroy_state = vop_crtc_destroy_state,
1322 .enable_vblank = vop_crtc_enable_vblank,
1323 .disable_vblank = vop_crtc_disable_vblank,
1324 .set_crc_source = vop_crtc_set_crc_source,
1325 .verify_crc_source = vop_crtc_verify_crc_source,
1326};
1327
1328static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
1329{
1330 struct vop *vop = container_of(work, struct vop, fb_unref_work);
1331 struct drm_framebuffer *fb = val;
1332
1333 drm_crtc_vblank_put(&vop->crtc);
1334 drm_framebuffer_put(fb);
1335}
1336
1337static void vop_handle_vblank(struct vop *vop)
1338{
1339 struct drm_device *drm = vop->drm_dev;
1340 struct drm_crtc *crtc = &vop->crtc;
1341
1342 spin_lock(&drm->event_lock);
1343 if (vop->event) {
1344 drm_crtc_send_vblank_event(crtc, vop->event);
1345 drm_crtc_vblank_put(crtc);
1346 vop->event = NULL;
1347 }
1348 spin_unlock(&drm->event_lock);
1349
1350 if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
1351 drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
1352}
1353
1354static irqreturn_t vop_isr(int irq, void *data)
1355{
1356 struct vop *vop = data;
1357 struct drm_crtc *crtc = &vop->crtc;
1358 uint32_t active_irqs;
1359 int ret = IRQ_NONE;
1360
1361
1362
1363
1364
1365 if (!pm_runtime_get_if_in_use(vop->dev))
1366 return IRQ_NONE;
1367
1368 if (vop_core_clks_enable(vop)) {
1369 DRM_DEV_ERROR_RATELIMITED(vop->dev, "couldn't enable clocks\n");
1370 goto out;
1371 }
1372
1373
1374
1375
1376
1377 spin_lock(&vop->irq_lock);
1378
1379 active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
1380
1381 if (active_irqs)
1382 VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
1383
1384 spin_unlock(&vop->irq_lock);
1385
1386
1387 if (!active_irqs)
1388 goto out_disable;
1389
1390 if (active_irqs & DSP_HOLD_VALID_INTR) {
1391 complete(&vop->dsp_hold_completion);
1392 active_irqs &= ~DSP_HOLD_VALID_INTR;
1393 ret = IRQ_HANDLED;
1394 }
1395
1396 if (active_irqs & LINE_FLAG_INTR) {
1397 complete(&vop->line_flag_completion);
1398 active_irqs &= ~LINE_FLAG_INTR;
1399 ret = IRQ_HANDLED;
1400 }
1401
1402 if (active_irqs & FS_INTR) {
1403 drm_crtc_handle_vblank(crtc);
1404 vop_handle_vblank(vop);
1405 active_irqs &= ~FS_INTR;
1406 ret = IRQ_HANDLED;
1407 }
1408
1409
1410 if (active_irqs)
1411 DRM_DEV_ERROR(vop->dev, "Unknown VOP IRQs: %#02x\n",
1412 active_irqs);
1413
1414out_disable:
1415 vop_core_clks_disable(vop);
1416out:
1417 pm_runtime_put(vop->dev);
1418 return ret;
1419}
1420
1421static void vop_plane_add_properties(struct drm_plane *plane,
1422 const struct vop_win_data *win_data)
1423{
1424 unsigned int flags = 0;
1425
1426 flags |= VOP_WIN_HAS_REG(win_data, x_mir_en) ? DRM_MODE_REFLECT_X : 0;
1427 flags |= VOP_WIN_HAS_REG(win_data, y_mir_en) ? DRM_MODE_REFLECT_Y : 0;
1428 if (flags)
1429 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1430 DRM_MODE_ROTATE_0 | flags);
1431}
1432
1433static int vop_create_crtc(struct vop *vop)
1434{
1435 const struct vop_data *vop_data = vop->data;
1436 struct device *dev = vop->dev;
1437 struct drm_device *drm_dev = vop->drm_dev;
1438 struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
1439 struct drm_crtc *crtc = &vop->crtc;
1440 struct device_node *port;
1441 int ret;
1442 int i;
1443
1444
1445
1446
1447
1448
1449 for (i = 0; i < vop_data->win_size; i++) {
1450 struct vop_win *vop_win = &vop->win[i];
1451 const struct vop_win_data *win_data = vop_win->data;
1452
1453 if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
1454 win_data->type != DRM_PLANE_TYPE_CURSOR)
1455 continue;
1456
1457 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1458 0, &vop_plane_funcs,
1459 win_data->phy->data_formats,
1460 win_data->phy->nformats,
1461 NULL, win_data->type, NULL);
1462 if (ret) {
1463 DRM_DEV_ERROR(vop->dev, "failed to init plane %d\n",
1464 ret);
1465 goto err_cleanup_planes;
1466 }
1467
1468 plane = &vop_win->base;
1469 drm_plane_helper_add(plane, &plane_helper_funcs);
1470 vop_plane_add_properties(plane, win_data);
1471 if (plane->type == DRM_PLANE_TYPE_PRIMARY)
1472 primary = plane;
1473 else if (plane->type == DRM_PLANE_TYPE_CURSOR)
1474 cursor = plane;
1475 }
1476
1477 ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
1478 &vop_crtc_funcs, NULL);
1479 if (ret)
1480 goto err_cleanup_planes;
1481
1482 drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
1483
1484
1485
1486
1487
1488 for (i = 0; i < vop_data->win_size; i++) {
1489 struct vop_win *vop_win = &vop->win[i];
1490 const struct vop_win_data *win_data = vop_win->data;
1491 unsigned long possible_crtcs = drm_crtc_mask(crtc);
1492
1493 if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
1494 continue;
1495
1496 ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
1497 possible_crtcs,
1498 &vop_plane_funcs,
1499 win_data->phy->data_formats,
1500 win_data->phy->nformats,
1501 NULL, win_data->type, NULL);
1502 if (ret) {
1503 DRM_DEV_ERROR(vop->dev, "failed to init overlay %d\n",
1504 ret);
1505 goto err_cleanup_crtc;
1506 }
1507 drm_plane_helper_add(&vop_win->base, &plane_helper_funcs);
1508 vop_plane_add_properties(&vop_win->base, win_data);
1509 }
1510
1511 port = of_get_child_by_name(dev->of_node, "port");
1512 if (!port) {
1513 DRM_DEV_ERROR(vop->dev, "no port node found in %pOF\n",
1514 dev->of_node);
1515 ret = -ENOENT;
1516 goto err_cleanup_crtc;
1517 }
1518
1519 drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
1520 vop_fb_unref_worker);
1521
1522 init_completion(&vop->dsp_hold_completion);
1523 init_completion(&vop->line_flag_completion);
1524 crtc->port = port;
1525
1526 return 0;
1527
1528err_cleanup_crtc:
1529 drm_crtc_cleanup(crtc);
1530err_cleanup_planes:
1531 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1532 head)
1533 drm_plane_cleanup(plane);
1534 return ret;
1535}
1536
1537static void vop_destroy_crtc(struct vop *vop)
1538{
1539 struct drm_crtc *crtc = &vop->crtc;
1540 struct drm_device *drm_dev = vop->drm_dev;
1541 struct drm_plane *plane, *tmp;
1542
1543 of_node_put(crtc->port);
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553 list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
1554 head)
1555 vop_plane_destroy(plane);
1556
1557
1558
1559
1560
1561 drm_crtc_cleanup(crtc);
1562 drm_flip_work_cleanup(&vop->fb_unref_work);
1563}
1564
1565static int vop_initial(struct vop *vop)
1566{
1567 const struct vop_data *vop_data = vop->data;
1568 struct reset_control *ahb_rst;
1569 int i, ret;
1570
1571 vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
1572 if (IS_ERR(vop->hclk)) {
1573 DRM_DEV_ERROR(vop->dev, "failed to get hclk source\n");
1574 return PTR_ERR(vop->hclk);
1575 }
1576 vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
1577 if (IS_ERR(vop->aclk)) {
1578 DRM_DEV_ERROR(vop->dev, "failed to get aclk source\n");
1579 return PTR_ERR(vop->aclk);
1580 }
1581 vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
1582 if (IS_ERR(vop->dclk)) {
1583 DRM_DEV_ERROR(vop->dev, "failed to get dclk source\n");
1584 return PTR_ERR(vop->dclk);
1585 }
1586
1587 ret = pm_runtime_get_sync(vop->dev);
1588 if (ret < 0) {
1589 DRM_DEV_ERROR(vop->dev, "failed to get pm runtime: %d\n", ret);
1590 return ret;
1591 }
1592
1593 ret = clk_prepare(vop->dclk);
1594 if (ret < 0) {
1595 DRM_DEV_ERROR(vop->dev, "failed to prepare dclk\n");
1596 goto err_put_pm_runtime;
1597 }
1598
1599
1600 ret = clk_prepare_enable(vop->hclk);
1601 if (ret < 0) {
1602 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable hclk\n");
1603 goto err_unprepare_dclk;
1604 }
1605
1606 ret = clk_prepare_enable(vop->aclk);
1607 if (ret < 0) {
1608 DRM_DEV_ERROR(vop->dev, "failed to prepare/enable aclk\n");
1609 goto err_disable_hclk;
1610 }
1611
1612
1613
1614
1615 ahb_rst = devm_reset_control_get(vop->dev, "ahb");
1616 if (IS_ERR(ahb_rst)) {
1617 DRM_DEV_ERROR(vop->dev, "failed to get ahb reset\n");
1618 ret = PTR_ERR(ahb_rst);
1619 goto err_disable_aclk;
1620 }
1621 reset_control_assert(ahb_rst);
1622 usleep_range(10, 20);
1623 reset_control_deassert(ahb_rst);
1624
1625 VOP_INTR_SET_TYPE(vop, clear, INTR_MASK, 1);
1626 VOP_INTR_SET_TYPE(vop, enable, INTR_MASK, 0);
1627
1628 for (i = 0; i < vop->len; i += sizeof(u32))
1629 vop->regsbak[i / 4] = readl_relaxed(vop->regs + i);
1630
1631 VOP_REG_SET(vop, misc, global_regdone_en, 1);
1632 VOP_REG_SET(vop, common, dsp_blank, 0);
1633
1634 for (i = 0; i < vop_data->win_size; i++) {
1635 const struct vop_win_data *win = &vop_data->win[i];
1636 int channel = i * 2 + 1;
1637
1638 VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
1639 vop_win_disable(vop, win);
1640 VOP_WIN_SET(vop, win, gate, 1);
1641 }
1642
1643 vop_cfg_done(vop);
1644
1645
1646
1647
1648 vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
1649 if (IS_ERR(vop->dclk_rst)) {
1650 DRM_DEV_ERROR(vop->dev, "failed to get dclk reset\n");
1651 ret = PTR_ERR(vop->dclk_rst);
1652 goto err_disable_aclk;
1653 }
1654 reset_control_assert(vop->dclk_rst);
1655 usleep_range(10, 20);
1656 reset_control_deassert(vop->dclk_rst);
1657
1658 clk_disable(vop->hclk);
1659 clk_disable(vop->aclk);
1660
1661 vop->is_enabled = false;
1662
1663 pm_runtime_put_sync(vop->dev);
1664
1665 return 0;
1666
1667err_disable_aclk:
1668 clk_disable_unprepare(vop->aclk);
1669err_disable_hclk:
1670 clk_disable_unprepare(vop->hclk);
1671err_unprepare_dclk:
1672 clk_unprepare(vop->dclk);
1673err_put_pm_runtime:
1674 pm_runtime_put_sync(vop->dev);
1675 return ret;
1676}
1677
1678
1679
1680
1681static void vop_win_init(struct vop *vop)
1682{
1683 const struct vop_data *vop_data = vop->data;
1684 unsigned int i;
1685
1686 for (i = 0; i < vop_data->win_size; i++) {
1687 struct vop_win *vop_win = &vop->win[i];
1688 const struct vop_win_data *win_data = &vop_data->win[i];
1689
1690 vop_win->data = win_data;
1691 vop_win->vop = vop;
1692
1693 if (vop_data->win_yuv2yuv)
1694 vop_win->yuv2yuv_data = &vop_data->win_yuv2yuv[i];
1695 }
1696}
1697
1698
1699
1700
1701
1702
1703
1704
1705
1706
1707
1708int rockchip_drm_wait_vact_end(struct drm_crtc *crtc, unsigned int mstimeout)
1709{
1710 struct vop *vop = to_vop(crtc);
1711 unsigned long jiffies_left;
1712 int ret = 0;
1713
1714 if (!crtc || !vop->is_enabled)
1715 return -ENODEV;
1716
1717 mutex_lock(&vop->vop_lock);
1718 if (mstimeout <= 0) {
1719 ret = -EINVAL;
1720 goto out;
1721 }
1722
1723 if (vop_line_flag_irq_is_enabled(vop)) {
1724 ret = -EBUSY;
1725 goto out;
1726 }
1727
1728 reinit_completion(&vop->line_flag_completion);
1729 vop_line_flag_irq_enable(vop);
1730
1731 jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
1732 msecs_to_jiffies(mstimeout));
1733 vop_line_flag_irq_disable(vop);
1734
1735 if (jiffies_left == 0) {
1736 DRM_DEV_ERROR(vop->dev, "Timeout waiting for IRQ\n");
1737 ret = -ETIMEDOUT;
1738 goto out;
1739 }
1740
1741out:
1742 mutex_unlock(&vop->vop_lock);
1743 return ret;
1744}
1745EXPORT_SYMBOL(rockchip_drm_wait_vact_end);
1746
1747static int vop_bind(struct device *dev, struct device *master, void *data)
1748{
1749 struct platform_device *pdev = to_platform_device(dev);
1750 const struct vop_data *vop_data;
1751 struct drm_device *drm_dev = data;
1752 struct vop *vop;
1753 struct resource *res;
1754 int ret, irq;
1755
1756 vop_data = of_device_get_match_data(dev);
1757 if (!vop_data)
1758 return -ENODEV;
1759
1760
1761 vop = devm_kzalloc(dev, struct_size(vop, win, vop_data->win_size),
1762 GFP_KERNEL);
1763 if (!vop)
1764 return -ENOMEM;
1765
1766 vop->dev = dev;
1767 vop->data = vop_data;
1768 vop->drm_dev = drm_dev;
1769 dev_set_drvdata(dev, vop);
1770
1771 vop_win_init(vop);
1772
1773 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1774 vop->len = resource_size(res);
1775 vop->regs = devm_ioremap_resource(dev, res);
1776 if (IS_ERR(vop->regs))
1777 return PTR_ERR(vop->regs);
1778
1779 vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
1780 if (!vop->regsbak)
1781 return -ENOMEM;
1782
1783 irq = platform_get_irq(pdev, 0);
1784 if (irq < 0) {
1785 DRM_DEV_ERROR(dev, "cannot find irq for vop\n");
1786 return irq;
1787 }
1788 vop->irq = (unsigned int)irq;
1789
1790 spin_lock_init(&vop->reg_lock);
1791 spin_lock_init(&vop->irq_lock);
1792 mutex_init(&vop->vop_lock);
1793
1794 ret = vop_create_crtc(vop);
1795 if (ret)
1796 return ret;
1797
1798 pm_runtime_enable(&pdev->dev);
1799
1800 ret = vop_initial(vop);
1801 if (ret < 0) {
1802 DRM_DEV_ERROR(&pdev->dev,
1803 "cannot initial vop dev - err %d\n", ret);
1804 goto err_disable_pm_runtime;
1805 }
1806
1807 ret = devm_request_irq(dev, vop->irq, vop_isr,
1808 IRQF_SHARED, dev_name(dev), vop);
1809 if (ret)
1810 goto err_disable_pm_runtime;
1811
1812 if (vop->data->feature & VOP_FEATURE_INTERNAL_RGB) {
1813 vop->rgb = rockchip_rgb_init(dev, &vop->crtc, vop->drm_dev);
1814 if (IS_ERR(vop->rgb)) {
1815 ret = PTR_ERR(vop->rgb);
1816 goto err_disable_pm_runtime;
1817 }
1818 }
1819
1820 return 0;
1821
1822err_disable_pm_runtime:
1823 pm_runtime_disable(&pdev->dev);
1824 vop_destroy_crtc(vop);
1825 return ret;
1826}
1827
1828static void vop_unbind(struct device *dev, struct device *master, void *data)
1829{
1830 struct vop *vop = dev_get_drvdata(dev);
1831
1832 if (vop->rgb)
1833 rockchip_rgb_fini(vop->rgb);
1834
1835 pm_runtime_disable(dev);
1836 vop_destroy_crtc(vop);
1837
1838 clk_unprepare(vop->aclk);
1839 clk_unprepare(vop->hclk);
1840 clk_unprepare(vop->dclk);
1841}
1842
1843const struct component_ops vop_component_ops = {
1844 .bind = vop_bind,
1845 .unbind = vop_unbind,
1846};
1847EXPORT_SYMBOL_GPL(vop_component_ops);
1848