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7#include <linux/clk.h>
8#include <linux/debugfs.h>
9#include <linux/gpio.h>
10#include <linux/hdmi.h>
11#include <linux/math64.h>
12#include <linux/of_device.h>
13#include <linux/pm_runtime.h>
14#include <linux/regulator/consumer.h>
15#include <linux/reset.h>
16
17#include <drm/drm_atomic_helper.h>
18#include <drm/drm_crtc.h>
19#include <drm/drm_probe_helper.h>
20
21#include "hda.h"
22#include "hdmi.h"
23#include "drm.h"
24#include "dc.h"
25#include "trace.h"
26
27#define HDMI_ELD_BUFFER_SIZE 96
28
29struct tmds_config {
30 unsigned int pclk;
31 u32 pll0;
32 u32 pll1;
33 u32 pe_current;
34 u32 drive_current;
35 u32 peak_current;
36};
37
38struct tegra_hdmi_config {
39 const struct tmds_config *tmds;
40 unsigned int num_tmds;
41
42 unsigned long fuse_override_offset;
43 u32 fuse_override_value;
44
45 bool has_sor_io_peak_current;
46 bool has_hda;
47 bool has_hbr;
48};
49
50struct tegra_hdmi {
51 struct host1x_client client;
52 struct tegra_output output;
53 struct device *dev;
54
55 struct regulator *hdmi;
56 struct regulator *pll;
57 struct regulator *vdd;
58
59 void __iomem *regs;
60 unsigned int irq;
61
62 struct clk *clk_parent;
63 struct clk *clk;
64 struct reset_control *rst;
65
66 const struct tegra_hdmi_config *config;
67
68 unsigned int audio_source;
69 struct tegra_hda_format format;
70
71 unsigned int pixel_clock;
72 bool stereo;
73 bool dvi;
74
75 struct drm_info_list *debugfs_files;
76};
77
78static inline struct tegra_hdmi *
79host1x_client_to_hdmi(struct host1x_client *client)
80{
81 return container_of(client, struct tegra_hdmi, client);
82}
83
84static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
85{
86 return container_of(output, struct tegra_hdmi, output);
87}
88
89#define HDMI_AUDIOCLK_FREQ 216000000
90#define HDMI_REKEY_DEFAULT 56
91
92enum {
93 AUTO = 0,
94 SPDIF,
95 HDA,
96};
97
98static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
99 unsigned int offset)
100{
101 u32 value = readl(hdmi->regs + (offset << 2));
102
103 trace_hdmi_readl(hdmi->dev, offset, value);
104
105 return value;
106}
107
108static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
109 unsigned int offset)
110{
111 trace_hdmi_writel(hdmi->dev, offset, value);
112 writel(value, hdmi->regs + (offset << 2));
113}
114
115struct tegra_hdmi_audio_config {
116 unsigned int n;
117 unsigned int cts;
118 unsigned int aval;
119};
120
121static const struct tmds_config tegra20_tmds_config[] = {
122 {
123 .pclk = 27000000,
124 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
125 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
126 SOR_PLL_TX_REG_LOAD(3),
127 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
128 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
129 PE_CURRENT1(PE_CURRENT_0_0_mA) |
130 PE_CURRENT2(PE_CURRENT_0_0_mA) |
131 PE_CURRENT3(PE_CURRENT_0_0_mA),
132 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
133 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
134 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
135 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
136 },
137 {
138 .pclk = UINT_MAX,
139 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
140 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
141 SOR_PLL_TX_REG_LOAD(3),
142 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
143 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
144 PE_CURRENT1(PE_CURRENT_6_0_mA) |
145 PE_CURRENT2(PE_CURRENT_6_0_mA) |
146 PE_CURRENT3(PE_CURRENT_6_0_mA),
147 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
148 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
149 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
150 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
151 },
152};
153
154static const struct tmds_config tegra30_tmds_config[] = {
155 {
156 .pclk = 27000000,
157 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
158 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
159 SOR_PLL_TX_REG_LOAD(0),
160 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
161 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
162 PE_CURRENT1(PE_CURRENT_0_0_mA) |
163 PE_CURRENT2(PE_CURRENT_0_0_mA) |
164 PE_CURRENT3(PE_CURRENT_0_0_mA),
165 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
166 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
167 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
168 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
169 }, {
170 .pclk = 74250000,
171 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
172 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
173 SOR_PLL_TX_REG_LOAD(0),
174 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
175 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
176 PE_CURRENT1(PE_CURRENT_5_0_mA) |
177 PE_CURRENT2(PE_CURRENT_5_0_mA) |
178 PE_CURRENT3(PE_CURRENT_5_0_mA),
179 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
180 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
181 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
182 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
183 }, {
184 .pclk = UINT_MAX,
185 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
186 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
187 SOR_PLL_TX_REG_LOAD(0),
188 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
189 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
190 PE_CURRENT1(PE_CURRENT_5_0_mA) |
191 PE_CURRENT2(PE_CURRENT_5_0_mA) |
192 PE_CURRENT3(PE_CURRENT_5_0_mA),
193 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
194 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
195 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
196 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
197 },
198};
199
200static const struct tmds_config tegra114_tmds_config[] = {
201 {
202 .pclk = 27000000,
203 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
204 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
205 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
206 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
207 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
208 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
209 PE_CURRENT3(PE_CURRENT_0_mA_T114),
210 .drive_current =
211 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
212 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
213 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
214 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
215 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
216 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
217 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
218 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
219 }, {
220 .pclk = 74250000,
221 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
222 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
223 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
224 SOR_PLL_TMDS_TERMADJ(0),
225 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
226 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
227 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
228 PE_CURRENT3(PE_CURRENT_15_mA_T114),
229 .drive_current =
230 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
231 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
232 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
233 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
234 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
235 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
236 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
237 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
238 }, {
239 .pclk = 148500000,
240 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
241 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
242 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
243 SOR_PLL_TMDS_TERMADJ(0),
244 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
245 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
246 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
247 PE_CURRENT3(PE_CURRENT_10_mA_T114),
248 .drive_current =
249 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
250 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
251 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
252 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
253 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
254 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
255 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
256 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
257 }, {
258 .pclk = UINT_MAX,
259 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
260 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
261 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
262 | SOR_PLL_TMDS_TERM_ENABLE,
263 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
264 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
265 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
266 PE_CURRENT3(PE_CURRENT_0_mA_T114),
267 .drive_current =
268 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
269 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
270 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
271 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
272 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
273 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
274 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
275 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
276 },
277};
278
279static const struct tmds_config tegra124_tmds_config[] = {
280 {
281 .pclk = 27000000,
282 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
283 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
284 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
285 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
286 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
287 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
288 PE_CURRENT3(PE_CURRENT_0_mA_T114),
289 .drive_current =
290 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
291 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
292 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
293 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
294 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
295 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
296 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
297 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
298 }, {
299 .pclk = 74250000,
300 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
301 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
302 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
303 SOR_PLL_TMDS_TERMADJ(0),
304 .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
305 PE_CURRENT1(PE_CURRENT_15_mA_T114) |
306 PE_CURRENT2(PE_CURRENT_15_mA_T114) |
307 PE_CURRENT3(PE_CURRENT_15_mA_T114),
308 .drive_current =
309 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
310 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
311 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
312 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
313 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
314 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
315 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
316 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
317 }, {
318 .pclk = 148500000,
319 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
320 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
321 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
322 SOR_PLL_TMDS_TERMADJ(0),
323 .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
324 PE_CURRENT1(PE_CURRENT_10_mA_T114) |
325 PE_CURRENT2(PE_CURRENT_10_mA_T114) |
326 PE_CURRENT3(PE_CURRENT_10_mA_T114),
327 .drive_current =
328 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
329 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
330 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
331 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
332 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
333 PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
334 PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
335 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
336 }, {
337 .pclk = UINT_MAX,
338 .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
339 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
340 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
341 | SOR_PLL_TMDS_TERM_ENABLE,
342 .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
343 PE_CURRENT1(PE_CURRENT_0_mA_T114) |
344 PE_CURRENT2(PE_CURRENT_0_mA_T114) |
345 PE_CURRENT3(PE_CURRENT_0_mA_T114),
346 .drive_current =
347 DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
348 DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
349 DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
350 DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
351 .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
352 PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
353 PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
354 PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
355 },
356};
357
358static int
359tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
360 struct tegra_hdmi_audio_config *config)
361{
362 const unsigned int afreq = 128 * audio_freq;
363 const unsigned int min_n = afreq / 1500;
364 const unsigned int max_n = afreq / 300;
365 const unsigned int ideal_n = afreq / 1000;
366 int64_t min_err = (uint64_t)-1 >> 1;
367 unsigned int min_delta = -1;
368 int n;
369
370 memset(config, 0, sizeof(*config));
371 config->n = -1;
372
373 for (n = min_n; n <= max_n; n++) {
374 uint64_t cts_f, aval_f;
375 unsigned int delta;
376 int64_t cts, err;
377
378
379 aval_f = ((int64_t)24000000 << 16) * n;
380 do_div(aval_f, afreq);
381
382 if (aval_f & 0xFFFF)
383 continue;
384
385
386 cts_f = ((int64_t)pix_clock << 16) * n;
387 do_div(cts_f, afreq);
388
389 cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
390
391 delta = abs(n - ideal_n);
392
393
394 err = abs((int64_t)cts_f - cts);
395 if (err < min_err || (err == min_err && delta < min_delta)) {
396 config->n = n;
397 config->cts = cts >> 16;
398 config->aval = aval_f >> 16;
399 min_delta = delta;
400 min_err = err;
401 }
402 }
403
404 return config->n != -1 ? 0 : -EINVAL;
405}
406
407static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
408{
409 const unsigned int freqs[] = {
410 32000, 44100, 48000, 88200, 96000, 176400, 192000
411 };
412 unsigned int i;
413
414 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
415 unsigned int f = freqs[i];
416 unsigned int eight_half;
417 unsigned int delta;
418 u32 value;
419
420 if (f > 96000)
421 delta = 2;
422 else if (f > 48000)
423 delta = 6;
424 else
425 delta = 9;
426
427 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
428 value = AUDIO_FS_LOW(eight_half - delta) |
429 AUDIO_FS_HIGH(eight_half + delta);
430 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
431 }
432}
433
434static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
435{
436 static const struct {
437 unsigned int sample_rate;
438 unsigned int offset;
439 } regs[] = {
440 { 32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
441 { 44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
442 { 48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
443 { 88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
444 { 96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
445 { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
446 { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
447 };
448 unsigned int i;
449
450 for (i = 0; i < ARRAY_SIZE(regs); i++) {
451 if (regs[i].sample_rate == hdmi->format.sample_rate) {
452 tegra_hdmi_writel(hdmi, value, regs[i].offset);
453 break;
454 }
455 }
456}
457
458static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
459{
460 struct tegra_hdmi_audio_config config;
461 u32 source, value;
462 int err;
463
464 switch (hdmi->audio_source) {
465 case HDA:
466 if (hdmi->config->has_hda)
467 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
468 else
469 return -EINVAL;
470
471 break;
472
473 case SPDIF:
474 if (hdmi->config->has_hda)
475 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
476 else
477 source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
478 break;
479
480 default:
481 if (hdmi->config->has_hda)
482 source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
483 else
484 source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
485 break;
486 }
487
488
489
490
491
492
493
494
495 if (hdmi->config->has_hda) {
496
497
498
499
500
501
502
503
504
505
506 if (hdmi->format.channels == 2)
507 value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
508 else
509 value = 0;
510
511 value |= source;
512
513 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
514 }
515
516
517
518
519
520 value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
521 AUDIO_CNTRL0_ERROR_TOLERANCE(6);
522
523 if (!hdmi->config->has_hda)
524 value |= source;
525
526 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
527
528
529
530
531 if (hdmi->config->has_hbr) {
532 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
533 value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
534 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
535 }
536
537 err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
538 hdmi->pixel_clock, &config);
539 if (err < 0) {
540 dev_err(hdmi->dev,
541 "cannot set audio to %u Hz at %u Hz pixel clock\n",
542 hdmi->format.sample_rate, hdmi->pixel_clock);
543 return err;
544 }
545
546 dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
547 hdmi->pixel_clock, config.n, config.cts, config.aval);
548
549 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
550
551 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
552 AUDIO_N_VALUE(config.n - 1);
553 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
554
555 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
556 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
557
558 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
559 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
560
561 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
562 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
563
564 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
565 value &= ~AUDIO_N_RESETF;
566 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
567
568 if (hdmi->config->has_hda)
569 tegra_hdmi_write_aval(hdmi, config.aval);
570
571 tegra_hdmi_setup_audio_fs_tables(hdmi);
572
573 return 0;
574}
575
576static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
577{
578 u32 value;
579
580 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
581 value &= ~GENERIC_CTRL_AUDIO;
582 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
583}
584
585static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
586{
587 u32 value;
588
589 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
590 value |= GENERIC_CTRL_AUDIO;
591 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
592}
593
594static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
595{
596 size_t length = drm_eld_size(hdmi->output.connector.eld), i;
597 u32 value;
598
599 for (i = 0; i < length; i++)
600 tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
601 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
602
603
604
605
606
607
608
609 for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
610 tegra_hdmi_writel(hdmi, i << 8 | 0,
611 HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
612
613 value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
614 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
615}
616
617static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
618{
619 u32 value = 0;
620 size_t i;
621
622 for (i = size; i > 0; i--)
623 value = (value << 8) | ptr[i - 1];
624
625 return value;
626}
627
628static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
629 size_t size)
630{
631 const u8 *ptr = data;
632 unsigned long offset;
633 size_t i, j;
634 u32 value;
635
636 switch (ptr[0]) {
637 case HDMI_INFOFRAME_TYPE_AVI:
638 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
639 break;
640
641 case HDMI_INFOFRAME_TYPE_AUDIO:
642 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
643 break;
644
645 case HDMI_INFOFRAME_TYPE_VENDOR:
646 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
647 break;
648
649 default:
650 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
651 ptr[0]);
652 return;
653 }
654
655 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
656 INFOFRAME_HEADER_VERSION(ptr[1]) |
657 INFOFRAME_HEADER_LEN(ptr[2]);
658 tegra_hdmi_writel(hdmi, value, offset);
659 offset++;
660
661
662
663
664
665
666 for (i = 3, j = 0; i < size; i += 7, j += 8) {
667 size_t rem = size - i, num = min_t(size_t, rem, 4);
668
669 value = tegra_hdmi_subpack(&ptr[i], num);
670 tegra_hdmi_writel(hdmi, value, offset++);
671
672 num = min_t(size_t, rem - num, 3);
673
674 value = tegra_hdmi_subpack(&ptr[i + 4], num);
675 tegra_hdmi_writel(hdmi, value, offset++);
676 }
677}
678
679static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
680 struct drm_display_mode *mode)
681{
682 struct hdmi_avi_infoframe frame;
683 u8 buffer[17];
684 ssize_t err;
685
686 err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
687 &hdmi->output.connector, mode);
688 if (err < 0) {
689 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
690 return;
691 }
692
693 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
694 if (err < 0) {
695 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
696 return;
697 }
698
699 tegra_hdmi_write_infopack(hdmi, buffer, err);
700}
701
702static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
703{
704 u32 value;
705
706 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
707 value &= ~INFOFRAME_CTRL_ENABLE;
708 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
709}
710
711static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
712{
713 u32 value;
714
715 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
716 value |= INFOFRAME_CTRL_ENABLE;
717 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
718}
719
720static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
721{
722 struct hdmi_audio_infoframe frame;
723 u8 buffer[14];
724 ssize_t err;
725
726 err = hdmi_audio_infoframe_init(&frame);
727 if (err < 0) {
728 dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
729 err);
730 return;
731 }
732
733 frame.channels = hdmi->format.channels;
734
735 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
736 if (err < 0) {
737 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
738 err);
739 return;
740 }
741
742
743
744
745
746
747
748 tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
749}
750
751static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
752{
753 u32 value;
754
755 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
756 value &= ~INFOFRAME_CTRL_ENABLE;
757 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
758}
759
760static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
761{
762 u32 value;
763
764 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
765 value |= INFOFRAME_CTRL_ENABLE;
766 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
767}
768
769static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
770{
771 struct hdmi_vendor_infoframe frame;
772 u8 buffer[10];
773 ssize_t err;
774
775 hdmi_vendor_infoframe_init(&frame);
776 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
777
778 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
779 if (err < 0) {
780 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
781 err);
782 return;
783 }
784
785 tegra_hdmi_write_infopack(hdmi, buffer, err);
786}
787
788static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
789{
790 u32 value;
791
792 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
793 value &= ~GENERIC_CTRL_ENABLE;
794 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
795}
796
797static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
798{
799 u32 value;
800
801 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
802 value |= GENERIC_CTRL_ENABLE;
803 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
804}
805
806static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
807 const struct tmds_config *tmds)
808{
809 u32 value;
810
811 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
812 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
813 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
814
815 tegra_hdmi_writel(hdmi, tmds->drive_current,
816 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
817
818 value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
819 value |= hdmi->config->fuse_override_value;
820 tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
821
822 if (hdmi->config->has_sor_io_peak_current)
823 tegra_hdmi_writel(hdmi, tmds->peak_current,
824 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
825}
826
827static bool tegra_output_is_hdmi(struct tegra_output *output)
828{
829 struct edid *edid;
830
831 if (!output->connector.edid_blob_ptr)
832 return false;
833
834 edid = (struct edid *)output->connector.edid_blob_ptr->data;
835
836 return drm_detect_hdmi_monitor(edid);
837}
838
839static enum drm_connector_status
840tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
841{
842 struct tegra_output *output = connector_to_output(connector);
843 struct tegra_hdmi *hdmi = to_hdmi(output);
844 enum drm_connector_status status;
845
846 status = tegra_output_connector_detect(connector, force);
847 if (status == connector_status_connected)
848 return status;
849
850 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
851 return status;
852}
853
854#define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
855
856static const struct debugfs_reg32 tegra_hdmi_regs[] = {
857 DEBUGFS_REG32(HDMI_CTXSW),
858 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
859 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
860 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
861 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
862 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
863 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
864 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
865 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
866 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
867 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
868 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
869 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
870 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
871 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
872 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
873 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
874 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
875 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
876 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
877 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
878 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
879 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
880 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
881 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
882 DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
883 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
884 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
885 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
886 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
887 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
888 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
889 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
890 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
891 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
892 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
893 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
894 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
895 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
896 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
897 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
898 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
899 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
900 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
901 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
902 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
903 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
904 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
905 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
906 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
907 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
908 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
909 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
910 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
911 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
912 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
913 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
914 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
915 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
916 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
917 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
918 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
919 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
920 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
921 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
922 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
923 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
924 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
925 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
926 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
927 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
928 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
929 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
930 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
931 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
932 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
933 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
934 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
935 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
936 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
937 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
938 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
939 DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
940 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
941 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
942 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
943 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
944 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
945 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
946 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
947 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
948 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
949 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
950 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
951 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
952 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
953 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
954 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
955 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
956 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
957 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
958 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
959 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
960 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
961 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
962 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
963 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
964 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
965 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
966 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
967 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
968 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
969 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
970 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
971 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
972 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
973 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
974 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
975 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
976 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
977 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
978 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
979 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
980 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
981 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
982 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
983 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
984 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
985 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
986 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
987 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
988 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
989 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
990 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
991 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
992 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
993 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
994 DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
995 DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
996 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
997 DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
998 DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
999 DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1000 DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1001 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1002 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1003 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1004 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1005 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1006 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1007 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1008 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1009 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1010 DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1011 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1012 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1013 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1014 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1015 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1016 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1017 DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1018 DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1019 DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1020 DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1021};
1022
1023static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1024{
1025 struct drm_info_node *node = s->private;
1026 struct tegra_hdmi *hdmi = node->info_ent->data;
1027 struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1028 struct drm_device *drm = node->minor->dev;
1029 unsigned int i;
1030 int err = 0;
1031
1032 drm_modeset_lock_all(drm);
1033
1034 if (!crtc || !crtc->state->active) {
1035 err = -EBUSY;
1036 goto unlock;
1037 }
1038
1039 for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1040 unsigned int offset = tegra_hdmi_regs[i].offset;
1041
1042 seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1043 offset, tegra_hdmi_readl(hdmi, offset));
1044 }
1045
1046unlock:
1047 drm_modeset_unlock_all(drm);
1048 return err;
1049}
1050
1051static struct drm_info_list debugfs_files[] = {
1052 { "regs", tegra_hdmi_show_regs, 0, NULL },
1053};
1054
1055static int tegra_hdmi_late_register(struct drm_connector *connector)
1056{
1057 struct tegra_output *output = connector_to_output(connector);
1058 unsigned int i, count = ARRAY_SIZE(debugfs_files);
1059 struct drm_minor *minor = connector->dev->primary;
1060 struct dentry *root = connector->debugfs_entry;
1061 struct tegra_hdmi *hdmi = to_hdmi(output);
1062 int err;
1063
1064 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1065 GFP_KERNEL);
1066 if (!hdmi->debugfs_files)
1067 return -ENOMEM;
1068
1069 for (i = 0; i < count; i++)
1070 hdmi->debugfs_files[i].data = hdmi;
1071
1072 err = drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1073 if (err < 0)
1074 goto free;
1075
1076 return 0;
1077
1078free:
1079 kfree(hdmi->debugfs_files);
1080 hdmi->debugfs_files = NULL;
1081
1082 return err;
1083}
1084
1085static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1086{
1087 struct tegra_output *output = connector_to_output(connector);
1088 struct drm_minor *minor = connector->dev->primary;
1089 unsigned int count = ARRAY_SIZE(debugfs_files);
1090 struct tegra_hdmi *hdmi = to_hdmi(output);
1091
1092 drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1093 kfree(hdmi->debugfs_files);
1094 hdmi->debugfs_files = NULL;
1095}
1096
1097static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1098 .reset = drm_atomic_helper_connector_reset,
1099 .detect = tegra_hdmi_connector_detect,
1100 .fill_modes = drm_helper_probe_single_connector_modes,
1101 .destroy = tegra_output_connector_destroy,
1102 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1103 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1104 .late_register = tegra_hdmi_late_register,
1105 .early_unregister = tegra_hdmi_early_unregister,
1106};
1107
1108static enum drm_mode_status
1109tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1110 struct drm_display_mode *mode)
1111{
1112 struct tegra_output *output = connector_to_output(connector);
1113 struct tegra_hdmi *hdmi = to_hdmi(output);
1114 unsigned long pclk = mode->clock * 1000;
1115 enum drm_mode_status status = MODE_OK;
1116 struct clk *parent;
1117 long err;
1118
1119 parent = clk_get_parent(hdmi->clk_parent);
1120
1121 err = clk_round_rate(parent, pclk * 4);
1122 if (err <= 0)
1123 status = MODE_NOCLOCK;
1124
1125 return status;
1126}
1127
1128static const struct drm_connector_helper_funcs
1129tegra_hdmi_connector_helper_funcs = {
1130 .get_modes = tegra_output_connector_get_modes,
1131 .mode_valid = tegra_hdmi_connector_mode_valid,
1132};
1133
1134static const struct drm_encoder_funcs tegra_hdmi_encoder_funcs = {
1135 .destroy = tegra_output_encoder_destroy,
1136};
1137
1138static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1139{
1140 struct tegra_output *output = encoder_to_output(encoder);
1141 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1142 struct tegra_hdmi *hdmi = to_hdmi(output);
1143 u32 value;
1144
1145
1146
1147
1148
1149 if (dc) {
1150 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1151 value &= ~HDMI_ENABLE;
1152 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1153
1154 tegra_dc_commit(dc);
1155 }
1156
1157 if (!hdmi->dvi) {
1158 if (hdmi->stereo)
1159 tegra_hdmi_disable_stereo_infoframe(hdmi);
1160
1161 tegra_hdmi_disable_audio_infoframe(hdmi);
1162 tegra_hdmi_disable_avi_infoframe(hdmi);
1163 tegra_hdmi_disable_audio(hdmi);
1164 }
1165
1166 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1167 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1168
1169 pm_runtime_put(hdmi->dev);
1170}
1171
1172static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1173{
1174 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1175 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1176 struct tegra_output *output = encoder_to_output(encoder);
1177 struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1178 struct tegra_hdmi *hdmi = to_hdmi(output);
1179 unsigned int pulse_start, div82;
1180 int retries = 1000;
1181 u32 value;
1182 int err;
1183
1184 pm_runtime_get_sync(hdmi->dev);
1185
1186
1187
1188
1189
1190
1191 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1192 tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1193
1194 hdmi->pixel_clock = mode->clock * 1000;
1195 h_sync_width = mode->hsync_end - mode->hsync_start;
1196 h_back_porch = mode->htotal - mode->hsync_end;
1197 h_front_porch = mode->hsync_start - mode->hdisplay;
1198
1199 err = clk_set_rate(hdmi->clk, hdmi->pixel_clock);
1200 if (err < 0) {
1201 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1202 err);
1203 }
1204
1205 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1206
1207
1208 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1209 value &= ~SOR_PLL_PDBG;
1210 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1211
1212 usleep_range(10, 20);
1213
1214 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1215 value &= ~SOR_PLL_PWR;
1216 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1217
1218 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1219 DC_DISP_DISP_TIMING_OPTIONS);
1220 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1221 DC_DISP_DISP_COLOR_CONTROL);
1222
1223
1224 pulse_start = 1 + h_sync_width + h_back_porch - 10;
1225
1226 tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1227
1228 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1229 PULSE_LAST_END_A;
1230 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1231
1232 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1233 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1234
1235 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1236 VSYNC_WINDOW_ENABLE;
1237 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1238
1239 if (dc->pipe)
1240 value = HDMI_SRC_DISPLAYB;
1241 else
1242 value = HDMI_SRC_DISPLAYA;
1243
1244 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1245 (mode->vdisplay == 576)))
1246 tegra_hdmi_writel(hdmi,
1247 value | ARM_VIDEO_RANGE_FULL,
1248 HDMI_NV_PDISP_INPUT_CONTROL);
1249 else
1250 tegra_hdmi_writel(hdmi,
1251 value | ARM_VIDEO_RANGE_LIMITED,
1252 HDMI_NV_PDISP_INPUT_CONTROL);
1253
1254 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1255 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1256 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1257
1258 hdmi->dvi = !tegra_output_is_hdmi(output);
1259 if (!hdmi->dvi) {
1260
1261
1262
1263
1264 if (hdmi->format.sample_rate > 0) {
1265 err = tegra_hdmi_setup_audio(hdmi);
1266 if (err < 0)
1267 hdmi->dvi = true;
1268 }
1269 }
1270
1271 if (hdmi->config->has_hda)
1272 tegra_hdmi_write_eld(hdmi);
1273
1274 rekey = HDMI_REKEY_DEFAULT;
1275 value = HDMI_CTRL_REKEY(rekey);
1276 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1277 h_front_porch - rekey - 18) / 32);
1278
1279 if (!hdmi->dvi)
1280 value |= HDMI_CTRL_ENABLE;
1281
1282 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1283
1284 if (!hdmi->dvi) {
1285 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1286 tegra_hdmi_setup_audio_infoframe(hdmi);
1287
1288 if (hdmi->stereo)
1289 tegra_hdmi_setup_stereo_infoframe(hdmi);
1290 }
1291
1292
1293 for (i = 0; i < hdmi->config->num_tmds; i++) {
1294 if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1295 tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1296 break;
1297 }
1298 }
1299
1300 tegra_hdmi_writel(hdmi,
1301 SOR_SEQ_PU_PC(0) |
1302 SOR_SEQ_PU_PC_ALT(0) |
1303 SOR_SEQ_PD_PC(8) |
1304 SOR_SEQ_PD_PC_ALT(8),
1305 HDMI_NV_PDISP_SOR_SEQ_CTL);
1306
1307 value = SOR_SEQ_INST_WAIT_TIME(1) |
1308 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1309 SOR_SEQ_INST_HALT |
1310 SOR_SEQ_INST_PIN_A_LOW |
1311 SOR_SEQ_INST_PIN_B_LOW |
1312 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1313
1314 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1315 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1316
1317 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1318 value &= ~SOR_CSTM_ROTCLK(~0);
1319 value |= SOR_CSTM_ROTCLK(2);
1320 value |= SOR_CSTM_PLLDIV;
1321 value &= ~SOR_CSTM_LVDS_ENABLE;
1322 value &= ~SOR_CSTM_MODE_MASK;
1323 value |= SOR_CSTM_MODE_TMDS;
1324 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1325
1326
1327 tegra_hdmi_writel(hdmi,
1328 SOR_PWR_NORMAL_STATE_PU |
1329 SOR_PWR_NORMAL_START_NORMAL |
1330 SOR_PWR_SAFE_STATE_PD |
1331 SOR_PWR_SETTING_NEW_TRIGGER,
1332 HDMI_NV_PDISP_SOR_PWR);
1333 tegra_hdmi_writel(hdmi,
1334 SOR_PWR_NORMAL_STATE_PU |
1335 SOR_PWR_NORMAL_START_NORMAL |
1336 SOR_PWR_SAFE_STATE_PD |
1337 SOR_PWR_SETTING_NEW_DONE,
1338 HDMI_NV_PDISP_SOR_PWR);
1339
1340 do {
1341 BUG_ON(--retries < 0);
1342 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1343 } while (value & SOR_PWR_SETTING_NEW_PENDING);
1344
1345 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1346 SOR_STATE_ASY_OWNER_HEAD0 |
1347 SOR_STATE_ASY_SUBOWNER_BOTH |
1348 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1349 SOR_STATE_ASY_DEPOL_POS;
1350
1351
1352 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1353 value |= SOR_STATE_ASY_HSYNCPOL_POS;
1354
1355 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1356 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1357
1358 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1359 value |= SOR_STATE_ASY_VSYNCPOL_POS;
1360
1361 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1362 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1363
1364 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1365
1366 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1367 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1368
1369 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1370 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1371 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1372 HDMI_NV_PDISP_SOR_STATE1);
1373 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1374
1375 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1376 value |= HDMI_ENABLE;
1377 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1378
1379 tegra_dc_commit(dc);
1380
1381 if (!hdmi->dvi) {
1382 tegra_hdmi_enable_avi_infoframe(hdmi);
1383 tegra_hdmi_enable_audio_infoframe(hdmi);
1384 tegra_hdmi_enable_audio(hdmi);
1385
1386 if (hdmi->stereo)
1387 tegra_hdmi_enable_stereo_infoframe(hdmi);
1388 }
1389
1390
1391}
1392
1393static int
1394tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1395 struct drm_crtc_state *crtc_state,
1396 struct drm_connector_state *conn_state)
1397{
1398 struct tegra_output *output = encoder_to_output(encoder);
1399 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1400 unsigned long pclk = crtc_state->mode.clock * 1000;
1401 struct tegra_hdmi *hdmi = to_hdmi(output);
1402 int err;
1403
1404 err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1405 pclk, 0);
1406 if (err < 0) {
1407 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1408 return err;
1409 }
1410
1411 return err;
1412}
1413
1414static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1415 .disable = tegra_hdmi_encoder_disable,
1416 .enable = tegra_hdmi_encoder_enable,
1417 .atomic_check = tegra_hdmi_encoder_atomic_check,
1418};
1419
1420static int tegra_hdmi_init(struct host1x_client *client)
1421{
1422 struct drm_device *drm = dev_get_drvdata(client->parent);
1423 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1424 int err;
1425
1426 hdmi->output.dev = client->dev;
1427
1428 drm_connector_init(drm, &hdmi->output.connector,
1429 &tegra_hdmi_connector_funcs,
1430 DRM_MODE_CONNECTOR_HDMIA);
1431 drm_connector_helper_add(&hdmi->output.connector,
1432 &tegra_hdmi_connector_helper_funcs);
1433 hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1434
1435 drm_encoder_init(drm, &hdmi->output.encoder, &tegra_hdmi_encoder_funcs,
1436 DRM_MODE_ENCODER_TMDS, NULL);
1437 drm_encoder_helper_add(&hdmi->output.encoder,
1438 &tegra_hdmi_encoder_helper_funcs);
1439
1440 drm_connector_attach_encoder(&hdmi->output.connector,
1441 &hdmi->output.encoder);
1442 drm_connector_register(&hdmi->output.connector);
1443
1444 err = tegra_output_init(drm, &hdmi->output);
1445 if (err < 0) {
1446 dev_err(client->dev, "failed to initialize output: %d\n", err);
1447 return err;
1448 }
1449
1450 hdmi->output.encoder.possible_crtcs = 0x3;
1451
1452 err = regulator_enable(hdmi->hdmi);
1453 if (err < 0) {
1454 dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1455 err);
1456 return err;
1457 }
1458
1459 err = regulator_enable(hdmi->pll);
1460 if (err < 0) {
1461 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1462 return err;
1463 }
1464
1465 err = regulator_enable(hdmi->vdd);
1466 if (err < 0) {
1467 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1468 return err;
1469 }
1470
1471 return 0;
1472}
1473
1474static int tegra_hdmi_exit(struct host1x_client *client)
1475{
1476 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1477
1478 tegra_output_exit(&hdmi->output);
1479
1480 regulator_disable(hdmi->vdd);
1481 regulator_disable(hdmi->pll);
1482 regulator_disable(hdmi->hdmi);
1483
1484 return 0;
1485}
1486
1487static const struct host1x_client_ops hdmi_client_ops = {
1488 .init = tegra_hdmi_init,
1489 .exit = tegra_hdmi_exit,
1490};
1491
1492static const struct tegra_hdmi_config tegra20_hdmi_config = {
1493 .tmds = tegra20_tmds_config,
1494 .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1495 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1496 .fuse_override_value = 1 << 31,
1497 .has_sor_io_peak_current = false,
1498 .has_hda = false,
1499 .has_hbr = false,
1500};
1501
1502static const struct tegra_hdmi_config tegra30_hdmi_config = {
1503 .tmds = tegra30_tmds_config,
1504 .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1505 .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1506 .fuse_override_value = 1 << 31,
1507 .has_sor_io_peak_current = false,
1508 .has_hda = true,
1509 .has_hbr = false,
1510};
1511
1512static const struct tegra_hdmi_config tegra114_hdmi_config = {
1513 .tmds = tegra114_tmds_config,
1514 .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1515 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1516 .fuse_override_value = 1 << 31,
1517 .has_sor_io_peak_current = true,
1518 .has_hda = true,
1519 .has_hbr = true,
1520};
1521
1522static const struct tegra_hdmi_config tegra124_hdmi_config = {
1523 .tmds = tegra124_tmds_config,
1524 .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1525 .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1526 .fuse_override_value = 1 << 31,
1527 .has_sor_io_peak_current = true,
1528 .has_hda = true,
1529 .has_hbr = true,
1530};
1531
1532static const struct of_device_id tegra_hdmi_of_match[] = {
1533 { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1534 { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1535 { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1536 { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1537 { },
1538};
1539MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1540
1541static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1542{
1543 struct tegra_hdmi *hdmi = data;
1544 u32 value;
1545 int err;
1546
1547 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1548 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1549
1550 if (value & INT_CODEC_SCRATCH0) {
1551 unsigned int format;
1552 u32 value;
1553
1554 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1555
1556 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1557 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1558
1559 tegra_hda_parse_format(format, &hdmi->format);
1560
1561 err = tegra_hdmi_setup_audio(hdmi);
1562 if (err < 0) {
1563 tegra_hdmi_disable_audio_infoframe(hdmi);
1564 tegra_hdmi_disable_audio(hdmi);
1565 } else {
1566 tegra_hdmi_setup_audio_infoframe(hdmi);
1567 tegra_hdmi_enable_audio_infoframe(hdmi);
1568 tegra_hdmi_enable_audio(hdmi);
1569 }
1570 } else {
1571 tegra_hdmi_disable_audio_infoframe(hdmi);
1572 tegra_hdmi_disable_audio(hdmi);
1573 }
1574 }
1575
1576 return IRQ_HANDLED;
1577}
1578
1579static int tegra_hdmi_probe(struct platform_device *pdev)
1580{
1581 struct tegra_hdmi *hdmi;
1582 struct resource *regs;
1583 int err;
1584
1585 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1586 if (!hdmi)
1587 return -ENOMEM;
1588
1589 hdmi->config = of_device_get_match_data(&pdev->dev);
1590 hdmi->dev = &pdev->dev;
1591
1592 hdmi->audio_source = AUTO;
1593 hdmi->stereo = false;
1594 hdmi->dvi = false;
1595
1596 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1597 if (IS_ERR(hdmi->clk)) {
1598 dev_err(&pdev->dev, "failed to get clock\n");
1599 return PTR_ERR(hdmi->clk);
1600 }
1601
1602 hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1603 if (IS_ERR(hdmi->rst)) {
1604 dev_err(&pdev->dev, "failed to get reset\n");
1605 return PTR_ERR(hdmi->rst);
1606 }
1607
1608 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1609 if (IS_ERR(hdmi->clk_parent))
1610 return PTR_ERR(hdmi->clk_parent);
1611
1612 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1613 if (err < 0) {
1614 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1615 return err;
1616 }
1617
1618 hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1619 if (IS_ERR(hdmi->hdmi)) {
1620 dev_err(&pdev->dev, "failed to get HDMI regulator\n");
1621 return PTR_ERR(hdmi->hdmi);
1622 }
1623
1624 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1625 if (IS_ERR(hdmi->pll)) {
1626 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1627 return PTR_ERR(hdmi->pll);
1628 }
1629
1630 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1631 if (IS_ERR(hdmi->vdd)) {
1632 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1633 return PTR_ERR(hdmi->vdd);
1634 }
1635
1636 hdmi->output.dev = &pdev->dev;
1637
1638 err = tegra_output_probe(&hdmi->output);
1639 if (err < 0)
1640 return err;
1641
1642 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1643 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1644 if (IS_ERR(hdmi->regs))
1645 return PTR_ERR(hdmi->regs);
1646
1647 err = platform_get_irq(pdev, 0);
1648 if (err < 0)
1649 return err;
1650
1651 hdmi->irq = err;
1652
1653 err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1654 dev_name(hdmi->dev), hdmi);
1655 if (err < 0) {
1656 dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1657 hdmi->irq, err);
1658 return err;
1659 }
1660
1661 platform_set_drvdata(pdev, hdmi);
1662 pm_runtime_enable(&pdev->dev);
1663
1664 INIT_LIST_HEAD(&hdmi->client.list);
1665 hdmi->client.ops = &hdmi_client_ops;
1666 hdmi->client.dev = &pdev->dev;
1667
1668 err = host1x_client_register(&hdmi->client);
1669 if (err < 0) {
1670 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1671 err);
1672 return err;
1673 }
1674
1675 return 0;
1676}
1677
1678static int tegra_hdmi_remove(struct platform_device *pdev)
1679{
1680 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1681 int err;
1682
1683 pm_runtime_disable(&pdev->dev);
1684
1685 err = host1x_client_unregister(&hdmi->client);
1686 if (err < 0) {
1687 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1688 err);
1689 return err;
1690 }
1691
1692 tegra_output_remove(&hdmi->output);
1693
1694 return 0;
1695}
1696
1697#ifdef CONFIG_PM
1698static int tegra_hdmi_suspend(struct device *dev)
1699{
1700 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1701 int err;
1702
1703 err = reset_control_assert(hdmi->rst);
1704 if (err < 0) {
1705 dev_err(dev, "failed to assert reset: %d\n", err);
1706 return err;
1707 }
1708
1709 usleep_range(1000, 2000);
1710
1711 clk_disable_unprepare(hdmi->clk);
1712
1713 return 0;
1714}
1715
1716static int tegra_hdmi_resume(struct device *dev)
1717{
1718 struct tegra_hdmi *hdmi = dev_get_drvdata(dev);
1719 int err;
1720
1721 err = clk_prepare_enable(hdmi->clk);
1722 if (err < 0) {
1723 dev_err(dev, "failed to enable clock: %d\n", err);
1724 return err;
1725 }
1726
1727 usleep_range(1000, 2000);
1728
1729 err = reset_control_deassert(hdmi->rst);
1730 if (err < 0) {
1731 dev_err(dev, "failed to deassert reset: %d\n", err);
1732 clk_disable_unprepare(hdmi->clk);
1733 return err;
1734 }
1735
1736 return 0;
1737}
1738#endif
1739
1740static const struct dev_pm_ops tegra_hdmi_pm_ops = {
1741 SET_RUNTIME_PM_OPS(tegra_hdmi_suspend, tegra_hdmi_resume, NULL)
1742};
1743
1744struct platform_driver tegra_hdmi_driver = {
1745 .driver = {
1746 .name = "tegra-hdmi",
1747 .of_match_table = tegra_hdmi_of_match,
1748 .pm = &tegra_hdmi_pm_ops,
1749 },
1750 .probe = tegra_hdmi_probe,
1751 .remove = tegra_hdmi_remove,
1752};
1753
