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8#include <linux/kernel.h>
9#include <linux/moduleparam.h>
10#include <linux/init.h>
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/io.h>
14#include <linux/err.h>
15#include <linux/fs.h>
16#include <linux/slab.h>
17#include <linux/delay.h>
18#include <linux/smp.h>
19#include <linux/sysfs.h>
20#include <linux/stat.h>
21#include <linux/pm_runtime.h>
22#include <linux/cpu.h>
23#include <linux/of.h>
24#include <linux/coresight.h>
25#include <linux/coresight-pmu.h>
26#include <linux/amba/bus.h>
27#include <linux/seq_file.h>
28#include <linux/uaccess.h>
29#include <linux/clk.h>
30#include <linux/perf_event.h>
31#include <asm/sections.h>
32
33#include "coresight-etm.h"
34#include "coresight-etm-perf.h"
35
36
37
38
39
40static int boot_enable;
41module_param_named(boot_enable, boot_enable, int, S_IRUGO);
42
43
44static int etm_count;
45static struct etm_drvdata *etmdrvdata[NR_CPUS];
46
47static enum cpuhp_state hp_online;
48
49
50
51
52
53
54static void etm_os_unlock(struct etm_drvdata *drvdata)
55{
56
57 etm_writel(drvdata, 0x0, ETMOSLAR);
58 drvdata->os_unlock = true;
59 isb();
60}
61
62static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
63{
64 u32 etmcr;
65
66
67 mb();
68 isb();
69 etmcr = etm_readl(drvdata, ETMCR);
70 etmcr |= ETMCR_PWD_DWN;
71 etm_writel(drvdata, etmcr, ETMCR);
72}
73
74static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
75{
76 u32 etmcr;
77
78 etmcr = etm_readl(drvdata, ETMCR);
79 etmcr &= ~ETMCR_PWD_DWN;
80 etm_writel(drvdata, etmcr, ETMCR);
81
82 mb();
83 isb();
84}
85
86static void etm_set_pwrup(struct etm_drvdata *drvdata)
87{
88 u32 etmpdcr;
89
90 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
91 etmpdcr |= ETMPDCR_PWD_UP;
92 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
93
94 mb();
95 isb();
96}
97
98static void etm_clr_pwrup(struct etm_drvdata *drvdata)
99{
100 u32 etmpdcr;
101
102
103 mb();
104 isb();
105 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
106 etmpdcr &= ~ETMPDCR_PWD_UP;
107 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
108}
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
125 int position, int value)
126{
127 int i;
128 u32 val;
129
130 for (i = TIMEOUT_US; i > 0; i--) {
131 val = etm_readl(drvdata, offset);
132
133 if (value) {
134 if (val & BIT(position))
135 return 0;
136
137 } else {
138 if (!(val & BIT(position)))
139 return 0;
140 }
141
142
143
144
145
146
147 if (i - 1)
148 udelay(1);
149 }
150
151 return -EAGAIN;
152}
153
154
155static void etm_set_prog(struct etm_drvdata *drvdata)
156{
157 u32 etmcr;
158
159 etmcr = etm_readl(drvdata, ETMCR);
160 etmcr |= ETMCR_ETM_PRG;
161 etm_writel(drvdata, etmcr, ETMCR);
162
163
164
165
166 isb();
167 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
168 dev_err(drvdata->dev,
169 "%s: timeout observed when probing at offset %#x\n",
170 __func__, ETMSR);
171 }
172}
173
174static void etm_clr_prog(struct etm_drvdata *drvdata)
175{
176 u32 etmcr;
177
178 etmcr = etm_readl(drvdata, ETMCR);
179 etmcr &= ~ETMCR_ETM_PRG;
180 etm_writel(drvdata, etmcr, ETMCR);
181
182
183
184
185 isb();
186 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
187 dev_err(drvdata->dev,
188 "%s: timeout observed when probing at offset %#x\n",
189 __func__, ETMSR);
190 }
191}
192
193void etm_set_default(struct etm_config *config)
194{
195 int i;
196
197 if (WARN_ON_ONCE(!config))
198 return;
199
200
201
202
203
204
205
206
207
208
209 config->enable_ctrl1 = BIT(24);
210 config->enable_ctrl2 = 0x0;
211 config->enable_event = ETM_HARD_WIRE_RES_A;
212
213 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
214 config->enable_event = ETM_HARD_WIRE_RES_A;
215
216 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
220 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
221 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
222 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
223
224 for (i = 0; i < ETM_MAX_CNTR; i++) {
225 config->cntr_rld_val[i] = 0x0;
226 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
227 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
228 config->cntr_val[i] = 0x0;
229 }
230
231 config->seq_curr_state = 0x0;
232 config->ctxid_idx = 0x0;
233 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
234 config->ctxid_pid[i] = 0x0;
235
236 config->ctxid_mask = 0x0;
237
238 config->sync_freq = 0x400;
239}
240
241void etm_config_trace_mode(struct etm_config *config)
242{
243 u32 flags, mode;
244
245 mode = config->mode;
246
247 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
248
249
250 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
251 return;
252
253
254 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
255 return;
256
257 flags = (1 << 0 |
258 3 << 3 |
259 0 << 5 |
260 0 << 7 |
261 0 << 8);
262
263
264 config->enable_ctrl2 = 0x0;
265
266
267 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
268
269
270
271
272
273
274
275
276
277
278
279
280
281 flags |= (0 << 12 | 1 << 10);
282
283 if (mode & ETM_MODE_EXCL_USER) {
284
285 flags |= (1 << 13 | 0 << 11);
286 } else {
287
288 flags |= (1 << 13 | 1 << 11);
289 }
290
291
292
293
294
295
296 config->addr_val[0] = (u32) 0x0;
297 config->addr_val[1] = (u32) ~0x0;
298 config->addr_acctype[0] = flags;
299 config->addr_acctype[1] = flags;
300 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
301 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
302}
303
304#define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
305 ETMCR_TIMESTAMP_EN | \
306 ETMCR_RETURN_STACK)
307
308static int etm_parse_event_config(struct etm_drvdata *drvdata,
309 struct perf_event *event)
310{
311 struct etm_config *config = &drvdata->config;
312 struct perf_event_attr *attr = &event->attr;
313
314 if (!attr)
315 return -EINVAL;
316
317
318 memset(config, 0, sizeof(struct etm_config));
319
320 if (attr->exclude_kernel)
321 config->mode = ETM_MODE_EXCL_KERN;
322
323 if (attr->exclude_user)
324 config->mode = ETM_MODE_EXCL_USER;
325
326
327 etm_set_default(config);
328
329
330
331
332
333 if (config->mode)
334 etm_config_trace_mode(config);
335
336
337
338
339
340 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
341 return -EINVAL;
342
343 config->ctrl = attr->config;
344
345
346
347
348
349
350
351 if ((config->ctrl & ETMCR_RETURN_STACK) &&
352 !(drvdata->etmccer & ETMCCER_RETSTACK))
353 config->ctrl &= ~ETMCR_RETURN_STACK;
354
355 return 0;
356}
357
358static int etm_enable_hw(struct etm_drvdata *drvdata)
359{
360 int i, rc;
361 u32 etmcr;
362 struct etm_config *config = &drvdata->config;
363
364 CS_UNLOCK(drvdata->base);
365
366 rc = coresight_claim_device_unlocked(drvdata->base);
367 if (rc)
368 goto done;
369
370
371 etm_clr_pwrdwn(drvdata);
372
373 etm_set_pwrup(drvdata);
374
375 etm_os_unlock(drvdata);
376
377 etm_set_prog(drvdata);
378
379 etmcr = etm_readl(drvdata, ETMCR);
380
381 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
382 etmcr |= drvdata->port_size;
383 etmcr |= ETMCR_ETM_EN;
384 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
385 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
386 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
387 etm_writel(drvdata, config->enable_event, ETMTEEVR);
388 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
389 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
390 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
391 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
392 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
393 }
394 for (i = 0; i < drvdata->nr_cntr; i++) {
395 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
396 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
397 etm_writel(drvdata, config->cntr_rld_event[i],
398 ETMCNTRLDEVRn(i));
399 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
400 }
401 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
402 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
403 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
404 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
405 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
406 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
407 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
408 for (i = 0; i < drvdata->nr_ext_out; i++)
409 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
410 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
411 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
412 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
413 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
414
415 etm_writel(drvdata, 0x0, ETMEXTINSELR);
416 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
417
418 etm_writel(drvdata, 0x0, ETMAUXCR);
419 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
420
421 etm_writel(drvdata, 0x0, ETMVMIDCVR);
422
423 etm_clr_prog(drvdata);
424
425done:
426 CS_LOCK(drvdata->base);
427
428 dev_dbg(drvdata->dev, "cpu: %d enable smp call done: %d\n",
429 drvdata->cpu, rc);
430 return rc;
431}
432
433struct etm_enable_arg {
434 struct etm_drvdata *drvdata;
435 int rc;
436};
437
438static void etm_enable_hw_smp_call(void *info)
439{
440 struct etm_enable_arg *arg = info;
441
442 if (WARN_ON(!arg))
443 return;
444 arg->rc = etm_enable_hw(arg->drvdata);
445}
446
447static int etm_cpu_id(struct coresight_device *csdev)
448{
449 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
450
451 return drvdata->cpu;
452}
453
454int etm_get_trace_id(struct etm_drvdata *drvdata)
455{
456 unsigned long flags;
457 int trace_id = -1;
458
459 if (!drvdata)
460 goto out;
461
462 if (!local_read(&drvdata->mode))
463 return drvdata->traceid;
464
465 pm_runtime_get_sync(drvdata->dev);
466
467 spin_lock_irqsave(&drvdata->spinlock, flags);
468
469 CS_UNLOCK(drvdata->base);
470 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
471 CS_LOCK(drvdata->base);
472
473 spin_unlock_irqrestore(&drvdata->spinlock, flags);
474 pm_runtime_put(drvdata->dev);
475
476out:
477 return trace_id;
478
479}
480
481static int etm_trace_id(struct coresight_device *csdev)
482{
483 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
484
485 return etm_get_trace_id(drvdata);
486}
487
488static int etm_enable_perf(struct coresight_device *csdev,
489 struct perf_event *event)
490{
491 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
492
493 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
494 return -EINVAL;
495
496
497 etm_parse_event_config(drvdata, event);
498
499 return etm_enable_hw(drvdata);
500}
501
502static int etm_enable_sysfs(struct coresight_device *csdev)
503{
504 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
505 struct etm_enable_arg arg = { 0 };
506 int ret;
507
508 spin_lock(&drvdata->spinlock);
509
510
511
512
513
514 if (cpu_online(drvdata->cpu)) {
515 arg.drvdata = drvdata;
516 ret = smp_call_function_single(drvdata->cpu,
517 etm_enable_hw_smp_call, &arg, 1);
518 if (!ret)
519 ret = arg.rc;
520 if (!ret)
521 drvdata->sticky_enable = true;
522 } else {
523 ret = -ENODEV;
524 }
525
526 spin_unlock(&drvdata->spinlock);
527
528 if (!ret)
529 dev_dbg(drvdata->dev, "ETM tracing enabled\n");
530 return ret;
531}
532
533static int etm_enable(struct coresight_device *csdev,
534 struct perf_event *event, u32 mode)
535{
536 int ret;
537 u32 val;
538 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
539
540 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
541
542
543 if (val)
544 return -EBUSY;
545
546 switch (mode) {
547 case CS_MODE_SYSFS:
548 ret = etm_enable_sysfs(csdev);
549 break;
550 case CS_MODE_PERF:
551 ret = etm_enable_perf(csdev, event);
552 break;
553 default:
554 ret = -EINVAL;
555 }
556
557
558 if (ret)
559 local_set(&drvdata->mode, CS_MODE_DISABLED);
560
561 return ret;
562}
563
564static void etm_disable_hw(void *info)
565{
566 int i;
567 struct etm_drvdata *drvdata = info;
568 struct etm_config *config = &drvdata->config;
569
570 CS_UNLOCK(drvdata->base);
571 etm_set_prog(drvdata);
572
573
574 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
575
576 for (i = 0; i < drvdata->nr_cntr; i++)
577 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
578
579 etm_set_pwrdwn(drvdata);
580 coresight_disclaim_device_unlocked(drvdata->base);
581
582 CS_LOCK(drvdata->base);
583
584 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
585}
586
587static void etm_disable_perf(struct coresight_device *csdev)
588{
589 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
590
591 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
592 return;
593
594 CS_UNLOCK(drvdata->base);
595
596
597 etm_set_prog(drvdata);
598
599
600
601
602
603 etm_set_pwrdwn(drvdata);
604 coresight_disclaim_device_unlocked(drvdata->base);
605
606 CS_LOCK(drvdata->base);
607}
608
609static void etm_disable_sysfs(struct coresight_device *csdev)
610{
611 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
612
613
614
615
616
617
618
619 cpus_read_lock();
620 spin_lock(&drvdata->spinlock);
621
622
623
624
625
626 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
627
628 spin_unlock(&drvdata->spinlock);
629 cpus_read_unlock();
630
631 dev_dbg(drvdata->dev, "ETM tracing disabled\n");
632}
633
634static void etm_disable(struct coresight_device *csdev,
635 struct perf_event *event)
636{
637 u32 mode;
638 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
639
640
641
642
643
644
645 mode = local_read(&drvdata->mode);
646
647 switch (mode) {
648 case CS_MODE_DISABLED:
649 break;
650 case CS_MODE_SYSFS:
651 etm_disable_sysfs(csdev);
652 break;
653 case CS_MODE_PERF:
654 etm_disable_perf(csdev);
655 break;
656 default:
657 WARN_ON_ONCE(mode);
658 return;
659 }
660
661 if (mode)
662 local_set(&drvdata->mode, CS_MODE_DISABLED);
663}
664
665static const struct coresight_ops_source etm_source_ops = {
666 .cpu_id = etm_cpu_id,
667 .trace_id = etm_trace_id,
668 .enable = etm_enable,
669 .disable = etm_disable,
670};
671
672static const struct coresight_ops etm_cs_ops = {
673 .source_ops = &etm_source_ops,
674};
675
676static int etm_online_cpu(unsigned int cpu)
677{
678 if (!etmdrvdata[cpu])
679 return 0;
680
681 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
682 coresight_enable(etmdrvdata[cpu]->csdev);
683 return 0;
684}
685
686static int etm_starting_cpu(unsigned int cpu)
687{
688 if (!etmdrvdata[cpu])
689 return 0;
690
691 spin_lock(&etmdrvdata[cpu]->spinlock);
692 if (!etmdrvdata[cpu]->os_unlock) {
693 etm_os_unlock(etmdrvdata[cpu]);
694 etmdrvdata[cpu]->os_unlock = true;
695 }
696
697 if (local_read(&etmdrvdata[cpu]->mode))
698 etm_enable_hw(etmdrvdata[cpu]);
699 spin_unlock(&etmdrvdata[cpu]->spinlock);
700 return 0;
701}
702
703static int etm_dying_cpu(unsigned int cpu)
704{
705 if (!etmdrvdata[cpu])
706 return 0;
707
708 spin_lock(&etmdrvdata[cpu]->spinlock);
709 if (local_read(&etmdrvdata[cpu]->mode))
710 etm_disable_hw(etmdrvdata[cpu]);
711 spin_unlock(&etmdrvdata[cpu]->spinlock);
712 return 0;
713}
714
715static bool etm_arch_supported(u8 arch)
716{
717 switch (arch) {
718 case ETM_ARCH_V3_3:
719 break;
720 case ETM_ARCH_V3_5:
721 break;
722 case PFT_ARCH_V1_0:
723 break;
724 case PFT_ARCH_V1_1:
725 break;
726 default:
727 return false;
728 }
729 return true;
730}
731
732static void etm_init_arch_data(void *info)
733{
734 u32 etmidr;
735 u32 etmccr;
736 struct etm_drvdata *drvdata = info;
737
738
739 etm_os_unlock(drvdata);
740
741 CS_UNLOCK(drvdata->base);
742
743
744 (void)etm_readl(drvdata, ETMPDSR);
745
746 etm_set_pwrup(drvdata);
747
748
749
750
751 etm_clr_pwrdwn(drvdata);
752
753
754
755
756 etm_set_prog(drvdata);
757
758
759 etmidr = etm_readl(drvdata, ETMIDR);
760 drvdata->arch = BMVAL(etmidr, 4, 11);
761 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
762
763 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
764 etmccr = etm_readl(drvdata, ETMCCR);
765 drvdata->etmccr = etmccr;
766 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
767 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
768 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
769 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
770 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
771
772 etm_set_pwrdwn(drvdata);
773 etm_clr_pwrup(drvdata);
774 CS_LOCK(drvdata->base);
775}
776
777static void etm_init_trace_id(struct etm_drvdata *drvdata)
778{
779 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
780}
781
782static int etm_probe(struct amba_device *adev, const struct amba_id *id)
783{
784 int ret;
785 void __iomem *base;
786 struct device *dev = &adev->dev;
787 struct coresight_platform_data *pdata = NULL;
788 struct etm_drvdata *drvdata;
789 struct resource *res = &adev->res;
790 struct coresight_desc desc = { 0 };
791 struct device_node *np = adev->dev.of_node;
792
793 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
794 if (!drvdata)
795 return -ENOMEM;
796
797 if (np) {
798 pdata = of_get_coresight_platform_data(dev, np);
799 if (IS_ERR(pdata))
800 return PTR_ERR(pdata);
801
802 adev->dev.platform_data = pdata;
803 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
804 }
805
806 drvdata->dev = &adev->dev;
807 dev_set_drvdata(dev, drvdata);
808
809
810 base = devm_ioremap_resource(dev, res);
811 if (IS_ERR(base))
812 return PTR_ERR(base);
813
814 drvdata->base = base;
815
816 spin_lock_init(&drvdata->spinlock);
817
818 drvdata->atclk = devm_clk_get(&adev->dev, "atclk");
819 if (!IS_ERR(drvdata->atclk)) {
820 ret = clk_prepare_enable(drvdata->atclk);
821 if (ret)
822 return ret;
823 }
824
825 drvdata->cpu = pdata ? pdata->cpu : 0;
826
827 cpus_read_lock();
828 etmdrvdata[drvdata->cpu] = drvdata;
829
830 if (smp_call_function_single(drvdata->cpu,
831 etm_init_arch_data, drvdata, 1))
832 dev_err(dev, "ETM arch init failed\n");
833
834 if (!etm_count++) {
835 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
836 "arm/coresight:starting",
837 etm_starting_cpu, etm_dying_cpu);
838 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
839 "arm/coresight:online",
840 etm_online_cpu, NULL);
841 if (ret < 0)
842 goto err_arch_supported;
843 hp_online = ret;
844 }
845 cpus_read_unlock();
846
847 if (etm_arch_supported(drvdata->arch) == false) {
848 ret = -EINVAL;
849 goto err_arch_supported;
850 }
851
852 etm_init_trace_id(drvdata);
853 etm_set_default(&drvdata->config);
854
855 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
856 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
857 desc.ops = &etm_cs_ops;
858 desc.pdata = pdata;
859 desc.dev = dev;
860 desc.groups = coresight_etm_groups;
861 drvdata->csdev = coresight_register(&desc);
862 if (IS_ERR(drvdata->csdev)) {
863 ret = PTR_ERR(drvdata->csdev);
864 goto err_arch_supported;
865 }
866
867 ret = etm_perf_symlink(drvdata->csdev, true);
868 if (ret) {
869 coresight_unregister(drvdata->csdev);
870 goto err_arch_supported;
871 }
872
873 pm_runtime_put(&adev->dev);
874 dev_info(dev, "%s initialized\n", (char *)coresight_get_uci_data(id));
875 if (boot_enable) {
876 coresight_enable(drvdata->csdev);
877 drvdata->boot_enable = true;
878 }
879
880 return 0;
881
882err_arch_supported:
883 if (--etm_count == 0) {
884 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
885 if (hp_online)
886 cpuhp_remove_state_nocalls(hp_online);
887 }
888 return ret;
889}
890
891#ifdef CONFIG_PM
892static int etm_runtime_suspend(struct device *dev)
893{
894 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
895
896 if (drvdata && !IS_ERR(drvdata->atclk))
897 clk_disable_unprepare(drvdata->atclk);
898
899 return 0;
900}
901
902static int etm_runtime_resume(struct device *dev)
903{
904 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
905
906 if (drvdata && !IS_ERR(drvdata->atclk))
907 clk_prepare_enable(drvdata->atclk);
908
909 return 0;
910}
911#endif
912
913static const struct dev_pm_ops etm_dev_pm_ops = {
914 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
915};
916
917static const struct amba_id etm_ids[] = {
918
919 CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"),
920
921 CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"),
922
923 CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"),
924
925 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"),
926
927 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"),
928
929 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
930 { 0, 0},
931};
932
933static struct amba_driver etm_driver = {
934 .drv = {
935 .name = "coresight-etm3x",
936 .owner = THIS_MODULE,
937 .pm = &etm_dev_pm_ops,
938 .suppress_bind_attrs = true,
939 },
940 .probe = etm_probe,
941 .id_table = etm_ids,
942};
943builtin_amba_driver(etm_driver);
944