1
2
3
4
5
6#include <linux/kernel.h>
7#include <linux/moduleparam.h>
8#include <linux/init.h>
9#include <linux/types.h>
10#include <linux/device.h>
11#include <linux/io.h>
12#include <linux/err.h>
13#include <linux/fs.h>
14#include <linux/slab.h>
15#include <linux/delay.h>
16#include <linux/smp.h>
17#include <linux/sysfs.h>
18#include <linux/stat.h>
19#include <linux/clk.h>
20#include <linux/cpu.h>
21#include <linux/coresight.h>
22#include <linux/coresight-pmu.h>
23#include <linux/pm_wakeup.h>
24#include <linux/amba/bus.h>
25#include <linux/seq_file.h>
26#include <linux/uaccess.h>
27#include <linux/perf_event.h>
28#include <linux/pm_runtime.h>
29#include <asm/sections.h>
30#include <asm/local.h>
31#include <asm/virt.h>
32
33#include "coresight-etm4x.h"
34#include "coresight-etm-perf.h"
35
36static int boot_enable;
37module_param_named(boot_enable, boot_enable, int, S_IRUGO);
38
39
40static int etm4_count;
41static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
42static void etm4_set_default_config(struct etmv4_config *config);
43static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
44 struct perf_event *event);
45
46static enum cpuhp_state hp_online;
47
48static void etm4_os_unlock(struct etmv4_drvdata *drvdata)
49{
50
51 writel_relaxed(0x0, drvdata->base + TRCOSLAR);
52 drvdata->os_unlock = true;
53 isb();
54}
55
56static bool etm4_arch_supported(u8 arch)
57{
58
59 switch (arch & 0xf0) {
60 case ETM_ARCH_V4:
61 break;
62 default:
63 return false;
64 }
65 return true;
66}
67
68static int etm4_cpu_id(struct coresight_device *csdev)
69{
70 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
71
72 return drvdata->cpu;
73}
74
75static int etm4_trace_id(struct coresight_device *csdev)
76{
77 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
78
79 return drvdata->trcid;
80}
81
82struct etm4_enable_arg {
83 struct etmv4_drvdata *drvdata;
84 int rc;
85};
86
87static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
88{
89 int i, rc;
90 struct etmv4_config *config = &drvdata->config;
91
92 CS_UNLOCK(drvdata->base);
93
94 etm4_os_unlock(drvdata);
95
96 rc = coresight_claim_device_unlocked(drvdata->base);
97 if (rc)
98 goto done;
99
100
101 writel_relaxed(0, drvdata->base + TRCPRGCTLR);
102
103
104 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
105 dev_err(drvdata->dev,
106 "timeout while waiting for Idle Trace Status\n");
107
108 writel_relaxed(config->pe_sel, drvdata->base + TRCPROCSELR);
109 writel_relaxed(config->cfg, drvdata->base + TRCCONFIGR);
110
111 writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
112 writel_relaxed(config->eventctrl0, drvdata->base + TRCEVENTCTL0R);
113 writel_relaxed(config->eventctrl1, drvdata->base + TRCEVENTCTL1R);
114 writel_relaxed(config->stall_ctrl, drvdata->base + TRCSTALLCTLR);
115 writel_relaxed(config->ts_ctrl, drvdata->base + TRCTSCTLR);
116 writel_relaxed(config->syncfreq, drvdata->base + TRCSYNCPR);
117 writel_relaxed(config->ccctlr, drvdata->base + TRCCCCTLR);
118 writel_relaxed(config->bb_ctrl, drvdata->base + TRCBBCTLR);
119 writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
120 writel_relaxed(config->vinst_ctrl, drvdata->base + TRCVICTLR);
121 writel_relaxed(config->viiectlr, drvdata->base + TRCVIIECTLR);
122 writel_relaxed(config->vissctlr,
123 drvdata->base + TRCVISSCTLR);
124 writel_relaxed(config->vipcssctlr,
125 drvdata->base + TRCVIPCSSCTLR);
126 for (i = 0; i < drvdata->nrseqstate - 1; i++)
127 writel_relaxed(config->seq_ctrl[i],
128 drvdata->base + TRCSEQEVRn(i));
129 writel_relaxed(config->seq_rst, drvdata->base + TRCSEQRSTEVR);
130 writel_relaxed(config->seq_state, drvdata->base + TRCSEQSTR);
131 writel_relaxed(config->ext_inp, drvdata->base + TRCEXTINSELR);
132 for (i = 0; i < drvdata->nr_cntr; i++) {
133 writel_relaxed(config->cntrldvr[i],
134 drvdata->base + TRCCNTRLDVRn(i));
135 writel_relaxed(config->cntr_ctrl[i],
136 drvdata->base + TRCCNTCTLRn(i));
137 writel_relaxed(config->cntr_val[i],
138 drvdata->base + TRCCNTVRn(i));
139 }
140
141
142
143
144
145 for (i = 2; i < drvdata->nr_resource * 2; i++)
146 writel_relaxed(config->res_ctrl[i],
147 drvdata->base + TRCRSCTLRn(i));
148
149 for (i = 0; i < drvdata->nr_ss_cmp; i++) {
150 writel_relaxed(config->ss_ctrl[i],
151 drvdata->base + TRCSSCCRn(i));
152 writel_relaxed(config->ss_status[i],
153 drvdata->base + TRCSSCSRn(i));
154 writel_relaxed(config->ss_pe_cmp[i],
155 drvdata->base + TRCSSPCICRn(i));
156 }
157 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
158 writeq_relaxed(config->addr_val[i],
159 drvdata->base + TRCACVRn(i));
160 writeq_relaxed(config->addr_acc[i],
161 drvdata->base + TRCACATRn(i));
162 }
163 for (i = 0; i < drvdata->numcidc; i++)
164 writeq_relaxed(config->ctxid_pid[i],
165 drvdata->base + TRCCIDCVRn(i));
166 writel_relaxed(config->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
167 writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
168
169 for (i = 0; i < drvdata->numvmidc; i++)
170 writeq_relaxed(config->vmid_val[i],
171 drvdata->base + TRCVMIDCVRn(i));
172 writel_relaxed(config->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
173 writel_relaxed(config->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
174
175
176
177
178
179 writel_relaxed(readl_relaxed(drvdata->base + TRCPDCR) | TRCPDCR_PU,
180 drvdata->base + TRCPDCR);
181
182
183 writel_relaxed(1, drvdata->base + TRCPRGCTLR);
184
185
186 if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
187 dev_err(drvdata->dev,
188 "timeout while waiting for Idle Trace Status\n");
189
190done:
191 CS_LOCK(drvdata->base);
192
193 dev_dbg(drvdata->dev, "cpu: %d enable smp call done: %d\n",
194 drvdata->cpu, rc);
195 return rc;
196}
197
198static void etm4_enable_hw_smp_call(void *info)
199{
200 struct etm4_enable_arg *arg = info;
201
202 if (WARN_ON(!arg))
203 return;
204 arg->rc = etm4_enable_hw(arg->drvdata);
205}
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220static int etm4_config_timestamp_event(struct etmv4_drvdata *drvdata)
221{
222 int ctridx, ret = -EINVAL;
223 int counter, rselector;
224 u32 val = 0;
225 struct etmv4_config *config = &drvdata->config;
226
227
228 if (!drvdata->nr_cntr)
229 goto out;
230
231
232 for (ctridx = 0; ctridx < drvdata->nr_cntr; ctridx++)
233 if (config->cntr_val[ctridx] == 0)
234 break;
235
236
237 if (ctridx == drvdata->nr_cntr) {
238 pr_debug("%s: no available counter found\n", __func__);
239 ret = -ENOSPC;
240 goto out;
241 }
242
243
244
245
246
247
248
249 for (rselector = 2; rselector < drvdata->nr_resource * 2; rselector++)
250 if (!config->res_ctrl[rselector])
251 break;
252
253 if (rselector == drvdata->nr_resource * 2) {
254 pr_debug("%s: no available resource selector found\n",
255 __func__);
256 ret = -ENOSPC;
257 goto out;
258 }
259
260
261 counter = 1 << ctridx;
262
263
264
265
266
267 config->cntr_val[ctridx] = 1;
268 config->cntrldvr[ctridx] = 1;
269
270
271 val = 0x1 << 16 |
272 0x0 << 7 |
273 0x1;
274
275 config->cntr_ctrl[ctridx] = val;
276
277 val = 0x2 << 16 |
278 counter << 0;
279
280 config->res_ctrl[rselector] = val;
281
282 val = 0x0 << 7 |
283 rselector;
284
285 config->ts_ctrl = val;
286
287 ret = 0;
288out:
289 return ret;
290}
291
292static int etm4_parse_event_config(struct etmv4_drvdata *drvdata,
293 struct perf_event *event)
294{
295 int ret = 0;
296 struct etmv4_config *config = &drvdata->config;
297 struct perf_event_attr *attr = &event->attr;
298
299 if (!attr) {
300 ret = -EINVAL;
301 goto out;
302 }
303
304
305 memset(config, 0, sizeof(struct etmv4_config));
306
307 if (attr->exclude_kernel)
308 config->mode = ETM_MODE_EXCL_KERN;
309
310 if (attr->exclude_user)
311 config->mode = ETM_MODE_EXCL_USER;
312
313
314 etm4_set_default_config(config);
315
316
317 ret = etm4_set_event_filters(drvdata, event);
318 if (ret)
319 goto out;
320
321
322 if (attr->config & BIT(ETM_OPT_CYCACC)) {
323 config->cfg |= BIT(4);
324
325 config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT;
326 }
327 if (attr->config & BIT(ETM_OPT_TS)) {
328
329
330
331
332
333 ret = etm4_config_timestamp_event(drvdata);
334
335
336
337
338
339 if (ret)
340 goto out;
341
342
343 config->cfg |= BIT(11);
344 }
345
346 if (attr->config & BIT(ETM_OPT_CTXTID))
347
348 config->cfg |= BIT(ETM4_CFG_BIT_CTXTID);
349
350
351 if ((attr->config & BIT(ETM_OPT_RETSTK)) && drvdata->retstack)
352
353 config->cfg |= BIT(12);
354
355out:
356 return ret;
357}
358
359static int etm4_enable_perf(struct coresight_device *csdev,
360 struct perf_event *event)
361{
362 int ret = 0;
363 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
364
365 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id())) {
366 ret = -EINVAL;
367 goto out;
368 }
369
370
371 ret = etm4_parse_event_config(drvdata, event);
372 if (ret)
373 goto out;
374
375 ret = etm4_enable_hw(drvdata);
376
377out:
378 return ret;
379}
380
381static int etm4_enable_sysfs(struct coresight_device *csdev)
382{
383 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
384 struct etm4_enable_arg arg = { 0 };
385 int ret;
386
387 spin_lock(&drvdata->spinlock);
388
389
390
391
392
393 arg.drvdata = drvdata;
394 ret = smp_call_function_single(drvdata->cpu,
395 etm4_enable_hw_smp_call, &arg, 1);
396 if (!ret)
397 ret = arg.rc;
398 if (!ret)
399 drvdata->sticky_enable = true;
400 spin_unlock(&drvdata->spinlock);
401
402 if (!ret)
403 dev_dbg(drvdata->dev, "ETM tracing enabled\n");
404 return ret;
405}
406
407static int etm4_enable(struct coresight_device *csdev,
408 struct perf_event *event, u32 mode)
409{
410 int ret;
411 u32 val;
412 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
413
414 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
415
416
417 if (val)
418 return -EBUSY;
419
420 switch (mode) {
421 case CS_MODE_SYSFS:
422 ret = etm4_enable_sysfs(csdev);
423 break;
424 case CS_MODE_PERF:
425 ret = etm4_enable_perf(csdev, event);
426 break;
427 default:
428 ret = -EINVAL;
429 }
430
431
432 if (ret)
433 local_set(&drvdata->mode, CS_MODE_DISABLED);
434
435 return ret;
436}
437
438static void etm4_disable_hw(void *info)
439{
440 u32 control;
441 struct etmv4_drvdata *drvdata = info;
442
443 CS_UNLOCK(drvdata->base);
444
445
446 control = readl_relaxed(drvdata->base + TRCPDCR);
447 control &= ~TRCPDCR_PU;
448 writel_relaxed(control, drvdata->base + TRCPDCR);
449
450 control = readl_relaxed(drvdata->base + TRCPRGCTLR);
451
452
453 control &= ~0x1;
454
455
456 mb();
457 isb();
458 writel_relaxed(control, drvdata->base + TRCPRGCTLR);
459
460 coresight_disclaim_device_unlocked(drvdata->base);
461
462 CS_LOCK(drvdata->base);
463
464 dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
465}
466
467static int etm4_disable_perf(struct coresight_device *csdev,
468 struct perf_event *event)
469{
470 u32 control;
471 struct etm_filters *filters = event->hw.addr_filters;
472 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
473
474 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
475 return -EINVAL;
476
477 etm4_disable_hw(drvdata);
478
479
480
481
482
483
484
485 control = readl_relaxed(drvdata->base + TRCVICTLR);
486
487 filters->ssstatus = (control & BIT(9));
488
489 return 0;
490}
491
492static void etm4_disable_sysfs(struct coresight_device *csdev)
493{
494 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
495
496
497
498
499
500
501
502 cpus_read_lock();
503 spin_lock(&drvdata->spinlock);
504
505
506
507
508
509 smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
510
511 spin_unlock(&drvdata->spinlock);
512 cpus_read_unlock();
513
514 dev_dbg(drvdata->dev, "ETM tracing disabled\n");
515}
516
517static void etm4_disable(struct coresight_device *csdev,
518 struct perf_event *event)
519{
520 u32 mode;
521 struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
522
523
524
525
526
527
528 mode = local_read(&drvdata->mode);
529
530 switch (mode) {
531 case CS_MODE_DISABLED:
532 break;
533 case CS_MODE_SYSFS:
534 etm4_disable_sysfs(csdev);
535 break;
536 case CS_MODE_PERF:
537 etm4_disable_perf(csdev, event);
538 break;
539 }
540
541 if (mode)
542 local_set(&drvdata->mode, CS_MODE_DISABLED);
543}
544
545static const struct coresight_ops_source etm4_source_ops = {
546 .cpu_id = etm4_cpu_id,
547 .trace_id = etm4_trace_id,
548 .enable = etm4_enable,
549 .disable = etm4_disable,
550};
551
552static const struct coresight_ops etm4_cs_ops = {
553 .source_ops = &etm4_source_ops,
554};
555
556static void etm4_init_arch_data(void *info)
557{
558 u32 etmidr0;
559 u32 etmidr1;
560 u32 etmidr2;
561 u32 etmidr3;
562 u32 etmidr4;
563 u32 etmidr5;
564 struct etmv4_drvdata *drvdata = info;
565
566
567 etm4_os_unlock(drvdata);
568
569 CS_UNLOCK(drvdata->base);
570
571
572 etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
573
574
575 if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
576 drvdata->instrp0 = true;
577 else
578 drvdata->instrp0 = false;
579
580
581 if (BMVAL(etmidr0, 5, 5))
582 drvdata->trcbb = true;
583 else
584 drvdata->trcbb = false;
585
586
587 if (BMVAL(etmidr0, 6, 6))
588 drvdata->trccond = true;
589 else
590 drvdata->trccond = false;
591
592
593 if (BMVAL(etmidr0, 7, 7))
594 drvdata->trccci = true;
595 else
596 drvdata->trccci = false;
597
598
599 if (BMVAL(etmidr0, 9, 9))
600 drvdata->retstack = true;
601 else
602 drvdata->retstack = false;
603
604
605 drvdata->nr_event = BMVAL(etmidr0, 10, 11);
606
607 drvdata->q_support = BMVAL(etmidr0, 15, 16);
608
609 drvdata->ts_size = BMVAL(etmidr0, 24, 28);
610
611
612 etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
613
614
615
616
617 drvdata->arch = BMVAL(etmidr1, 4, 11);
618
619
620 etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
621
622 drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
623
624 drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
625
626 drvdata->ccsize = BMVAL(etmidr2, 25, 28);
627
628 etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
629
630 drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
631
632 drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
633
634 drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
635
636
637
638
639
640 if (BMVAL(etmidr3, 24, 24))
641 drvdata->trc_error = true;
642 else
643 drvdata->trc_error = false;
644
645
646 if (BMVAL(etmidr3, 25, 25))
647 drvdata->syncpr = true;
648 else
649 drvdata->syncpr = false;
650
651
652 if (BMVAL(etmidr3, 26, 26))
653 drvdata->stallctl = true;
654 else
655 drvdata->stallctl = false;
656
657
658 if (BMVAL(etmidr3, 27, 27))
659 drvdata->sysstall = true;
660 else
661 drvdata->sysstall = false;
662
663
664 drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
665
666
667 if (BMVAL(etmidr3, 31, 31))
668 drvdata->nooverflow = true;
669 else
670 drvdata->nooverflow = false;
671
672
673 etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
674
675 drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
676
677 drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
678
679
680
681
682
683
684 drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
685
686
687
688
689 drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
690
691 drvdata->numcidc = BMVAL(etmidr4, 24, 27);
692
693 drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
694
695 etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
696
697 drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
698
699 drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
700
701 if (BMVAL(etmidr5, 22, 22))
702 drvdata->atbtrig = true;
703 else
704 drvdata->atbtrig = false;
705
706
707
708
709 if (BMVAL(etmidr5, 23, 23))
710 drvdata->lpoverride = true;
711 else
712 drvdata->lpoverride = false;
713
714 drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
715
716 drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
717 CS_LOCK(drvdata->base);
718}
719
720static void etm4_set_default_config(struct etmv4_config *config)
721{
722
723 config->eventctrl0 = 0x0;
724 config->eventctrl1 = 0x0;
725
726
727 config->stall_ctrl = 0x0;
728
729
730 config->syncfreq = 0xC;
731
732
733 config->ts_ctrl = 0x0;
734
735
736 config->vinst_ctrl |= BIT(0);
737}
738
739static u64 etm4_get_ns_access_type(struct etmv4_config *config)
740{
741 u64 access_type = 0;
742
743
744
745
746
747
748
749
750
751 if (!is_kernel_in_hyp_mode()) {
752
753 access_type = ETM_EXLEVEL_NS_HYP;
754 if (config->mode & ETM_MODE_EXCL_KERN)
755 access_type |= ETM_EXLEVEL_NS_OS;
756 } else if (config->mode & ETM_MODE_EXCL_KERN) {
757 access_type = ETM_EXLEVEL_NS_HYP;
758 }
759
760 if (config->mode & ETM_MODE_EXCL_USER)
761 access_type |= ETM_EXLEVEL_NS_APP;
762
763 return access_type;
764}
765
766static u64 etm4_get_access_type(struct etmv4_config *config)
767{
768 u64 access_type = etm4_get_ns_access_type(config);
769
770
771
772
773
774 access_type |= (ETM_EXLEVEL_S_APP |
775 ETM_EXLEVEL_S_OS |
776 ETM_EXLEVEL_S_HYP);
777
778 return access_type;
779}
780
781static void etm4_set_comparator_filter(struct etmv4_config *config,
782 u64 start, u64 stop, int comparator)
783{
784 u64 access_type = etm4_get_access_type(config);
785
786
787 config->addr_val[comparator] = start;
788 config->addr_acc[comparator] = access_type;
789 config->addr_type[comparator] = ETM_ADDR_TYPE_RANGE;
790
791
792 config->addr_val[comparator + 1] = stop;
793 config->addr_acc[comparator + 1] = access_type;
794 config->addr_type[comparator + 1] = ETM_ADDR_TYPE_RANGE;
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811 config->viiectlr |= BIT(comparator / 2);
812}
813
814static void etm4_set_start_stop_filter(struct etmv4_config *config,
815 u64 address, int comparator,
816 enum etm_addr_type type)
817{
818 int shift;
819 u64 access_type = etm4_get_access_type(config);
820
821
822 config->addr_val[comparator] = address;
823 config->addr_acc[comparator] = access_type;
824 config->addr_type[comparator] = type;
825
826
827
828
829
830
831 shift = (type == ETM_ADDR_TYPE_START ? 0 : 16);
832 config->vissctlr |= BIT(shift + comparator);
833}
834
835static void etm4_set_default_filter(struct etmv4_config *config)
836{
837 u64 start, stop;
838
839
840
841
842
843 start = 0x0;
844 stop = ~0x0;
845
846 etm4_set_comparator_filter(config, start, stop,
847 ETM_DEFAULT_ADDR_COMP);
848
849
850
851
852
853 config->vinst_ctrl |= BIT(9);
854
855
856 config->vissctlr = 0x0;
857}
858
859static void etm4_set_default(struct etmv4_config *config)
860{
861 if (WARN_ON_ONCE(!config))
862 return;
863
864
865
866
867
868
869
870
871
872
873 etm4_set_default_config(config);
874 etm4_set_default_filter(config);
875}
876
877static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 type)
878{
879 int nr_comparator, index = 0;
880 struct etmv4_config *config = &drvdata->config;
881
882
883
884
885
886 nr_comparator = drvdata->nr_addr_cmp * 2;
887
888
889 while (index < nr_comparator) {
890 switch (type) {
891 case ETM_ADDR_TYPE_RANGE:
892 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE &&
893 config->addr_type[index + 1] == ETM_ADDR_TYPE_NONE)
894 return index;
895
896
897 index += 2;
898 break;
899 case ETM_ADDR_TYPE_START:
900 case ETM_ADDR_TYPE_STOP:
901 if (config->addr_type[index] == ETM_ADDR_TYPE_NONE)
902 return index;
903
904
905 index += 1;
906 break;
907 default:
908 return -EINVAL;
909 }
910 }
911
912
913 return -ENOSPC;
914}
915
916static int etm4_set_event_filters(struct etmv4_drvdata *drvdata,
917 struct perf_event *event)
918{
919 int i, comparator, ret = 0;
920 u64 address;
921 struct etmv4_config *config = &drvdata->config;
922 struct etm_filters *filters = event->hw.addr_filters;
923
924 if (!filters)
925 goto default_filter;
926
927
928 perf_event_addr_filters_sync(event);
929
930
931
932
933
934 if (!filters->nr_filters)
935 goto default_filter;
936
937 for (i = 0; i < filters->nr_filters; i++) {
938 struct etm_filter *filter = &filters->etm_filter[i];
939 enum etm_addr_type type = filter->type;
940
941
942 comparator = etm4_get_next_comparator(drvdata, type);
943 if (comparator < 0) {
944 ret = comparator;
945 goto out;
946 }
947
948 switch (type) {
949 case ETM_ADDR_TYPE_RANGE:
950 etm4_set_comparator_filter(config,
951 filter->start_addr,
952 filter->stop_addr,
953 comparator);
954
955
956
957
958 config->vinst_ctrl |= BIT(9);
959
960
961 config->vissctlr = 0x0;
962 break;
963 case ETM_ADDR_TYPE_START:
964 case ETM_ADDR_TYPE_STOP:
965
966 address = (type == ETM_ADDR_TYPE_START ?
967 filter->start_addr :
968 filter->stop_addr);
969
970
971 etm4_set_start_stop_filter(config, address,
972 comparator, type);
973
974
975
976
977
978
979
980
981
982
983
984
985 if (filters->ssstatus)
986 config->vinst_ctrl |= BIT(9);
987
988
989 config->viiectlr = 0x0;
990 break;
991 default:
992 ret = -EINVAL;
993 goto out;
994 }
995 }
996
997 goto out;
998
999
1000default_filter:
1001 etm4_set_default_filter(config);
1002
1003out:
1004 return ret;
1005}
1006
1007void etm4_config_trace_mode(struct etmv4_config *config)
1008{
1009 u32 addr_acc, mode;
1010
1011 mode = config->mode;
1012 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
1013
1014
1015 WARN_ON_ONCE(mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER));
1016
1017
1018 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
1019 return;
1020
1021 addr_acc = config->addr_acc[ETM_DEFAULT_ADDR_COMP];
1022
1023 addr_acc &= ~(ETM_EXLEVEL_NS_APP | ETM_EXLEVEL_NS_OS |
1024 ETM_EXLEVEL_NS_HYP);
1025
1026 addr_acc |= etm4_get_ns_access_type(config);
1027
1028 config->addr_acc[ETM_DEFAULT_ADDR_COMP] = addr_acc;
1029 config->addr_acc[ETM_DEFAULT_ADDR_COMP + 1] = addr_acc;
1030}
1031
1032static int etm4_online_cpu(unsigned int cpu)
1033{
1034 if (!etmdrvdata[cpu])
1035 return 0;
1036
1037 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
1038 coresight_enable(etmdrvdata[cpu]->csdev);
1039 return 0;
1040}
1041
1042static int etm4_starting_cpu(unsigned int cpu)
1043{
1044 if (!etmdrvdata[cpu])
1045 return 0;
1046
1047 spin_lock(&etmdrvdata[cpu]->spinlock);
1048 if (!etmdrvdata[cpu]->os_unlock) {
1049 etm4_os_unlock(etmdrvdata[cpu]);
1050 etmdrvdata[cpu]->os_unlock = true;
1051 }
1052
1053 if (local_read(&etmdrvdata[cpu]->mode))
1054 etm4_enable_hw(etmdrvdata[cpu]);
1055 spin_unlock(&etmdrvdata[cpu]->spinlock);
1056 return 0;
1057}
1058
1059static int etm4_dying_cpu(unsigned int cpu)
1060{
1061 if (!etmdrvdata[cpu])
1062 return 0;
1063
1064 spin_lock(&etmdrvdata[cpu]->spinlock);
1065 if (local_read(&etmdrvdata[cpu]->mode))
1066 etm4_disable_hw(etmdrvdata[cpu]);
1067 spin_unlock(&etmdrvdata[cpu]->spinlock);
1068 return 0;
1069}
1070
1071static void etm4_init_trace_id(struct etmv4_drvdata *drvdata)
1072{
1073 drvdata->trcid = coresight_get_trace_id(drvdata->cpu);
1074}
1075
1076static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1077{
1078 int ret;
1079 void __iomem *base;
1080 struct device *dev = &adev->dev;
1081 struct coresight_platform_data *pdata = NULL;
1082 struct etmv4_drvdata *drvdata;
1083 struct resource *res = &adev->res;
1084 struct coresight_desc desc = { 0 };
1085 struct device_node *np = adev->dev.of_node;
1086
1087 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1088 if (!drvdata)
1089 return -ENOMEM;
1090
1091 if (np) {
1092 pdata = of_get_coresight_platform_data(dev, np);
1093 if (IS_ERR(pdata))
1094 return PTR_ERR(pdata);
1095 adev->dev.platform_data = pdata;
1096 }
1097
1098 drvdata->dev = &adev->dev;
1099 dev_set_drvdata(dev, drvdata);
1100
1101
1102 base = devm_ioremap_resource(dev, res);
1103 if (IS_ERR(base))
1104 return PTR_ERR(base);
1105
1106 drvdata->base = base;
1107
1108 spin_lock_init(&drvdata->spinlock);
1109
1110 drvdata->cpu = pdata ? pdata->cpu : 0;
1111
1112 cpus_read_lock();
1113 etmdrvdata[drvdata->cpu] = drvdata;
1114
1115 if (smp_call_function_single(drvdata->cpu,
1116 etm4_init_arch_data, drvdata, 1))
1117 dev_err(dev, "ETM arch init failed\n");
1118
1119 if (!etm4_count++) {
1120 cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
1121 "arm/coresight4:starting",
1122 etm4_starting_cpu, etm4_dying_cpu);
1123 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
1124 "arm/coresight4:online",
1125 etm4_online_cpu, NULL);
1126 if (ret < 0)
1127 goto err_arch_supported;
1128 hp_online = ret;
1129 }
1130
1131 cpus_read_unlock();
1132
1133 if (etm4_arch_supported(drvdata->arch) == false) {
1134 ret = -EINVAL;
1135 goto err_arch_supported;
1136 }
1137
1138 etm4_init_trace_id(drvdata);
1139 etm4_set_default(&drvdata->config);
1140
1141 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
1142 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1143 desc.ops = &etm4_cs_ops;
1144 desc.pdata = pdata;
1145 desc.dev = dev;
1146 desc.groups = coresight_etmv4_groups;
1147 drvdata->csdev = coresight_register(&desc);
1148 if (IS_ERR(drvdata->csdev)) {
1149 ret = PTR_ERR(drvdata->csdev);
1150 goto err_arch_supported;
1151 }
1152
1153 ret = etm_perf_symlink(drvdata->csdev, true);
1154 if (ret) {
1155 coresight_unregister(drvdata->csdev);
1156 goto err_arch_supported;
1157 }
1158
1159 pm_runtime_put(&adev->dev);
1160 dev_info(dev, "CPU%d: ETM v%d.%d initialized\n",
1161 drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
1162
1163 if (boot_enable) {
1164 coresight_enable(drvdata->csdev);
1165 drvdata->boot_enable = true;
1166 }
1167
1168 return 0;
1169
1170err_arch_supported:
1171 if (--etm4_count == 0) {
1172 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
1173 if (hp_online)
1174 cpuhp_remove_state_nocalls(hp_online);
1175 }
1176 return ret;
1177}
1178
1179static struct amba_cs_uci_id uci_id_etm4[] = {
1180 {
1181
1182 .devarch = 0x47704a13,
1183 .devarch_mask = 0xfff0ffff,
1184 .devtype = 0x00000013,
1185 }
1186};
1187
1188static const struct amba_id etm4_ids[] = {
1189 CS_AMBA_ID(0x000bb95d),
1190 CS_AMBA_ID(0x000bb95e),
1191 CS_AMBA_ID(0x000bb95a),
1192 CS_AMBA_ID(0x000bb959),
1193 CS_AMBA_UCI_ID(0x000bb9da, uci_id_etm4),
1194 {},
1195};
1196
1197static struct amba_driver etm4x_driver = {
1198 .drv = {
1199 .name = "coresight-etm4x",
1200 .suppress_bind_attrs = true,
1201 },
1202 .probe = etm4_probe,
1203 .id_table = etm4_ids,
1204};
1205builtin_amba_driver(etm4x_driver);
1206