LXR linux/drivers/isdn/hisax/hfc

   1/* $Id: hfc_sx.c,v 1.12.2.5 2004/02/11 13:21:33 keil Exp $
   2 *
   3 * level driver for Cologne Chip Designs hfc-s+/sp based cards
   4 *
   5 * Author       Werner Cornelius
   6 *              based on existing driver for CCD HFC PCI cards
   7 * Copyright    by Werner Cornelius  <werner@isdn4linux.de>
   8 *
   9 * This software may be used and distributed according to the terms
  10 * of the GNU General Public License, incorporated herein by reference.
  11 *
  12 */
  13
  14#include <linux/init.h>
  15#include "hisax.h"
  16#include "hfc_sx.h"
  17#include "isdnl1.h"
  18#include <linux/interrupt.h>
  19#include <linux/isapnp.h>
  20#include <linux/slab.h>
  21
  22static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
  23
  24/***************************************/
  25/* IRQ-table for CCDs demo board       */
  26/* IRQs 6,5,10,11,12,15 are supported  */
  27/***************************************/
  28
  29/* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
  30 *
  31 * Thanks to Uwe Wisniewski
  32 *
  33 * ISA-SLOT  Signal      PIN
  34 * B25        IRQ3     92 IRQ_G
  35 * B23        IRQ5     94 IRQ_A
  36 * B4         IRQ2/9   95 IRQ_B
  37 * D3         IRQ10    96 IRQ_C
  38 * D4         IRQ11    97 IRQ_D
  39 * D5         IRQ12    98 IRQ_E
  40 * D6         IRQ15    99 IRQ_F
  41 */
  42
  43#undef CCD_DEMO_BOARD
  44#ifdef CCD_DEMO_BOARD
  45static u_char ccd_sp_irqtab[16] = {
  46        0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 3, 4, 5, 0, 0, 6
  47};
  48#else /* Teles 16.3c */
  49static u_char ccd_sp_irqtab[16] = {
  50        0, 0, 0, 7, 0, 1, 0, 0, 0, 2, 3, 4, 5, 0, 0, 6
  51};
  52#endif
  53#define NT_T1_COUNT 20          /* number of 3.125ms interrupts for G2 timeout */
  54
  55#define byteout(addr, val) outb(val, addr)
  56#define bytein(addr) inb(addr)
  57
  58/******************************/
  59/* In/Out access to registers */
  60/******************************/
  61static inline void
  62Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
  63{
  64        byteout(cs->hw.hfcsx.base + 1, regnum);
  65        byteout(cs->hw.hfcsx.base, val);
  66}
  67
  68static inline u_char
  69Read_hfc(struct IsdnCardState *cs, u_char regnum)
  70{
  71        u_char ret;
  72
  73        byteout(cs->hw.hfcsx.base + 1, regnum);
  74        ret = bytein(cs->hw.hfcsx.base);
  75        return (ret);
  76}
  77
  78
  79/**************************************************/
  80/* select a fifo and remember which one for reuse */
  81/**************************************************/
  82static void
  83fifo_select(struct IsdnCardState *cs, u_char fifo)
  84{
  85        if (fifo == cs->hw.hfcsx.last_fifo)
  86                return; /* still valid */
  87
  88        byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL);
  89        byteout(cs->hw.hfcsx.base, fifo);
  90        while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
  91        udelay(4);
  92        byteout(cs->hw.hfcsx.base, fifo);
  93        while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
  94}
  95
  96/******************************************/
  97/* reset the specified fifo to defaults.  */
  98/* If its a send fifo init needed markers */
  99/******************************************/
 100static void
 101reset_fifo(struct IsdnCardState *cs, u_char fifo)
 102{
 103        fifo_select(cs, fifo); /* first select the fifo */
 104        byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM);
 105        byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
 106        udelay(1);
 107        while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 108}
 109
 110
 111/*************************************************************/
 112/* write_fifo writes the skb contents to the desired fifo    */
 113/* if no space is available or an error occurs 0 is returned */
 114/* the skb is not released in any way.                       */
 115/*************************************************************/
 116static int
 117write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
 118{
 119        unsigned short *msp;
 120        int fifo_size, count, z1, z2;
 121        u_char f_msk, f1, f2, *src;
 122
 123        if (skb->len <= 0) return (0);
 124        if (fifo & 1) return (0); /* no write fifo */
 125
 126        fifo_select(cs, fifo);
 127        if (fifo & 4) {
 128                fifo_size = D_FIFO_SIZE; /* D-channel */
 129                f_msk = MAX_D_FRAMES;
 130                if (trans_max) return (0); /* only HDLC */
 131        }
 132        else {
 133                fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 134                f_msk = MAX_B_FRAMES;
 135        }
 136
 137        z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 138        z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 139
 140        /* Check for transparent mode */
 141        if (trans_max) {
 142                z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 143                z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 144                count = z2 - z1;
 145                if (count <= 0)
 146                        count += fifo_size; /* free bytes */
 147                if (count < skb->len + 1) return (0); /* no room */
 148                count = fifo_size - count; /* bytes still not send */
 149                if (count > 2 * trans_max) return (0); /* delay to long */
 150                count = skb->len;
 151                src = skb->data;
 152                while (count--)
 153                        Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 154                return (1); /* success */
 155        }
 156
 157        msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
 158        msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES + 1));
 159        f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 160        f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 161
 162        count = f1 - f2; /* frame count actually buffered */
 163        if (count < 0)
 164                count += (f_msk + 1);   /* if wrap around */
 165        if (count > f_msk - 1) {
 166                if (cs->debug & L1_DEB_ISAC_FIFO)
 167                        debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1);
 168                return (0);
 169        }
 170
 171        *(msp + f1) = z1; /* remember marker */
 172
 173        if (cs->debug & L1_DEB_ISAC_FIFO)
 174                debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
 175                        fifo, f1, f2, z1);
 176        /* now determine free bytes in FIFO buffer */
 177        count = *(msp + f2) - z1;
 178        if (count <= 0)
 179                count += fifo_size;     /* count now contains available bytes */
 180
 181        if (cs->debug & L1_DEB_ISAC_FIFO)
 182                debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)",
 183                        fifo, skb->len, count);
 184        if (count < skb->len) {
 185                if (cs->debug & L1_DEB_ISAC_FIFO)
 186                        debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
 187                return (0);
 188        }
 189
 190        count = skb->len; /* get frame len */
 191        src = skb->data;        /* source pointer */
 192        while (count--)
 193                Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 194
 195        Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
 196        udelay(1);
 197        while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 198        return (1);
 199}
 200
 201/***************************************************************/
 202/* read_fifo reads data to an skb from the desired fifo        */
 203/* if no data is available or an error occurs NULL is returned */
 204/* the skb is not released in any way.                         */
 205/***************************************************************/
 206static struct sk_buff *
 207read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
 208{       int fifo_size, count, z1, z2;
 209        u_char f_msk, f1, f2, *dst;
 210        struct sk_buff *skb;
 211
 212        if (!(fifo & 1)) return (NULL); /* no read fifo */
 213        fifo_select(cs, fifo);
 214        if (fifo & 4) {
 215                fifo_size = D_FIFO_SIZE; /* D-channel */
 216                f_msk = MAX_D_FRAMES;
 217                if (trans_max) return (NULL); /* only hdlc */
 218        }
 219        else {
 220                fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 221                f_msk = MAX_B_FRAMES;
 222        }
 223
 224        /* transparent mode */
 225        if (trans_max) {
 226                z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 227                z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 228                z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 229                z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 230                /* now determine bytes in actual FIFO buffer */
 231                count = z1 - z2;
 232                if (count <= 0)
 233                        count += fifo_size;     /* count now contains buffered bytes */
 234                count++;
 235                if (count > trans_max)
 236                        count = trans_max; /* limit length */
 237                skb = dev_alloc_skb(count);
 238                if (skb) {
 239                        dst = skb_put(skb, count);
 240                        while (count--)
 241                                *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 242                        return skb;
 243                } else
 244                        return NULL; /* no memory */
 245        }
 246
 247        do {
 248                f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 249                f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 250
 251                if (f1 == f2) return (NULL); /* no frame available */
 252
 253                z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 254                z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 255                z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 256                z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 257
 258                if (cs->debug & L1_DEB_ISAC_FIFO)
 259                        debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
 260                                fifo, f1, f2, z1, z2);
 261                /* now determine bytes in actual FIFO buffer */
 262                count = z1 - z2;
 263                if (count <= 0)
 264                        count += fifo_size;     /* count now contains buffered bytes */
 265                count++;
 266
 267                if (cs->debug & L1_DEB_ISAC_FIFO)
 268                        debugl1(cs, "hfcsx_read_fifo %d count %u)",
 269                                fifo, count);
 270
 271                if ((count > fifo_size) || (count < 4)) {
 272                        if (cs->debug & L1_DEB_WARN)
 273                                debugl1(cs, "hfcsx_read_fifo %d packet inv. len %d ", fifo , count);
 274                        while (count) {
 275                                count--; /* empty fifo */
 276                                Read_hfc(cs, HFCSX_FIF_DRD);
 277                        }
 278                        skb = NULL;
 279                } else
 280                        if ((skb = dev_alloc_skb(count - 3))) {
 281                                count -= 3;
 282                                dst = skb_put(skb, count);
 283
 284                                while (count--)
 285                                        *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 286
 287                                Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
 288                                Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
 289                                if (Read_hfc(cs, HFCSX_FIF_DRD)) {
 290                                        dev_kfree_skb_irq(skb);
 291                                        if (cs->debug & L1_DEB_ISAC_FIFO)
 292                                                debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
 293                                        skb = NULL;
 294                                }
 295                        } else {
 296                                printk(KERN_WARNING "HFC-SX: receive out of memory\n");
 297                                return (NULL);
 298                        }
 299
 300                Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
 301                udelay(1);
 302                while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */
 303                udelay(1);
 304        } while (!skb); /* retry in case of crc error */
 305        return (skb);
 306}
 307
 308/******************************************/
 309/* free hardware resources used by driver */
 310/******************************************/
 311static void
 312release_io_hfcsx(struct IsdnCardState *cs)
 313{
 314        cs->hw.hfcsx.int_m2 = 0;        /* interrupt output off ! */
 315        Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 316        Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
 317        msleep(30);                             /* Timeout 30ms */
 318        Write_hfc(cs, HFCSX_CIRM, 0);   /* Reset Off */
 319        del_timer(&cs->hw.hfcsx.timer);
 320        release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
 321        kfree(cs->hw.hfcsx.extra);
 322        cs->hw.hfcsx.extra = NULL;
 323}
 324
 325/**********************************************************/
 326/* set_fifo_size determines the size of the RAM and FIFOs */
 327/* returning 0 -> need to reset the chip again.           */
 328/**********************************************************/
 329static int set_fifo_size(struct IsdnCardState *cs)
 330{
 331
 332        if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */
 333
 334        if ((cs->hw.hfcsx.chip >> 4) == 9) {
 335                cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
 336                return (1);
 337        }
 338
 339        cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
 340        cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
 341        return (0);
 342
 343}
 344
 345/********************************************************************************/
 346/* function called to reset the HFC SX chip. A complete software reset of chip */
 347/* and fifos is done.                                                           */
 348/********************************************************************************/
 349static void
 350reset_hfcsx(struct IsdnCardState *cs)
 351{
 352        cs->hw.hfcsx.int_m2 = 0;        /* interrupt output off ! */
 353        Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 354
 355        printk(KERN_INFO "HFC_SX: resetting card\n");
 356        while (1) {
 357                Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */
 358                mdelay(30);
 359                Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
 360                mdelay(20);
 361                if (Read_hfc(cs, HFCSX_STATUS) & 2)
 362                        printk(KERN_WARNING "HFC-SX init bit busy\n");
 363                cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
 364                if (!set_fifo_size(cs)) continue;
 365                break;
 366        }
 367
 368        cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK;  /* no echo connect , threshold */
 369        Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 370
 371        Write_hfc(cs, HFCSX_CLKDEL, 0x0e);      /* ST-Bit delay for TE-Mode */
 372        cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
 373        Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);     /* S/T Auto awake */
 374        cs->hw.hfcsx.bswapped = 0;      /* no exchange */
 375        cs->hw.hfcsx.nt_mode = 0;       /* we are in TE mode */
 376        cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
 377        Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 378
 379        cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
 380                HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
 381        Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 382
 383        /* Clear already pending ints */
 384        Read_hfc(cs, HFCSX_INT_S1);
 385
 386        Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2);      /* HFC ST 2 */
 387        udelay(10);
 388        Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
 389        cs->hw.hfcsx.mst_m = HFCSX_MASTER;      /* HFC Master Mode */
 390
 391        Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 392        cs->hw.hfcsx.sctrl = 0x40;      /* set tx_lo mode, error in datasheet ! */
 393        Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 394        cs->hw.hfcsx.sctrl_r = 0;
 395        Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 396
 397        /* Init GCI/IOM2 in master mode */
 398        /* Slots 0 and 1 are set for B-chan 1 and 2 */
 399        /* D- and monitor/CI channel are not enabled */
 400        /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
 401        /* STIO2 is used as data input, B1+B2 from IOM->ST */
 402        /* ST B-channel send disabled -> continuous 1s */
 403        /* The IOM slots are always enabled */
 404        cs->hw.hfcsx.conn = 0x36;       /* set data flow directions */
 405        Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 406        Write_hfc(cs, HFCSX_B1_SSL, 0x80);      /* B1-Slot 0 STIO1 out enabled */
 407        Write_hfc(cs, HFCSX_B2_SSL, 0x81);      /* B2-Slot 1 STIO1 out enabled */
 408        Write_hfc(cs, HFCSX_B1_RSL, 0x80);      /* B1-Slot 0 STIO2 in enabled */
 409        Write_hfc(cs, HFCSX_B2_RSL, 0x81);      /* B2-Slot 1 STIO2 in enabled */
 410
 411        /* Finally enable IRQ output */
 412        cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
 413        Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 414        Read_hfc(cs, HFCSX_INT_S2);
 415}
 416
 417/***************************************************/
 418/* Timer function called when kernel timer expires */
 419/***************************************************/
 420static void
 421hfcsx_Timer(struct timer_list *t)
 422{
 423        struct IsdnCardState *cs = from_timer(cs, t, hw.hfcsx.timer);
 424        cs->hw.hfcsx.timer.expires = jiffies + 75;
 425        /* WD RESET */
 426/*      WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
 427        add_timer(&cs->hw.hfcsx.timer);
 428*/
 429}
 430
 431/************************************************/
 432/* select a b-channel entry matching and active */
 433/************************************************/
 434static
 435struct BCState *
 436Sel_BCS(struct IsdnCardState *cs, int channel)
 437{
 438        if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 439                return (&cs->bcs[0]);
 440        else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 441                return (&cs->bcs[1]);
 442        else
 443                return (NULL);
 444}
 445
 446/*******************************/
 447/* D-channel receive procedure */
 448/*******************************/
 449static
 450int
 451receive_dmsg(struct IsdnCardState *cs)
 452{
 453        struct sk_buff *skb;
 454        int count = 5;
 455
 456        if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 457                debugl1(cs, "rec_dmsg blocked");
 458                return (1);
 459        }
 460
 461        do {
 462                skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
 463                if (skb) {
 464                        skb_queue_tail(&cs->rq, skb);
 465                        schedule_event(cs, D_RCVBUFREADY);
 466                }
 467        } while (--count && skb);
 468
 469        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 470        return (1);
 471}
 472
 473/**********************************/
 474/* B-channel main receive routine */
 475/**********************************/
 476static void
 477main_rec_hfcsx(struct BCState *bcs)
 478{
 479        struct IsdnCardState *cs = bcs->cs;
 480        int count = 5;
 481        struct sk_buff *skb;
 482
 483Begin:
 484        count--;
 485        if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 486                debugl1(cs, "rec_data %d blocked", bcs->channel);
 487                return;
 488        }
 489        skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 490                        HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
 491                        (bcs->mode == L1_MODE_TRANS) ?
 492                        HFCSX_BTRANS_THRESHOLD : 0);
 493
 494        if (skb) {
 495                skb_queue_tail(&bcs->rqueue, skb);
 496                schedule_event(bcs, B_RCVBUFREADY);
 497        }
 498
 499        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 500        if (count && skb)
 501                goto Begin;
 502        return;
 503}
 504
 505/**************************/
 506/* D-channel send routine */
 507/**************************/
 508static void
 509hfcsx_fill_dfifo(struct IsdnCardState *cs)
 510{
 511        if (!cs->tx_skb)
 512                return;
 513        if (cs->tx_skb->len <= 0)
 514                return;
 515
 516        if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
 517                dev_kfree_skb_any(cs->tx_skb);
 518                cs->tx_skb = NULL;
 519        }
 520        return;
 521}
 522
 523/**************************/
 524/* B-channel send routine */
 525/**************************/
 526static void
 527hfcsx_fill_fifo(struct BCState *bcs)
 528{
 529        struct IsdnCardState *cs = bcs->cs;
 530
 531        if (!bcs->tx_skb)
 532                return;
 533        if (bcs->tx_skb->len <= 0)
 534                return;
 535
 536        if (write_fifo(cs, bcs->tx_skb,
 537                       ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 538                       HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
 539                       (bcs->mode == L1_MODE_TRANS) ?
 540                       HFCSX_BTRANS_THRESHOLD : 0)) {
 541
 542                bcs->tx_cnt -= bcs->tx_skb->len;
 543                if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
 544                    (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 545                        u_long  flags;
 546                        spin_lock_irqsave(&bcs->aclock, flags);
 547                        bcs->ackcnt += bcs->tx_skb->len;
 548                        spin_unlock_irqrestore(&bcs->aclock, flags);
 549                        schedule_event(bcs, B_ACKPENDING);
 550                }
 551                dev_kfree_skb_any(bcs->tx_skb);
 552                bcs->tx_skb = NULL;
 553                test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 554        }
 555}
 556
 557/**********************************************/
 558/* D-channel l1 state call for leased NT-mode */
 559/**********************************************/
 560static void
 561dch_nt_l2l1(struct PStack *st, int pr, void *arg)
 562{
 563        struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 564
 565        switch (pr) {
 566        case (PH_DATA | REQUEST):
 567        case (PH_PULL | REQUEST):
 568        case (PH_PULL | INDICATION):
 569                st->l1.l1hw(st, pr, arg);
 570                break;
 571        case (PH_ACTIVATE | REQUEST):
 572                st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
 573                break;
 574        case (PH_TESTLOOP | REQUEST):
 575                if (1 & (long) arg)
 576                        debugl1(cs, "PH_TEST_LOOP B1");
 577                if (2 & (long) arg)
 578                        debugl1(cs, "PH_TEST_LOOP B2");
 579                if (!(3 & (long) arg))
 580                        debugl1(cs, "PH_TEST_LOOP DISABLED");
 581                st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
 582                break;
 583        default:
 584                if (cs->debug)
 585                        debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
 586                break;
 587        }
 588}
 589
 590
 591
 592/***********************/
 593/* set/reset echo mode */
 594/***********************/
 595static int
 596hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic)
 597{
 598        unsigned long flags;
 599        int i = *(unsigned int *) ic->parm.num;
 600
 601        if ((ic->arg == 98) &&
 602            (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
 603                spin_lock_irqsave(&cs->lock, flags);
 604                Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0);      /* HFC ST G0 */
 605                udelay(10);
 606                cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
 607                Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
 608                udelay(10);
 609                Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1);      /* HFC ST G1 */
 610                udelay(10);
 611                Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 612                cs->dc.hfcsx.ph_state = 1;
 613                cs->hw.hfcsx.nt_mode = 1;
 614                cs->hw.hfcsx.nt_timer = 0;
 615                spin_unlock_irqrestore(&cs->lock, flags);
 616                cs->stlist->l2.l2l1 = dch_nt_l2l1;
 617                debugl1(cs, "NT mode activated");
 618                return (0);
 619        }
 620        if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
 621            (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
 622                return (-EINVAL);
 623
 624        if (i) {
 625                cs->logecho = 1;
 626                cs->hw.hfcsx.trm |= 0x20;       /* enable echo chan */
 627                cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
 628                /* reset Channel !!!!! */
 629        } else {
 630                cs->logecho = 0;
 631                cs->hw.hfcsx.trm &= ~0x20;      /* disable echo chan */
 632                cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
 633        }
 634        cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
 635        cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
 636        cs->hw.hfcsx.conn |= 0x10;      /* B2-IOM -> B2-ST */
 637        cs->hw.hfcsx.ctmt &= ~2;
 638        spin_lock_irqsave(&cs->lock, flags);
 639        Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 640        Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 641        Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 642        Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 643        Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 644        Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 645        spin_unlock_irqrestore(&cs->lock, flags);
 646        return (0);
 647}                               /* hfcsx_auxcmd */
 648
 649/*****************************/
 650/* E-channel receive routine */
 651/*****************************/
 652static void
 653receive_emsg(struct IsdnCardState *cs)
 654{
 655        int count = 5;
 656        u_char *ptr;
 657        struct sk_buff *skb;
 658
 659        if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 660                debugl1(cs, "echo_rec_data blocked");
 661                return;
 662        }
 663        do {
 664                skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
 665                if (skb) {
 666                        if (cs->debug & DEB_DLOG_HEX) {
 667                                ptr = cs->dlog;
 668                                if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
 669                                        *ptr++ = 'E';
 670                                        *ptr++ = 'C';
 671                                        *ptr++ = 'H';
 672                                        *ptr++ = 'O';
 673                                        *ptr++ = ':';
 674                                        ptr += QuickHex(ptr, skb->data, skb->len);
 675                                        ptr--;
 676                                        *ptr++ = '\n';
 677                                        *ptr = 0;
 678                                        HiSax_putstatus(cs, NULL, cs->dlog);
 679                                } else
 680                                        HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
 681                        }
 682                        dev_kfree_skb_any(skb);
 683                }
 684        } while (--count && skb);
 685
 686        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 687        return;
 688}                               /* receive_emsg */
 689
 690
 691/*********************/
 692/* Interrupt handler */
 693/*********************/
 694static irqreturn_t
 695hfcsx_interrupt(int intno, void *dev_id)
 696{
 697        struct IsdnCardState *cs = dev_id;
 698        u_char exval;
 699        struct BCState *bcs;
 700        int count = 15;
 701        u_long flags;
 702        u_char val, stat;
 703
 704        if (!(cs->hw.hfcsx.int_m2 & 0x08))
 705                return IRQ_NONE;                /* not initialised */
 706
 707        spin_lock_irqsave(&cs->lock, flags);
 708        if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
 709                val = Read_hfc(cs, HFCSX_INT_S1);
 710                if (cs->debug & L1_DEB_ISAC)
 711                        debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
 712        } else {
 713                spin_unlock_irqrestore(&cs->lock, flags);
 714                return IRQ_NONE;
 715        }
 716        if (cs->debug & L1_DEB_ISAC)
 717                debugl1(cs, "HFC-SX irq %x %s", val,
 718                        test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
 719                        "locked" : "unlocked");
 720        val &= cs->hw.hfcsx.int_m1;
 721        if (val & 0x40) {       /* state machine irq */
 722                exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
 723                if (cs->debug & L1_DEB_ISAC)
 724                        debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
 725                                exval);
 726                cs->dc.hfcsx.ph_state = exval;
 727                schedule_event(cs, D_L1STATECHANGE);
 728                val &= ~0x40;
 729        }
 730        if (val & 0x80) {       /* timer irq */
 731                if (cs->hw.hfcsx.nt_mode) {
 732                        if ((--cs->hw.hfcsx.nt_timer) < 0)
 733                                schedule_event(cs, D_L1STATECHANGE);
 734                }
 735                val &= ~0x80;
 736                Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
 737        }
 738        while (val) {
 739                if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 740                        cs->hw.hfcsx.int_s1 |= val;
 741                        spin_unlock_irqrestore(&cs->lock, flags);
 742                        return IRQ_HANDLED;
 743                }
 744                if (cs->hw.hfcsx.int_s1 & 0x18) {
 745                        exval = val;
 746                        val = cs->hw.hfcsx.int_s1;
 747                        cs->hw.hfcsx.int_s1 = exval;
 748                }
 749                if (val & 0x08) {
 750                        if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 751                                if (cs->debug)
 752                                        debugl1(cs, "hfcsx spurious 0x08 IRQ");
 753                        } else
 754                                main_rec_hfcsx(bcs);
 755                }
 756                if (val & 0x10) {
 757                        if (cs->logecho)
 758                                receive_emsg(cs);
 759                        else if (!(bcs = Sel_BCS(cs, 1))) {
 760                                if (cs->debug)
 761                                        debugl1(cs, "hfcsx spurious 0x10 IRQ");
 762                        } else
 763                                main_rec_hfcsx(bcs);
 764                }
 765                if (val & 0x01) {
 766                        if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 767                                if (cs->debug)
 768                                        debugl1(cs, "hfcsx spurious 0x01 IRQ");
 769                        } else {
 770                                if (bcs->tx_skb) {
 771                                        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 772                                                hfcsx_fill_fifo(bcs);
 773                                                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 774                                        } else
 775                                                debugl1(cs, "fill_data %d blocked", bcs->channel);
 776                                } else {
 777                                        if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 778                                                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 779                                                        hfcsx_fill_fifo(bcs);
 780                                                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 781                                                } else
 782                                                        debugl1(cs, "fill_data %d blocked", bcs->channel);
 783                                        } else {
 784                                                schedule_event(bcs, B_XMTBUFREADY);
 785                                        }
 786                                }
 787                        }
 788                }
 789                if (val & 0x02) {
 790                        if (!(bcs = Sel_BCS(cs, 1))) {
 791                                if (cs->debug)
 792                                        debugl1(cs, "hfcsx spurious 0x02 IRQ");
 793                        } else {
 794                                if (bcs->tx_skb) {
 795                                        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 796                                                hfcsx_fill_fifo(bcs);
 797                                                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 798                                        } else
 799                                                debugl1(cs, "fill_data %d blocked", bcs->channel);
 800                                } else {
 801                                        if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 802                                                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 803                                                        hfcsx_fill_fifo(bcs);
 804                                                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 805                                                } else
 806                                                        debugl1(cs, "fill_data %d blocked", bcs->channel);
 807                                        } else {
 808                                                schedule_event(bcs, B_XMTBUFREADY);
 809                                        }
 810                                }
 811                        }
 812                }
 813                if (val & 0x20) {       /* receive dframe */
 814                        receive_dmsg(cs);
 815                }
 816                if (val & 0x04) {       /* dframe transmitted */
 817                        if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 818                                del_timer(&cs->dbusytimer);
 819                        if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
 820                                schedule_event(cs, D_CLEARBUSY);
 821                        if (cs->tx_skb) {
 822                                if (cs->tx_skb->len) {
 823                                        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 824                                                hfcsx_fill_dfifo(cs);
 825                                                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 826                                        } else {
 827                                                debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 828                                        }
 829                                        goto afterXPR;
 830                                } else {
 831                                        dev_kfree_skb_irq(cs->tx_skb);
 832                                        cs->tx_cnt = 0;
 833                                        cs->tx_skb = NULL;
 834                                }
 835                        }
 836                        if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
 837                                cs->tx_cnt = 0;
 838                                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 839                                        hfcsx_fill_dfifo(cs);
 840                                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 841                                } else {
 842                                        debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 843                                }
 844                        } else
 845                                schedule_event(cs, D_XMTBUFREADY);
 846                }
 847        afterXPR:
 848                if (cs->hw.hfcsx.int_s1 && count--) {
 849                        val = cs->hw.hfcsx.int_s1;
 850                        cs->hw.hfcsx.int_s1 = 0;
 851                        if (cs->debug & L1_DEB_ISAC)
 852                                debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
 853                } else
 854                        val = 0;
 855        }
 856        spin_unlock_irqrestore(&cs->lock, flags);
 857        return IRQ_HANDLED;
 858}
 859
 860/********************************************************************/
 861/* timer callback for D-chan busy resolution. Currently no function */
 862/********************************************************************/
 863static void
 864hfcsx_dbusy_timer(struct timer_list *t)
 865{
 866}
 867
 868/*************************************/
 869/* Layer 1 D-channel hardware access */
 870/*************************************/
 871static void
 872HFCSX_l1hw(struct PStack *st, int pr, void *arg)
 873{
 874        struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 875        struct sk_buff *skb = arg;
 876        u_long flags;
 877
 878        switch (pr) {
 879        case (PH_DATA | REQUEST):
 880                if (cs->debug & DEB_DLOG_HEX)
 881                        LogFrame(cs, skb->data, skb->len);
 882                if (cs->debug & DEB_DLOG_VERBOSE)
 883                        dlogframe(cs, skb, 0);
 884                spin_lock_irqsave(&cs->lock, flags);
 885                if (cs->tx_skb) {
 886                        skb_queue_tail(&cs->sq, skb);
 887#ifdef L2FRAME_DEBUG            /* psa */
 888                        if (cs->debug & L1_DEB_LAPD)
 889                                Logl2Frame(cs, skb, "PH_DATA Queued", 0);
 890#endif
 891                } else {
 892                        cs->tx_skb = skb;
 893                        cs->tx_cnt = 0;
 894#ifdef L2FRAME_DEBUG            /* psa */
 895                        if (cs->debug & L1_DEB_LAPD)
 896                                Logl2Frame(cs, skb, "PH_DATA", 0);
 897#endif
 898                        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 899                                hfcsx_fill_dfifo(cs);
 900                                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 901                        } else
 902                                debugl1(cs, "hfcsx_fill_dfifo blocked");
 903
 904                }
 905                spin_unlock_irqrestore(&cs->lock, flags);
 906                break;
 907        case (PH_PULL | INDICATION):
 908                spin_lock_irqsave(&cs->lock, flags);
 909                if (cs->tx_skb) {
 910                        if (cs->debug & L1_DEB_WARN)
 911                                debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
 912                        skb_queue_tail(&cs->sq, skb);
 913                        spin_unlock_irqrestore(&cs->lock, flags);
 914                        break;
 915                }
 916                if (cs->debug & DEB_DLOG_HEX)
 917                        LogFrame(cs, skb->data, skb->len);
 918                if (cs->debug & DEB_DLOG_VERBOSE)
 919                        dlogframe(cs, skb, 0);
 920                cs->tx_skb = skb;
 921                cs->tx_cnt = 0;
 922#ifdef L2FRAME_DEBUG            /* psa */
 923                if (cs->debug & L1_DEB_LAPD)
 924                        Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 925#endif
 926                if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 927                        hfcsx_fill_dfifo(cs);
 928                        test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 929                } else
 930                        debugl1(cs, "hfcsx_fill_dfifo blocked");
 931                spin_unlock_irqrestore(&cs->lock, flags);
 932                break;
 933        case (PH_PULL | REQUEST):
 934#ifdef L2FRAME_DEBUG            /* psa */
 935                if (cs->debug & L1_DEB_LAPD)
 936                        debugl1(cs, "-> PH_REQUEST_PULL");
 937#endif
 938                if (!cs->tx_skb) {
 939                        test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 940                        st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 941                } else
 942                        test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 943                break;
 944        case (HW_RESET | REQUEST):
 945                spin_lock_irqsave(&cs->lock, flags);
 946                Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3);      /* HFC ST 3 */
 947                udelay(6);
 948                Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
 949                cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 950                Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 951                Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 952                spin_unlock_irqrestore(&cs->lock, flags);
 953                l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
 954                break;
 955        case (HW_ENABLE | REQUEST):
 956                spin_lock_irqsave(&cs->lock, flags);
 957                Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 958                spin_unlock_irqrestore(&cs->lock, flags);
 959                break;
 960        case (HW_DEACTIVATE | REQUEST):
 961                spin_lock_irqsave(&cs->lock, flags);
 962                cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
 963                Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 964                spin_unlock_irqrestore(&cs->lock, flags);
 965                break;
 966        case (HW_INFO3 | REQUEST):
 967                spin_lock_irqsave(&cs->lock, flags);
 968                cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 969                Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 970                spin_unlock_irqrestore(&cs->lock, flags);
 971                break;
 972        case (HW_TESTLOOP | REQUEST):
 973                spin_lock_irqsave(&cs->lock, flags);
 974                switch ((long) arg) {
 975                case (1):
 976                        Write_hfc(cs, HFCSX_B1_SSL, 0x80);      /* tx slot */
 977                        Write_hfc(cs, HFCSX_B1_RSL, 0x80);      /* rx slot */
 978                        cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
 979                        Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 980                        break;
 981                case (2):
 982                        Write_hfc(cs, HFCSX_B2_SSL, 0x81);      /* tx slot */
 983                        Write_hfc(cs, HFCSX_B2_RSL, 0x81);      /* rx slot */
 984                        cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
 985                        Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 986                        break;
 987                default:
 988                        spin_unlock_irqrestore(&cs->lock, flags);
 989                        if (cs->debug & L1_DEB_WARN)
 990                                debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg);
 991                        return;
 992                }
 993                cs->hw.hfcsx.trm |= 0x80;       /* enable IOM-loop */
 994                Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 995                spin_unlock_irqrestore(&cs->lock, flags);
 996                break;
 997        default:
 998                if (cs->debug & L1_DEB_WARN)
 999                        debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
1000                break;

1001        }
1002}
1003
1004/***********************************************/
1005/* called during init setting l1 stack pointer */
1006/***********************************************/
1007static void
1008setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1009{
1010        st->l1.l1hw = HFCSX_l1hw;
1011}
1012
1013/**************************************/
1014/* send B-channel data if not blocked */
1015/**************************************/
1016static void
1017hfcsx_send_data(struct BCState *bcs)
1018{
1019        struct IsdnCardState *cs = bcs->cs;
1020
1021        if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1022                hfcsx_fill_fifo(bcs);
1023                test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1024        } else
1025                debugl1(cs, "send_data %d blocked", bcs->channel);
1026}
1027
1028/***************************************************************/
1029/* activate/deactivate hardware for selected channels and mode */
1030/***************************************************************/
1031static void
1032mode_hfcsx(struct BCState *bcs, int mode, int bc)
1033{
1034        struct IsdnCardState *cs = bcs->cs;
1035        int fifo2;
1036
1037        if (cs->debug & L1_DEB_HSCX)
1038                debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1039                        mode, bc, bcs->channel);
1040        bcs->mode = mode;
1041        bcs->channel = bc;
1042        fifo2 = bc;
1043        if (cs->chanlimit > 1) {
1044                cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1045                cs->hw.hfcsx.sctrl_e &= ~0x80;
1046        } else {
1047                if (bc) {
1048                        if (mode != L1_MODE_NULL) {
1049                                cs->hw.hfcsx.bswapped = 1;      /* B1 and B2 exchanged */
1050                                cs->hw.hfcsx.sctrl_e |= 0x80;
1051                        } else {
1052                                cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1053                                cs->hw.hfcsx.sctrl_e &= ~0x80;
1054                        }
1055                        fifo2 = 0;
1056                } else {
1057                        cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1058                        cs->hw.hfcsx.sctrl_e &= ~0x80;
1059                }
1060        }
1061        switch (mode) {
1062        case (L1_MODE_NULL):
1063                if (bc) {
1064                        cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1065                        cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1066                } else {
1067                        cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1068                        cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1069                }
1070                if (fifo2) {
1071                        cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1072                } else {
1073                        cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1074                }
1075                break;
1076        case (L1_MODE_TRANS):
1077                if (bc) {
1078                        cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1079                        cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1080                } else {
1081                        cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1082                        cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1083                }
1084                if (fifo2) {
1085                        cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1086                        cs->hw.hfcsx.ctmt |= 2;
1087                        cs->hw.hfcsx.conn &= ~0x18;
1088                } else {
1089                        cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1090                        cs->hw.hfcsx.ctmt |= 1;
1091                        cs->hw.hfcsx.conn &= ~0x03;
1092                }
1093                break;
1094        case (L1_MODE_HDLC):
1095                if (bc) {
1096                        cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1097                        cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1098                } else {
1099                        cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1100                        cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1101                }
1102                if (fifo2) {
1103                        cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1104                        cs->hw.hfcsx.ctmt &= ~2;
1105                        cs->hw.hfcsx.conn &= ~0x18;
1106                } else {
1107                        cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1108                        cs->hw.hfcsx.ctmt &= ~1;
1109                        cs->hw.hfcsx.conn &= ~0x03;
1110                }
1111                break;
1112        case (L1_MODE_EXTRN):
1113                if (bc) {
1114                        cs->hw.hfcsx.conn |= 0x10;
1115                        cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1116                        cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1117                        cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1118                } else {
1119                        cs->hw.hfcsx.conn |= 0x02;
1120                        cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1121                        cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1122                        cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1123                }
1124                break;
1125        }
1126        Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1127        Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1128        Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1129        Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1130        Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1131        Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1132        if (mode != L1_MODE_EXTRN) {
1133                reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1134                reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1135        }
1136}
1137
1138/******************************/
1139/* Layer2 -> Layer 1 Transfer */
1140/******************************/
1141static void
1142hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1143{
1144        struct BCState *bcs = st->l1.bcs;
1145        struct sk_buff *skb = arg;
1146        u_long flags;
1147
1148        switch (pr) {
1149        case (PH_DATA | REQUEST):
1150                spin_lock_irqsave(&bcs->cs->lock, flags);
1151                if (bcs->tx_skb) {
1152                        skb_queue_tail(&bcs->squeue, skb);
1153                } else {
1154                        bcs->tx_skb = skb;
1155//                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1156                        bcs->cs->BC_Send_Data(bcs);
1157                }
1158                spin_unlock_irqrestore(&bcs->cs->lock, flags);
1159                break;
1160        case (PH_PULL | INDICATION):
1161                spin_lock_irqsave(&bcs->cs->lock, flags);
1162                if (bcs->tx_skb) {
1163                        printk(KERN_WARNING "%s: this shouldn't happen\n",
1164                               __func__);
1165                } else {
1166//                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1167                        bcs->tx_skb = skb;
1168                        bcs->cs->BC_Send_Data(bcs);
1169                }
1170                spin_unlock_irqrestore(&bcs->cs->lock, flags);
1171                break;
1172        case (PH_PULL | REQUEST):
1173                if (!bcs->tx_skb) {
1174                        test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1175                        st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1176                } else
1177                        test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1178                break;
1179        case (PH_ACTIVATE | REQUEST):
1180                spin_lock_irqsave(&bcs->cs->lock, flags);
1181                test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1182                mode_hfcsx(bcs, st->l1.mode, st->l1.bc);
1183                spin_unlock_irqrestore(&bcs->cs->lock, flags);
1184                l1_msg_b(st, pr, arg);
1185                break;
1186        case (PH_DEACTIVATE | REQUEST):
1187                l1_msg_b(st, pr, arg);
1188                break;
1189        case (PH_DEACTIVATE | CONFIRM):
1190                spin_lock_irqsave(&bcs->cs->lock, flags);
1191                test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1192                test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1193                mode_hfcsx(bcs, 0, st->l1.bc);
1194                spin_unlock_irqrestore(&bcs->cs->lock, flags);
1195                st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1196                break;
1197        }
1198}
1199
1200/******************************************/
1201/* deactivate B-channel access and queues */
1202/******************************************/
1203static void
1204close_hfcsx(struct BCState *bcs)
1205{
1206        mode_hfcsx(bcs, 0, bcs->channel);
1207        if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1208                skb_queue_purge(&bcs->rqueue);
1209                skb_queue_purge(&bcs->squeue);
1210                if (bcs->tx_skb) {
1211                        dev_kfree_skb_any(bcs->tx_skb);
1212                        bcs->tx_skb = NULL;
1213                        test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1214                }
1215        }
1216}
1217
1218/*************************************/
1219/* init B-channel queues and control */
1220/*************************************/
1221static int
1222open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1223{
1224        if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1225                skb_queue_head_init(&bcs->rqueue);
1226                skb_queue_head_init(&bcs->squeue);
1227        }
1228        bcs->tx_skb = NULL;
1229        test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1230        bcs->event = 0;
1231        bcs->tx_cnt = 0;
1232        return (0);
1233}
1234
1235/*********************************/
1236/* inits the stack for B-channel */
1237/*********************************/
1238static int
1239setstack_2b(struct PStack *st, struct BCState *bcs)
1240{
1241        bcs->channel = st->l1.bc;
1242        if (open_hfcsxstate(st->l1.hardware, bcs))
1243                return (-1);
1244        st->l1.bcs = bcs;
1245        st->l2.l2l1 = hfcsx_l2l1;
1246        setstack_manager(st);
1247        bcs->st = st;
1248        setstack_l1_B(st);
1249        return (0);
1250}
1251
1252/***************************/
1253/* handle L1 state changes */
1254/***************************/
1255static void
1256hfcsx_bh(struct work_struct *work)
1257{
1258        struct IsdnCardState *cs =
1259                container_of(work, struct IsdnCardState, tqueue);
1260        u_long flags;
1261
1262        if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1263                if (!cs->hw.hfcsx.nt_mode)
1264                        switch (cs->dc.hfcsx.ph_state) {
1265                        case (0):
1266                                l1_msg(cs, HW_RESET | INDICATION, NULL);
1267                                break;
1268                        case (3):
1269                                l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1270                                break;
1271                        case (8):
1272                                l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1273                                break;
1274                        case (6):
1275                                l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1276                                break;
1277                        case (7):
1278                                l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1279                                break;
1280                        default:
1281                                break;
1282                        } else {
1283                        switch (cs->dc.hfcsx.ph_state) {
1284                        case (2):
1285                                spin_lock_irqsave(&cs->lock, flags);
1286                                if (cs->hw.hfcsx.nt_timer < 0) {
1287                                        cs->hw.hfcsx.nt_timer = 0;
1288                                        cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1289                                        Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1290                                        /* Clear already pending ints */
1291                                        Read_hfc(cs, HFCSX_INT_S1);
1292
1293                                        Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1294                                        udelay(10);
1295                                        Write_hfc(cs, HFCSX_STATES, 4);
1296                                        cs->dc.hfcsx.ph_state = 4;
1297                                } else {
1298                                        cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1299                                        Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1300                                        cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1301                                        cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1302                                        Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1303                                        Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1304                                        cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1305                                        Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3);        /* allow G2 -> G3 transition */
1306                                }
1307                                spin_unlock_irqrestore(&cs->lock, flags);
1308                                break;
1309                        case (1):
1310                        case (3):
1311                        case (4):
1312                                spin_lock_irqsave(&cs->lock, flags);
1313                                cs->hw.hfcsx.nt_timer = 0;
1314                                cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1315                                Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1316                                spin_unlock_irqrestore(&cs->lock, flags);
1317                                break;
1318                        default:
1319                                break;
1320                        }
1321                }
1322        }
1323        if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1324                DChannel_proc_rcv(cs);
1325        if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1326                DChannel_proc_xmt(cs);
1327}
1328
1329
1330/********************************/
1331/* called for card init message */
1332/********************************/
1333static void inithfcsx(struct IsdnCardState *cs)
1334{
1335        cs->setstack_d = setstack_hfcsx;
1336        cs->BC_Send_Data = &hfcsx_send_data;
1337        cs->bcs[0].BC_SetStack = setstack_2b;
1338        cs->bcs[1].BC_SetStack = setstack_2b;
1339        cs->bcs[0].BC_Close = close_hfcsx;
1340        cs->bcs[1].BC_Close = close_hfcsx;
1341        mode_hfcsx(cs->bcs, 0, 0);
1342        mode_hfcsx(cs->bcs + 1, 0, 1);
1343}
1344
1345
1346
1347/*******************************************/
1348/* handle card messages from control layer */
1349/*******************************************/
1350static int
1351hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1352{
1353        u_long flags;
1354
1355        if (cs->debug & L1_DEB_ISAC)
1356                debugl1(cs, "HFCSX: card_msg %x", mt);
1357        switch (mt) {
1358        case CARD_RESET:
1359                spin_lock_irqsave(&cs->lock, flags);
1360                reset_hfcsx(cs);
1361                spin_unlock_irqrestore(&cs->lock, flags);
1362                return (0);
1363        case CARD_RELEASE:
1364                release_io_hfcsx(cs);
1365                return (0);
1366        case CARD_INIT:
1367                spin_lock_irqsave(&cs->lock, flags);
1368                inithfcsx(cs);
1369                spin_unlock_irqrestore(&cs->lock, flags);
1370                msleep(80);                             /* Timeout 80ms */
1371                /* now switch timer interrupt off */
1372                spin_lock_irqsave(&cs->lock, flags);
1373                cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1374                Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1375                /* reinit mode reg */
1376                Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1377                spin_unlock_irqrestore(&cs->lock, flags);
1378                return (0);
1379        case CARD_TEST:
1380                return (0);
1381        }
1382        return (0);
1383}
1384
1385#ifdef __ISAPNP__
1386static struct isapnp_device_id hfc_ids[] = {
1387        { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1388          ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1389          (unsigned long) "Teles 16.3c2" },
1390        { 0, }
1391};
1392
1393static struct isapnp_device_id *ipid = &hfc_ids[0];
1394static struct pnp_card *pnp_c = NULL;
1395#endif
1396
1397int setup_hfcsx(struct IsdnCard *card)
1398{
1399        struct IsdnCardState *cs = card->cs;
1400        char tmp[64];
1401
1402        strcpy(tmp, hfcsx_revision);
1403        printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1404#ifdef __ISAPNP__
1405        if (!card->para[1] && isapnp_present()) {
1406                struct pnp_dev *pnp_d;
1407                while (ipid->card_vendor) {
1408                        if ((pnp_c = pnp_find_card(ipid->card_vendor,
1409                                                   ipid->card_device, pnp_c))) {
1410                                pnp_d = NULL;
1411                                if ((pnp_d = pnp_find_dev(pnp_c,
1412                                                          ipid->vendor, ipid->function, pnp_d))) {
1413                                        int err;
1414
1415                                        printk(KERN_INFO "HiSax: %s detected\n",
1416                                               (char *)ipid->driver_data);
1417                                        pnp_disable_dev(pnp_d);
1418                                        err = pnp_activate_dev(pnp_d);
1419                                        if (err < 0) {
1420                                                printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1421                                                       __func__, err);
1422                                                return (0);
1423                                        }
1424                                        card->para[1] = pnp_port_start(pnp_d, 0);
1425                                        card->para[0] = pnp_irq(pnp_d, 0);
1426                                        if (card->para[0] == -1 || !card->para[1]) {
1427                                                printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1428                                                       card->para[0], card->para[1]);
1429                                                pnp_disable_dev(pnp_d);
1430                                                return (0);
1431                                        }
1432                                        break;
1433                                } else {
1434                                        printk(KERN_ERR "HFC PnP: PnP error card found, no device\n");
1435                                }
1436                        }
1437                        ipid++;
1438                        pnp_c = NULL;
1439                }
1440                if (!ipid->card_vendor) {
1441                        printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1442                        return (0);
1443                }
1444        }
1445#endif
1446        cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1447        cs->irq = card->para[0];
1448        cs->hw.hfcsx.int_s1 = 0;
1449        cs->dc.hfcsx.ph_state = 0;
1450        cs->hw.hfcsx.fifo = 255;
1451        if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1452            (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1453                if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) {
1454                        printk(KERN_WARNING
1455                               "HiSax: HFC-SX io-base %#lx already in use\n",
1456                               cs->hw.hfcsx.base);
1457                        return (0);
1458                }
1459                byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1460                byteout(cs->hw.hfcsx.base + 1,
1461                        ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1462                udelay(10);
1463                cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID);
1464                switch (cs->hw.hfcsx.chip >> 4) {
1465                case 1:
1466                        tmp[0] = '+';
1467                        break;
1468                case 9:
1469                        tmp[0] = 'P';
1470                        break;
1471                default:
1472                        printk(KERN_WARNING
1473                               "HFC-SX: invalid chip id 0x%x\n",
1474                               cs->hw.hfcsx.chip >> 4);
1475                        release_region(cs->hw.hfcsx.base, 2);
1476                        return (0);
1477                }
1478                if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1479                        printk(KERN_WARNING
1480                               "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF);
1481                        release_region(cs->hw.hfcsx.base, 2);
1482                        return (0);
1483                }
1484                if (!(cs->hw.hfcsx.extra =
1485                      kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1486                        release_region(cs->hw.hfcsx.base, 2);
1487                        printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1488                        return (0);
1489                }
1490                printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1491                       tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ);
1492                cs->hw.hfcsx.int_m2 = 0;        /* disable alle interrupts */
1493                cs->hw.hfcsx.int_m1 = 0;
1494                Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1495                Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1496        } else
1497                return (0);     /* no valid card type */
1498
1499        timer_setup(&cs->dbusytimer, hfcsx_dbusy_timer, 0);
1500        INIT_WORK(&cs->tqueue, hfcsx_bh);
1501        cs->readisac = NULL;
1502        cs->writeisac = NULL;
1503        cs->readisacfifo = NULL;
1504        cs->writeisacfifo = NULL;
1505        cs->BC_Read_Reg = NULL;
1506        cs->BC_Write_Reg = NULL;
1507        cs->irq_func = &hfcsx_interrupt;
1508
1509        cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1510        cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1511        timer_setup(&cs->hw.hfcsx.timer, hfcsx_Timer, 0);
1512
1513        reset_hfcsx(cs);
1514        cs->cardmsg = &hfcsx_card_msg;
1515        cs->auxcmd = &hfcsx_auxcmd;
1516        return (1);
1517}
1518