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8#include <linux/bitfield.h>
9#include <linux/clk.h>
10#include <linux/interrupt.h>
11#include <linux/io.h>
12#include <linux/mailbox_controller.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/pm_wakeirq.h>
16
17#define IPCC_XCR 0x000
18#define XCR_RXOIE BIT(0)
19#define XCR_TXOIE BIT(16)
20
21#define IPCC_XMR 0x004
22#define IPCC_XSCR 0x008
23#define IPCC_XTOYSR 0x00c
24
25#define IPCC_PROC_OFFST 0x010
26
27#define IPCC_HWCFGR 0x3f0
28#define IPCFGR_CHAN_MASK GENMASK(7, 0)
29
30#define IPCC_VER 0x3f4
31#define VER_MINREV_MASK GENMASK(3, 0)
32#define VER_MAJREV_MASK GENMASK(7, 4)
33
34#define RX_BIT_MASK GENMASK(15, 0)
35#define RX_BIT_CHAN(chan) BIT(chan)
36#define TX_BIT_SHIFT 16
37#define TX_BIT_MASK GENMASK(31, 16)
38#define TX_BIT_CHAN(chan) BIT(TX_BIT_SHIFT + (chan))
39
40#define STM32_MAX_PROCS 2
41
42enum {
43 IPCC_IRQ_RX,
44 IPCC_IRQ_TX,
45 IPCC_IRQ_NUM,
46};
47
48struct stm32_ipcc {
49 struct mbox_controller controller;
50 void __iomem *reg_base;
51 void __iomem *reg_proc;
52 struct clk *clk;
53 int irqs[IPCC_IRQ_NUM];
54 int wkp;
55 u32 proc_id;
56 u32 n_chans;
57 u32 xcr;
58 u32 xmr;
59};
60
61static inline void stm32_ipcc_set_bits(void __iomem *reg, u32 mask)
62{
63 writel_relaxed(readl_relaxed(reg) | mask, reg);
64}
65
66static inline void stm32_ipcc_clr_bits(void __iomem *reg, u32 mask)
67{
68 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
69}
70
71static irqreturn_t stm32_ipcc_rx_irq(int irq, void *data)
72{
73 struct stm32_ipcc *ipcc = data;
74 struct device *dev = ipcc->controller.dev;
75 u32 status, mr, tosr, chan;
76 irqreturn_t ret = IRQ_NONE;
77 int proc_offset;
78
79
80 proc_offset = ipcc->proc_id ? -IPCC_PROC_OFFST : IPCC_PROC_OFFST;
81 tosr = readl_relaxed(ipcc->reg_proc + proc_offset + IPCC_XTOYSR);
82 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
83
84
85 status = tosr & FIELD_GET(RX_BIT_MASK, ~mr);
86
87 for (chan = 0; chan < ipcc->n_chans; chan++) {
88 if (!(status & (1 << chan)))
89 continue;
90
91 dev_dbg(dev, "%s: chan:%d rx\n", __func__, chan);
92
93 mbox_chan_received_data(&ipcc->controller.chans[chan], NULL);
94
95 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR,
96 RX_BIT_CHAN(chan));
97
98 ret = IRQ_HANDLED;
99 }
100
101 return ret;
102}
103
104static irqreturn_t stm32_ipcc_tx_irq(int irq, void *data)
105{
106 struct stm32_ipcc *ipcc = data;
107 struct device *dev = ipcc->controller.dev;
108 u32 status, mr, tosr, chan;
109 irqreturn_t ret = IRQ_NONE;
110
111 tosr = readl_relaxed(ipcc->reg_proc + IPCC_XTOYSR);
112 mr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
113
114
115 status = ~tosr & FIELD_GET(TX_BIT_MASK, ~mr);
116
117 for (chan = 0; chan < ipcc->n_chans ; chan++) {
118 if (!(status & (1 << chan)))
119 continue;
120
121 dev_dbg(dev, "%s: chan:%d tx\n", __func__, chan);
122
123
124 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
125 TX_BIT_CHAN(chan));
126
127 mbox_chan_txdone(&ipcc->controller.chans[chan], 0);
128
129 ret = IRQ_HANDLED;
130 }
131
132 return ret;
133}
134
135static int stm32_ipcc_send_data(struct mbox_chan *link, void *data)
136{
137 unsigned int chan = (unsigned int)link->con_priv;
138 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
139 controller);
140
141 dev_dbg(ipcc->controller.dev, "%s: chan:%d\n", __func__, chan);
142
143
144 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XSCR, TX_BIT_CHAN(chan));
145
146
147 stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, TX_BIT_CHAN(chan));
148
149 return 0;
150}
151
152static int stm32_ipcc_startup(struct mbox_chan *link)
153{
154 unsigned int chan = (unsigned int)link->con_priv;
155 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
156 controller);
157 int ret;
158
159 ret = clk_prepare_enable(ipcc->clk);
160 if (ret) {
161 dev_err(ipcc->controller.dev, "can not enable the clock\n");
162 return ret;
163 }
164
165
166 stm32_ipcc_clr_bits(ipcc->reg_proc + IPCC_XMR, RX_BIT_CHAN(chan));
167
168 return 0;
169}
170
171static void stm32_ipcc_shutdown(struct mbox_chan *link)
172{
173 unsigned int chan = (unsigned int)link->con_priv;
174 struct stm32_ipcc *ipcc = container_of(link->mbox, struct stm32_ipcc,
175 controller);
176
177
178 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
179 RX_BIT_CHAN(chan) | TX_BIT_CHAN(chan));
180
181 clk_disable_unprepare(ipcc->clk);
182}
183
184static const struct mbox_chan_ops stm32_ipcc_ops = {
185 .send_data = stm32_ipcc_send_data,
186 .startup = stm32_ipcc_startup,
187 .shutdown = stm32_ipcc_shutdown,
188};
189
190static int stm32_ipcc_probe(struct platform_device *pdev)
191{
192 struct device *dev = &pdev->dev;
193 struct device_node *np = dev->of_node;
194 struct stm32_ipcc *ipcc;
195 struct resource *res;
196 unsigned int i;
197 int ret;
198 u32 ip_ver;
199 static const char * const irq_name[] = {"rx", "tx"};
200 irq_handler_t irq_thread[] = {stm32_ipcc_rx_irq, stm32_ipcc_tx_irq};
201
202 if (!np) {
203 dev_err(dev, "No DT found\n");
204 return -ENODEV;
205 }
206
207 ipcc = devm_kzalloc(dev, sizeof(*ipcc), GFP_KERNEL);
208 if (!ipcc)
209 return -ENOMEM;
210
211
212 if (of_property_read_u32(np, "st,proc-id", &ipcc->proc_id)) {
213 dev_err(dev, "Missing st,proc-id\n");
214 return -ENODEV;
215 }
216
217 if (ipcc->proc_id >= STM32_MAX_PROCS) {
218 dev_err(dev, "Invalid proc_id (%d)\n", ipcc->proc_id);
219 return -EINVAL;
220 }
221
222
223 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
224 ipcc->reg_base = devm_ioremap_resource(dev, res);
225 if (IS_ERR(ipcc->reg_base))
226 return PTR_ERR(ipcc->reg_base);
227
228 ipcc->reg_proc = ipcc->reg_base + ipcc->proc_id * IPCC_PROC_OFFST;
229
230
231 ipcc->clk = devm_clk_get(dev, NULL);
232 if (IS_ERR(ipcc->clk))
233 return PTR_ERR(ipcc->clk);
234
235 ret = clk_prepare_enable(ipcc->clk);
236 if (ret) {
237 dev_err(dev, "can not enable the clock\n");
238 return ret;
239 }
240
241
242 for (i = 0; i < IPCC_IRQ_NUM; i++) {
243 ipcc->irqs[i] = platform_get_irq_byname(pdev, irq_name[i]);
244 if (ipcc->irqs[i] < 0) {
245 if (ipcc->irqs[i] != -EPROBE_DEFER)
246 dev_err(dev, "no IRQ specified %s\n",
247 irq_name[i]);
248 ret = ipcc->irqs[i];
249 goto err_clk;
250 }
251
252 ret = devm_request_threaded_irq(dev, ipcc->irqs[i], NULL,
253 irq_thread[i], IRQF_ONESHOT,
254 dev_name(dev), ipcc);
255 if (ret) {
256 dev_err(dev, "failed to request irq %d (%d)\n", i, ret);
257 goto err_clk;
258 }
259 }
260
261
262 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XMR,
263 RX_BIT_MASK | TX_BIT_MASK);
264 stm32_ipcc_set_bits(ipcc->reg_proc + IPCC_XCR, XCR_RXOIE | XCR_TXOIE);
265
266
267 if (of_property_read_bool(np, "wakeup-source")) {
268 ipcc->wkp = platform_get_irq_byname(pdev, "wakeup");
269 if (ipcc->wkp < 0) {
270 if (ipcc->wkp != -EPROBE_DEFER)
271 dev_err(dev, "could not get wakeup IRQ\n");
272 ret = ipcc->wkp;
273 goto err_clk;
274 }
275
276 device_set_wakeup_capable(dev, true);
277 ret = dev_pm_set_dedicated_wake_irq(dev, ipcc->wkp);
278 if (ret) {
279 dev_err(dev, "Failed to set wake up irq\n");
280 goto err_init_wkp;
281 }
282 }
283
284
285 ipcc->n_chans = readl_relaxed(ipcc->reg_base + IPCC_HWCFGR);
286 ipcc->n_chans &= IPCFGR_CHAN_MASK;
287
288 ipcc->controller.dev = dev;
289 ipcc->controller.txdone_irq = true;
290 ipcc->controller.ops = &stm32_ipcc_ops;
291 ipcc->controller.num_chans = ipcc->n_chans;
292 ipcc->controller.chans = devm_kcalloc(dev, ipcc->controller.num_chans,
293 sizeof(*ipcc->controller.chans),
294 GFP_KERNEL);
295 if (!ipcc->controller.chans) {
296 ret = -ENOMEM;
297 goto err_irq_wkp;
298 }
299
300 for (i = 0; i < ipcc->controller.num_chans; i++)
301 ipcc->controller.chans[i].con_priv = (void *)i;
302
303 ret = devm_mbox_controller_register(dev, &ipcc->controller);
304 if (ret)
305 goto err_irq_wkp;
306
307 platform_set_drvdata(pdev, ipcc);
308
309 ip_ver = readl_relaxed(ipcc->reg_base + IPCC_VER);
310
311 dev_info(dev, "ipcc rev:%ld.%ld enabled, %d chans, proc %d\n",
312 FIELD_GET(VER_MAJREV_MASK, ip_ver),
313 FIELD_GET(VER_MINREV_MASK, ip_ver),
314 ipcc->controller.num_chans, ipcc->proc_id);
315
316 clk_disable_unprepare(ipcc->clk);
317 return 0;
318
319err_irq_wkp:
320 if (ipcc->wkp)
321 dev_pm_clear_wake_irq(dev);
322err_init_wkp:
323 device_init_wakeup(dev, false);
324err_clk:
325 clk_disable_unprepare(ipcc->clk);
326 return ret;
327}
328
329static int stm32_ipcc_remove(struct platform_device *pdev)
330{
331 struct stm32_ipcc *ipcc = platform_get_drvdata(pdev);
332
333 if (ipcc->wkp)
334 dev_pm_clear_wake_irq(&pdev->dev);
335
336 device_init_wakeup(&pdev->dev, false);
337
338 return 0;
339}
340
341#ifdef CONFIG_PM_SLEEP
342static void stm32_ipcc_set_irq_wake(struct device *dev, bool enable)
343{
344 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
345 unsigned int i;
346
347 if (device_may_wakeup(dev))
348 for (i = 0; i < IPCC_IRQ_NUM; i++)
349 irq_set_irq_wake(ipcc->irqs[i], enable);
350}
351
352static int stm32_ipcc_suspend(struct device *dev)
353{
354 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
355
356 ipcc->xmr = readl_relaxed(ipcc->reg_proc + IPCC_XMR);
357 ipcc->xcr = readl_relaxed(ipcc->reg_proc + IPCC_XCR);
358
359 stm32_ipcc_set_irq_wake(dev, true);
360
361 return 0;
362}
363
364static int stm32_ipcc_resume(struct device *dev)
365{
366 struct stm32_ipcc *ipcc = dev_get_drvdata(dev);
367
368 stm32_ipcc_set_irq_wake(dev, false);
369
370 writel_relaxed(ipcc->xmr, ipcc->reg_proc + IPCC_XMR);
371 writel_relaxed(ipcc->xcr, ipcc->reg_proc + IPCC_XCR);
372
373 return 0;
374}
375#endif
376
377static SIMPLE_DEV_PM_OPS(stm32_ipcc_pm_ops,
378 stm32_ipcc_suspend, stm32_ipcc_resume);
379
380static const struct of_device_id stm32_ipcc_of_match[] = {
381 { .compatible = "st,stm32mp1-ipcc" },
382 {},
383};
384MODULE_DEVICE_TABLE(of, stm32_ipcc_of_match);
385
386static struct platform_driver stm32_ipcc_driver = {
387 .driver = {
388 .name = "stm32-ipcc",
389 .pm = &stm32_ipcc_pm_ops,
390 .of_match_table = stm32_ipcc_of_match,
391 },
392 .probe = stm32_ipcc_probe,
393 .remove = stm32_ipcc_remove,
394};
395
396module_platform_driver(stm32_ipcc_driver);
397
398MODULE_AUTHOR("Ludovic Barre <ludovic.barre@st.com>");
399MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
400MODULE_DESCRIPTION("STM32 IPCC driver");
401MODULE_LICENSE("GPL v2");
402
