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12#include "stv0900.h"
13#include "stv0900_reg.h"
14#include "stv0900_priv.h"
15
16s32 shiftx(s32 x, int demod, s32 shift)
17{
18 if (demod == 1)
19 return x - shift;
20
21 return x;
22}
23
24int stv0900_check_signal_presence(struct stv0900_internal *intp,
25 enum fe_stv0900_demod_num demod)
26{
27 s32 carr_offset,
28 agc2_integr,
29 max_carrier;
30
31 int no_signal = FALSE;
32
33 carr_offset = (stv0900_read_reg(intp, CFR2) << 8)
34 | stv0900_read_reg(intp, CFR1);
35 carr_offset = ge2comp(carr_offset, 16);
36 agc2_integr = (stv0900_read_reg(intp, AGC2I1) << 8)
37 | stv0900_read_reg(intp, AGC2I0);
38 max_carrier = intp->srch_range[demod] / 1000;
39
40 max_carrier += (max_carrier / 10);
41 max_carrier = 65536 * (max_carrier / 2);
42 max_carrier /= intp->mclk / 1000;
43 if (max_carrier > 0x4000)
44 max_carrier = 0x4000;
45
46 if ((agc2_integr > 0x2000)
47 || (carr_offset > (2 * max_carrier))
48 || (carr_offset < (-2 * max_carrier)))
49 no_signal = TRUE;
50
51 return no_signal;
52}
53
54static void stv0900_get_sw_loop_params(struct stv0900_internal *intp,
55 s32 *frequency_inc, s32 *sw_timeout,
56 s32 *steps,
57 enum fe_stv0900_demod_num demod)
58{
59 s32 timeout, freq_inc, max_steps, srate, max_carrier;
60
61 enum fe_stv0900_search_standard standard;
62
63 srate = intp->symbol_rate[demod];
64 max_carrier = intp->srch_range[demod] / 1000;
65 max_carrier += max_carrier / 10;
66 standard = intp->srch_standard[demod];
67
68 max_carrier = 65536 * (max_carrier / 2);
69 max_carrier /= intp->mclk / 1000;
70
71 if (max_carrier > 0x4000)
72 max_carrier = 0x4000;
73
74 freq_inc = srate;
75 freq_inc /= intp->mclk >> 10;
76 freq_inc = freq_inc << 6;
77
78 switch (standard) {
79 case STV0900_SEARCH_DVBS1:
80 case STV0900_SEARCH_DSS:
81 freq_inc *= 3;
82 timeout = 20;
83 break;
84 case STV0900_SEARCH_DVBS2:
85 freq_inc *= 4;
86 timeout = 25;
87 break;
88 case STV0900_AUTO_SEARCH:
89 default:
90 freq_inc *= 3;
91 timeout = 25;
92 break;
93 }
94
95 freq_inc /= 100;
96
97 if ((freq_inc > max_carrier) || (freq_inc < 0))
98 freq_inc = max_carrier / 2;
99
100 timeout *= 27500;
101
102 if (srate > 0)
103 timeout /= srate / 1000;
104
105 if ((timeout > 100) || (timeout < 0))
106 timeout = 100;
107
108 max_steps = (max_carrier / freq_inc) + 1;
109
110 if ((max_steps > 100) || (max_steps < 0)) {
111 max_steps = 100;
112 freq_inc = max_carrier / max_steps;
113 }
114
115 *frequency_inc = freq_inc;
116 *sw_timeout = timeout;
117 *steps = max_steps;
118
119}
120
121static int stv0900_search_carr_sw_loop(struct stv0900_internal *intp,
122 s32 FreqIncr, s32 Timeout, int zigzag,
123 s32 MaxStep, enum fe_stv0900_demod_num demod)
124{
125 int no_signal,
126 lock = FALSE;
127 s32 stepCpt,
128 freqOffset,
129 max_carrier;
130
131 max_carrier = intp->srch_range[demod] / 1000;
132 max_carrier += (max_carrier / 10);
133
134 max_carrier = 65536 * (max_carrier / 2);
135 max_carrier /= intp->mclk / 1000;
136
137 if (max_carrier > 0x4000)
138 max_carrier = 0x4000;
139
140 if (zigzag == TRUE)
141 freqOffset = 0;
142 else
143 freqOffset = -max_carrier + FreqIncr;
144
145 stepCpt = 0;
146
147 do {
148 stv0900_write_reg(intp, DMDISTATE, 0x1c);
149 stv0900_write_reg(intp, CFRINIT1, (freqOffset / 256) & 0xff);
150 stv0900_write_reg(intp, CFRINIT0, freqOffset & 0xff);
151 stv0900_write_reg(intp, DMDISTATE, 0x18);
152 stv0900_write_bits(intp, ALGOSWRST, 1);
153
154 if (intp->chip_id == 0x12) {
155 stv0900_write_bits(intp, RST_HWARE, 1);
156 stv0900_write_bits(intp, RST_HWARE, 0);
157 }
158
159 if (zigzag == TRUE) {
160 if (freqOffset >= 0)
161 freqOffset = -freqOffset - 2 * FreqIncr;
162 else
163 freqOffset = -freqOffset;
164 } else
165 freqOffset += + 2 * FreqIncr;
166
167 stepCpt++;
168 lock = stv0900_get_demod_lock(intp, demod, Timeout);
169 no_signal = stv0900_check_signal_presence(intp, demod);
170
171 } while ((lock == FALSE)
172 && (no_signal == FALSE)
173 && ((freqOffset - FreqIncr) < max_carrier)
174 && ((freqOffset + FreqIncr) > -max_carrier)
175 && (stepCpt < MaxStep));
176
177 stv0900_write_bits(intp, ALGOSWRST, 0);
178
179 return lock;
180}
181
182static int stv0900_sw_algo(struct stv0900_internal *intp,
183 enum fe_stv0900_demod_num demod)
184{
185 int lock = FALSE,
186 no_signal,
187 zigzag;
188 s32 s2fw,
189 fqc_inc,
190 sft_stp_tout,
191 trial_cntr,
192 max_steps;
193
194 stv0900_get_sw_loop_params(intp, &fqc_inc, &sft_stp_tout,
195 &max_steps, demod);
196 switch (intp->srch_standard[demod]) {
197 case STV0900_SEARCH_DVBS1:
198 case STV0900_SEARCH_DSS:
199 if (intp->chip_id >= 0x20)
200 stv0900_write_reg(intp, CARFREQ, 0x3b);
201 else
202 stv0900_write_reg(intp, CARFREQ, 0xef);
203
204 stv0900_write_reg(intp, DMDCFGMD, 0x49);
205 zigzag = FALSE;
206 break;
207 case STV0900_SEARCH_DVBS2:
208 if (intp->chip_id >= 0x20)
209 stv0900_write_reg(intp, CORRELABS, 0x79);
210 else
211 stv0900_write_reg(intp, CORRELABS, 0x68);
212
213 stv0900_write_reg(intp, DMDCFGMD, 0x89);
214
215 zigzag = TRUE;
216 break;
217 case STV0900_AUTO_SEARCH:
218 default:
219 if (intp->chip_id >= 0x20) {
220 stv0900_write_reg(intp, CARFREQ, 0x3b);
221 stv0900_write_reg(intp, CORRELABS, 0x79);
222 } else {
223 stv0900_write_reg(intp, CARFREQ, 0xef);
224 stv0900_write_reg(intp, CORRELABS, 0x68);
225 }
226
227 stv0900_write_reg(intp, DMDCFGMD, 0xc9);
228 zigzag = FALSE;
229 break;
230 }
231
232 trial_cntr = 0;
233 do {
234 lock = stv0900_search_carr_sw_loop(intp,
235 fqc_inc,
236 sft_stp_tout,
237 zigzag,
238 max_steps,
239 demod);
240 no_signal = stv0900_check_signal_presence(intp, demod);
241 trial_cntr++;
242 if ((lock == TRUE)
243 || (no_signal == TRUE)
244 || (trial_cntr == 2)) {
245
246 if (intp->chip_id >= 0x20) {
247 stv0900_write_reg(intp, CARFREQ, 0x49);
248 stv0900_write_reg(intp, CORRELABS, 0x9e);
249 } else {
250 stv0900_write_reg(intp, CARFREQ, 0xed);
251 stv0900_write_reg(intp, CORRELABS, 0x88);
252 }
253
254 if ((stv0900_get_bits(intp, HEADER_MODE) ==
255 STV0900_DVBS2_FOUND) &&
256 (lock == TRUE)) {
257 msleep(sft_stp_tout);
258 s2fw = stv0900_get_bits(intp, FLYWHEEL_CPT);
259
260 if (s2fw < 0xd) {
261 msleep(sft_stp_tout);
262 s2fw = stv0900_get_bits(intp,
263 FLYWHEEL_CPT);
264 }
265
266 if (s2fw < 0xd) {
267 lock = FALSE;
268
269 if (trial_cntr < 2) {
270 if (intp->chip_id >= 0x20)
271 stv0900_write_reg(intp,
272 CORRELABS,
273 0x79);
274 else
275 stv0900_write_reg(intp,
276 CORRELABS,
277 0x68);
278
279 stv0900_write_reg(intp,
280 DMDCFGMD,
281 0x89);
282 }
283 }
284 }
285 }
286
287 } while ((lock == FALSE)
288 && (trial_cntr < 2)
289 && (no_signal == FALSE));
290
291 return lock;
292}
293
294static u32 stv0900_get_symbol_rate(struct stv0900_internal *intp,
295 u32 mclk,
296 enum fe_stv0900_demod_num demod)
297{
298 s32 rem1, rem2, intval1, intval2, srate;
299
300 srate = (stv0900_get_bits(intp, SYMB_FREQ3) << 24) +
301 (stv0900_get_bits(intp, SYMB_FREQ2) << 16) +
302 (stv0900_get_bits(intp, SYMB_FREQ1) << 8) +
303 (stv0900_get_bits(intp, SYMB_FREQ0));
304 dprintk("lock: srate=%d r0=0x%x r1=0x%x r2=0x%x r3=0x%x \n",
305 srate, stv0900_get_bits(intp, SYMB_FREQ0),
306 stv0900_get_bits(intp, SYMB_FREQ1),
307 stv0900_get_bits(intp, SYMB_FREQ2),
308 stv0900_get_bits(intp, SYMB_FREQ3));
309
310 intval1 = (mclk) >> 16;
311 intval2 = (srate) >> 16;
312
313 rem1 = (mclk) % 0x10000;
314 rem2 = (srate) % 0x10000;
315 srate = (intval1 * intval2) +
316 ((intval1 * rem2) >> 16) +
317 ((intval2 * rem1) >> 16);
318
319 return srate;
320}
321
322static void stv0900_set_symbol_rate(struct stv0900_internal *intp,
323 u32 mclk, u32 srate,
324 enum fe_stv0900_demod_num demod)
325{
326 u32 symb;
327
328 dprintk("%s: Mclk %d, SR %d, Dmd %d\n", __func__, mclk,
329 srate, demod);
330
331 if (srate > 60000000) {
332 symb = srate << 4;
333 symb /= (mclk >> 12);
334 } else if (srate > 6000000) {
335 symb = srate << 6;
336 symb /= (mclk >> 10);
337 } else {
338 symb = srate << 9;
339 symb /= (mclk >> 7);
340 }
341
342 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0x7f);
343 stv0900_write_reg(intp, SFRINIT1 + 1, (symb & 0xff));
344}
345
346static void stv0900_set_max_symbol_rate(struct stv0900_internal *intp,
347 u32 mclk, u32 srate,
348 enum fe_stv0900_demod_num demod)
349{
350 u32 symb;
351
352 srate = 105 * (srate / 100);
353
354 if (srate > 60000000) {
355 symb = srate << 4;
356 symb /= (mclk >> 12);
357 } else if (srate > 6000000) {
358 symb = srate << 6;
359 symb /= (mclk >> 10);
360 } else {
361 symb = srate << 9;
362 symb /= (mclk >> 7);
363 }
364
365 if (symb < 0x7fff) {
366 stv0900_write_reg(intp, SFRUP1, (symb >> 8) & 0x7f);
367 stv0900_write_reg(intp, SFRUP1 + 1, (symb & 0xff));
368 } else {
369 stv0900_write_reg(intp, SFRUP1, 0x7f);
370 stv0900_write_reg(intp, SFRUP1 + 1, 0xff);
371 }
372}
373
374static void stv0900_set_min_symbol_rate(struct stv0900_internal *intp,
375 u32 mclk, u32 srate,
376 enum fe_stv0900_demod_num demod)
377{
378 u32 symb;
379
380 srate = 95 * (srate / 100);
381 if (srate > 60000000) {
382 symb = srate << 4;
383 symb /= (mclk >> 12);
384
385 } else if (srate > 6000000) {
386 symb = srate << 6;
387 symb /= (mclk >> 10);
388
389 } else {
390 symb = srate << 9;
391 symb /= (mclk >> 7);
392 }
393
394 stv0900_write_reg(intp, SFRLOW1, (symb >> 8) & 0xff);
395 stv0900_write_reg(intp, SFRLOW1 + 1, (symb & 0xff));
396}
397
398static s32 stv0900_get_timing_offst(struct stv0900_internal *intp,
399 u32 srate,
400 enum fe_stv0900_demod_num demod)
401{
402 s32 timingoffset;
403
404
405 timingoffset = (stv0900_read_reg(intp, TMGREG2) << 16) +
406 (stv0900_read_reg(intp, TMGREG2 + 1) << 8) +
407 (stv0900_read_reg(intp, TMGREG2 + 2));
408
409 timingoffset = ge2comp(timingoffset, 24);
410
411
412 if (timingoffset == 0)
413 timingoffset = 1;
414
415 timingoffset = ((s32)srate * 10) / ((s32)0x1000000 / timingoffset);
416 timingoffset /= 320;
417
418 return timingoffset;
419}
420
421static void stv0900_set_dvbs2_rolloff(struct stv0900_internal *intp,
422 enum fe_stv0900_demod_num demod)
423{
424 s32 rolloff;
425
426 if (intp->chip_id == 0x10) {
427 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
428 rolloff = stv0900_read_reg(intp, MATSTR1) & 0x03;
429 stv0900_write_bits(intp, ROLLOFF_CONTROL, rolloff);
430 } else if (intp->chip_id <= 0x20)
431 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 0);
432 else
433 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 0);
434}
435
436static u32 stv0900_carrier_width(u32 srate, enum fe_stv0900_rolloff ro)
437{
438 u32 rolloff;
439
440 switch (ro) {
441 case STV0900_20:
442 rolloff = 20;
443 break;
444 case STV0900_25:
445 rolloff = 25;
446 break;
447 case STV0900_35:
448 default:
449 rolloff = 35;
450 break;
451 }
452
453 return srate + (srate * rolloff) / 100;
454}
455
456static int stv0900_check_timing_lock(struct stv0900_internal *intp,
457 enum fe_stv0900_demod_num demod)
458{
459 int timingLock = FALSE;
460 s32 i,
461 timingcpt = 0;
462 u8 car_freq,
463 tmg_th_high,
464 tmg_th_low;
465
466 car_freq = stv0900_read_reg(intp, CARFREQ);
467 tmg_th_high = stv0900_read_reg(intp, TMGTHRISE);
468 tmg_th_low = stv0900_read_reg(intp, TMGTHFALL);
469 stv0900_write_reg(intp, TMGTHRISE, 0x20);
470 stv0900_write_reg(intp, TMGTHFALL, 0x0);
471 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
472 stv0900_write_reg(intp, RTC, 0x80);
473 stv0900_write_reg(intp, RTCS2, 0x40);
474 stv0900_write_reg(intp, CARFREQ, 0x0);
475 stv0900_write_reg(intp, CFRINIT1, 0x0);
476 stv0900_write_reg(intp, CFRINIT0, 0x0);
477 stv0900_write_reg(intp, AGC2REF, 0x65);
478 stv0900_write_reg(intp, DMDISTATE, 0x18);
479 msleep(7);
480
481 for (i = 0; i < 10; i++) {
482 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
483 timingcpt++;
484
485 msleep(1);
486 }
487
488 if (timingcpt >= 3)
489 timingLock = TRUE;
490
491 stv0900_write_reg(intp, AGC2REF, 0x38);
492 stv0900_write_reg(intp, RTC, 0x88);
493 stv0900_write_reg(intp, RTCS2, 0x68);
494 stv0900_write_reg(intp, CARFREQ, car_freq);
495 stv0900_write_reg(intp, TMGTHRISE, tmg_th_high);
496 stv0900_write_reg(intp, TMGTHFALL, tmg_th_low);
497
498 return timingLock;
499}
500
501static int stv0900_get_demod_cold_lock(struct dvb_frontend *fe,
502 s32 demod_timeout)
503{
504 struct stv0900_state *state = fe->demodulator_priv;
505 struct stv0900_internal *intp = state->internal;
506 enum fe_stv0900_demod_num demod = state->demod;
507 int lock = FALSE,
508 d = demod;
509 s32 srate,
510 search_range,
511 locktimeout,
512 currier_step,
513 nb_steps,
514 current_step,
515 direction,
516 tuner_freq,
517 timeout,
518 freq;
519
520 srate = intp->symbol_rate[d];
521 search_range = intp->srch_range[d];
522
523 if (srate >= 10000000)
524 locktimeout = demod_timeout / 3;
525 else
526 locktimeout = demod_timeout / 2;
527
528 lock = stv0900_get_demod_lock(intp, d, locktimeout);
529
530 if (lock != FALSE)
531 return lock;
532
533 if (srate >= 10000000) {
534 if (stv0900_check_timing_lock(intp, d) == TRUE) {
535 stv0900_write_reg(intp, DMDISTATE, 0x1f);
536 stv0900_write_reg(intp, DMDISTATE, 0x15);
537 lock = stv0900_get_demod_lock(intp, d, demod_timeout);
538 } else
539 lock = FALSE;
540
541 return lock;
542 }
543
544 if (intp->chip_id <= 0x20) {
545 if (srate <= 1000000)
546 currier_step = 500;
547 else if (srate <= 4000000)
548 currier_step = 1000;
549 else if (srate <= 7000000)
550 currier_step = 2000;
551 else if (srate <= 10000000)
552 currier_step = 3000;
553 else
554 currier_step = 5000;
555
556 if (srate >= 2000000) {
557 timeout = (demod_timeout / 3);
558 if (timeout > 1000)
559 timeout = 1000;
560 } else
561 timeout = (demod_timeout / 2);
562 } else {
563
564 currier_step = srate / 4000;
565 timeout = (demod_timeout * 3) / 4;
566 }
567
568 nb_steps = ((search_range / 1000) / currier_step);
569
570 if ((nb_steps % 2) != 0)
571 nb_steps += 1;
572
573 if (nb_steps <= 0)
574 nb_steps = 2;
575 else if (nb_steps > 12)
576 nb_steps = 12;
577
578 current_step = 1;
579 direction = 1;
580
581 if (intp->chip_id <= 0x20) {
582 tuner_freq = intp->freq[d];
583 intp->bw[d] = stv0900_carrier_width(intp->symbol_rate[d],
584 intp->rolloff) + intp->symbol_rate[d];
585 } else
586 tuner_freq = 0;
587
588 while ((current_step <= nb_steps) && (lock == FALSE)) {
589 if (direction > 0)
590 tuner_freq += (current_step * currier_step);
591 else
592 tuner_freq -= (current_step * currier_step);
593
594 if (intp->chip_id <= 0x20) {
595 if (intp->tuner_type[d] == 3)
596 stv0900_set_tuner_auto(intp, tuner_freq,
597 intp->bw[d], demod);
598 else
599 stv0900_set_tuner(fe, tuner_freq, intp->bw[d]);
600
601 stv0900_write_reg(intp, DMDISTATE, 0x1c);
602 stv0900_write_reg(intp, CFRINIT1, 0);
603 stv0900_write_reg(intp, CFRINIT0, 0);
604 stv0900_write_reg(intp, DMDISTATE, 0x1f);
605 stv0900_write_reg(intp, DMDISTATE, 0x15);
606 } else {
607 stv0900_write_reg(intp, DMDISTATE, 0x1c);
608 freq = (tuner_freq * 65536) / (intp->mclk / 1000);
609 stv0900_write_bits(intp, CFR_INIT1, MSB(freq));
610 stv0900_write_bits(intp, CFR_INIT0, LSB(freq));
611 stv0900_write_reg(intp, DMDISTATE, 0x1f);
612 stv0900_write_reg(intp, DMDISTATE, 0x05);
613 }
614
615 lock = stv0900_get_demod_lock(intp, d, timeout);
616 direction *= -1;
617 current_step++;
618 }
619
620 return lock;
621}
622
623static void stv0900_get_lock_timeout(s32 *demod_timeout, s32 *fec_timeout,
624 s32 srate,
625 enum fe_stv0900_search_algo algo)
626{
627 switch (algo) {
628 case STV0900_BLIND_SEARCH:
629 if (srate <= 1500000) {
630 (*demod_timeout) = 1500;
631 (*fec_timeout) = 400;
632 } else if (srate <= 5000000) {
633 (*demod_timeout) = 1000;
634 (*fec_timeout) = 300;
635 } else {
636 (*demod_timeout) = 700;
637 (*fec_timeout) = 100;
638 }
639
640 break;
641 case STV0900_COLD_START:
642 case STV0900_WARM_START:
643 default:
644 if (srate <= 1000000) {
645 (*demod_timeout) = 3000;
646 (*fec_timeout) = 1700;
647 } else if (srate <= 2000000) {
648 (*demod_timeout) = 2500;
649 (*fec_timeout) = 1100;
650 } else if (srate <= 5000000) {
651 (*demod_timeout) = 1000;
652 (*fec_timeout) = 550;
653 } else if (srate <= 10000000) {
654 (*demod_timeout) = 700;
655 (*fec_timeout) = 250;
656 } else if (srate <= 20000000) {
657 (*demod_timeout) = 400;
658 (*fec_timeout) = 130;
659 } else {
660 (*demod_timeout) = 300;
661 (*fec_timeout) = 100;
662 }
663
664 break;
665
666 }
667
668 if (algo == STV0900_WARM_START)
669 (*demod_timeout) /= 2;
670}
671
672static void stv0900_set_viterbi_tracq(struct stv0900_internal *intp,
673 enum fe_stv0900_demod_num demod)
674{
675
676 s32 vth_reg = VTH12;
677
678 dprintk("%s\n", __func__);
679
680 stv0900_write_reg(intp, vth_reg++, 0xd0);
681 stv0900_write_reg(intp, vth_reg++, 0x7d);
682 stv0900_write_reg(intp, vth_reg++, 0x53);
683 stv0900_write_reg(intp, vth_reg++, 0x2f);
684 stv0900_write_reg(intp, vth_reg++, 0x24);
685 stv0900_write_reg(intp, vth_reg++, 0x1f);
686}
687
688static void stv0900_set_viterbi_standard(struct stv0900_internal *intp,
689 enum fe_stv0900_search_standard standard,
690 enum fe_stv0900_fec fec,
691 enum fe_stv0900_demod_num demod)
692{
693 dprintk("%s: ViterbiStandard = ", __func__);
694
695 switch (standard) {
696 case STV0900_AUTO_SEARCH:
697 dprintk("Auto\n");
698 stv0900_write_reg(intp, FECM, 0x10);
699 stv0900_write_reg(intp, PRVIT, 0x3f);
700 break;
701 case STV0900_SEARCH_DVBS1:
702 dprintk("DVBS1\n");
703 stv0900_write_reg(intp, FECM, 0x00);
704 switch (fec) {
705 case STV0900_FEC_UNKNOWN:
706 default:
707 stv0900_write_reg(intp, PRVIT, 0x2f);
708 break;
709 case STV0900_FEC_1_2:
710 stv0900_write_reg(intp, PRVIT, 0x01);
711 break;
712 case STV0900_FEC_2_3:
713 stv0900_write_reg(intp, PRVIT, 0x02);
714 break;
715 case STV0900_FEC_3_4:
716 stv0900_write_reg(intp, PRVIT, 0x04);
717 break;
718 case STV0900_FEC_5_6:
719 stv0900_write_reg(intp, PRVIT, 0x08);
720 break;
721 case STV0900_FEC_7_8:
722 stv0900_write_reg(intp, PRVIT, 0x20);
723 break;
724 }
725
726 break;
727 case STV0900_SEARCH_DSS:
728 dprintk("DSS\n");
729 stv0900_write_reg(intp, FECM, 0x80);
730 switch (fec) {
731 case STV0900_FEC_UNKNOWN:
732 default:
733 stv0900_write_reg(intp, PRVIT, 0x13);
734 break;
735 case STV0900_FEC_1_2:
736 stv0900_write_reg(intp, PRVIT, 0x01);
737 break;
738 case STV0900_FEC_2_3:
739 stv0900_write_reg(intp, PRVIT, 0x02);
740 break;
741 case STV0900_FEC_6_7:
742 stv0900_write_reg(intp, PRVIT, 0x10);
743 break;
744 }
745 break;
746 default:
747 break;
748 }
749}
750
751static enum fe_stv0900_fec stv0900_get_vit_fec(struct stv0900_internal *intp,
752 enum fe_stv0900_demod_num demod)
753{
754 enum fe_stv0900_fec prate;
755 s32 rate_fld = stv0900_get_bits(intp, VIT_CURPUN);
756
757 switch (rate_fld) {
758 case 13:
759 prate = STV0900_FEC_1_2;
760 break;
761 case 18:
762 prate = STV0900_FEC_2_3;
763 break;
764 case 21:
765 prate = STV0900_FEC_3_4;
766 break;
767 case 24:
768 prate = STV0900_FEC_5_6;
769 break;
770 case 25:
771 prate = STV0900_FEC_6_7;
772 break;
773 case 26:
774 prate = STV0900_FEC_7_8;
775 break;
776 default:
777 prate = STV0900_FEC_UNKNOWN;
778 break;
779 }
780
781 return prate;
782}
783
784static void stv0900_set_dvbs1_track_car_loop(struct stv0900_internal *intp,
785 enum fe_stv0900_demod_num demod,
786 u32 srate)
787{
788 if (intp->chip_id >= 0x30) {
789 if (srate >= 15000000) {
790 stv0900_write_reg(intp, ACLC, 0x2b);
791 stv0900_write_reg(intp, BCLC, 0x1a);
792 } else if ((srate >= 7000000) && (15000000 > srate)) {
793 stv0900_write_reg(intp, ACLC, 0x0c);
794 stv0900_write_reg(intp, BCLC, 0x1b);
795 } else if (srate < 7000000) {
796 stv0900_write_reg(intp, ACLC, 0x2c);
797 stv0900_write_reg(intp, BCLC, 0x1c);
798 }
799
800 } else {
801 stv0900_write_reg(intp, ACLC, 0x1a);
802 stv0900_write_reg(intp, BCLC, 0x09);
803 }
804
805}
806
807static void stv0900_track_optimization(struct dvb_frontend *fe)
808{
809 struct stv0900_state *state = fe->demodulator_priv;
810 struct stv0900_internal *intp = state->internal;
811 enum fe_stv0900_demod_num demod = state->demod;
812
813 s32 srate,
814 pilots,
815 aclc,
816 freq1,
817 freq0,
818 i = 0,
819 timed,
820 timef,
821 blind_tun_sw = 0,
822 modulation;
823
824 enum fe_stv0900_modcode foundModcod;
825
826 dprintk("%s\n", __func__);
827
828 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
829 srate += stv0900_get_timing_offst(intp, srate, demod);
830
831 switch (intp->result[demod].standard) {
832 case STV0900_DVBS1_STANDARD:
833 case STV0900_DSS_STANDARD:
834 dprintk("%s: found DVB-S or DSS\n", __func__);
835 if (intp->srch_standard[demod] == STV0900_AUTO_SEARCH) {
836 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
837 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
838 }
839
840 stv0900_write_bits(intp, ROLLOFF_CONTROL, intp->rolloff);
841 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
842
843 if (intp->chip_id < 0x30) {
844 stv0900_write_reg(intp, ERRCTRL1, 0x75);
845 break;
846 }
847
848 if (stv0900_get_vit_fec(intp, demod) == STV0900_FEC_1_2) {
849 stv0900_write_reg(intp, GAUSSR0, 0x98);
850 stv0900_write_reg(intp, CCIR0, 0x18);
851 } else {
852 stv0900_write_reg(intp, GAUSSR0, 0x18);
853 stv0900_write_reg(intp, CCIR0, 0x18);
854 }
855
856 stv0900_write_reg(intp, ERRCTRL1, 0x75);
857 break;
858 case STV0900_DVBS2_STANDARD:
859 dprintk("%s: found DVB-S2\n", __func__);
860 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
861 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
862 stv0900_write_reg(intp, ACLC, 0);
863 stv0900_write_reg(intp, BCLC, 0);
864 if (intp->result[demod].frame_len == STV0900_LONG_FRAME) {
865 foundModcod = stv0900_get_bits(intp, DEMOD_MODCOD);
866 pilots = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
867 aclc = stv0900_get_optim_carr_loop(srate,
868 foundModcod,
869 pilots,
870 intp->chip_id);
871 if (foundModcod <= STV0900_QPSK_910)
872 stv0900_write_reg(intp, ACLC2S2Q, aclc);
873 else if (foundModcod <= STV0900_8PSK_910) {
874 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
875 stv0900_write_reg(intp, ACLC2S28, aclc);
876 }
877
878 if ((intp->demod_mode == STV0900_SINGLE) &&
879 (foundModcod > STV0900_8PSK_910)) {
880 if (foundModcod <= STV0900_16APSK_910) {
881 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
882 stv0900_write_reg(intp, ACLC2S216A,
883 aclc);
884 } else if (foundModcod <= STV0900_32APSK_910) {
885 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
886 stv0900_write_reg(intp, ACLC2S232A,
887 aclc);
888 }
889 }
890
891 } else {
892 modulation = intp->result[demod].modulation;
893 aclc = stv0900_get_optim_short_carr_loop(srate,
894 modulation, intp->chip_id);
895 if (modulation == STV0900_QPSK)
896 stv0900_write_reg(intp, ACLC2S2Q, aclc);
897 else if (modulation == STV0900_8PSK) {
898 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
899 stv0900_write_reg(intp, ACLC2S28, aclc);
900 } else if (modulation == STV0900_16APSK) {
901 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
902 stv0900_write_reg(intp, ACLC2S216A, aclc);
903 } else if (modulation == STV0900_32APSK) {
904 stv0900_write_reg(intp, ACLC2S2Q, 0x2a);
905 stv0900_write_reg(intp, ACLC2S232A, aclc);
906 }
907
908 }
909
910 if (intp->chip_id <= 0x11) {
911 if (intp->demod_mode != STV0900_SINGLE)
912 stv0900_activate_s2_modcod(intp, demod);
913
914 }
915
916 stv0900_write_reg(intp, ERRCTRL1, 0x67);
917 break;
918 case STV0900_UNKNOWN_STANDARD:
919 default:
920 dprintk("%s: found unknown standard\n", __func__);
921 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
922 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
923 break;
924 }
925
926 freq1 = stv0900_read_reg(intp, CFR2);
927 freq0 = stv0900_read_reg(intp, CFR1);
928 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
929 stv0900_write_reg(intp, SFRSTEP, 0x00);
930 stv0900_write_bits(intp, SCAN_ENABLE, 0);
931 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
932 stv0900_write_reg(intp, TMGCFG2, 0xc1);
933 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
934 blind_tun_sw = 1;
935 if (intp->result[demod].standard != STV0900_DVBS2_STANDARD)
936 stv0900_set_dvbs1_track_car_loop(intp, demod, srate);
937
938 }
939
940 if (intp->chip_id >= 0x20) {
941 if ((intp->srch_standard[demod] == STV0900_SEARCH_DVBS1) ||
942 (intp->srch_standard[demod] ==
943 STV0900_SEARCH_DSS) ||
944 (intp->srch_standard[demod] ==
945 STV0900_AUTO_SEARCH)) {
946 stv0900_write_reg(intp, VAVSRVIT, 0x0a);
947 stv0900_write_reg(intp, VITSCALE, 0x0);
948 }
949 }
950
951 if (intp->chip_id < 0x20)
952 stv0900_write_reg(intp, CARHDR, 0x08);
953
954 if (intp->chip_id == 0x10)
955 stv0900_write_reg(intp, CORRELEXP, 0x0a);
956
957 stv0900_write_reg(intp, AGC2REF, 0x38);
958
959 if ((intp->chip_id >= 0x20) ||
960 (blind_tun_sw == 1) ||
961 (intp->symbol_rate[demod] < 10000000)) {
962 stv0900_write_reg(intp, CFRINIT1, freq1);
963 stv0900_write_reg(intp, CFRINIT0, freq0);
964 intp->bw[demod] = stv0900_carrier_width(srate,
965 intp->rolloff) + 10000000;
966
967 if ((intp->chip_id >= 0x20) || (blind_tun_sw == 1)) {
968 if (intp->srch_algo[demod] != STV0900_WARM_START) {
969 if (intp->tuner_type[demod] == 3)
970 stv0900_set_tuner_auto(intp,
971 intp->freq[demod],
972 intp->bw[demod],
973 demod);
974 else
975 stv0900_set_bandwidth(fe,
976 intp->bw[demod]);
977 }
978 }
979
980 if ((intp->srch_algo[demod] == STV0900_BLIND_SEARCH) ||
981 (intp->symbol_rate[demod] < 10000000))
982 msleep(50);
983 else
984 msleep(5);
985
986 stv0900_get_lock_timeout(&timed, &timef, srate,
987 STV0900_WARM_START);
988
989 if (stv0900_get_demod_lock(intp, demod, timed / 2) == FALSE) {
990 stv0900_write_reg(intp, DMDISTATE, 0x1f);
991 stv0900_write_reg(intp, CFRINIT1, freq1);
992 stv0900_write_reg(intp, CFRINIT0, freq0);
993 stv0900_write_reg(intp, DMDISTATE, 0x18);
994 i = 0;
995 while ((stv0900_get_demod_lock(intp,
996 demod,
997 timed / 2) == FALSE) &&
998 (i <= 2)) {
999 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1000 stv0900_write_reg(intp, CFRINIT1, freq1);
1001 stv0900_write_reg(intp, CFRINIT0, freq0);
1002 stv0900_write_reg(intp, DMDISTATE, 0x18);
1003 i++;
1004 }
1005 }
1006
1007 }
1008
1009 if (intp->chip_id >= 0x20)
1010 stv0900_write_reg(intp, CARFREQ, 0x49);
1011
1012 if ((intp->result[demod].standard == STV0900_DVBS1_STANDARD) ||
1013 (intp->result[demod].standard == STV0900_DSS_STANDARD))
1014 stv0900_set_viterbi_tracq(intp, demod);
1015
1016}
1017
1018static int stv0900_get_fec_lock(struct stv0900_internal *intp,
1019 enum fe_stv0900_demod_num demod, s32 time_out)
1020{
1021 s32 timer = 0, lock = 0;
1022
1023 enum fe_stv0900_search_state dmd_state;
1024
1025 dprintk("%s\n", __func__);
1026
1027 dmd_state = stv0900_get_bits(intp, HEADER_MODE);
1028
1029 while ((timer < time_out) && (lock == 0)) {
1030 switch (dmd_state) {
1031 case STV0900_SEARCH:
1032 case STV0900_PLH_DETECTED:
1033 default:
1034 lock = 0;
1035 break;
1036 case STV0900_DVBS2_FOUND:
1037 lock = stv0900_get_bits(intp, PKTDELIN_LOCK);
1038 break;
1039 case STV0900_DVBS_FOUND:
1040 lock = stv0900_get_bits(intp, LOCKEDVIT);
1041 break;
1042 }
1043
1044 if (lock == 0) {
1045 msleep(10);
1046 timer += 10;
1047 }
1048 }
1049
1050 if (lock)
1051 dprintk("%s: DEMOD FEC LOCK OK\n", __func__);
1052 else
1053 dprintk("%s: DEMOD FEC LOCK FAIL\n", __func__);
1054
1055 return lock;
1056}
1057
1058static int stv0900_wait_for_lock(struct stv0900_internal *intp,
1059 enum fe_stv0900_demod_num demod,
1060 s32 dmd_timeout, s32 fec_timeout)
1061{
1062
1063 s32 timer = 0, lock = 0;
1064
1065 dprintk("%s\n", __func__);
1066
1067 lock = stv0900_get_demod_lock(intp, demod, dmd_timeout);
1068
1069 if (lock)
1070 lock = stv0900_get_fec_lock(intp, demod, fec_timeout);
1071
1072 if (lock) {
1073 lock = 0;
1074
1075 dprintk("%s: Timer = %d, time_out = %d\n",
1076 __func__, timer, fec_timeout);
1077
1078 while ((timer < fec_timeout) && (lock == 0)) {
1079 lock = stv0900_get_bits(intp, TSFIFO_LINEOK);
1080 msleep(1);
1081 timer++;
1082 }
1083 }
1084
1085 if (lock)
1086 dprintk("%s: DEMOD LOCK OK\n", __func__);
1087 else
1088 dprintk("%s: DEMOD LOCK FAIL\n", __func__);
1089
1090 if (lock)
1091 return TRUE;
1092 else
1093 return FALSE;
1094}
1095
1096enum fe_stv0900_tracking_standard stv0900_get_standard(struct dvb_frontend *fe,
1097 enum fe_stv0900_demod_num demod)
1098{
1099 struct stv0900_state *state = fe->demodulator_priv;
1100 struct stv0900_internal *intp = state->internal;
1101 enum fe_stv0900_tracking_standard fnd_standard;
1102
1103 int hdr_mode = stv0900_get_bits(intp, HEADER_MODE);
1104
1105 switch (hdr_mode) {
1106 case 2:
1107 fnd_standard = STV0900_DVBS2_STANDARD;
1108 break;
1109 case 3:
1110 if (stv0900_get_bits(intp, DSS_DVB) == 1)
1111 fnd_standard = STV0900_DSS_STANDARD;
1112 else
1113 fnd_standard = STV0900_DVBS1_STANDARD;
1114
1115 break;
1116 default:
1117 fnd_standard = STV0900_UNKNOWN_STANDARD;
1118 }
1119
1120 dprintk("%s: standard %d\n", __func__, fnd_standard);
1121
1122 return fnd_standard;
1123}
1124
1125static s32 stv0900_get_carr_freq(struct stv0900_internal *intp, u32 mclk,
1126 enum fe_stv0900_demod_num demod)
1127{
1128 s32 derot,
1129 rem1,
1130 rem2,
1131 intval1,
1132 intval2;
1133
1134 derot = (stv0900_get_bits(intp, CAR_FREQ2) << 16) +
1135 (stv0900_get_bits(intp, CAR_FREQ1) << 8) +
1136 (stv0900_get_bits(intp, CAR_FREQ0));
1137
1138 derot = ge2comp(derot, 24);
1139 intval1 = mclk >> 12;
1140 intval2 = derot >> 12;
1141 rem1 = mclk % 0x1000;
1142 rem2 = derot % 0x1000;
1143 derot = (intval1 * intval2) +
1144 ((intval1 * rem2) >> 12) +
1145 ((intval2 * rem1) >> 12);
1146
1147 return derot;
1148}
1149
1150static u32 stv0900_get_tuner_freq(struct dvb_frontend *fe)
1151{
1152 struct dvb_frontend_ops *frontend_ops = NULL;
1153 struct dvb_tuner_ops *tuner_ops = NULL;
1154 u32 freq = 0;
1155
1156 frontend_ops = &fe->ops;
1157 tuner_ops = &frontend_ops->tuner_ops;
1158
1159 if (tuner_ops->get_frequency) {
1160 if ((tuner_ops->get_frequency(fe, &freq)) < 0)
1161 dprintk("%s: Invalid parameter\n", __func__);
1162 else
1163 dprintk("%s: Frequency=%d\n", __func__, freq);
1164
1165 }
1166
1167 return freq;
1168}
1169
1170static enum
1171fe_stv0900_signal_type stv0900_get_signal_params(struct dvb_frontend *fe)
1172{
1173 struct stv0900_state *state = fe->demodulator_priv;
1174 struct stv0900_internal *intp = state->internal;
1175 enum fe_stv0900_demod_num demod = state->demod;
1176 enum fe_stv0900_signal_type range = STV0900_OUTOFRANGE;
1177 struct stv0900_signal_info *result = &intp->result[demod];
1178 s32 offsetFreq,
1179 srate_offset;
1180 int i = 0,
1181 d = demod;
1182
1183 u8 timing;
1184
1185 msleep(5);
1186 if (intp->srch_algo[d] == STV0900_BLIND_SEARCH) {
1187 timing = stv0900_read_reg(intp, TMGREG2);
1188 i = 0;
1189 stv0900_write_reg(intp, SFRSTEP, 0x5c);
1190
1191 while ((i <= 50) && (timing != 0) && (timing != 0xff)) {
1192 timing = stv0900_read_reg(intp, TMGREG2);
1193 msleep(5);
1194 i += 5;
1195 }
1196 }
1197
1198 result->standard = stv0900_get_standard(fe, d);
1199 if (intp->tuner_type[demod] == 3)
1200 result->frequency = stv0900_get_freq_auto(intp, d);
1201 else
1202 result->frequency = stv0900_get_tuner_freq(fe);
1203
1204 offsetFreq = stv0900_get_carr_freq(intp, intp->mclk, d) / 1000;
1205 result->frequency += offsetFreq;
1206 result->symbol_rate = stv0900_get_symbol_rate(intp, intp->mclk, d);
1207 srate_offset = stv0900_get_timing_offst(intp, result->symbol_rate, d);
1208 result->symbol_rate += srate_offset;
1209 result->fec = stv0900_get_vit_fec(intp, d);
1210 result->modcode = stv0900_get_bits(intp, DEMOD_MODCOD);
1211 result->pilot = stv0900_get_bits(intp, DEMOD_TYPE) & 0x01;
1212 result->frame_len = ((u32)stv0900_get_bits(intp, DEMOD_TYPE)) >> 1;
1213 result->rolloff = stv0900_get_bits(intp, ROLLOFF_STATUS);
1214
1215 dprintk("%s: modcode=0x%x \n", __func__, result->modcode);
1216
1217 switch (result->standard) {
1218 case STV0900_DVBS2_STANDARD:
1219 result->spectrum = stv0900_get_bits(intp, SPECINV_DEMOD);
1220 if (result->modcode <= STV0900_QPSK_910)
1221 result->modulation = STV0900_QPSK;
1222 else if (result->modcode <= STV0900_8PSK_910)
1223 result->modulation = STV0900_8PSK;
1224 else if (result->modcode <= STV0900_16APSK_910)
1225 result->modulation = STV0900_16APSK;
1226 else if (result->modcode <= STV0900_32APSK_910)
1227 result->modulation = STV0900_32APSK;
1228 else
1229 result->modulation = STV0900_UNKNOWN;
1230 break;
1231 case STV0900_DVBS1_STANDARD:
1232 case STV0900_DSS_STANDARD:
1233 result->spectrum = stv0900_get_bits(intp, IQINV);
1234 result->modulation = STV0900_QPSK;
1235 break;
1236 default:
1237 break;
1238 }
1239
1240 if ((intp->srch_algo[d] == STV0900_BLIND_SEARCH) ||
1241 (intp->symbol_rate[d] < 10000000)) {
1242 offsetFreq = result->frequency - intp->freq[d];
1243 if (intp->tuner_type[demod] == 3)
1244 intp->freq[d] = stv0900_get_freq_auto(intp, d);
1245 else
1246 intp->freq[d] = stv0900_get_tuner_freq(fe);
1247
1248 if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1249 range = STV0900_RANGEOK;
1250 else if (abs(offsetFreq) <=
1251 (stv0900_carrier_width(result->symbol_rate,
1252 result->rolloff) / 2000))
1253 range = STV0900_RANGEOK;
1254
1255 } else if (abs(offsetFreq) <= ((intp->srch_range[d] / 2000) + 500))
1256 range = STV0900_RANGEOK;
1257
1258 dprintk("%s: range %d\n", __func__, range);
1259
1260 return range;
1261}
1262
1263static enum
1264fe_stv0900_signal_type stv0900_dvbs1_acq_workaround(struct dvb_frontend *fe)
1265{
1266 struct stv0900_state *state = fe->demodulator_priv;
1267 struct stv0900_internal *intp = state->internal;
1268 enum fe_stv0900_demod_num demod = state->demod;
1269 enum fe_stv0900_signal_type signal_type = STV0900_NODATA;
1270
1271 s32 srate,
1272 demod_timeout,
1273 fec_timeout,
1274 freq1,
1275 freq0;
1276
1277 intp->result[demod].locked = FALSE;
1278
1279 if (stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) {
1280 srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1281 srate += stv0900_get_timing_offst(intp, srate, demod);
1282 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH)
1283 stv0900_set_symbol_rate(intp, intp->mclk, srate, demod);
1284
1285 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1286 srate, STV0900_WARM_START);
1287 freq1 = stv0900_read_reg(intp, CFR2);
1288 freq0 = stv0900_read_reg(intp, CFR1);
1289 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1290 stv0900_write_bits(intp, SPECINV_CONTROL,
1291 STV0900_IQ_FORCE_SWAPPED);
1292 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1293 stv0900_write_reg(intp, CFRINIT1, freq1);
1294 stv0900_write_reg(intp, CFRINIT0, freq0);
1295 stv0900_write_reg(intp, DMDISTATE, 0x18);
1296 if (stv0900_wait_for_lock(intp, demod,
1297 demod_timeout, fec_timeout) == TRUE) {
1298 intp->result[demod].locked = TRUE;
1299 signal_type = stv0900_get_signal_params(fe);
1300 stv0900_track_optimization(fe);
1301 } else {
1302 stv0900_write_bits(intp, SPECINV_CONTROL,
1303 STV0900_IQ_FORCE_NORMAL);
1304 stv0900_write_reg(intp, DMDISTATE, 0x1c);
1305 stv0900_write_reg(intp, CFRINIT1, freq1);
1306 stv0900_write_reg(intp, CFRINIT0, freq0);
1307 stv0900_write_reg(intp, DMDISTATE, 0x18);
1308 if (stv0900_wait_for_lock(intp, demod,
1309 demod_timeout, fec_timeout) == TRUE) {
1310 intp->result[demod].locked = TRUE;
1311 signal_type = stv0900_get_signal_params(fe);
1312 stv0900_track_optimization(fe);
1313 }
1314
1315 }
1316
1317 } else
1318 intp->result[demod].locked = FALSE;
1319
1320 return signal_type;
1321}
1322
1323static u16 stv0900_blind_check_agc2_min_level(struct stv0900_internal *intp,
1324 enum fe_stv0900_demod_num demod)
1325{
1326 u32 minagc2level = 0xffff,
1327 agc2level,
1328 init_freq, freq_step;
1329
1330 s32 i, j, nb_steps, direction;
1331
1332 dprintk("%s\n", __func__);
1333
1334 stv0900_write_reg(intp, AGC2REF, 0x38);
1335 stv0900_write_bits(intp, SCAN_ENABLE, 0);
1336 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1337
1338 stv0900_write_bits(intp, AUTO_GUP, 1);
1339 stv0900_write_bits(intp, AUTO_GLOW, 1);
1340
1341 stv0900_write_reg(intp, DMDT0M, 0x0);
1342
1343 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1344 nb_steps = -1 + (intp->srch_range[demod] / 1000000);
1345 nb_steps /= 2;
1346 nb_steps = (2 * nb_steps) + 1;
1347
1348 if (nb_steps < 0)
1349 nb_steps = 1;
1350
1351 direction = 1;
1352
1353 freq_step = (1000000 << 8) / (intp->mclk >> 8);
1354
1355 init_freq = 0;
1356
1357 for (i = 0; i < nb_steps; i++) {
1358 if (direction > 0)
1359 init_freq = init_freq + (freq_step * i);
1360 else
1361 init_freq = init_freq - (freq_step * i);
1362
1363 direction *= -1;
1364 stv0900_write_reg(intp, DMDISTATE, 0x5C);
1365 stv0900_write_reg(intp, CFRINIT1, (init_freq >> 8) & 0xff);
1366 stv0900_write_reg(intp, CFRINIT0, init_freq & 0xff);
1367 stv0900_write_reg(intp, DMDISTATE, 0x58);
1368 msleep(10);
1369 agc2level = 0;
1370
1371 for (j = 0; j < 10; j++)
1372 agc2level += (stv0900_read_reg(intp, AGC2I1) << 8)
1373 | stv0900_read_reg(intp, AGC2I0);
1374
1375 agc2level /= 10;
1376
1377 if (agc2level < minagc2level)
1378 minagc2level = agc2level;
1379
1380 }
1381
1382 return (u16)minagc2level;
1383}
1384
1385static u32 stv0900_search_srate_coarse(struct dvb_frontend *fe)
1386{
1387 struct stv0900_state *state = fe->demodulator_priv;
1388 struct stv0900_internal *intp = state->internal;
1389 enum fe_stv0900_demod_num demod = state->demod;
1390 int timing_lck = FALSE;
1391 s32 i, timingcpt = 0,
1392 direction = 1,
1393 nb_steps,
1394 current_step = 0,
1395 tuner_freq;
1396 u32 agc2_th,
1397 coarse_srate = 0,
1398 agc2_integr = 0,
1399 currier_step = 1200;
1400
1401 if (intp->chip_id >= 0x30)
1402 agc2_th = 0x2e00;
1403 else
1404 agc2_th = 0x1f00;
1405
1406 stv0900_write_bits(intp, DEMOD_MODE, 0x1f);
1407 stv0900_write_reg(intp, TMGCFG, 0x12);
1408 stv0900_write_reg(intp, TMGTHRISE, 0xf0);
1409 stv0900_write_reg(intp, TMGTHFALL, 0xe0);
1410 stv0900_write_bits(intp, SCAN_ENABLE, 1);
1411 stv0900_write_bits(intp, CFR_AUTOSCAN, 1);
1412 stv0900_write_reg(intp, SFRUP1, 0x83);
1413 stv0900_write_reg(intp, SFRUP0, 0xc0);
1414 stv0900_write_reg(intp, SFRLOW1, 0x82);
1415 stv0900_write_reg(intp, SFRLOW0, 0xa0);
1416 stv0900_write_reg(intp, DMDT0M, 0x0);
1417 stv0900_write_reg(intp, AGC2REF, 0x50);
1418
1419 if (intp->chip_id >= 0x30) {
1420 stv0900_write_reg(intp, CARFREQ, 0x99);
1421 stv0900_write_reg(intp, SFRSTEP, 0x98);
1422 } else if (intp->chip_id >= 0x20) {
1423 stv0900_write_reg(intp, CARFREQ, 0x6a);
1424 stv0900_write_reg(intp, SFRSTEP, 0x95);
1425 } else {
1426 stv0900_write_reg(intp, CARFREQ, 0xed);
1427 stv0900_write_reg(intp, SFRSTEP, 0x73);
1428 }
1429
1430 if (intp->symbol_rate[demod] <= 2000000)
1431 currier_step = 1000;
1432 else if (intp->symbol_rate[demod] <= 5000000)
1433 currier_step = 2000;
1434 else if (intp->symbol_rate[demod] <= 12000000)
1435 currier_step = 3000;
1436 else
1437 currier_step = 5000;
1438
1439 nb_steps = -1 + ((intp->srch_range[demod] / 1000) / currier_step);
1440 nb_steps /= 2;
1441 nb_steps = (2 * nb_steps) + 1;
1442
1443 if (nb_steps < 0)
1444 nb_steps = 1;
1445 else if (nb_steps > 10) {
1446 nb_steps = 11;
1447 currier_step = (intp->srch_range[demod] / 1000) / 10;
1448 }
1449
1450 current_step = 0;
1451 direction = 1;
1452
1453 tuner_freq = intp->freq[demod];
1454
1455 while ((timing_lck == FALSE) && (current_step < nb_steps)) {
1456 stv0900_write_reg(intp, DMDISTATE, 0x5f);
1457 stv0900_write_bits(intp, DEMOD_MODE, 0);
1458
1459 msleep(50);
1460
1461 for (i = 0; i < 10; i++) {
1462 if (stv0900_get_bits(intp, TMGLOCK_QUALITY) >= 2)
1463 timingcpt++;
1464
1465 agc2_integr += (stv0900_read_reg(intp, AGC2I1) << 8) |
1466 stv0900_read_reg(intp, AGC2I0);
1467 }
1468
1469 agc2_integr /= 10;
1470 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1471 current_step++;
1472 direction *= -1;
1473
1474 dprintk("lock: I2C_DEMOD_MODE_FIELD =0. Search started. tuner freq=%d agc2=0x%x srate_coarse=%d tmg_cpt=%d\n",
1475 tuner_freq, agc2_integr, coarse_srate, timingcpt);
1476
1477 if ((timingcpt >= 5) &&
1478 (agc2_integr < agc2_th) &&
1479 (coarse_srate < 55000000) &&
1480 (coarse_srate > 850000))
1481 timing_lck = TRUE;
1482 else if (current_step < nb_steps) {
1483 if (direction > 0)
1484 tuner_freq += (current_step * currier_step);
1485 else
1486 tuner_freq -= (current_step * currier_step);
1487
1488 if (intp->tuner_type[demod] == 3)
1489 stv0900_set_tuner_auto(intp, tuner_freq,
1490 intp->bw[demod], demod);
1491 else
1492 stv0900_set_tuner(fe, tuner_freq,
1493 intp->bw[demod]);
1494 }
1495 }
1496
1497 if (timing_lck == FALSE)
1498 coarse_srate = 0;
1499 else
1500 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1501
1502 return coarse_srate;
1503}
1504
1505static u32 stv0900_search_srate_fine(struct dvb_frontend *fe)
1506{
1507 struct stv0900_state *state = fe->demodulator_priv;
1508 struct stv0900_internal *intp = state->internal;
1509 enum fe_stv0900_demod_num demod = state->demod;
1510 u32 coarse_srate,
1511 coarse_freq,
1512 symb,
1513 symbmax,
1514 symbmin,
1515 symbcomp;
1516
1517 coarse_srate = stv0900_get_symbol_rate(intp, intp->mclk, demod);
1518
1519 if (coarse_srate > 3000000) {
1520 symbmax = 13 * (coarse_srate / 10);
1521 symbmax = (symbmax / 1000) * 65536;
1522 symbmax /= (intp->mclk / 1000);
1523
1524 symbmin = 10 * (coarse_srate / 13);
1525 symbmin = (symbmin / 1000)*65536;
1526 symbmin /= (intp->mclk / 1000);
1527
1528 symb = (coarse_srate / 1000) * 65536;
1529 symb /= (intp->mclk / 1000);
1530 } else {
1531 symbmax = 13 * (coarse_srate / 10);
1532 symbmax = (symbmax / 100) * 65536;
1533 symbmax /= (intp->mclk / 100);
1534
1535 symbmin = 10 * (coarse_srate / 14);
1536 symbmin = (symbmin / 100) * 65536;
1537 symbmin /= (intp->mclk / 100);
1538
1539 symb = (coarse_srate / 100) * 65536;
1540 symb /= (intp->mclk / 100);
1541 }
1542
1543 symbcomp = 13 * (coarse_srate / 10);
1544 coarse_freq = (stv0900_read_reg(intp, CFR2) << 8)
1545 | stv0900_read_reg(intp, CFR1);
1546
1547 if (symbcomp < intp->symbol_rate[demod])
1548 coarse_srate = 0;
1549 else {
1550 stv0900_write_reg(intp, DMDISTATE, 0x1f);
1551 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1552 stv0900_write_reg(intp, TMGTHRISE, 0x20);
1553 stv0900_write_reg(intp, TMGTHFALL, 0x00);
1554 stv0900_write_reg(intp, TMGCFG, 0xd2);
1555 stv0900_write_bits(intp, CFR_AUTOSCAN, 0);
1556 stv0900_write_reg(intp, AGC2REF, 0x38);
1557
1558 if (intp->chip_id >= 0x30)
1559 stv0900_write_reg(intp, CARFREQ, 0x79);
1560 else if (intp->chip_id >= 0x20)
1561 stv0900_write_reg(intp, CARFREQ, 0x49);
1562 else
1563 stv0900_write_reg(intp, CARFREQ, 0xed);
1564
1565 stv0900_write_reg(intp, SFRUP1, (symbmax >> 8) & 0x7f);
1566 stv0900_write_reg(intp, SFRUP0, (symbmax & 0xff));
1567
1568 stv0900_write_reg(intp, SFRLOW1, (symbmin >> 8) & 0x7f);
1569 stv0900_write_reg(intp, SFRLOW0, (symbmin & 0xff));
1570
1571 stv0900_write_reg(intp, SFRINIT1, (symb >> 8) & 0xff);
1572 stv0900_write_reg(intp, SFRINIT0, (symb & 0xff));
1573
1574 stv0900_write_reg(intp, DMDT0M, 0x20);
1575 stv0900_write_reg(intp, CFRINIT1, (coarse_freq >> 8) & 0xff);
1576 stv0900_write_reg(intp, CFRINIT0, coarse_freq & 0xff);
1577 stv0900_write_reg(intp, DMDISTATE, 0x15);
1578 }
1579
1580 return coarse_srate;
1581}
1582
1583static int stv0900_blind_search_algo(struct dvb_frontend *fe)
1584{
1585 struct stv0900_state *state = fe->demodulator_priv;
1586 struct stv0900_internal *intp = state->internal;
1587 enum fe_stv0900_demod_num demod = state->demod;
1588 u8 k_ref_tmg,
1589 k_ref_tmg_max,
1590 k_ref_tmg_min;
1591 u32 coarse_srate,
1592 agc2_th;
1593 int lock = FALSE,
1594 coarse_fail = FALSE;
1595 s32 demod_timeout = 500,
1596 fec_timeout = 50,
1597 fail_cpt,
1598 i,
1599 agc2_overflow;
1600 u16 agc2_int;
1601 u8 dstatus2;
1602
1603 dprintk("%s\n", __func__);
1604
1605 if (intp->chip_id < 0x20) {
1606 k_ref_tmg_max = 233;
1607 k_ref_tmg_min = 143;
1608 } else {
1609 k_ref_tmg_max = 110;
1610 k_ref_tmg_min = 10;
1611 }
1612
1613 if (intp->chip_id <= 0x20)
1614 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH;
1615 else
1616 agc2_th = STV0900_BLIND_SEARCH_AGC2_TH_CUT30;
1617
1618 agc2_int = stv0900_blind_check_agc2_min_level(intp, demod);
1619
1620 dprintk("%s agc2_int=%d agc2_th=%d \n", __func__, agc2_int, agc2_th);
1621 if (agc2_int > agc2_th)
1622 return FALSE;
1623
1624 if (intp->chip_id == 0x10)
1625 stv0900_write_reg(intp, CORRELEXP, 0xaa);
1626
1627 if (intp->chip_id < 0x20)
1628 stv0900_write_reg(intp, CARHDR, 0x55);
1629 else
1630 stv0900_write_reg(intp, CARHDR, 0x20);
1631
1632 if (intp->chip_id <= 0x20)
1633 stv0900_write_reg(intp, CARCFG, 0xc4);
1634 else
1635 stv0900_write_reg(intp, CARCFG, 0x6);
1636
1637 stv0900_write_reg(intp, RTCS2, 0x44);
1638
1639 if (intp->chip_id >= 0x20) {
1640 stv0900_write_reg(intp, EQUALCFG, 0x41);
1641 stv0900_write_reg(intp, FFECFG, 0x41);
1642 stv0900_write_reg(intp, VITSCALE, 0x82);
1643 stv0900_write_reg(intp, VAVSRVIT, 0x0);
1644 }
1645
1646 k_ref_tmg = k_ref_tmg_max;
1647
1648 do {
1649 stv0900_write_reg(intp, KREFTMG, k_ref_tmg);
1650 if (stv0900_search_srate_coarse(fe) != 0) {
1651 coarse_srate = stv0900_search_srate_fine(fe);
1652
1653 if (coarse_srate != 0) {
1654 stv0900_get_lock_timeout(&demod_timeout,
1655 &fec_timeout,
1656 coarse_srate,
1657 STV0900_BLIND_SEARCH);
1658 lock = stv0900_get_demod_lock(intp,
1659 demod,
1660 demod_timeout);
1661 } else
1662 lock = FALSE;
1663 } else {
1664 fail_cpt = 0;
1665 agc2_overflow = 0;
1666
1667 for (i = 0; i < 10; i++) {
1668 agc2_int = (stv0900_read_reg(intp, AGC2I1) << 8)
1669 | stv0900_read_reg(intp, AGC2I0);
1670
1671 if (agc2_int >= 0xff00)
1672 agc2_overflow++;
1673
1674 dstatus2 = stv0900_read_reg(intp, DSTATUS2);
1675
1676 if (((dstatus2 & 0x1) == 0x1) &&
1677 ((dstatus2 >> 7) == 1))
1678 fail_cpt++;
1679 }
1680
1681 if ((fail_cpt > 7) || (agc2_overflow > 7))
1682 coarse_fail = TRUE;
1683
1684 lock = FALSE;
1685 }
1686 k_ref_tmg -= 30;
1687 } while ((k_ref_tmg >= k_ref_tmg_min) &&
1688 (lock == FALSE) &&
1689 (coarse_fail == FALSE));
1690
1691 return lock;
1692}
1693
1694static void stv0900_set_viterbi_acq(struct stv0900_internal *intp,
1695 enum fe_stv0900_demod_num demod)
1696{
1697 s32 vth_reg = VTH12;
1698
1699 dprintk("%s\n", __func__);
1700
1701 stv0900_write_reg(intp, vth_reg++, 0x96);
1702 stv0900_write_reg(intp, vth_reg++, 0x64);
1703 stv0900_write_reg(intp, vth_reg++, 0x36);
1704 stv0900_write_reg(intp, vth_reg++, 0x23);
1705 stv0900_write_reg(intp, vth_reg++, 0x1e);
1706 stv0900_write_reg(intp, vth_reg++, 0x19);
1707}
1708
1709static void stv0900_set_search_standard(struct stv0900_internal *intp,
1710 enum fe_stv0900_demod_num demod)
1711{
1712
1713 dprintk("%s\n", __func__);
1714
1715 switch (intp->srch_standard[demod]) {
1716 case STV0900_SEARCH_DVBS1:
1717 dprintk("Search Standard = DVBS1\n");
1718 break;
1719 case STV0900_SEARCH_DSS:
1720 dprintk("Search Standard = DSS\n");
1721 break;
1722 case STV0900_SEARCH_DVBS2:
1723 dprintk("Search Standard = DVBS2\n");
1724 break;
1725 case STV0900_AUTO_SEARCH:
1726 default:
1727 dprintk("Search Standard = AUTO\n");
1728 break;
1729 }
1730
1731 switch (intp->srch_standard[demod]) {
1732 case STV0900_SEARCH_DVBS1:
1733 case STV0900_SEARCH_DSS:
1734 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1735 stv0900_write_bits(intp, DVBS2_ENABLE, 0);
1736 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1737 stv0900_set_dvbs1_track_car_loop(intp,
1738 demod,
1739 intp->symbol_rate[demod]);
1740 stv0900_write_reg(intp, CAR2CFG, 0x22);
1741
1742 stv0900_set_viterbi_acq(intp, demod);
1743 stv0900_set_viterbi_standard(intp,
1744 intp->srch_standard[demod],
1745 intp->fec[demod], demod);
1746
1747 break;
1748 case STV0900_SEARCH_DVBS2:
1749 stv0900_write_bits(intp, DVBS1_ENABLE, 0);
1750 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1751 stv0900_write_bits(intp, STOP_CLKVIT, 1);
1752 stv0900_write_reg(intp, ACLC, 0x1a);
1753 stv0900_write_reg(intp, BCLC, 0x09);
1754 if (intp->chip_id <= 0x20)
1755 stv0900_write_reg(intp, CAR2CFG, 0x26);
1756 else
1757 stv0900_write_reg(intp, CAR2CFG, 0x66);
1758
1759 if (intp->demod_mode != STV0900_SINGLE) {
1760 if (intp->chip_id <= 0x11)
1761 stv0900_stop_all_s2_modcod(intp, demod);
1762 else
1763 stv0900_activate_s2_modcod(intp, demod);
1764
1765 } else
1766 stv0900_activate_s2_modcod_single(intp, demod);
1767
1768 stv0900_set_viterbi_tracq(intp, demod);
1769
1770 break;
1771 case STV0900_AUTO_SEARCH:
1772 default:
1773 stv0900_write_bits(intp, DVBS1_ENABLE, 1);
1774 stv0900_write_bits(intp, DVBS2_ENABLE, 1);
1775 stv0900_write_bits(intp, STOP_CLKVIT, 0);
1776 stv0900_write_reg(intp, ACLC, 0x1a);
1777 stv0900_write_reg(intp, BCLC, 0x09);
1778 stv0900_set_dvbs1_track_car_loop(intp,
1779 demod,
1780 intp->symbol_rate[demod]);
1781 if (intp->chip_id <= 0x20)
1782 stv0900_write_reg(intp, CAR2CFG, 0x26);
1783 else
1784 stv0900_write_reg(intp, CAR2CFG, 0x66);
1785
1786 if (intp->demod_mode != STV0900_SINGLE) {
1787 if (intp->chip_id <= 0x11)
1788 stv0900_stop_all_s2_modcod(intp, demod);
1789 else
1790 stv0900_activate_s2_modcod(intp, demod);
1791
1792 } else
1793 stv0900_activate_s2_modcod_single(intp, demod);
1794
1795 stv0900_set_viterbi_tracq(intp, demod);
1796 stv0900_set_viterbi_standard(intp,
1797 intp->srch_standard[demod],
1798 intp->fec[demod], demod);
1799
1800 break;
1801 }
1802}
1803
1804enum fe_stv0900_signal_type stv0900_algo(struct dvb_frontend *fe)
1805{
1806 struct stv0900_state *state = fe->demodulator_priv;
1807 struct stv0900_internal *intp = state->internal;
1808 enum fe_stv0900_demod_num demod = state->demod;
1809
1810 s32 demod_timeout = 500, fec_timeout = 50;
1811 s32 aq_power, agc1_power, i;
1812
1813 int lock = FALSE, low_sr = FALSE;
1814
1815 enum fe_stv0900_signal_type signal_type = STV0900_NOCARRIER;
1816 enum fe_stv0900_search_algo algo;
1817 int no_signal = FALSE;
1818
1819 dprintk("%s\n", __func__);
1820
1821 algo = intp->srch_algo[demod];
1822 stv0900_write_bits(intp, RST_HWARE, 1);
1823 stv0900_write_reg(intp, DMDISTATE, 0x5c);
1824 if (intp->chip_id >= 0x20) {
1825 if (intp->symbol_rate[demod] > 5000000)
1826 stv0900_write_reg(intp, CORRELABS, 0x9e);
1827 else
1828 stv0900_write_reg(intp, CORRELABS, 0x82);
1829 } else
1830 stv0900_write_reg(intp, CORRELABS, 0x88);
1831
1832 stv0900_get_lock_timeout(&demod_timeout, &fec_timeout,
1833 intp->symbol_rate[demod],
1834 intp->srch_algo[demod]);
1835
1836 if (intp->srch_algo[demod] == STV0900_BLIND_SEARCH) {
1837 intp->bw[demod] = 2 * 36000000;
1838
1839 stv0900_write_reg(intp, TMGCFG2, 0xc0);
1840 stv0900_write_reg(intp, CORRELMANT, 0x70);
1841
1842 stv0900_set_symbol_rate(intp, intp->mclk, 1000000, demod);
1843 } else {
1844 stv0900_write_reg(intp, DMDT0M, 0x20);
1845 stv0900_write_reg(intp, TMGCFG, 0xd2);
1846
1847 if (intp->symbol_rate[demod] < 2000000)
1848 stv0900_write_reg(intp, CORRELMANT, 0x63);
1849 else
1850 stv0900_write_reg(intp, CORRELMANT, 0x70);
1851
1852 stv0900_write_reg(intp, AGC2REF, 0x38);
1853
1854 intp->bw[demod] =
1855 stv0900_carrier_width(intp->symbol_rate[demod],
1856 intp->rolloff);
1857 if (intp->chip_id >= 0x20) {
1858 stv0900_write_reg(intp, KREFTMG, 0x5a);
1859
1860 if (intp->srch_algo[demod] == STV0900_COLD_START) {
1861 intp->bw[demod] += 10000000;
1862 intp->bw[demod] *= 15;
1863 intp->bw[demod] /= 10;
1864 } else if (intp->srch_algo[demod] == STV0900_WARM_START)
1865 intp->bw[demod] += 10000000;
1866
1867 } else {
1868 stv0900_write_reg(intp, KREFTMG, 0xc1);
1869 intp->bw[demod] += 10000000;
1870 intp->bw[demod] *= 15;
1871 intp->bw[demod] /= 10;
1872 }
1873
1874 stv0900_write_reg(intp, TMGCFG2, 0xc1);
1875
1876 stv0900_set_symbol_rate(intp, intp->mclk,
1877 intp->symbol_rate[demod], demod);
1878 stv0900_set_max_symbol_rate(intp, intp->mclk,
1879 intp->symbol_rate[demod], demod);
1880 stv0900_set_min_symbol_rate(intp, intp->mclk,
1881 intp->symbol_rate[demod], demod);
1882 if (intp->symbol_rate[demod] >= 10000000)
1883 low_sr = FALSE;
1884 else
1885 low_sr = TRUE;
1886
1887 }
1888
1889 if (intp->tuner_type[demod] == 3)
1890 stv0900_set_tuner_auto(intp, intp->freq[demod],
1891 intp->bw[demod], demod);
1892 else
1893 stv0900_set_tuner(fe, intp->freq[demod], intp->bw[demod]);
1894
1895 agc1_power = MAKEWORD(stv0900_get_bits(intp, AGCIQ_VALUE1),
1896 stv0900_get_bits(intp, AGCIQ_VALUE0));
1897
1898 aq_power = 0;
1899
1900 if (agc1_power == 0) {
1901 for (i = 0; i < 5; i++)
1902 aq_power += (stv0900_get_bits(intp, POWER_I) +
1903 stv0900_get_bits(intp, POWER_Q)) / 2;
1904
1905 aq_power /= 5;
1906 }
1907
1908 if ((agc1_power == 0) && (aq_power < IQPOWER_THRESHOLD)) {
1909 intp->result[demod].locked = FALSE;
1910 signal_type = STV0900_NOAGC1;
1911 dprintk("%s: NO AGC1, POWERI, POWERQ\n", __func__);
1912 } else {
1913 stv0900_write_bits(intp, SPECINV_CONTROL,
1914 intp->srch_iq_inv[demod]);
1915 if (intp->chip_id <= 0x20)
1916 stv0900_write_bits(intp, MANUALSX_ROLLOFF, 1);
1917 else
1918 stv0900_write_bits(intp, MANUALS2_ROLLOFF, 1);
1919
1920 stv0900_set_search_standard(intp, demod);
1921
1922 if (intp->srch_algo[demod] != STV0900_BLIND_SEARCH)
1923 stv0900_start_search(intp, demod);
1924 }
1925
1926 if (signal_type == STV0900_NOAGC1)
1927 return signal_type;
1928
1929 if (intp->chip_id == 0x12) {
1930 stv0900_write_bits(intp, RST_HWARE, 0);
1931 msleep(3);
1932 stv0900_write_bits(intp, RST_HWARE, 1);
1933 stv0900_write_bits(intp, RST_HWARE, 0);
1934 }
1935
1936 if (algo == STV0900_BLIND_SEARCH)
1937 lock = stv0900_blind_search_algo(fe);
1938 else if (algo == STV0900_COLD_START)
1939 lock = stv0900_get_demod_cold_lock(fe, demod_timeout);
1940 else if (algo == STV0900_WARM_START)
1941 lock = stv0900_get_demod_lock(intp, demod, demod_timeout);
1942
1943 if ((lock == FALSE) && (algo == STV0900_COLD_START)) {
1944 if (low_sr == FALSE) {
1945 if (stv0900_check_timing_lock(intp, demod) == TRUE)
1946 lock = stv0900_sw_algo(intp, demod);
1947 }
1948 }
1949
1950 if (lock == TRUE)
1951 signal_type = stv0900_get_signal_params(fe);
1952
1953 if ((lock == TRUE) && (signal_type == STV0900_RANGEOK)) {
1954 stv0900_track_optimization(fe);
1955 if (intp->chip_id <= 0x11) {
1956 if ((stv0900_get_standard(fe, 0) ==
1957 STV0900_DVBS1_STANDARD) &&
1958 (stv0900_get_standard(fe, 1) ==
1959 STV0900_DVBS1_STANDARD)) {
1960 msleep(20);
1961 stv0900_write_bits(intp, RST_HWARE, 0);
1962 } else {
1963 stv0900_write_bits(intp, RST_HWARE, 0);
1964 msleep(3);
1965 stv0900_write_bits(intp, RST_HWARE, 1);
1966 stv0900_write_bits(intp, RST_HWARE, 0);
1967 }
1968
1969 } else if (intp->chip_id >= 0x20) {
1970 stv0900_write_bits(intp, RST_HWARE, 0);
1971 msleep(3);
1972 stv0900_write_bits(intp, RST_HWARE, 1);
1973 stv0900_write_bits(intp, RST_HWARE, 0);
1974 }
1975
1976 if (stv0900_wait_for_lock(intp, demod,
1977 fec_timeout, fec_timeout) == TRUE) {
1978 lock = TRUE;
1979 intp->result[demod].locked = TRUE;
1980 if (intp->result[demod].standard ==
1981 STV0900_DVBS2_STANDARD) {
1982 stv0900_set_dvbs2_rolloff(intp, demod);
1983 stv0900_write_bits(intp, RESET_UPKO_COUNT, 1);
1984 stv0900_write_bits(intp, RESET_UPKO_COUNT, 0);
1985 stv0900_write_reg(intp, ERRCTRL1, 0x67);
1986 } else {
1987 stv0900_write_reg(intp, ERRCTRL1, 0x75);
1988 }
1989
1990 stv0900_write_reg(intp, FBERCPT4, 0);
1991 stv0900_write_reg(intp, ERRCTRL2, 0xc1);
1992 } else {
1993 lock = FALSE;
1994 signal_type = STV0900_NODATA;
1995 no_signal = stv0900_check_signal_presence(intp, demod);
1996
1997 intp->result[demod].locked = FALSE;
1998 }
1999 }
2000
2001 if ((signal_type != STV0900_NODATA) || (no_signal != FALSE))
2002 return signal_type;
2003
2004 if (intp->chip_id > 0x11) {
2005 intp->result[demod].locked = FALSE;
2006 return signal_type;
2007 }
2008
2009 if ((stv0900_get_bits(intp, HEADER_MODE) == STV0900_DVBS_FOUND) &&
2010 (intp->srch_iq_inv[demod] <= STV0900_IQ_AUTO_NORMAL_FIRST))
2011 signal_type = stv0900_dvbs1_acq_workaround(fe);
2012
2013 return signal_type;
2014}
2015
2016
