linux/drivers/media/i2c/ad9389b.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Analog Devices AD9389B/AD9889B video encoder driver
   4 *
   5 * Copyright 2012 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
   6 */
   7
   8/*
   9 * References (c = chapter, p = page):
  10 * REF_01 - Analog Devices, Programming Guide, AD9889B/AD9389B,
  11 * HDMI Transitter, Rev. A, October 2010
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/module.h>
  16#include <linux/slab.h>
  17#include <linux/i2c.h>
  18#include <linux/delay.h>
  19#include <linux/videodev2.h>
  20#include <linux/workqueue.h>
  21#include <linux/v4l2-dv-timings.h>
  22#include <media/v4l2-device.h>
  23#include <media/v4l2-common.h>
  24#include <media/v4l2-dv-timings.h>
  25#include <media/v4l2-ctrls.h>
  26#include <media/i2c/ad9389b.h>
  27
  28static int debug;
  29module_param(debug, int, 0644);
  30MODULE_PARM_DESC(debug, "debug level (0-2)");
  31
  32MODULE_DESCRIPTION("Analog Devices AD9389B/AD9889B video encoder driver");
  33MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
  34MODULE_AUTHOR("Martin Bugge <marbugge@cisco.com>");
  35MODULE_LICENSE("GPL");
  36
  37#define MASK_AD9389B_EDID_RDY_INT   0x04
  38#define MASK_AD9389B_MSEN_INT       0x40
  39#define MASK_AD9389B_HPD_INT        0x80
  40
  41#define MASK_AD9389B_HPD_DETECT     0x40
  42#define MASK_AD9389B_MSEN_DETECT    0x20
  43#define MASK_AD9389B_EDID_RDY       0x10
  44
  45#define EDID_MAX_RETRIES (8)
  46#define EDID_DELAY 250
  47#define EDID_MAX_SEGM 8
  48
  49/*
  50**********************************************************************
  51*
  52*  Arrays with configuration parameters for the AD9389B
  53*
  54**********************************************************************
  55*/
  56
  57struct ad9389b_state_edid {
  58        /* total number of blocks */
  59        u32 blocks;
  60        /* Number of segments read */
  61        u32 segments;
  62        u8 data[EDID_MAX_SEGM * 256];
  63        /* Number of EDID read retries left */
  64        unsigned read_retries;
  65};
  66
  67struct ad9389b_state {
  68        struct ad9389b_platform_data pdata;
  69        struct v4l2_subdev sd;
  70        struct media_pad pad;
  71        struct v4l2_ctrl_handler hdl;
  72        int chip_revision;
  73        /* Is the ad9389b powered on? */
  74        bool power_on;
  75        /* Did we receive hotplug and rx-sense signals? */
  76        bool have_monitor;
  77        /* timings from s_dv_timings */
  78        struct v4l2_dv_timings dv_timings;
  79        /* controls */
  80        struct v4l2_ctrl *hdmi_mode_ctrl;
  81        struct v4l2_ctrl *hotplug_ctrl;
  82        struct v4l2_ctrl *rx_sense_ctrl;
  83        struct v4l2_ctrl *have_edid0_ctrl;
  84        struct v4l2_ctrl *rgb_quantization_range_ctrl;
  85        struct i2c_client *edid_i2c_client;
  86        struct ad9389b_state_edid edid;
  87        /* Running counter of the number of detected EDIDs (for debugging) */
  88        unsigned edid_detect_counter;
  89        struct delayed_work edid_handler; /* work entry */
  90};
  91
  92static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd);
  93static bool ad9389b_check_edid_status(struct v4l2_subdev *sd);
  94static void ad9389b_setup(struct v4l2_subdev *sd);
  95static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq);
  96static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
  97
  98static inline struct ad9389b_state *get_ad9389b_state(struct v4l2_subdev *sd)
  99{
 100        return container_of(sd, struct ad9389b_state, sd);
 101}
 102
 103static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
 104{
 105        return &container_of(ctrl->handler, struct ad9389b_state, hdl)->sd;
 106}
 107
 108/* ------------------------ I2C ----------------------------------------------- */
 109
 110static int ad9389b_rd(struct v4l2_subdev *sd, u8 reg)
 111{
 112        struct i2c_client *client = v4l2_get_subdevdata(sd);
 113
 114        return i2c_smbus_read_byte_data(client, reg);
 115}
 116
 117static int ad9389b_wr(struct v4l2_subdev *sd, u8 reg, u8 val)
 118{
 119        struct i2c_client *client = v4l2_get_subdevdata(sd);
 120        int ret;
 121        int i;
 122
 123        for (i = 0; i < 3; i++) {
 124                ret = i2c_smbus_write_byte_data(client, reg, val);
 125                if (ret == 0)
 126                        return 0;
 127        }
 128        v4l2_err(sd, "%s: failed reg 0x%x, val 0x%x\n", __func__, reg, val);
 129        return ret;
 130}
 131
 132/* To set specific bits in the register, a clear-mask is given (to be AND-ed),
 133   and then the value-mask (to be OR-ed). */
 134static inline void ad9389b_wr_and_or(struct v4l2_subdev *sd, u8 reg,
 135                                     u8 clr_mask, u8 val_mask)
 136{
 137        ad9389b_wr(sd, reg, (ad9389b_rd(sd, reg) & clr_mask) | val_mask);
 138}
 139
 140static void ad9389b_edid_rd(struct v4l2_subdev *sd, u16 len, u8 *buf)
 141{
 142        struct ad9389b_state *state = get_ad9389b_state(sd);
 143        int i;
 144
 145        v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 146
 147        for (i = 0; i < len; i++)
 148                buf[i] = i2c_smbus_read_byte_data(state->edid_i2c_client, i);
 149}
 150
 151static inline bool ad9389b_have_hotplug(struct v4l2_subdev *sd)
 152{
 153        return ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT;
 154}
 155
 156static inline bool ad9389b_have_rx_sense(struct v4l2_subdev *sd)
 157{
 158        return ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT;
 159}
 160
 161static void ad9389b_csc_conversion_mode(struct v4l2_subdev *sd, u8 mode)
 162{
 163        ad9389b_wr_and_or(sd, 0x17, 0xe7, (mode & 0x3)<<3);
 164        ad9389b_wr_and_or(sd, 0x18, 0x9f, (mode & 0x3)<<5);
 165}
 166
 167static void ad9389b_csc_coeff(struct v4l2_subdev *sd,
 168                              u16 A1, u16 A2, u16 A3, u16 A4,
 169                              u16 B1, u16 B2, u16 B3, u16 B4,
 170                              u16 C1, u16 C2, u16 C3, u16 C4)
 171{
 172        /* A */
 173        ad9389b_wr_and_or(sd, 0x18, 0xe0, A1>>8);
 174        ad9389b_wr(sd, 0x19, A1);
 175        ad9389b_wr_and_or(sd, 0x1A, 0xe0, A2>>8);
 176        ad9389b_wr(sd, 0x1B, A2);
 177        ad9389b_wr_and_or(sd, 0x1c, 0xe0, A3>>8);
 178        ad9389b_wr(sd, 0x1d, A3);
 179        ad9389b_wr_and_or(sd, 0x1e, 0xe0, A4>>8);
 180        ad9389b_wr(sd, 0x1f, A4);
 181
 182        /* B */
 183        ad9389b_wr_and_or(sd, 0x20, 0xe0, B1>>8);
 184        ad9389b_wr(sd, 0x21, B1);
 185        ad9389b_wr_and_or(sd, 0x22, 0xe0, B2>>8);
 186        ad9389b_wr(sd, 0x23, B2);
 187        ad9389b_wr_and_or(sd, 0x24, 0xe0, B3>>8);
 188        ad9389b_wr(sd, 0x25, B3);
 189        ad9389b_wr_and_or(sd, 0x26, 0xe0, B4>>8);
 190        ad9389b_wr(sd, 0x27, B4);
 191
 192        /* C */
 193        ad9389b_wr_and_or(sd, 0x28, 0xe0, C1>>8);
 194        ad9389b_wr(sd, 0x29, C1);
 195        ad9389b_wr_and_or(sd, 0x2A, 0xe0, C2>>8);
 196        ad9389b_wr(sd, 0x2B, C2);
 197        ad9389b_wr_and_or(sd, 0x2C, 0xe0, C3>>8);
 198        ad9389b_wr(sd, 0x2D, C3);
 199        ad9389b_wr_and_or(sd, 0x2E, 0xe0, C4>>8);
 200        ad9389b_wr(sd, 0x2F, C4);
 201}
 202
 203static void ad9389b_csc_rgb_full2limit(struct v4l2_subdev *sd, bool enable)
 204{
 205        if (enable) {
 206                u8 csc_mode = 0;
 207
 208                ad9389b_csc_conversion_mode(sd, csc_mode);
 209                ad9389b_csc_coeff(sd,
 210                                  4096-564, 0, 0, 256,
 211                                  0, 4096-564, 0, 256,
 212                                  0, 0, 4096-564, 256);
 213                /* enable CSC */
 214                ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x1);
 215                /* AVI infoframe: Limited range RGB (16-235) */
 216                ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x02);
 217        } else {
 218                /* disable CSC */
 219                ad9389b_wr_and_or(sd, 0x3b, 0xfe, 0x0);
 220                /* AVI infoframe: Full range RGB (0-255) */
 221                ad9389b_wr_and_or(sd, 0xcd, 0xf9, 0x04);
 222        }
 223}
 224
 225static void ad9389b_set_IT_content_AVI_InfoFrame(struct v4l2_subdev *sd)
 226{
 227        struct ad9389b_state *state = get_ad9389b_state(sd);
 228
 229        if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
 230                /* CE format, not IT  */
 231                ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x00);
 232        } else {
 233                /* IT format */
 234                ad9389b_wr_and_or(sd, 0xcd, 0xbf, 0x40);
 235        }
 236}
 237
 238static int ad9389b_set_rgb_quantization_mode(struct v4l2_subdev *sd, struct v4l2_ctrl *ctrl)
 239{
 240        struct ad9389b_state *state = get_ad9389b_state(sd);
 241
 242        switch (ctrl->val) {
 243        case V4L2_DV_RGB_RANGE_AUTO:
 244                /* automatic */
 245                if (state->dv_timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
 246                        /* CE format, RGB limited range (16-235) */
 247                        ad9389b_csc_rgb_full2limit(sd, true);
 248                } else {
 249                        /* not CE format, RGB full range (0-255) */
 250                        ad9389b_csc_rgb_full2limit(sd, false);
 251                }
 252                break;
 253        case V4L2_DV_RGB_RANGE_LIMITED:
 254                /* RGB limited range (16-235) */
 255                ad9389b_csc_rgb_full2limit(sd, true);
 256                break;
 257        case V4L2_DV_RGB_RANGE_FULL:
 258                /* RGB full range (0-255) */
 259                ad9389b_csc_rgb_full2limit(sd, false);
 260                break;
 261        default:
 262                return -EINVAL;
 263        }
 264        return 0;
 265}
 266
 267static void ad9389b_set_manual_pll_gear(struct v4l2_subdev *sd, u32 pixelclock)
 268{
 269        u8 gear;
 270
 271        /* Workaround for TMDS PLL problem
 272         * The TMDS PLL in AD9389b change gear when the chip is heated above a
 273         * certain temperature. The output is disabled when the PLL change gear
 274         * so the monitor has to lock on the signal again. A workaround for
 275         * this is to use the manual PLL gears. This is a solution from Analog
 276         * Devices that is not documented in the datasheets.
 277         * 0x98 [7] = enable manual gearing. 0x98 [6:4] = gear
 278         *
 279         * The pixel frequency ranges are based on readout of the gear the
 280         * automatic gearing selects for different pixel clocks
 281         * (read from 0x9e [3:1]).
 282         */
 283
 284        if (pixelclock > 140000000)
 285                gear = 0xc0; /* 4th gear */
 286        else if (pixelclock > 117000000)
 287                gear = 0xb0; /* 3rd gear */
 288        else if (pixelclock > 87000000)
 289                gear = 0xa0; /* 2nd gear */
 290        else if (pixelclock > 60000000)
 291                gear = 0x90; /* 1st gear */
 292        else
 293                gear = 0x80; /* 0th gear */
 294
 295        ad9389b_wr_and_or(sd, 0x98, 0x0f, gear);
 296}
 297
 298/* ------------------------------ CTRL OPS ------------------------------ */
 299
 300static int ad9389b_s_ctrl(struct v4l2_ctrl *ctrl)
 301{
 302        struct v4l2_subdev *sd = to_sd(ctrl);
 303        struct ad9389b_state *state = get_ad9389b_state(sd);
 304
 305        v4l2_dbg(1, debug, sd,
 306                 "%s: ctrl id: %d, ctrl->val %d\n", __func__, ctrl->id, ctrl->val);
 307
 308        if (state->hdmi_mode_ctrl == ctrl) {
 309                /* Set HDMI or DVI-D */
 310                ad9389b_wr_and_or(sd, 0xaf, 0xfd,
 311                                  ctrl->val == V4L2_DV_TX_MODE_HDMI ? 0x02 : 0x00);
 312                return 0;
 313        }
 314        if (state->rgb_quantization_range_ctrl == ctrl)
 315                return ad9389b_set_rgb_quantization_mode(sd, ctrl);
 316        return -EINVAL;
 317}
 318
 319static const struct v4l2_ctrl_ops ad9389b_ctrl_ops = {
 320        .s_ctrl = ad9389b_s_ctrl,
 321};
 322
 323/* ---------------------------- CORE OPS ------------------------------------------- */
 324
 325#ifdef CONFIG_VIDEO_ADV_DEBUG
 326static int ad9389b_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
 327{
 328        reg->val = ad9389b_rd(sd, reg->reg & 0xff);
 329        reg->size = 1;
 330        return 0;
 331}
 332
 333static int ad9389b_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
 334{
 335        ad9389b_wr(sd, reg->reg & 0xff, reg->val & 0xff);
 336        return 0;
 337}
 338#endif
 339
 340static int ad9389b_log_status(struct v4l2_subdev *sd)
 341{
 342        struct ad9389b_state *state = get_ad9389b_state(sd);
 343        struct ad9389b_state_edid *edid = &state->edid;
 344
 345        static const char * const states[] = {
 346                "in reset",
 347                "reading EDID",
 348                "idle",
 349                "initializing HDCP",
 350                "HDCP enabled",
 351                "initializing HDCP repeater",
 352                "6", "7", "8", "9", "A", "B", "C", "D", "E", "F"
 353        };
 354        static const char * const errors[] = {
 355                "no error",
 356                "bad receiver BKSV",
 357                "Ri mismatch",
 358                "Pj mismatch",
 359                "i2c error",
 360                "timed out",
 361                "max repeater cascade exceeded",
 362                "hash check failed",
 363                "too many devices",
 364                "9", "A", "B", "C", "D", "E", "F"
 365        };
 366
 367        u8 manual_gear;
 368
 369        v4l2_info(sd, "chip revision %d\n", state->chip_revision);
 370        v4l2_info(sd, "power %s\n", state->power_on ? "on" : "off");
 371        v4l2_info(sd, "%s hotplug, %s Rx Sense, %s EDID (%d block(s))\n",
 372                  (ad9389b_rd(sd, 0x42) & MASK_AD9389B_HPD_DETECT) ?
 373                  "detected" : "no",
 374                  (ad9389b_rd(sd, 0x42) & MASK_AD9389B_MSEN_DETECT) ?
 375                  "detected" : "no",
 376                  edid->segments ? "found" : "no", edid->blocks);
 377        v4l2_info(sd, "%s output %s\n",
 378                  (ad9389b_rd(sd, 0xaf) & 0x02) ?
 379                  "HDMI" : "DVI-D",
 380                  (ad9389b_rd(sd, 0xa1) & 0x3c) ?
 381                  "disabled" : "enabled");
 382        v4l2_info(sd, "ad9389b: %s\n", (ad9389b_rd(sd, 0xb8) & 0x40) ?
 383                  "encrypted" : "no encryption");
 384        v4l2_info(sd, "state: %s, error: %s, detect count: %u, msk/irq: %02x/%02x\n",
 385                  states[ad9389b_rd(sd, 0xc8) & 0xf],
 386                  errors[ad9389b_rd(sd, 0xc8) >> 4],
 387                  state->edid_detect_counter,
 388                  ad9389b_rd(sd, 0x94), ad9389b_rd(sd, 0x96));
 389        manual_gear = ad9389b_rd(sd, 0x98) & 0x80;
 390        v4l2_info(sd, "ad9389b: RGB quantization: %s range\n",
 391                  ad9389b_rd(sd, 0x3b) & 0x01 ? "limited" : "full");
 392        v4l2_info(sd, "ad9389b: %s gear %d\n",
 393                  manual_gear ? "manual" : "automatic",
 394                  manual_gear ? ((ad9389b_rd(sd, 0x98) & 0x70) >> 4) :
 395                  ((ad9389b_rd(sd, 0x9e) & 0x0e) >> 1));
 396        if (ad9389b_rd(sd, 0xaf) & 0x02) {
 397                /* HDMI only */
 398                u8 manual_cts = ad9389b_rd(sd, 0x0a) & 0x80;
 399                u32 N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 400                        ad9389b_rd(sd, 0x02) << 8 |
 401                        ad9389b_rd(sd, 0x03);
 402                u8 vic_detect = ad9389b_rd(sd, 0x3e) >> 2;
 403                u8 vic_sent = ad9389b_rd(sd, 0x3d) & 0x3f;
 404                u32 CTS;
 405
 406                if (manual_cts)
 407                        CTS = (ad9389b_rd(sd, 0x07) & 0xf) << 16 |
 408                              ad9389b_rd(sd, 0x08) << 8 |
 409                              ad9389b_rd(sd, 0x09);
 410                else
 411                        CTS = (ad9389b_rd(sd, 0x04) & 0xf) << 16 |
 412                              ad9389b_rd(sd, 0x05) << 8 |
 413                              ad9389b_rd(sd, 0x06);
 414                N = (ad9389b_rd(sd, 0x01) & 0xf) << 16 |
 415                    ad9389b_rd(sd, 0x02) << 8 |
 416                    ad9389b_rd(sd, 0x03);
 417
 418                v4l2_info(sd, "ad9389b: CTS %s mode: N %d, CTS %d\n",
 419                          manual_cts ? "manual" : "automatic", N, CTS);
 420
 421                v4l2_info(sd, "ad9389b: VIC: detected %d, sent %d\n",
 422                          vic_detect, vic_sent);
 423        }
 424        if (state->dv_timings.type == V4L2_DV_BT_656_1120)
 425                v4l2_print_dv_timings(sd->name, "timings: ",
 426                                &state->dv_timings, false);
 427        else
 428                v4l2_info(sd, "no timings set\n");
 429        return 0;
 430}
 431
 432/* Power up/down ad9389b */
 433static int ad9389b_s_power(struct v4l2_subdev *sd, int on)
 434{
 435        struct ad9389b_state *state = get_ad9389b_state(sd);
 436        struct ad9389b_platform_data *pdata = &state->pdata;
 437        const int retries = 20;
 438        int i;
 439
 440        v4l2_dbg(1, debug, sd, "%s: power %s\n", __func__, on ? "on" : "off");
 441
 442        state->power_on = on;
 443
 444        if (!on) {
 445                /* Power down */
 446                ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 447                return true;
 448        }
 449
 450        /* Power up */
 451        /* The ad9389b does not always come up immediately.
 452           Retry multiple times. */
 453        for (i = 0; i < retries; i++) {
 454                ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x0);
 455                if ((ad9389b_rd(sd, 0x41) & 0x40) == 0)
 456                        break;
 457                ad9389b_wr_and_or(sd, 0x41, 0xbf, 0x40);
 458                msleep(10);
 459        }
 460        if (i == retries) {
 461                v4l2_dbg(1, debug, sd, "failed to powerup the ad9389b\n");
 462                ad9389b_s_power(sd, 0);
 463                return false;
 464        }
 465        if (i > 1)
 466                v4l2_dbg(1, debug, sd,
 467                         "needed %d retries to powerup the ad9389b\n", i);
 468
 469        /* Select chip: AD9389B */
 470        ad9389b_wr_and_or(sd, 0xba, 0xef, 0x10);
 471
 472        /* Reserved registers that must be set according to REF_01 p. 11*/
 473        ad9389b_wr_and_or(sd, 0x98, 0xf0, 0x07);
 474        ad9389b_wr(sd, 0x9c, 0x38);
 475        ad9389b_wr_and_or(sd, 0x9d, 0xfc, 0x01);
 476
 477        /* Differential output drive strength */
 478        if (pdata->diff_data_drive_strength > 0)
 479                ad9389b_wr(sd, 0xa2, pdata->diff_data_drive_strength);
 480        else
 481                ad9389b_wr(sd, 0xa2, 0x87);
 482
 483        if (pdata->diff_clk_drive_strength > 0)
 484                ad9389b_wr(sd, 0xa3, pdata->diff_clk_drive_strength);
 485        else
 486                ad9389b_wr(sd, 0xa3, 0x87);
 487
 488        ad9389b_wr(sd, 0x0a, 0x01);
 489        ad9389b_wr(sd, 0xbb, 0xff);
 490
 491        /* Set number of attempts to read the EDID */
 492        ad9389b_wr(sd, 0xc9, 0xf);
 493        return true;
 494}
 495
 496/* Enable interrupts */
 497static void ad9389b_set_isr(struct v4l2_subdev *sd, bool enable)
 498{
 499        u8 irqs = MASK_AD9389B_HPD_INT | MASK_AD9389B_MSEN_INT;
 500        u8 irqs_rd;
 501        int retries = 100;
 502
 503        /* The datasheet says that the EDID ready interrupt should be
 504           disabled if there is no hotplug. */
 505        if (!enable)
 506                irqs = 0;
 507        else if (ad9389b_have_hotplug(sd))
 508                irqs |= MASK_AD9389B_EDID_RDY_INT;
 509
 510        /*
 511         * This i2c write can fail (approx. 1 in 1000 writes). But it
 512         * is essential that this register is correct, so retry it
 513         * multiple times.
 514         *
 515         * Note that the i2c write does not report an error, but the readback
 516         * clearly shows the wrong value.
 517         */
 518        do {
 519                ad9389b_wr(sd, 0x94, irqs);
 520                irqs_rd = ad9389b_rd(sd, 0x94);
 521        } while (retries-- && irqs_rd != irqs);
 522
 523        if (irqs_rd != irqs)
 524                v4l2_err(sd, "Could not set interrupts: hw failure?\n");
 525}
 526
 527/* Interrupt handler */
 528static int ad9389b_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
 529{
 530        u8 irq_status;
 531
 532        /* disable interrupts to prevent a race condition */
 533        ad9389b_set_isr(sd, false);
 534        irq_status = ad9389b_rd(sd, 0x96);
 535        /* clear detected interrupts */
 536        ad9389b_wr(sd, 0x96, irq_status);
 537        /* enable interrupts */
 538        ad9389b_set_isr(sd, true);
 539
 540        v4l2_dbg(1, debug, sd, "%s: irq_status 0x%x\n", __func__, irq_status);
 541
 542        if (irq_status & (MASK_AD9389B_HPD_INT))
 543                ad9389b_check_monitor_present_status(sd);
 544        if (irq_status & MASK_AD9389B_EDID_RDY_INT)
 545                ad9389b_check_edid_status(sd);
 546
 547        *handled = true;
 548        return 0;
 549}
 550
 551static const struct v4l2_subdev_core_ops ad9389b_core_ops = {
 552        .log_status = ad9389b_log_status,
 553#ifdef CONFIG_VIDEO_ADV_DEBUG
 554        .g_register = ad9389b_g_register,
 555        .s_register = ad9389b_s_register,
 556#endif
 557        .s_power = ad9389b_s_power,
 558        .interrupt_service_routine = ad9389b_isr,
 559};
 560
 561/* ------------------------------ VIDEO OPS ------------------------------ */
 562
 563/* Enable/disable ad9389b output */
 564static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
 565{
 566        v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 567
 568        ad9389b_wr_and_or(sd, 0xa1, ~0x3c, (enable ? 0 : 0x3c));
 569        if (enable) {
 570                ad9389b_check_monitor_present_status(sd);
 571        } else {
 572                ad9389b_s_power(sd, 0);
 573        }
 574        return 0;
 575}
 576
 577static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
 578        .type = V4L2_DV_BT_656_1120,
 579        /* keep this initialization for compatibility with GCC < 4.4.6 */
 580        .reserved = { 0 },
 581        V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
 582                V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
 583                        V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
 584                V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
 585                V4L2_DV_BT_CAP_CUSTOM)
 586};
 587
 588static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
 589                                struct v4l2_dv_timings *timings)
 590{
 591        struct ad9389b_state *state = get_ad9389b_state(sd);
 592
 593        v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 594
 595        /* quick sanity check */
 596        if (!v4l2_valid_dv_timings(timings, &ad9389b_timings_cap, NULL, NULL))
 597                return -EINVAL;
 598
 599        /* Fill the optional fields .standards and .flags in struct v4l2_dv_timings
 600           if the format is one of the CEA or DMT timings. */
 601        v4l2_find_dv_timings_cap(timings, &ad9389b_timings_cap, 0, NULL, NULL);
 602
 603        timings->bt.flags &= ~V4L2_DV_FL_REDUCED_FPS;
 604
 605        /* save timings */
 606        state->dv_timings = *timings;
 607
 608        /* update quantization range based on new dv_timings */
 609        ad9389b_set_rgb_quantization_mode(sd, state->rgb_quantization_range_ctrl);
 610
 611        /* update PLL gear based on new dv_timings */
 612        if (state->pdata.tmds_pll_gear == AD9389B_TMDS_PLL_GEAR_SEMI_AUTOMATIC)
 613                ad9389b_set_manual_pll_gear(sd, (u32)timings->bt.pixelclock);
 614
 615        /* update AVI infoframe */
 616        ad9389b_set_IT_content_AVI_InfoFrame(sd);
 617
 618        return 0;
 619}
 620
 621static int ad9389b_g_dv_timings(struct v4l2_subdev *sd,
 622                                struct v4l2_dv_timings *timings)
 623{
 624        struct ad9389b_state *state = get_ad9389b_state(sd);
 625
 626        v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 627
 628        if (!timings)
 629                return -EINVAL;
 630
 631        *timings = state->dv_timings;
 632
 633        return 0;
 634}
 635
 636static int ad9389b_enum_dv_timings(struct v4l2_subdev *sd,
 637                                   struct v4l2_enum_dv_timings *timings)
 638{
 639        if (timings->pad != 0)
 640                return -EINVAL;
 641
 642        return v4l2_enum_dv_timings_cap(timings, &ad9389b_timings_cap,
 643                        NULL, NULL);
 644}
 645
 646static int ad9389b_dv_timings_cap(struct v4l2_subdev *sd,
 647                                  struct v4l2_dv_timings_cap *cap)
 648{
 649        if (cap->pad != 0)
 650                return -EINVAL;
 651
 652        *cap = ad9389b_timings_cap;
 653        return 0;
 654}
 655
 656static const struct v4l2_subdev_video_ops ad9389b_video_ops = {
 657        .s_stream = ad9389b_s_stream,
 658        .s_dv_timings = ad9389b_s_dv_timings,
 659        .g_dv_timings = ad9389b_g_dv_timings,
 660};
 661
 662/* ------------------------------ PAD OPS ------------------------------ */
 663
 664static int ad9389b_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
 665{
 666        struct ad9389b_state *state = get_ad9389b_state(sd);
 667
 668        if (edid->pad != 0)
 669                return -EINVAL;
 670        if (edid->blocks == 0 || edid->blocks > 256)
 671                return -EINVAL;
 672        if (!state->edid.segments) {
 673                v4l2_dbg(1, debug, sd, "EDID segment 0 not found\n");
 674                return -ENODATA;
 675        }
 676        if (edid->start_block >= state->edid.segments * 2)
 677                return -E2BIG;
 678        if (edid->blocks + edid->start_block >= state->edid.segments * 2)
 679                edid->blocks = state->edid.segments * 2 - edid->start_block;
 680        memcpy(edid->edid, &state->edid.data[edid->start_block * 128],
 681               128 * edid->blocks);
 682        return 0;
 683}
 684
 685static const struct v4l2_subdev_pad_ops ad9389b_pad_ops = {
 686        .get_edid = ad9389b_get_edid,
 687        .enum_dv_timings = ad9389b_enum_dv_timings,
 688        .dv_timings_cap = ad9389b_dv_timings_cap,
 689};
 690
 691/* ------------------------------ AUDIO OPS ------------------------------ */
 692
 693static int ad9389b_s_audio_stream(struct v4l2_subdev *sd, int enable)
 694{
 695        v4l2_dbg(1, debug, sd, "%s: %sable\n", __func__, (enable ? "en" : "dis"));
 696
 697        if (enable)
 698                ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x80);
 699        else
 700                ad9389b_wr_and_or(sd, 0x45, 0x3f, 0x40);
 701
 702        return 0;
 703}
 704
 705static int ad9389b_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 706{
 707        u32 N;
 708
 709        switch (freq) {
 710        case 32000:  N = 4096;  break;
 711        case 44100:  N = 6272;  break;
 712        case 48000:  N = 6144;  break;
 713        case 88200:  N = 12544; break;
 714        case 96000:  N = 12288; break;
 715        case 176400: N = 25088; break;
 716        case 192000: N = 24576; break;
 717        default:
 718             return -EINVAL;
 719        }
 720
 721        /* Set N (used with CTS to regenerate the audio clock) */
 722        ad9389b_wr(sd, 0x01, (N >> 16) & 0xf);
 723        ad9389b_wr(sd, 0x02, (N >> 8) & 0xff);
 724        ad9389b_wr(sd, 0x03, N & 0xff);
 725
 726        return 0;
 727}
 728
 729static int ad9389b_s_i2s_clock_freq(struct v4l2_subdev *sd, u32 freq)
 730{
 731        u32 i2s_sf;
 732
 733        switch (freq) {
 734        case 32000:  i2s_sf = 0x30; break;
 735        case 44100:  i2s_sf = 0x00; break;
 736        case 48000:  i2s_sf = 0x20; break;
 737        case 88200:  i2s_sf = 0x80; break;
 738        case 96000:  i2s_sf = 0xa0; break;
 739        case 176400: i2s_sf = 0xc0; break;
 740        case 192000: i2s_sf = 0xe0; break;
 741        default:
 742             return -EINVAL;
 743        }
 744
 745        /* Set sampling frequency for I2S audio to 48 kHz */
 746        ad9389b_wr_and_or(sd, 0x15, 0xf, i2s_sf);
 747
 748        return 0;
 749}
 750
 751static int ad9389b_s_routing(struct v4l2_subdev *sd, u32 input, u32 output, u32 config)
 752{
 753        /* TODO based on input/output/config */
 754        /* TODO See datasheet "Programmers guide" p. 39-40 */
 755
 756        /* Only 2 channels in use for application */
 757        ad9389b_wr_and_or(sd, 0x50, 0x1f, 0x20);
 758        /* Speaker mapping */
 759        ad9389b_wr(sd, 0x51, 0x00);
 760
 761        /* TODO Where should this be placed? */
 762        /* 16 bit audio word length */
 763        ad9389b_wr_and_or(sd, 0x14, 0xf0, 0x02);
 764
 765        return 0;
 766}
 767
 768static const struct v4l2_subdev_audio_ops ad9389b_audio_ops = {
 769        .s_stream = ad9389b_s_audio_stream,
 770        .s_clock_freq = ad9389b_s_clock_freq,
 771        .s_i2s_clock_freq = ad9389b_s_i2s_clock_freq,
 772        .s_routing = ad9389b_s_routing,
 773};
 774
 775/* --------------------- SUBDEV OPS --------------------------------------- */
 776
 777static const struct v4l2_subdev_ops ad9389b_ops = {
 778        .core  = &ad9389b_core_ops,
 779        .video = &ad9389b_video_ops,
 780        .audio = &ad9389b_audio_ops,
 781        .pad = &ad9389b_pad_ops,
 782};
 783
 784/* ----------------------------------------------------------------------- */
 785static void ad9389b_dbg_dump_edid(int lvl, int debug, struct v4l2_subdev *sd,
 786                                  int segment, u8 *buf)
 787{
 788        int i, j;
 789
 790        if (debug < lvl)
 791                return;
 792
 793        v4l2_dbg(lvl, debug, sd, "edid segment %d\n", segment);
 794        for (i = 0; i < 256; i += 16) {
 795                u8 b[128];
 796                u8 *bp = b;
 797
 798                if (i == 128)
 799                        v4l2_dbg(lvl, debug, sd, "\n");
 800                for (j = i; j < i + 16; j++) {
 801                        sprintf(bp, "0x%02x, ", buf[j]);
 802                        bp += 6;
 803                }
 804                bp[0] = '\0';
 805                v4l2_dbg(lvl, debug, sd, "%s\n", b);
 806        }
 807}
 808
 809static void ad9389b_edid_handler(struct work_struct *work)
 810{
 811        struct delayed_work *dwork = to_delayed_work(work);
 812        struct ad9389b_state *state =
 813                container_of(dwork, struct ad9389b_state, edid_handler);
 814        struct v4l2_subdev *sd = &state->sd;
 815        struct ad9389b_edid_detect ed;
 816
 817        v4l2_dbg(1, debug, sd, "%s:\n", __func__);
 818
 819        if (ad9389b_check_edid_status(sd)) {
 820                /* Return if we received the EDID. */
 821                return;
 822        }
 823
 824        if (ad9389b_have_hotplug(sd)) {
 825                /* We must retry reading the EDID several times, it is possible
 826                 * that initially the EDID couldn't be read due to i2c errors
 827                 * (DVI connectors are particularly prone to this problem). */
 828                if (state->edid.read_retries) {
 829                        state->edid.read_retries--;
 830                        v4l2_dbg(1, debug, sd, "%s: edid read failed\n", __func__);
 831                        ad9389b_s_power(sd, false);
 832                        ad9389b_s_power(sd, true);
 833                        schedule_delayed_work(&state->edid_handler, EDID_DELAY);
 834                        return;
 835                }
 836        }
 837
 838        /* We failed to read the EDID, so send an event for this. */
 839        ed.present = false;
 840        ed.segment = ad9389b_rd(sd, 0xc4);
 841        v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
 842        v4l2_dbg(1, debug, sd, "%s: no edid found\n", __func__);
 843}
 844
 845static void ad9389b_audio_setup(struct v4l2_subdev *sd)
 846{
 847        v4l2_dbg(1, debug, sd, "%s\n", __func__);
 848
 849        ad9389b_s_i2s_clock_freq(sd, 48000);
 850        ad9389b_s_clock_freq(sd, 48000);
 851        ad9389b_s_routing(sd, 0, 0, 0);
 852}
 853
 854/* Initial setup of AD9389b */
 855
 856/* Configure hdmi transmitter. */
 857static void ad9389b_setup(struct v4l2_subdev *sd)
 858{
 859        struct ad9389b_state *state = get_ad9389b_state(sd);
 860
 861        v4l2_dbg(1, debug, sd, "%s\n", __func__);
 862
 863        /* Input format: RGB 4:4:4 */
 864        ad9389b_wr_and_or(sd, 0x15, 0xf1, 0x0);
 865        /* Output format: RGB 4:4:4 */
 866        ad9389b_wr_and_or(sd, 0x16, 0x3f, 0x0);
 867        /* 1st order interpolation 4:2:2 -> 4:4:4 up conversion,
 868           Aspect ratio: 16:9 */
 869        ad9389b_wr_and_or(sd, 0x17, 0xf9, 0x06);
 870        /* Output format: RGB 4:4:4, Active Format Information is valid. */
 871        ad9389b_wr_and_or(sd, 0x45, 0xc7, 0x08);
 872        /* Underscanned */
 873        ad9389b_wr_and_or(sd, 0x46, 0x3f, 0x80);
 874        /* Setup video format */
 875        ad9389b_wr(sd, 0x3c, 0x0);
 876        /* Active format aspect ratio: same as picure. */
 877        ad9389b_wr(sd, 0x47, 0x80);
 878        /* No encryption */
 879        ad9389b_wr_and_or(sd, 0xaf, 0xef, 0x0);
 880        /* Positive clk edge capture for input video clock */
 881        ad9389b_wr_and_or(sd, 0xba, 0x1f, 0x60);
 882
 883        ad9389b_audio_setup(sd);
 884
 885        v4l2_ctrl_handler_setup(&state->hdl);
 886
 887        ad9389b_set_IT_content_AVI_InfoFrame(sd);
 888}
 889
 890static void ad9389b_notify_monitor_detect(struct v4l2_subdev *sd)
 891{
 892        struct ad9389b_monitor_detect mdt;
 893        struct ad9389b_state *state = get_ad9389b_state(sd);
 894
 895        mdt.present = state->have_monitor;
 896        v4l2_subdev_notify(sd, AD9389B_MONITOR_DETECT, (void *)&mdt);
 897}
 898
 899static void ad9389b_update_monitor_present_status(struct v4l2_subdev *sd)
 900{
 901        struct ad9389b_state *state = get_ad9389b_state(sd);
 902        /* read hotplug and rx-sense state */
 903        u8 status = ad9389b_rd(sd, 0x42);
 904
 905        v4l2_dbg(1, debug, sd, "%s: status: 0x%x%s%s\n",
 906                 __func__,
 907                 status,
 908                 status & MASK_AD9389B_HPD_DETECT ? ", hotplug" : "",
 909                 status & MASK_AD9389B_MSEN_DETECT ? ", rx-sense" : "");
 910
 911        if (status & MASK_AD9389B_HPD_DETECT) {
 912                v4l2_dbg(1, debug, sd, "%s: hotplug detected\n", __func__);
 913                state->have_monitor = true;
 914                if (!ad9389b_s_power(sd, true)) {
 915                        v4l2_dbg(1, debug, sd,
 916                                 "%s: monitor detected, powerup failed\n", __func__);
 917                        return;
 918                }
 919                ad9389b_setup(sd);
 920                ad9389b_notify_monitor_detect(sd);
 921                state->edid.read_retries = EDID_MAX_RETRIES;
 922                schedule_delayed_work(&state->edid_handler, EDID_DELAY);
 923        } else if (!(status & MASK_AD9389B_HPD_DETECT)) {
 924                v4l2_dbg(1, debug, sd, "%s: hotplug not detected\n", __func__);
 925                state->have_monitor = false;
 926                ad9389b_notify_monitor_detect(sd);
 927                ad9389b_s_power(sd, false);
 928                memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
 929        }
 930
 931        /* update read only ctrls */
 932        v4l2_ctrl_s_ctrl(state->hotplug_ctrl, ad9389b_have_hotplug(sd) ? 0x1 : 0x0);
 933        v4l2_ctrl_s_ctrl(state->rx_sense_ctrl, ad9389b_have_rx_sense(sd) ? 0x1 : 0x0);
 934        v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
 935
 936        /* update with setting from ctrls */
 937        ad9389b_s_ctrl(state->rgb_quantization_range_ctrl);
 938        ad9389b_s_ctrl(state->hdmi_mode_ctrl);
 939}
 940
 941static void ad9389b_check_monitor_present_status(struct v4l2_subdev *sd)
 942{
 943        struct ad9389b_state *state = get_ad9389b_state(sd);
 944        int retry = 0;
 945
 946        ad9389b_update_monitor_present_status(sd);
 947
 948        /*
 949         * Rapid toggling of the hotplug may leave the chip powered off,
 950         * even if we think it is on. In that case reset and power up again.
 951         */
 952        while (state->power_on && (ad9389b_rd(sd, 0x41) & 0x40)) {
 953                if (++retry > 5) {
 954                        v4l2_err(sd, "retried %d times, give up\n", retry);
 955                        return;
 956                }
 957                v4l2_dbg(1, debug, sd, "%s: reset and re-check status (%d)\n", __func__, retry);
 958                ad9389b_notify_monitor_detect(sd);
 959                cancel_delayed_work_sync(&state->edid_handler);
 960                memset(&state->edid, 0, sizeof(struct ad9389b_state_edid));
 961                ad9389b_s_power(sd, false);
 962                ad9389b_update_monitor_present_status(sd);
 963        }
 964}
 965
 966static bool edid_block_verify_crc(u8 *edid_block)
 967{
 968        u8 sum = 0;
 969        int i;
 970
 971        for (i = 0; i < 128; i++)
 972                sum += edid_block[i];
 973        return sum == 0;
 974}
 975
 976static bool edid_verify_crc(struct v4l2_subdev *sd, u32 segment)
 977{
 978        struct ad9389b_state *state = get_ad9389b_state(sd);
 979        u32 blocks = state->edid.blocks;
 980        u8 *data = state->edid.data;
 981
 982        if (edid_block_verify_crc(&data[segment * 256])) {
 983                if ((segment + 1) * 2 <= blocks)
 984                        return edid_block_verify_crc(&data[segment * 256 + 128]);
 985                return true;
 986        }
 987        return false;
 988}
 989
 990static bool edid_verify_header(struct v4l2_subdev *sd, u32 segment)
 991{
 992        static const u8 hdmi_header[] = {
 993                0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00
 994        };
 995        struct ad9389b_state *state = get_ad9389b_state(sd);
 996        u8 *data = state->edid.data;
 997        int i;
 998
 999        if (segment)
1000                return true;
1001
1002        for (i = 0; i < ARRAY_SIZE(hdmi_header); i++)
1003                if (data[i] != hdmi_header[i])
1004                        return false;
1005
1006        return true;
1007}
1008
1009static bool ad9389b_check_edid_status(struct v4l2_subdev *sd)
1010{
1011        struct ad9389b_state *state = get_ad9389b_state(sd);
1012        struct ad9389b_edid_detect ed;
1013        int segment;
1014        u8 edidRdy = ad9389b_rd(sd, 0xc5);
1015
1016        v4l2_dbg(1, debug, sd, "%s: edid ready (retries: %d)\n",
1017                 __func__, EDID_MAX_RETRIES - state->edid.read_retries);
1018
1019        if (!(edidRdy & MASK_AD9389B_EDID_RDY))
1020                return false;
1021
1022        segment = ad9389b_rd(sd, 0xc4);
1023        if (segment >= EDID_MAX_SEGM) {
1024                v4l2_err(sd, "edid segment number too big\n");
1025                return false;
1026        }
1027        v4l2_dbg(1, debug, sd, "%s: got segment %d\n", __func__, segment);
1028        ad9389b_edid_rd(sd, 256, &state->edid.data[segment * 256]);
1029        ad9389b_dbg_dump_edid(2, debug, sd, segment,
1030                              &state->edid.data[segment * 256]);
1031        if (segment == 0) {
1032                state->edid.blocks = state->edid.data[0x7e] + 1;
1033                v4l2_dbg(1, debug, sd, "%s: %d blocks in total\n",
1034                         __func__, state->edid.blocks);
1035        }
1036        if (!edid_verify_crc(sd, segment) ||
1037            !edid_verify_header(sd, segment)) {
1038                /* edid crc error, force reread of edid segment */
1039                v4l2_err(sd, "%s: edid crc or header error\n", __func__);
1040                ad9389b_s_power(sd, false);
1041                ad9389b_s_power(sd, true);
1042                return false;
1043        }
1044        /* one more segment read ok */
1045        state->edid.segments = segment + 1;
1046        if (((state->edid.data[0x7e] >> 1) + 1) > state->edid.segments) {
1047                /* Request next EDID segment */
1048                v4l2_dbg(1, debug, sd, "%s: request segment %d\n",
1049                         __func__, state->edid.segments);
1050                ad9389b_wr(sd, 0xc9, 0xf);
1051                ad9389b_wr(sd, 0xc4, state->edid.segments);
1052                state->edid.read_retries = EDID_MAX_RETRIES;
1053                schedule_delayed_work(&state->edid_handler, EDID_DELAY);
1054                return false;
1055        }
1056
1057        /* report when we have all segments but report only for segment 0 */
1058        ed.present = true;
1059        ed.segment = 0;
1060        v4l2_subdev_notify(sd, AD9389B_EDID_DETECT, (void *)&ed);
1061        state->edid_detect_counter++;
1062        v4l2_ctrl_s_ctrl(state->have_edid0_ctrl, state->edid.segments ? 0x1 : 0x0);
1063        return ed.present;
1064}
1065
1066/* ----------------------------------------------------------------------- */
1067
1068static void ad9389b_init_setup(struct v4l2_subdev *sd)
1069{
1070        struct ad9389b_state *state = get_ad9389b_state(sd);
1071        struct ad9389b_state_edid *edid = &state->edid;
1072
1073        v4l2_dbg(1, debug, sd, "%s\n", __func__);
1074
1075        /* clear all interrupts */
1076        ad9389b_wr(sd, 0x96, 0xff);
1077
1078        memset(edid, 0, sizeof(struct ad9389b_state_edid));
1079        state->have_monitor = false;
1080        ad9389b_set_isr(sd, false);
1081}
1082
1083static int ad9389b_probe(struct i2c_client *client, const struct i2c_device_id *id)
1084{
1085        const struct v4l2_dv_timings dv1080p60 = V4L2_DV_BT_CEA_1920X1080P60;
1086        struct ad9389b_state *state;
1087        struct ad9389b_platform_data *pdata = client->dev.platform_data;
1088        struct v4l2_ctrl_handler *hdl;
1089        struct v4l2_subdev *sd;
1090        int err = -EIO;
1091
1092        /* Check if the adapter supports the needed features */
1093        if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1094                return -EIO;
1095
1096        v4l_dbg(1, debug, client, "detecting ad9389b client on address 0x%x\n",
1097                client->addr << 1);
1098
1099        state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1100        if (!state)
1101                return -ENOMEM;
1102
1103        /* Platform data */
1104        if (pdata == NULL) {
1105                v4l_err(client, "No platform data!\n");
1106                return -ENODEV;
1107        }
1108        memcpy(&state->pdata, pdata, sizeof(state->pdata));
1109
1110        sd = &state->sd;
1111        v4l2_i2c_subdev_init(sd, client, &ad9389b_ops);
1112        sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1113
1114        hdl = &state->hdl;
1115        v4l2_ctrl_handler_init(hdl, 5);
1116
1117        state->hdmi_mode_ctrl = v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1118                        V4L2_CID_DV_TX_MODE, V4L2_DV_TX_MODE_HDMI,
1119                        0, V4L2_DV_TX_MODE_DVI_D);
1120        state->hotplug_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1121                        V4L2_CID_DV_TX_HOTPLUG, 0, 1, 0, 0);
1122        state->rx_sense_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1123                        V4L2_CID_DV_TX_RXSENSE, 0, 1, 0, 0);
1124        state->have_edid0_ctrl = v4l2_ctrl_new_std(hdl, NULL,
1125                        V4L2_CID_DV_TX_EDID_PRESENT, 0, 1, 0, 0);
1126        state->rgb_quantization_range_ctrl =
1127                v4l2_ctrl_new_std_menu(hdl, &ad9389b_ctrl_ops,
1128                        V4L2_CID_DV_TX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
1129                        0, V4L2_DV_RGB_RANGE_AUTO);
1130        sd->ctrl_handler = hdl;
1131        if (hdl->error) {
1132                err = hdl->error;
1133
1134                goto err_hdl;
1135        }
1136        state->pad.flags = MEDIA_PAD_FL_SINK;
1137        sd->entity.function = MEDIA_ENT_F_DV_ENCODER;
1138        err = media_entity_pads_init(&sd->entity, 1, &state->pad);
1139        if (err)
1140                goto err_hdl;
1141
1142        state->chip_revision = ad9389b_rd(sd, 0x0);
1143        if (state->chip_revision != 2) {
1144                v4l2_err(sd, "chip_revision %d != 2\n", state->chip_revision);
1145                err = -EIO;
1146                goto err_entity;
1147        }
1148        v4l2_dbg(1, debug, sd, "reg 0x41 0x%x, chip version (reg 0x00) 0x%x\n",
1149                 ad9389b_rd(sd, 0x41), state->chip_revision);
1150
1151        state->edid_i2c_client = i2c_new_dummy(client->adapter, (0x7e>>1));
1152        if (state->edid_i2c_client == NULL) {
1153                v4l2_err(sd, "failed to register edid i2c client\n");
1154                err = -ENOMEM;
1155                goto err_entity;
1156        }
1157
1158        INIT_DELAYED_WORK(&state->edid_handler, ad9389b_edid_handler);
1159        state->dv_timings = dv1080p60;
1160
1161        ad9389b_init_setup(sd);
1162        ad9389b_set_isr(sd, true);
1163
1164        v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
1165                  client->addr << 1, client->adapter->name);
1166        return 0;
1167
1168err_entity:
1169        media_entity_cleanup(&sd->entity);
1170err_hdl:
1171        v4l2_ctrl_handler_free(&state->hdl);
1172        return err;
1173}
1174
1175/* ----------------------------------------------------------------------- */
1176
1177static int ad9389b_remove(struct i2c_client *client)
1178{
1179        struct v4l2_subdev *sd = i2c_get_clientdata(client);
1180        struct ad9389b_state *state = get_ad9389b_state(sd);
1181
1182        state->chip_revision = -1;
1183
1184        v4l2_dbg(1, debug, sd, "%s removed @ 0x%x (%s)\n", client->name,
1185                 client->addr << 1, client->adapter->name);
1186
1187        ad9389b_s_stream(sd, false);
1188        ad9389b_s_audio_stream(sd, false);
1189        ad9389b_init_setup(sd);
1190        cancel_delayed_work_sync(&state->edid_handler);
1191        i2c_unregister_device(state->edid_i2c_client);
1192        v4l2_device_unregister_subdev(sd);
1193        media_entity_cleanup(&sd->entity);
1194        v4l2_ctrl_handler_free(sd->ctrl_handler);
1195        return 0;
1196}
1197
1198/* ----------------------------------------------------------------------- */
1199
1200static const struct i2c_device_id ad9389b_id[] = {
1201        { "ad9389b", 0 },
1202        { "ad9889b", 0 },
1203        { }
1204};
1205MODULE_DEVICE_TABLE(i2c, ad9389b_id);
1206
1207static struct i2c_driver ad9389b_driver = {
1208        .driver = {
1209                .name = "ad9389b",
1210        },
1211        .probe = ad9389b_probe,
1212        .remove = ad9389b_remove,
1213        .id_table = ad9389b_id,
1214};
1215
1216module_i2c_driver(ad9389b_driver);
1217