LXR linux/drivers/net/dsa/mv88e6xxx/chip.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx Ethernet switch single-chip definition
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 */
   7
   8#ifndef _MV88E6XXX_CHIP_H
   9#define _MV88E6XXX_CHIP_H
  10
  11#include <linux/if_vlan.h>
  12#include <linux/irq.h>
  13#include <linux/gpio/consumer.h>
  14#include <linux/kthread.h>
  15#include <linux/phy.h>
  16#include <linux/ptp_clock_kernel.h>
  17#include <linux/timecounter.h>
  18#include <net/dsa.h>
  19
  20#define MV88E6XXX_N_FID         4096
  21
  22/* PVT limits for 4-bit port and 5-bit switch */
  23#define MV88E6XXX_MAX_PVT_SWITCHES      32
  24#define MV88E6XXX_MAX_PVT_PORTS         16
  25
  26#define MV88E6XXX_MAX_GPIO      16
  27
  28enum mv88e6xxx_egress_mode {
  29        MV88E6XXX_EGRESS_MODE_UNMODIFIED,
  30        MV88E6XXX_EGRESS_MODE_UNTAGGED,
  31        MV88E6XXX_EGRESS_MODE_TAGGED,
  32        MV88E6XXX_EGRESS_MODE_ETHERTYPE,
  33};
  34
  35enum mv88e6xxx_frame_mode {
  36        MV88E6XXX_FRAME_MODE_NORMAL,
  37        MV88E6XXX_FRAME_MODE_DSA,
  38        MV88E6XXX_FRAME_MODE_PROVIDER,
  39        MV88E6XXX_FRAME_MODE_ETHERTYPE,
  40};
  41
  42/* List of supported models */
  43enum mv88e6xxx_model {
  44        MV88E6085,
  45        MV88E6095,
  46        MV88E6097,
  47        MV88E6123,
  48        MV88E6131,
  49        MV88E6141,
  50        MV88E6161,
  51        MV88E6165,
  52        MV88E6171,
  53        MV88E6172,
  54        MV88E6175,
  55        MV88E6176,
  56        MV88E6185,
  57        MV88E6190,
  58        MV88E6190X,
  59        MV88E6191,
  60        MV88E6240,
  61        MV88E6290,
  62        MV88E6320,
  63        MV88E6321,
  64        MV88E6341,
  65        MV88E6350,
  66        MV88E6351,
  67        MV88E6352,
  68        MV88E6390,
  69        MV88E6390X,
  70};
  71
  72enum mv88e6xxx_family {
  73        MV88E6XXX_FAMILY_NONE,
  74        MV88E6XXX_FAMILY_6065,  /* 6031 6035 6061 6065 */
  75        MV88E6XXX_FAMILY_6095,  /* 6092 6095 */
  76        MV88E6XXX_FAMILY_6097,  /* 6046 6085 6096 6097 */
  77        MV88E6XXX_FAMILY_6165,  /* 6123 6161 6165 */
  78        MV88E6XXX_FAMILY_6185,  /* 6108 6121 6122 6131 6152 6155 6182 6185 */
  79        MV88E6XXX_FAMILY_6320,  /* 6320 6321 */
  80        MV88E6XXX_FAMILY_6341,  /* 6141 6341 */
  81        MV88E6XXX_FAMILY_6351,  /* 6171 6175 6350 6351 */
  82        MV88E6XXX_FAMILY_6352,  /* 6172 6176 6240 6352 */
  83        MV88E6XXX_FAMILY_6390,  /* 6190 6190X 6191 6290 6390 6390X */
  84};
  85
  86struct mv88e6xxx_ops;
  87
  88struct mv88e6xxx_info {
  89        enum mv88e6xxx_family family;
  90        u16 prod_num;
  91        const char *name;
  92        unsigned int num_databases;
  93        unsigned int num_ports;
  94        unsigned int num_internal_phys;
  95        unsigned int num_gpio;
  96        unsigned int max_vid;
  97        unsigned int port_base_addr;
  98        unsigned int phy_base_addr;
  99        unsigned int global1_addr;
 100        unsigned int global2_addr;
 101        unsigned int age_time_coeff;
 102        unsigned int g1_irqs;
 103        unsigned int g2_irqs;
 104        bool pvt;
 105
 106        /* Multi-chip Addressing Mode.
 107         * Some chips respond to only 2 registers of its own SMI device address
 108         * when it is non-zero, and use indirect access to internal registers.
 109         */
 110        bool multi_chip;
 111        enum dsa_tag_protocol tag_protocol;
 112
 113        /* Mask for FromPort and ToPort value of PortVec used in ATU Move
 114         * operation. 0 means that the ATU Move operation is not supported.
 115         */
 116        u8 atu_move_port_mask;
 117        const struct mv88e6xxx_ops *ops;
 118
 119        /* Supports PTP */
 120        bool ptp_support;
 121};
 122
 123struct mv88e6xxx_atu_entry {
 124        u8      state;
 125        bool    trunk;
 126        u16     portvec;
 127        u8      mac[ETH_ALEN];
 128};
 129
 130struct mv88e6xxx_vtu_entry {
 131        u16     vid;
 132        u16     fid;
 133        u8      sid;
 134        bool    valid;
 135        u8      member[DSA_MAX_PORTS];
 136        u8      state[DSA_MAX_PORTS];
 137};
 138
 139struct mv88e6xxx_bus_ops;
 140struct mv88e6xxx_irq_ops;
 141struct mv88e6xxx_gpio_ops;
 142struct mv88e6xxx_avb_ops;
 143struct mv88e6xxx_ptp_ops;
 144
 145struct mv88e6xxx_irq {
 146        u16 masked;
 147        struct irq_chip chip;
 148        struct irq_domain *domain;
 149        unsigned int nirqs;
 150};
 151
 152/* state flags for mv88e6xxx_port_hwtstamp::state */
 153enum {
 154        MV88E6XXX_HWTSTAMP_ENABLED,
 155        MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
 156};
 157
 158struct mv88e6xxx_port_hwtstamp {
 159        /* Port index */
 160        int port_id;
 161
 162        /* Timestamping state */
 163        unsigned long state;
 164
 165        /* Resources for receive timestamping */
 166        struct sk_buff_head rx_queue;
 167        struct sk_buff_head rx_queue2;
 168
 169        /* Resources for transmit timestamping */
 170        unsigned long tx_tstamp_start;
 171        struct sk_buff *tx_skb;
 172        u16 tx_seq_id;
 173
 174        /* Current timestamp configuration */
 175        struct hwtstamp_config tstamp_config;
 176};
 177
 178struct mv88e6xxx_port {
 179        struct mv88e6xxx_chip *chip;
 180        int port;
 181        u64 serdes_stats[2];
 182        u64 atu_member_violation;
 183        u64 atu_miss_violation;
 184        u64 atu_full_violation;
 185        u64 vtu_member_violation;
 186        u64 vtu_miss_violation;
 187        u8 cmode;
 188        int serdes_irq;
 189};
 190
 191struct mv88e6xxx_chip {
 192        const struct mv88e6xxx_info *info;
 193
 194        /* The dsa_switch this private structure is related to */
 195        struct dsa_switch *ds;
 196
 197        /* The device this structure is associated to */
 198        struct device *dev;
 199
 200        /* This mutex protects the access to the switch registers */
 201        struct mutex reg_lock;
 202
 203        /* The MII bus and the address on the bus that is used to
 204         * communication with the switch
 205         */
 206        const struct mv88e6xxx_bus_ops *smi_ops;
 207        struct mii_bus *bus;
 208        int sw_addr;
 209
 210        /* Handles automatic disabling and re-enabling of the PHY
 211         * polling unit.
 212         */
 213        const struct mv88e6xxx_bus_ops *phy_ops;
 214        struct mutex            ppu_mutex;
 215        int                     ppu_disabled;
 216        struct work_struct      ppu_work;
 217        struct timer_list       ppu_timer;
 218
 219        /* This mutex serialises access to the statistics unit.
 220         * Hold this mutex over snapshot + dump sequences.
 221         */
 222        struct mutex    stats_mutex;
 223
 224        /* A switch may have a GPIO line tied to its reset pin. Parse
 225         * this from the device tree, and use it before performing
 226         * switch soft reset.
 227         */
 228        struct gpio_desc *reset;
 229
 230        /* set to size of eeprom if supported by the switch */
 231        u32 eeprom_len;
 232
 233        /* List of mdio busses */
 234        struct list_head mdios;
 235
 236        /* There can be two interrupt controllers, which are chained
 237         * off a GPIO as interrupt source
 238         */
 239        struct mv88e6xxx_irq g1_irq;
 240        struct mv88e6xxx_irq g2_irq;
 241        int irq;
 242        int device_irq;
 243        int watchdog_irq;
 244
 245        int atu_prob_irq;
 246        int vtu_prob_irq;
 247        struct kthread_worker *kworker;
 248        struct kthread_delayed_work irq_poll_work;
 249
 250        /* GPIO resources */
 251        u8 gpio_data[2];
 252
 253        /* This cyclecounter abstracts the switch PTP time.
 254         * reg_lock must be held for any operation that read()s.
 255         */
 256        struct cyclecounter     tstamp_cc;
 257        struct timecounter      tstamp_tc;
 258        struct delayed_work     overflow_work;
 259
 260        struct ptp_clock        *ptp_clock;
 261        struct ptp_clock_info   ptp_clock_info;
 262        struct delayed_work     tai_event_work;
 263        struct ptp_pin_desc     pin_config[MV88E6XXX_MAX_GPIO];
 264        u16 trig_config;
 265        u16 evcap_config;
 266        u16 enable_count;
 267
 268        /* Per-port timestamping resources. */
 269        struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
 270
 271        /* Array of port structures. */
 272        struct mv88e6xxx_port ports[DSA_MAX_PORTS];
 273};
 274
 275struct mv88e6xxx_bus_ops {
 276        int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 277        int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 278};
 279
 280struct mv88e6xxx_mdio_bus {
 281        struct mii_bus *bus;
 282        struct mv88e6xxx_chip *chip;
 283        struct list_head list;
 284        bool external;
 285};
 286
 287struct mv88e6xxx_ops {
 288        /* Switch Setup Errata, called early in the switch setup to
 289         * allow any errata actions to be performed
 290         */
 291        int (*setup_errata)(struct mv88e6xxx_chip *chip);
 292
 293        int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
 294        int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
 295
 296        /* Ingress Rate Limit unit (IRL) operations */
 297        int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
 298
 299        int (*get_eeprom)(struct mv88e6xxx_chip *chip,
 300                          struct ethtool_eeprom *eeprom, u8 *data);
 301        int (*set_eeprom)(struct mv88e6xxx_chip *chip,
 302                          struct ethtool_eeprom *eeprom, u8 *data);
 303
 304        int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
 305
 306        int (*phy_read)(struct mv88e6xxx_chip *chip,
 307                        struct mii_bus *bus,
 308                        int addr, int reg, u16 *val);
 309        int (*phy_write)(struct mv88e6xxx_chip *chip,
 310                         struct mii_bus *bus,
 311                         int addr, int reg, u16 val);
 312
 313        /* Priority Override Table operations */
 314        int (*pot_clear)(struct mv88e6xxx_chip *chip);
 315
 316        /* PHY Polling Unit (PPU) operations */
 317        int (*ppu_enable)(struct mv88e6xxx_chip *chip);
 318        int (*ppu_disable)(struct mv88e6xxx_chip *chip);
 319
 320        /* Switch Software Reset */
 321        int (*reset)(struct mv88e6xxx_chip *chip);
 322
 323        /* RGMII Receive/Transmit Timing Control
 324         * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
 325         */
 326        int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
 327                                    phy_interface_t mode);
 328
 329#define LINK_FORCED_DOWN        0
 330#define LINK_FORCED_UP          1
 331#define LINK_UNFORCED           -2
 332
 333        /* Port's MAC link state
 334         * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
 335         * or LINK_UNFORCED for normal link detection.
 336         */
 337        int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
 338
 339#define DUPLEX_UNFORCED         -2
 340
 341        /* Port's MAC duplex mode
 342         *
 343         * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
 344         * or DUPLEX_UNFORCED for normal duplex detection.
 345         */
 346        int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
 347
 348#define PAUSE_ON                1
 349#define PAUSE_OFF               0
 350
 351        /* Enable/disable sending Pause */
 352        int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
 353                              int pause);
 354
 355#define SPEED_MAX               INT_MAX
 356#define SPEED_UNFORCED          -2
 357
 358        /* Port's MAC speed (in Mbps)
 359         *
 360         * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
 361         * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
 362         */
 363        int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
 364
 365        /* What interface mode should be used for maximum speed? */
 366        phy_interface_t (*port_max_speed_mode)(int port);
 367
 368        int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
 369
 370        int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
 371                                   enum mv88e6xxx_frame_mode mode);
 372        int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
 373                                      bool unicast, bool multicast);
 374        int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
 375                                   u16 etype);
 376        int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
 377                                   size_t size);
 378
 379        int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
 380        int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
 381                                u8 out);
 382        int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
 383        int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
 384
 385        /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
 386         * Some chips allow this to be configured on specific ports.
 387         */
 388        int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
 389                              phy_interface_t mode);
 390        int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 391
 392        /* Some devices have a per port register indicating what is
 393         * the upstream port this port should forward to.
 394         */
 395        int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
 396                                      int upstream_port);
 397        /* Return the port link state, as required by phylink */
 398        int (*port_link_state)(struct mv88e6xxx_chip *chip, int port,
 399                               struct phylink_link_state *state);
 400
 401        /* Snapshot the statistics for a port. The statistics can then
 402         * be read back a leisure but still with a consistent view.
 403         */
 404        int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
 405
 406        /* Set the histogram mode for statistics, when the control registers
 407         * are separated out of the STATS_OP register.
 408         */
 409        int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
 410
 411        /* Return the number of strings describing statistics */
 412        int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
 413        int (*stats_get_strings)(struct mv88e6xxx_chip *chip,  uint8_t *data);
 414        int (*stats_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 415                               uint64_t *data);
 416        int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
 417        int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
 418
 419#define MV88E6XXX_CASCADE_PORT_NONE             0xe
 420#define MV88E6XXX_CASCADE_PORT_MULTIPLE         0xf
 421
 422        int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
 423
 424        const struct mv88e6xxx_irq_ops *watchdog_ops;
 425
 426        int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
 427
 428        /* Power on/off a SERDES interface */
 429        int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
 430
 431        /* SERDES interrupt handling */
 432        int (*serdes_irq_setup)(struct mv88e6xxx_chip *chip, int port);
 433        void (*serdes_irq_free)(struct mv88e6xxx_chip *chip, int port);
 434
 435        /* Statistics from the SERDES interface */
 436        int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
 437        int (*serdes_get_strings)(struct mv88e6xxx_chip *chip,  int port,
 438                                  uint8_t *data);
 439        int (*serdes_get_stats)(struct mv88e6xxx_chip *chip,  int port,
 440                                uint64_t *data);
 441
 442        /* VLAN Translation Unit operations */
 443        int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
 444                           struct mv88e6xxx_vtu_entry *entry);
 445        int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
 446                             struct mv88e6xxx_vtu_entry *entry);
 447
 448        /* GPIO operations */
 449        const struct mv88e6xxx_gpio_ops *gpio_ops;
 450
 451        /* Interface to the AVB/PTP registers */
 452        const struct mv88e6xxx_avb_ops *avb_ops;
 453
 454        /* Remote Management Unit operations */
 455        int (*rmu_disable)(struct mv88e6xxx_chip *chip);
 456
 457        /* Precision Time Protocol operations */
 458        const struct mv88e6xxx_ptp_ops *ptp_ops;
 459
 460        /* Phylink */
 461        void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
 462                                 unsigned long *mask,
 463                                 struct phylink_link_state *state);
 464};
 465
 466struct mv88e6xxx_irq_ops {
 467        /* Action to be performed when the interrupt happens */
 468        int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
 469        /* Setup the hardware to generate the interrupt */
 470        int (*irq_setup)(struct mv88e6xxx_chip *chip);
 471        /* Reset the hardware to stop generating the interrupt */
 472        void (*irq_free)(struct mv88e6xxx_chip *chip);
 473};
 474
 475struct mv88e6xxx_gpio_ops {
 476        /* Get/set data on GPIO pin */
 477        int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
 478        int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
 479                        int value);
 480
 481        /* get/set GPIO direction */
 482        int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
 483        int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
 484                       bool input);
 485
 486        /* get/set GPIO pin control */
 487        int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 488                        int *func);
 489        int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
 490                        int func);
 491};
 492
 493struct mv88e6xxx_avb_ops {
 494        /* Access port-scoped Precision Time Protocol registers */
 495        int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
 496                             u16 *data, int len);
 497        int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
 498                              u16 data);
 499
 500        /* Access global Precision Time Protocol registers */
 501        int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 502                        int len);
 503        int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 504
 505        /* Access global Time Application Interface registers */
 506        int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
 507                        int len);
 508        int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
 509};
 510
 511struct mv88e6xxx_ptp_ops {
 512        u64 (*clock_read)(const struct cyclecounter *cc);
 513        int (*ptp_enable)(struct ptp_clock_info *ptp,
 514                          struct ptp_clock_request *rq, int on);
 515        int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
 516                          enum ptp_pin_function func, unsigned int chan);
 517        void (*event_work)(struct work_struct *ugly);
 518        int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
 519        int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
 520        int (*global_enable)(struct mv88e6xxx_chip *chip);
 521        int (*global_disable)(struct mv88e6xxx_chip *chip);
 522        int n_ext_ts;
 523        int arr0_sts_reg;
 524        int arr1_sts_reg;
 525        int dep_sts_reg;
 526        u32 rx_filters;
 527};
 528
 529#define STATS_TYPE_PORT         BIT(0)
 530#define STATS_TYPE_BANK0        BIT(1)
 531#define STATS_TYPE_BANK1        BIT(2)
 532
 533struct mv88e6xxx_hw_stat {
 534        char string[ETH_GSTRING_LEN];
 535        size_t size;
 536        int reg;
 537        int type;
 538};
 539
 540static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
 541{
 542        return chip->info->pvt;
 543}
 544
 545static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
 546{
 547        return chip->info->num_databases;
 548}
 549
 550static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
 551{
 552        return chip->info->num_ports;
 553}
 554
 555static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
 556{
 557        return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
 558}
 559
 560static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
 561{
 562        return chip->info->num_gpio;
 563}
 564
 565int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
 566int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
 567int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
 568                     u16 update);
 569int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
 570int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link,
 571                             int speed, int duplex, int pause,
 572                             phy_interface_t mode);
 573struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
 574
 575#endif /* _MV88E6XXX_CHIP_H */
 576