LXR linux/drivers/net/dsa/mv88e6xxx/port.h

   1/* SPDX-License-Identifier: GPL-2.0-or-later */
   2/*
   3 * Marvell 88E6xxx Switch Port Registers support
   4 *
   5 * Copyright (c) 2008 Marvell Semiconductor
   6 *
   7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
   8 *      Vivien Didelot <vivien.didelot@savoirfairelinux.com>
   9 */
  10
  11#ifndef _MV88E6XXX_PORT_H
  12#define _MV88E6XXX_PORT_H
  13
  14#include "chip.h"
  15
  16/* Offset 0x00: Port Status Register */
  17#define MV88E6XXX_PORT_STS                      0x00
  18#define MV88E6XXX_PORT_STS_PAUSE_EN             0x8000
  19#define MV88E6XXX_PORT_STS_MY_PAUSE             0x4000
  20#define MV88E6XXX_PORT_STS_HD_FLOW              0x2000
  21#define MV88E6XXX_PORT_STS_PHY_DETECT           0x1000
  22#define MV88E6XXX_PORT_STS_LINK                 0x0800
  23#define MV88E6XXX_PORT_STS_DUPLEX               0x0400
  24#define MV88E6XXX_PORT_STS_SPEED_MASK           0x0300
  25#define MV88E6XXX_PORT_STS_SPEED_10             0x0000
  26#define MV88E6XXX_PORT_STS_SPEED_100            0x0100
  27#define MV88E6XXX_PORT_STS_SPEED_1000           0x0200
  28#define MV88E6XXX_PORT_STS_SPEED_10000          0x0300
  29#define MV88E6352_PORT_STS_EEE                  0x0040
  30#define MV88E6165_PORT_STS_AM_DIS               0x0040
  31#define MV88E6185_PORT_STS_MGMII                0x0040
  32#define MV88E6XXX_PORT_STS_TX_PAUSED            0x0020
  33#define MV88E6XXX_PORT_STS_FLOW_CTL             0x0010
  34#define MV88E6XXX_PORT_STS_CMODE_MASK           0x000f
  35#define MV88E6XXX_PORT_STS_CMODE_100BASE_X      0x0008
  36#define MV88E6XXX_PORT_STS_CMODE_1000BASE_X     0x0009
  37#define MV88E6XXX_PORT_STS_CMODE_SGMII          0x000a
  38#define MV88E6XXX_PORT_STS_CMODE_2500BASEX      0x000b
  39#define MV88E6XXX_PORT_STS_CMODE_XAUI           0x000c
  40#define MV88E6XXX_PORT_STS_CMODE_RXAUI          0x000d
  41#define MV88E6185_PORT_STS_CDUPLEX              0x0008
  42#define MV88E6185_PORT_STS_CMODE_MASK           0x0007
  43#define MV88E6185_PORT_STS_CMODE_GMII_FD        0x0000
  44#define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS  0x0001
  45#define MV88E6185_PORT_STS_CMODE_MII_100        0x0002
  46#define MV88E6185_PORT_STS_CMODE_MII_10         0x0003
  47#define MV88E6185_PORT_STS_CMODE_SERDES         0x0004
  48#define MV88E6185_PORT_STS_CMODE_1000BASE_X     0x0005
  49#define MV88E6185_PORT_STS_CMODE_PHY            0x0006
  50#define MV88E6185_PORT_STS_CMODE_DISABLED       0x0007
  51
  52/* Offset 0x01: MAC (or PCS or Physical) Control Register */
  53#define MV88E6XXX_PORT_MAC_CTL                          0x01
  54#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK        0x8000
  55#define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK        0x4000
  56#define MV88E6185_PORT_MAC_CTL_SYNC_OK                  0x4000
  57#define MV88E6390_PORT_MAC_CTL_FORCE_SPEED              0x2000
  58#define MV88E6390_PORT_MAC_CTL_ALTSPEED                 0x1000
  59#define MV88E6352_PORT_MAC_CTL_200BASE                  0x1000
  60#define MV88E6185_PORT_MAC_CTL_AN_EN                    0x0400
  61#define MV88E6185_PORT_MAC_CTL_AN_RESTART               0x0200
  62#define MV88E6185_PORT_MAC_CTL_AN_DONE                  0x0100
  63#define MV88E6XXX_PORT_MAC_CTL_FC                       0x0080
  64#define MV88E6XXX_PORT_MAC_CTL_FORCE_FC                 0x0040
  65#define MV88E6XXX_PORT_MAC_CTL_LINK_UP                  0x0020
  66#define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK               0x0010
  67#define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL              0x0008
  68#define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX             0x0004
  69#define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK               0x0003
  70#define MV88E6XXX_PORT_MAC_CTL_SPEED_10                 0x0000
  71#define MV88E6XXX_PORT_MAC_CTL_SPEED_100                0x0001
  72#define MV88E6065_PORT_MAC_CTL_SPEED_200                0x0002
  73#define MV88E6XXX_PORT_MAC_CTL_SPEED_1000               0x0002
  74#define MV88E6390_PORT_MAC_CTL_SPEED_10000              0x0003
  75#define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED           0x0003
  76
  77/* Offset 0x02: Jamming Control Register */
  78#define MV88E6097_PORT_JAM_CTL                  0x02
  79#define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK   0xff00
  80#define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK    0x00ff
  81
  82/* Offset 0x02: Flow Control Register */
  83#define MV88E6390_PORT_FLOW_CTL                 0x02
  84#define MV88E6390_PORT_FLOW_CTL_UPDATE          0x8000
  85#define MV88E6390_PORT_FLOW_CTL_PTR_MASK        0x7f00
  86#define MV88E6390_PORT_FLOW_CTL_LIMIT_IN        0x0000
  87#define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT       0x0100
  88#define MV88E6390_PORT_FLOW_CTL_DATA_MASK       0x00ff
  89
  90/* Offset 0x03: Switch Identifier Register */
  91#define MV88E6XXX_PORT_SWITCH_ID                0x03
  92#define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK      0xfff0
  93#define MV88E6XXX_PORT_SWITCH_ID_PROD_6085      0x04a0
  94#define MV88E6XXX_PORT_SWITCH_ID_PROD_6095      0x0950
  95#define MV88E6XXX_PORT_SWITCH_ID_PROD_6097      0x0990
  96#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X     0x0a00
  97#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X     0x0a10
  98#define MV88E6XXX_PORT_SWITCH_ID_PROD_6131      0x1060
  99#define MV88E6XXX_PORT_SWITCH_ID_PROD_6320      0x1150
 100#define MV88E6XXX_PORT_SWITCH_ID_PROD_6123      0x1210
 101#define MV88E6XXX_PORT_SWITCH_ID_PROD_6161      0x1610
 102#define MV88E6XXX_PORT_SWITCH_ID_PROD_6165      0x1650
 103#define MV88E6XXX_PORT_SWITCH_ID_PROD_6171      0x1710
 104#define MV88E6XXX_PORT_SWITCH_ID_PROD_6172      0x1720
 105#define MV88E6XXX_PORT_SWITCH_ID_PROD_6175      0x1750
 106#define MV88E6XXX_PORT_SWITCH_ID_PROD_6176      0x1760
 107#define MV88E6XXX_PORT_SWITCH_ID_PROD_6190      0x1900
 108#define MV88E6XXX_PORT_SWITCH_ID_PROD_6191      0x1910
 109#define MV88E6XXX_PORT_SWITCH_ID_PROD_6185      0x1a70
 110#define MV88E6XXX_PORT_SWITCH_ID_PROD_6240      0x2400
 111#define MV88E6XXX_PORT_SWITCH_ID_PROD_6290      0x2900
 112#define MV88E6XXX_PORT_SWITCH_ID_PROD_6321      0x3100
 113#define MV88E6XXX_PORT_SWITCH_ID_PROD_6141      0x3400
 114#define MV88E6XXX_PORT_SWITCH_ID_PROD_6341      0x3410
 115#define MV88E6XXX_PORT_SWITCH_ID_PROD_6352      0x3520
 116#define MV88E6XXX_PORT_SWITCH_ID_PROD_6350      0x3710
 117#define MV88E6XXX_PORT_SWITCH_ID_PROD_6351      0x3750
 118#define MV88E6XXX_PORT_SWITCH_ID_PROD_6390      0x3900
 119#define MV88E6XXX_PORT_SWITCH_ID_REV_MASK       0x000f
 120
 121/* Offset 0x04: Port Control Register */
 122#define MV88E6XXX_PORT_CTL0                                     0x04
 123#define MV88E6XXX_PORT_CTL0_USE_CORE_TAG                        0x8000
 124#define MV88E6XXX_PORT_CTL0_DROP_ON_LOCK                        0x4000
 125#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK                    0x3000
 126#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED              0x0000
 127#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED                0x1000
 128#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED                  0x2000
 129#define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA          0x3000
 130#define MV88E6XXX_PORT_CTL0_HEADER                              0x0800
 131#define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP                      0x0400
 132#define MV88E6XXX_PORT_CTL0_DOUBLE_TAG                          0x0200
 133#define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK                     0x0300
 134#define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL                   0x0000
 135#define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA                      0x0100
 136#define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER                 0x0200
 137#define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA           0x0300
 138#define MV88E6XXX_PORT_CTL0_DSA_TAG                             0x0100
 139#define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL                         0x0080
 140#define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH                         0x0040
 141#define MV88E6185_PORT_CTL0_USE_IP                              0x0020
 142#define MV88E6185_PORT_CTL0_USE_TAG                             0x0010
 143#define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN                     0x0004
 144#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK                  0x000c
 145#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA         0x0000
 146#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA      0x0004
 147#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA      0x0008
 148#define MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA        0x000c
 149#define MV88E6XXX_PORT_CTL0_STATE_MASK                          0x0003
 150#define MV88E6XXX_PORT_CTL0_STATE_DISABLED                      0x0000
 151#define MV88E6XXX_PORT_CTL0_STATE_BLOCKING                      0x0001
 152#define MV88E6XXX_PORT_CTL0_STATE_LEARNING                      0x0002
 153#define MV88E6XXX_PORT_CTL0_STATE_FORWARDING                    0x0003
 154
 155/* Offset 0x05: Port Control 1 */
 156#define MV88E6XXX_PORT_CTL1                     0x05
 157#define MV88E6XXX_PORT_CTL1_MESSAGE_PORT        0x8000
 158#define MV88E6XXX_PORT_CTL1_FID_11_4_MASK       0x00ff
 159
 160/* Offset 0x06: Port Based VLAN Map */
 161#define MV88E6XXX_PORT_BASE_VLAN                0x06
 162#define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK   0xf000
 163
 164/* Offset 0x07: Default Port VLAN ID & Priority */
 165#define MV88E6XXX_PORT_DEFAULT_VLAN             0x07
 166#define MV88E6XXX_PORT_DEFAULT_VLAN_MASK        0x0fff
 167
 168/* Offset 0x08: Port Control 2 Register */
 169#define MV88E6XXX_PORT_CTL2                             0x08
 170#define MV88E6XXX_PORT_CTL2_IGNORE_FCS                  0x8000
 171#define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE            0x4000
 172#define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE            0x2000
 173#define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE            0x1000
 174#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK             0x3000
 175#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522             0x0000
 176#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048             0x1000
 177#define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240            0x2000
 178#define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK             0x0c00
 179#define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED         0x0000
 180#define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK         0x0400
 181#define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK            0x0800
 182#define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE           0x0c00
 183#define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED              0x0200
 184#define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED            0x0100
 185#define MV88E6XXX_PORT_CTL2_MAP_DA                      0x0080
 186#define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD             0x0040
 187#define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR              0x0020
 188#define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR             0x0010
 189#define MV88E6095_PORT_CTL2_CPU_PORT_MASK               0x000f
 190
 191/* Offset 0x09: Egress Rate Control */
 192#define MV88E6XXX_PORT_EGRESS_RATE_CTL1         0x09
 193
 194/* Offset 0x0A: Egress Rate Control 2 */
 195#define MV88E6XXX_PORT_EGRESS_RATE_CTL2         0x0a
 196
 197/* Offset 0x0B: Port Association Vector */
 198#define MV88E6XXX_PORT_ASSOC_VECTOR                     0x0b
 199#define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1           0x8000
 200#define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT         0x4000
 201#define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT         0x2000
 202#define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG        0x1000
 203#define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED      0x0800
 204
 205/* Offset 0x0C: Port ATU Control */
 206#define MV88E6XXX_PORT_ATU_CTL          0x0c
 207
 208/* Offset 0x0D: Priority Override Register */
 209#define MV88E6XXX_PORT_PRI_OVERRIDE     0x0d
 210
 211/* Offset 0x0E: Policy Control Register */
 212#define MV88E6XXX_PORT_POLICY_CTL       0x0e
 213
 214/* Offset 0x0F: Port Special Ether Type */
 215#define MV88E6XXX_PORT_ETH_TYPE         0x0f
 216#define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100
 217
 218/* Offset 0x10: InDiscards Low Counter */
 219#define MV88E6XXX_PORT_IN_DISCARD_LO    0x10
 220
 221/* Offset 0x11: InDiscards High Counter */
 222#define MV88E6XXX_PORT_IN_DISCARD_HI    0x11
 223
 224/* Offset 0x12: InFiltered Counter */
 225#define MV88E6XXX_PORT_IN_FILTERED      0x12
 226
 227/* Offset 0x13: OutFiltered Counter */
 228#define MV88E6XXX_PORT_OUT_FILTERED     0x13
 229
 230/* Offset 0x18: IEEE Priority Mapping Table */
 231#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE                      0x18
 232#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE               0x8000
 233#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK                 0x7000
 234#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP          0x0000
 235#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP     0x1000
 236#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP    0x2000
 237#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP       0x3000
 238#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP    0x5000
 239#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP   0x6000
 240#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP      0x7000
 241#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK             0x0e00
 242#define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK            0x01ff
 243
 244/* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */
 245#define MV88E6095_PORT_IEEE_PRIO_REMAP_0123     0x18
 246
 247/* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */
 248#define MV88E6095_PORT_IEEE_PRIO_REMAP_4567     0x19
 249
 250/* Offset 0x1a: Magic undocumented errata register */
 251#define PORT_RESERVED_1A                        0x1a
 252#define PORT_RESERVED_1A_BUSY                   BIT(15)
 253#define PORT_RESERVED_1A_WRITE                  BIT(14)
 254#define PORT_RESERVED_1A_READ                   0
 255#define PORT_RESERVED_1A_PORT_SHIFT             5
 256#define PORT_RESERVED_1A_BLOCK                  (0xf << 10)
 257#define PORT_RESERVED_1A_CTRL_PORT              4
 258#define PORT_RESERVED_1A_DATA_PORT              5
 259
 260int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg,
 261                        u16 *val);
 262int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg,
 263                         u16 val);
 264
 265int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port,
 266                             int pause);
 267int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 268                                   phy_interface_t mode);
 269int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port,
 270                                   phy_interface_t mode);
 271
 272int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link);
 273
 274int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip *chip, int port, int dup);
 275
 276int mv88e6065_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 277int mv88e6185_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 278int mv88e6341_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 279int mv88e6352_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 280int mv88e6390_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 281int mv88e6390x_port_set_speed(struct mv88e6xxx_chip *chip, int port, int speed);
 282
 283phy_interface_t mv88e6341_port_max_speed_mode(int port);
 284phy_interface_t mv88e6390_port_max_speed_mode(int port);
 285phy_interface_t mv88e6390x_port_max_speed_mode(int port);
 286
 287int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state);
 288
 289int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map);
 290
 291int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid);
 292int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid);
 293
 294int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid);
 295int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid);
 296
 297int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port,
 298                                  u16 mode);
 299int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
 300int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port);
 301int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port,
 302                                   enum mv88e6xxx_egress_mode mode);
 303int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 304                                  enum mv88e6xxx_frame_mode mode);
 305int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port,
 306                                  enum mv88e6xxx_frame_mode mode);
 307int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 308                                     bool unicast, bool multicast);
 309int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip *chip, int port,
 310                                     bool unicast, bool multicast);
 311int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port,
 312                                  u16 etype);
 313int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port,
 314                                    bool message_port);
 315int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port,
 316                                  size_t size);
 317int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
 318int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port);
 319int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 320                               u8 out);
 321int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in,
 322                               u8 out);
 323int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 324                             phy_interface_t mode);
 325int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port,
 326                              phy_interface_t mode);
 327int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 328int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
 329int mv88e6185_port_link_state(struct mv88e6xxx_chip *chip, int port,
 330                              struct phylink_link_state *state);
 331int mv88e6352_port_link_state(struct mv88e6xxx_chip *chip, int port,
 332                              struct phylink_link_state *state);
 333int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port);
 334int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port,
 335                                     int upstream_port);
 336
 337int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port);
 338int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port);
 339
 340#endif /* _MV88E6XXX_PORT_H */
 341