1
2
3
4
5
6
7#include <linux/init.h>
8#include <linux/interrupt.h>
9#include <linux/module.h>
10#include <linux/clk.h>
11#include <linux/etherdevice.h>
12#include <linux/slab.h>
13#include <linux/delay.h>
14#include <linux/ethtool.h>
15#include <linux/crc32.h>
16#include <linux/err.h>
17#include <linux/dma-mapping.h>
18#include <linux/platform_device.h>
19#include <linux/if_vlan.h>
20
21#include <bcm63xx_dev_enet.h>
22#include "bcm63xx_enet.h"
23
24static char bcm_enet_driver_name[] = "bcm63xx_enet";
25static char bcm_enet_driver_version[] = "1.0";
26
27static int copybreak __read_mostly = 128;
28module_param(copybreak, int, 0);
29MODULE_PARM_DESC(copybreak, "Receive copy threshold");
30
31
32static void __iomem *bcm_enet_shared_base[3];
33
34
35
36
37static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off)
38{
39 return bcm_readl(priv->base + off);
40}
41
42static inline void enet_writel(struct bcm_enet_priv *priv,
43 u32 val, u32 off)
44{
45 bcm_writel(val, priv->base + off);
46}
47
48
49
50
51static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
52{
53 return bcm_readl(priv->base + off);
54}
55
56static inline void enetsw_writel(struct bcm_enet_priv *priv,
57 u32 val, u32 off)
58{
59 bcm_writel(val, priv->base + off);
60}
61
62static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
63{
64 return bcm_readw(priv->base + off);
65}
66
67static inline void enetsw_writew(struct bcm_enet_priv *priv,
68 u16 val, u32 off)
69{
70 bcm_writew(val, priv->base + off);
71}
72
73static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
74{
75 return bcm_readb(priv->base + off);
76}
77
78static inline void enetsw_writeb(struct bcm_enet_priv *priv,
79 u8 val, u32 off)
80{
81 bcm_writeb(val, priv->base + off);
82}
83
84
85
86static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
87{
88 return bcm_readl(bcm_enet_shared_base[0] + off);
89}
90
91static inline void enet_dma_writel(struct bcm_enet_priv *priv,
92 u32 val, u32 off)
93{
94 bcm_writel(val, bcm_enet_shared_base[0] + off);
95}
96
97static inline u32 enet_dmac_readl(struct bcm_enet_priv *priv, u32 off, int chan)
98{
99 return bcm_readl(bcm_enet_shared_base[1] +
100 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
101}
102
103static inline void enet_dmac_writel(struct bcm_enet_priv *priv,
104 u32 val, u32 off, int chan)
105{
106 bcm_writel(val, bcm_enet_shared_base[1] +
107 bcm63xx_enetdmacreg(off) + chan * priv->dma_chan_width);
108}
109
110static inline u32 enet_dmas_readl(struct bcm_enet_priv *priv, u32 off, int chan)
111{
112 return bcm_readl(bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
113}
114
115static inline void enet_dmas_writel(struct bcm_enet_priv *priv,
116 u32 val, u32 off, int chan)
117{
118 bcm_writel(val, bcm_enet_shared_base[2] + off + chan * priv->dma_chan_width);
119}
120
121
122
123
124
125static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data)
126{
127 int limit;
128
129
130 enet_writel(priv, ENET_IR_MII, ENET_IR_REG);
131
132 enet_writel(priv, data, ENET_MIIDATA_REG);
133 wmb();
134
135
136 limit = 1000;
137 do {
138 if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII)
139 break;
140 udelay(1);
141 } while (limit-- > 0);
142
143 return (limit < 0) ? 1 : 0;
144}
145
146
147
148
149static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id,
150 int regnum)
151{
152 u32 tmp, val;
153
154 tmp = regnum << ENET_MIIDATA_REG_SHIFT;
155 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
156 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
157 tmp |= ENET_MIIDATA_OP_READ_MASK;
158
159 if (do_mdio_op(priv, tmp))
160 return -1;
161
162 val = enet_readl(priv, ENET_MIIDATA_REG);
163 val &= 0xffff;
164 return val;
165}
166
167
168
169
170static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id,
171 int regnum, u16 value)
172{
173 u32 tmp;
174
175 tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT;
176 tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT;
177 tmp |= regnum << ENET_MIIDATA_REG_SHIFT;
178 tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT;
179 tmp |= ENET_MIIDATA_OP_WRITE_MASK;
180
181 (void)do_mdio_op(priv, tmp);
182 return 0;
183}
184
185
186
187
188static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id,
189 int regnum)
190{
191 return bcm_enet_mdio_read(bus->priv, mii_id, regnum);
192}
193
194
195
196
197static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id,
198 int regnum, u16 value)
199{
200 return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value);
201}
202
203
204
205
206static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id,
207 int regnum)
208{
209 return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum);
210}
211
212
213
214
215static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id,
216 int regnum, int value)
217{
218 bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value);
219}
220
221
222
223
224static int bcm_enet_refill_rx(struct net_device *dev)
225{
226 struct bcm_enet_priv *priv;
227
228 priv = netdev_priv(dev);
229
230 while (priv->rx_desc_count < priv->rx_ring_size) {
231 struct bcm_enet_desc *desc;
232 struct sk_buff *skb;
233 dma_addr_t p;
234 int desc_idx;
235 u32 len_stat;
236
237 desc_idx = priv->rx_dirty_desc;
238 desc = &priv->rx_desc_cpu[desc_idx];
239
240 if (!priv->rx_skb[desc_idx]) {
241 skb = netdev_alloc_skb(dev, priv->rx_skb_size);
242 if (!skb)
243 break;
244 priv->rx_skb[desc_idx] = skb;
245 p = dma_map_single(&priv->pdev->dev, skb->data,
246 priv->rx_skb_size,
247 DMA_FROM_DEVICE);
248 desc->address = p;
249 }
250
251 len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT;
252 len_stat |= DMADESC_OWNER_MASK;
253 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
254 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
255 priv->rx_dirty_desc = 0;
256 } else {
257 priv->rx_dirty_desc++;
258 }
259 wmb();
260 desc->len_stat = len_stat;
261
262 priv->rx_desc_count++;
263
264
265 if (priv->dma_has_sram)
266 enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan));
267 else
268 enet_dmac_writel(priv, 1, ENETDMAC_BUFALLOC, priv->rx_chan);
269 }
270
271
272
273 if (priv->rx_desc_count == 0 && netif_running(dev)) {
274 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
275 priv->rx_timeout.expires = jiffies + HZ;
276 add_timer(&priv->rx_timeout);
277 }
278
279 return 0;
280}
281
282
283
284
285static void bcm_enet_refill_rx_timer(struct timer_list *t)
286{
287 struct bcm_enet_priv *priv = from_timer(priv, t, rx_timeout);
288 struct net_device *dev = priv->net_dev;
289
290 spin_lock(&priv->rx_lock);
291 bcm_enet_refill_rx(dev);
292 spin_unlock(&priv->rx_lock);
293}
294
295
296
297
298static int bcm_enet_receive_queue(struct net_device *dev, int budget)
299{
300 struct bcm_enet_priv *priv;
301 struct device *kdev;
302 int processed;
303
304 priv = netdev_priv(dev);
305 kdev = &priv->pdev->dev;
306 processed = 0;
307
308
309
310 if (budget > priv->rx_desc_count)
311 budget = priv->rx_desc_count;
312
313 do {
314 struct bcm_enet_desc *desc;
315 struct sk_buff *skb;
316 int desc_idx;
317 u32 len_stat;
318 unsigned int len;
319
320 desc_idx = priv->rx_curr_desc;
321 desc = &priv->rx_desc_cpu[desc_idx];
322
323
324
325 rmb();
326
327 len_stat = desc->len_stat;
328
329
330 if (len_stat & DMADESC_OWNER_MASK)
331 break;
332
333 processed++;
334 priv->rx_curr_desc++;
335 if (priv->rx_curr_desc == priv->rx_ring_size)
336 priv->rx_curr_desc = 0;
337 priv->rx_desc_count--;
338
339
340
341 if ((len_stat & (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) !=
342 (DMADESC_ESOP_MASK >> priv->dma_desc_shift)) {
343 dev->stats.rx_dropped++;
344 continue;
345 }
346
347
348 if (!priv->enet_is_sw &&
349 unlikely(len_stat & DMADESC_ERR_MASK)) {
350 dev->stats.rx_errors++;
351
352 if (len_stat & DMADESC_OVSIZE_MASK)
353 dev->stats.rx_length_errors++;
354 if (len_stat & DMADESC_CRC_MASK)
355 dev->stats.rx_crc_errors++;
356 if (len_stat & DMADESC_UNDER_MASK)
357 dev->stats.rx_frame_errors++;
358 if (len_stat & DMADESC_OV_MASK)
359 dev->stats.rx_fifo_errors++;
360 continue;
361 }
362
363
364 skb = priv->rx_skb[desc_idx];
365 len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT;
366
367 len -= 4;
368
369 if (len < copybreak) {
370 struct sk_buff *nskb;
371
372 nskb = napi_alloc_skb(&priv->napi, len);
373 if (!nskb) {
374
375 dev->stats.rx_dropped++;
376 continue;
377 }
378
379 dma_sync_single_for_cpu(kdev, desc->address,
380 len, DMA_FROM_DEVICE);
381 memcpy(nskb->data, skb->data, len);
382 dma_sync_single_for_device(kdev, desc->address,
383 len, DMA_FROM_DEVICE);
384 skb = nskb;
385 } else {
386 dma_unmap_single(&priv->pdev->dev, desc->address,
387 priv->rx_skb_size, DMA_FROM_DEVICE);
388 priv->rx_skb[desc_idx] = NULL;
389 }
390
391 skb_put(skb, len);
392 skb->protocol = eth_type_trans(skb, dev);
393 dev->stats.rx_packets++;
394 dev->stats.rx_bytes += len;
395 netif_receive_skb(skb);
396
397 } while (--budget > 0);
398
399 if (processed || !priv->rx_desc_count) {
400 bcm_enet_refill_rx(dev);
401
402
403 enet_dmac_writel(priv, priv->dma_chan_en_mask,
404 ENETDMAC_CHANCFG, priv->rx_chan);
405 }
406
407 return processed;
408}
409
410
411
412
413
414static int bcm_enet_tx_reclaim(struct net_device *dev, int force)
415{
416 struct bcm_enet_priv *priv;
417 int released;
418
419 priv = netdev_priv(dev);
420 released = 0;
421
422 while (priv->tx_desc_count < priv->tx_ring_size) {
423 struct bcm_enet_desc *desc;
424 struct sk_buff *skb;
425
426
427
428 spin_lock(&priv->tx_lock);
429
430 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
431
432 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
433 spin_unlock(&priv->tx_lock);
434 break;
435 }
436
437
438
439 rmb();
440
441 skb = priv->tx_skb[priv->tx_dirty_desc];
442 priv->tx_skb[priv->tx_dirty_desc] = NULL;
443 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
444 DMA_TO_DEVICE);
445
446 priv->tx_dirty_desc++;
447 if (priv->tx_dirty_desc == priv->tx_ring_size)
448 priv->tx_dirty_desc = 0;
449 priv->tx_desc_count++;
450
451 spin_unlock(&priv->tx_lock);
452
453 if (desc->len_stat & DMADESC_UNDER_MASK)
454 dev->stats.tx_errors++;
455
456 dev_kfree_skb(skb);
457 released++;
458 }
459
460 if (netif_queue_stopped(dev) && released)
461 netif_wake_queue(dev);
462
463 return released;
464}
465
466
467
468
469static int bcm_enet_poll(struct napi_struct *napi, int budget)
470{
471 struct bcm_enet_priv *priv;
472 struct net_device *dev;
473 int rx_work_done;
474
475 priv = container_of(napi, struct bcm_enet_priv, napi);
476 dev = priv->net_dev;
477
478
479 enet_dmac_writel(priv, priv->dma_chan_int_mask,
480 ENETDMAC_IR, priv->rx_chan);
481 enet_dmac_writel(priv, priv->dma_chan_int_mask,
482 ENETDMAC_IR, priv->tx_chan);
483
484
485 bcm_enet_tx_reclaim(dev, 0);
486
487 spin_lock(&priv->rx_lock);
488 rx_work_done = bcm_enet_receive_queue(dev, budget);
489 spin_unlock(&priv->rx_lock);
490
491 if (rx_work_done >= budget) {
492
493 return rx_work_done;
494 }
495
496
497
498 napi_complete_done(napi, rx_work_done);
499
500
501 enet_dmac_writel(priv, priv->dma_chan_int_mask,
502 ENETDMAC_IRMASK, priv->rx_chan);
503 enet_dmac_writel(priv, priv->dma_chan_int_mask,
504 ENETDMAC_IRMASK, priv->tx_chan);
505
506 return rx_work_done;
507}
508
509
510
511
512static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id)
513{
514 struct net_device *dev;
515 struct bcm_enet_priv *priv;
516 u32 stat;
517
518 dev = dev_id;
519 priv = netdev_priv(dev);
520
521 stat = enet_readl(priv, ENET_IR_REG);
522 if (!(stat & ENET_IR_MIB))
523 return IRQ_NONE;
524
525
526 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
527 enet_writel(priv, 0, ENET_IRMASK_REG);
528
529
530 schedule_work(&priv->mib_update_task);
531
532 return IRQ_HANDLED;
533}
534
535
536
537
538static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id)
539{
540 struct net_device *dev;
541 struct bcm_enet_priv *priv;
542
543 dev = dev_id;
544 priv = netdev_priv(dev);
545
546
547 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
548 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
549
550 napi_schedule(&priv->napi);
551
552 return IRQ_HANDLED;
553}
554
555
556
557
558static netdev_tx_t
559bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
560{
561 struct bcm_enet_priv *priv;
562 struct bcm_enet_desc *desc;
563 u32 len_stat;
564 netdev_tx_t ret;
565
566 priv = netdev_priv(dev);
567
568
569 spin_lock(&priv->tx_lock);
570
571
572
573 if (unlikely(!priv->tx_desc_count)) {
574 netif_stop_queue(dev);
575 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
576 "available?\n");
577 ret = NETDEV_TX_BUSY;
578 goto out_unlock;
579 }
580
581
582 if (priv->enet_is_sw && skb->len < 64) {
583 int needed = 64 - skb->len;
584 char *data;
585
586 if (unlikely(skb_tailroom(skb) < needed)) {
587 struct sk_buff *nskb;
588
589 nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
590 if (!nskb) {
591 ret = NETDEV_TX_BUSY;
592 goto out_unlock;
593 }
594 dev_kfree_skb(skb);
595 skb = nskb;
596 }
597 data = skb_put_zero(skb, needed);
598 }
599
600
601 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
602 priv->tx_skb[priv->tx_curr_desc] = skb;
603
604
605 desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
606 DMA_TO_DEVICE);
607
608 len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
609 len_stat |= (DMADESC_ESOP_MASK >> priv->dma_desc_shift) |
610 DMADESC_APPEND_CRC |
611 DMADESC_OWNER_MASK;
612
613 priv->tx_curr_desc++;
614 if (priv->tx_curr_desc == priv->tx_ring_size) {
615 priv->tx_curr_desc = 0;
616 len_stat |= (DMADESC_WRAP_MASK >> priv->dma_desc_shift);
617 }
618 priv->tx_desc_count--;
619
620
621
622 wmb();
623 desc->len_stat = len_stat;
624 wmb();
625
626
627 enet_dmac_writel(priv, priv->dma_chan_en_mask,
628 ENETDMAC_CHANCFG, priv->tx_chan);
629
630
631 if (!priv->tx_desc_count)
632 netif_stop_queue(dev);
633
634 dev->stats.tx_bytes += skb->len;
635 dev->stats.tx_packets++;
636 ret = NETDEV_TX_OK;
637
638out_unlock:
639 spin_unlock(&priv->tx_lock);
640 return ret;
641}
642
643
644
645
646static int bcm_enet_set_mac_address(struct net_device *dev, void *p)
647{
648 struct bcm_enet_priv *priv;
649 struct sockaddr *addr = p;
650 u32 val;
651
652 priv = netdev_priv(dev);
653 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
654
655
656 val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) |
657 (dev->dev_addr[4] << 8) | dev->dev_addr[5];
658 enet_writel(priv, val, ENET_PML_REG(0));
659
660 val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]);
661 val |= ENET_PMH_DATAVALID_MASK;
662 enet_writel(priv, val, ENET_PMH_REG(0));
663
664 return 0;
665}
666
667
668
669
670static void bcm_enet_set_multicast_list(struct net_device *dev)
671{
672 struct bcm_enet_priv *priv;
673 struct netdev_hw_addr *ha;
674 u32 val;
675 int i;
676
677 priv = netdev_priv(dev);
678
679 val = enet_readl(priv, ENET_RXCFG_REG);
680
681 if (dev->flags & IFF_PROMISC)
682 val |= ENET_RXCFG_PROMISC_MASK;
683 else
684 val &= ~ENET_RXCFG_PROMISC_MASK;
685
686
687
688 if ((dev->flags & IFF_ALLMULTI) || netdev_mc_count(dev) > 3)
689 val |= ENET_RXCFG_ALLMCAST_MASK;
690 else
691 val &= ~ENET_RXCFG_ALLMCAST_MASK;
692
693
694
695 if (val & ENET_RXCFG_ALLMCAST_MASK) {
696 enet_writel(priv, val, ENET_RXCFG_REG);
697 return;
698 }
699
700 i = 0;
701 netdev_for_each_mc_addr(ha, dev) {
702 u8 *dmi_addr;
703 u32 tmp;
704
705 if (i == 3)
706 break;
707
708 dmi_addr = ha->addr;
709 tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) |
710 (dmi_addr[4] << 8) | dmi_addr[5];
711 enet_writel(priv, tmp, ENET_PML_REG(i + 1));
712
713 tmp = (dmi_addr[0] << 8 | dmi_addr[1]);
714 tmp |= ENET_PMH_DATAVALID_MASK;
715 enet_writel(priv, tmp, ENET_PMH_REG(i++ + 1));
716 }
717
718 for (; i < 3; i++) {
719 enet_writel(priv, 0, ENET_PML_REG(i + 1));
720 enet_writel(priv, 0, ENET_PMH_REG(i + 1));
721 }
722
723 enet_writel(priv, val, ENET_RXCFG_REG);
724}
725
726
727
728
729static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex)
730{
731 u32 val;
732
733 val = enet_readl(priv, ENET_TXCTL_REG);
734 if (fullduplex)
735 val |= ENET_TXCTL_FD_MASK;
736 else
737 val &= ~ENET_TXCTL_FD_MASK;
738 enet_writel(priv, val, ENET_TXCTL_REG);
739}
740
741
742
743
744static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en)
745{
746 u32 val;
747
748
749 val = enet_readl(priv, ENET_RXCFG_REG);
750 if (rx_en)
751 val |= ENET_RXCFG_ENFLOW_MASK;
752 else
753 val &= ~ENET_RXCFG_ENFLOW_MASK;
754 enet_writel(priv, val, ENET_RXCFG_REG);
755
756 if (!priv->dma_has_sram)
757 return;
758
759
760 val = enet_dma_readl(priv, ENETDMA_CFG_REG);
761 if (tx_en)
762 val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
763 else
764 val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan);
765 enet_dma_writel(priv, val, ENETDMA_CFG_REG);
766}
767
768
769
770
771static void bcm_enet_adjust_phy_link(struct net_device *dev)
772{
773 struct bcm_enet_priv *priv;
774 struct phy_device *phydev;
775 int status_changed;
776
777 priv = netdev_priv(dev);
778 phydev = dev->phydev;
779 status_changed = 0;
780
781 if (priv->old_link != phydev->link) {
782 status_changed = 1;
783 priv->old_link = phydev->link;
784 }
785
786
787 if (phydev->link && phydev->duplex != priv->old_duplex) {
788 bcm_enet_set_duplex(priv,
789 (phydev->duplex == DUPLEX_FULL) ? 1 : 0);
790 status_changed = 1;
791 priv->old_duplex = phydev->duplex;
792 }
793
794
795
796 if (phydev->link && phydev->pause != priv->old_pause) {
797 int rx_pause_en, tx_pause_en;
798
799 if (phydev->pause) {
800
801 rx_pause_en = 1;
802 tx_pause_en = 1;
803 } else if (!priv->pause_auto) {
804
805 rx_pause_en = priv->pause_rx;
806 tx_pause_en = priv->pause_tx;
807 } else {
808 rx_pause_en = 0;
809 tx_pause_en = 0;
810 }
811
812 bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en);
813 status_changed = 1;
814 priv->old_pause = phydev->pause;
815 }
816
817 if (status_changed) {
818 pr_info("%s: link %s", dev->name, phydev->link ?
819 "UP" : "DOWN");
820 if (phydev->link)
821 pr_cont(" - %d/%s - flow control %s", phydev->speed,
822 DUPLEX_FULL == phydev->duplex ? "full" : "half",
823 phydev->pause == 1 ? "rx&tx" : "off");
824
825 pr_cont("\n");
826 }
827}
828
829
830
831
832static void bcm_enet_adjust_link(struct net_device *dev)
833{
834 struct bcm_enet_priv *priv;
835
836 priv = netdev_priv(dev);
837 bcm_enet_set_duplex(priv, priv->force_duplex_full);
838 bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx);
839 netif_carrier_on(dev);
840
841 pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n",
842 dev->name,
843 priv->force_speed_100 ? 100 : 10,
844 priv->force_duplex_full ? "full" : "half",
845 priv->pause_rx ? "rx" : "off",
846 priv->pause_tx ? "tx" : "off");
847}
848
849
850
851
852static int bcm_enet_open(struct net_device *dev)
853{
854 struct bcm_enet_priv *priv;
855 struct sockaddr addr;
856 struct device *kdev;
857 struct phy_device *phydev;
858 int i, ret;
859 unsigned int size;
860 char phy_id[MII_BUS_ID_SIZE + 3];
861 void *p;
862 u32 val;
863
864 priv = netdev_priv(dev);
865 kdev = &priv->pdev->dev;
866
867 if (priv->has_phy) {
868
869 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
870 priv->mii_bus->id, priv->phy_id);
871
872 phydev = phy_connect(dev, phy_id, bcm_enet_adjust_phy_link,
873 PHY_INTERFACE_MODE_MII);
874
875 if (IS_ERR(phydev)) {
876 dev_err(kdev, "could not attach to PHY\n");
877 return PTR_ERR(phydev);
878 }
879
880
881 phy_support_sym_pause(phydev);
882 phy_set_max_speed(phydev, SPEED_100);
883 phy_set_sym_pause(phydev, priv->pause_rx, priv->pause_rx,
884 priv->pause_auto);
885
886 phy_attached_info(phydev);
887
888 priv->old_link = 0;
889 priv->old_duplex = -1;
890 priv->old_pause = -1;
891 } else {
892 phydev = NULL;
893 }
894
895
896 enet_writel(priv, 0, ENET_IRMASK_REG);
897 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
898 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
899
900 ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev);
901 if (ret)
902 goto out_phy_disconnect;
903
904 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, 0,
905 dev->name, dev);
906 if (ret)
907 goto out_freeirq;
908
909 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
910 0, dev->name, dev);
911 if (ret)
912 goto out_freeirq_rx;
913
914
915 for (i = 0; i < 4; i++) {
916 enet_writel(priv, 0, ENET_PML_REG(i));
917 enet_writel(priv, 0, ENET_PMH_REG(i));
918 }
919
920
921 memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN);
922 bcm_enet_set_mac_address(dev, &addr);
923
924
925 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
926 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
927 if (!p) {
928 ret = -ENOMEM;
929 goto out_freeirq_tx;
930 }
931
932 priv->rx_desc_alloc_size = size;
933 priv->rx_desc_cpu = p;
934
935
936 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
937 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
938 if (!p) {
939 ret = -ENOMEM;
940 goto out_free_rx_ring;
941 }
942
943 priv->tx_desc_alloc_size = size;
944 priv->tx_desc_cpu = p;
945
946 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
947 GFP_KERNEL);
948 if (!priv->tx_skb) {
949 ret = -ENOMEM;
950 goto out_free_tx_ring;
951 }
952
953 priv->tx_desc_count = priv->tx_ring_size;
954 priv->tx_dirty_desc = 0;
955 priv->tx_curr_desc = 0;
956 spin_lock_init(&priv->tx_lock);
957
958
959 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
960 GFP_KERNEL);
961 if (!priv->rx_skb) {
962 ret = -ENOMEM;
963 goto out_free_tx_skb;
964 }
965
966 priv->rx_desc_count = 0;
967 priv->rx_dirty_desc = 0;
968 priv->rx_curr_desc = 0;
969
970
971 if (priv->dma_has_sram)
972 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
973 ENETDMA_BUFALLOC_REG(priv->rx_chan));
974 else
975 enet_dmac_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
976 ENETDMAC_BUFALLOC, priv->rx_chan);
977
978 if (bcm_enet_refill_rx(dev)) {
979 dev_err(kdev, "cannot allocate rx skb queue\n");
980 ret = -ENOMEM;
981 goto out;
982 }
983
984
985 if (priv->dma_has_sram) {
986 enet_dmas_writel(priv, priv->rx_desc_dma,
987 ENETDMAS_RSTART_REG, priv->rx_chan);
988 enet_dmas_writel(priv, priv->tx_desc_dma,
989 ENETDMAS_RSTART_REG, priv->tx_chan);
990 } else {
991 enet_dmac_writel(priv, priv->rx_desc_dma,
992 ENETDMAC_RSTART, priv->rx_chan);
993 enet_dmac_writel(priv, priv->tx_desc_dma,
994 ENETDMAC_RSTART, priv->tx_chan);
995 }
996
997
998 if (priv->dma_has_sram) {
999 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
1000 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
1001 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
1002 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
1003 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
1004 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
1005 } else {
1006 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->rx_chan);
1007 enet_dmac_writel(priv, 0, ENETDMAC_FC, priv->tx_chan);
1008 }
1009
1010
1011 enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG);
1012 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
1013
1014
1015 enet_dmac_writel(priv, priv->dma_maxburst,
1016 ENETDMAC_MAXBURST, priv->rx_chan);
1017 enet_dmac_writel(priv, priv->dma_maxburst,
1018 ENETDMAC_MAXBURST, priv->tx_chan);
1019
1020
1021 enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG);
1022
1023
1024 if (priv->dma_has_sram) {
1025 val = priv->rx_ring_size / 3;
1026 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
1027 val = (priv->rx_ring_size * 2) / 3;
1028 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
1029 } else {
1030 enet_dmac_writel(priv, 5, ENETDMAC_FC, priv->rx_chan);
1031 enet_dmac_writel(priv, priv->rx_ring_size, ENETDMAC_LEN, priv->rx_chan);
1032 enet_dmac_writel(priv, priv->tx_ring_size, ENETDMAC_LEN, priv->tx_chan);
1033 }
1034
1035
1036
1037 wmb();
1038 val = enet_readl(priv, ENET_CTL_REG);
1039 val |= ENET_CTL_ENABLE_MASK;
1040 enet_writel(priv, val, ENET_CTL_REG);
1041 if (priv->dma_has_sram)
1042 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
1043 enet_dmac_writel(priv, priv->dma_chan_en_mask,
1044 ENETDMAC_CHANCFG, priv->rx_chan);
1045
1046
1047 enet_writel(priv, ENET_IR_MIB, ENET_IR_REG);
1048 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1049
1050
1051 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1052 ENETDMAC_IR, priv->rx_chan);
1053 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1054 ENETDMAC_IR, priv->tx_chan);
1055
1056
1057 napi_enable(&priv->napi);
1058
1059 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1060 ENETDMAC_IRMASK, priv->rx_chan);
1061 enet_dmac_writel(priv, priv->dma_chan_int_mask,
1062 ENETDMAC_IRMASK, priv->tx_chan);
1063
1064 if (phydev)
1065 phy_start(phydev);
1066 else
1067 bcm_enet_adjust_link(dev);
1068
1069 netif_start_queue(dev);
1070 return 0;
1071
1072out:
1073 for (i = 0; i < priv->rx_ring_size; i++) {
1074 struct bcm_enet_desc *desc;
1075
1076 if (!priv->rx_skb[i])
1077 continue;
1078
1079 desc = &priv->rx_desc_cpu[i];
1080 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1081 DMA_FROM_DEVICE);
1082 kfree_skb(priv->rx_skb[i]);
1083 }
1084 kfree(priv->rx_skb);
1085
1086out_free_tx_skb:
1087 kfree(priv->tx_skb);
1088
1089out_free_tx_ring:
1090 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1091 priv->tx_desc_cpu, priv->tx_desc_dma);
1092
1093out_free_rx_ring:
1094 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1095 priv->rx_desc_cpu, priv->rx_desc_dma);
1096
1097out_freeirq_tx:
1098 free_irq(priv->irq_tx, dev);
1099
1100out_freeirq_rx:
1101 free_irq(priv->irq_rx, dev);
1102
1103out_freeirq:
1104 free_irq(dev->irq, dev);
1105
1106out_phy_disconnect:
1107 if (phydev)
1108 phy_disconnect(phydev);
1109
1110 return ret;
1111}
1112
1113
1114
1115
1116static void bcm_enet_disable_mac(struct bcm_enet_priv *priv)
1117{
1118 int limit;
1119 u32 val;
1120
1121 val = enet_readl(priv, ENET_CTL_REG);
1122 val |= ENET_CTL_DISABLE_MASK;
1123 enet_writel(priv, val, ENET_CTL_REG);
1124
1125 limit = 1000;
1126 do {
1127 u32 val;
1128
1129 val = enet_readl(priv, ENET_CTL_REG);
1130 if (!(val & ENET_CTL_DISABLE_MASK))
1131 break;
1132 udelay(1);
1133 } while (limit--);
1134}
1135
1136
1137
1138
1139static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan)
1140{
1141 int limit;
1142
1143 enet_dmac_writel(priv, 0, ENETDMAC_CHANCFG, chan);
1144
1145 limit = 1000;
1146 do {
1147 u32 val;
1148
1149 val = enet_dmac_readl(priv, ENETDMAC_CHANCFG, chan);
1150 if (!(val & ENETDMAC_CHANCFG_EN_MASK))
1151 break;
1152 udelay(1);
1153 } while (limit--);
1154}
1155
1156
1157
1158
1159static int bcm_enet_stop(struct net_device *dev)
1160{
1161 struct bcm_enet_priv *priv;
1162 struct device *kdev;
1163 int i;
1164
1165 priv = netdev_priv(dev);
1166 kdev = &priv->pdev->dev;
1167
1168 netif_stop_queue(dev);
1169 napi_disable(&priv->napi);
1170 if (priv->has_phy)
1171 phy_stop(dev->phydev);
1172 del_timer_sync(&priv->rx_timeout);
1173
1174
1175 enet_writel(priv, 0, ENET_IRMASK_REG);
1176 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
1177 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
1178
1179
1180 cancel_work_sync(&priv->mib_update_task);
1181
1182
1183 bcm_enet_disable_dma(priv, priv->tx_chan);
1184 bcm_enet_disable_dma(priv, priv->rx_chan);
1185 bcm_enet_disable_mac(priv);
1186
1187
1188 bcm_enet_tx_reclaim(dev, 1);
1189
1190
1191 for (i = 0; i < priv->rx_ring_size; i++) {
1192 struct bcm_enet_desc *desc;
1193
1194 if (!priv->rx_skb[i])
1195 continue;
1196
1197 desc = &priv->rx_desc_cpu[i];
1198 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
1199 DMA_FROM_DEVICE);
1200 kfree_skb(priv->rx_skb[i]);
1201 }
1202
1203
1204 kfree(priv->rx_skb);
1205 kfree(priv->tx_skb);
1206 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
1207 priv->rx_desc_cpu, priv->rx_desc_dma);
1208 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
1209 priv->tx_desc_cpu, priv->tx_desc_dma);
1210 free_irq(priv->irq_tx, dev);
1211 free_irq(priv->irq_rx, dev);
1212 free_irq(dev->irq, dev);
1213
1214
1215 if (priv->has_phy)
1216 phy_disconnect(dev->phydev);
1217
1218 return 0;
1219}
1220
1221
1222
1223
1224struct bcm_enet_stats {
1225 char stat_string[ETH_GSTRING_LEN];
1226 int sizeof_stat;
1227 int stat_offset;
1228 int mib_reg;
1229};
1230
1231#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \
1232 offsetof(struct bcm_enet_priv, m)
1233#define DEV_STAT(m) sizeof(((struct net_device_stats *)0)->m), \
1234 offsetof(struct net_device_stats, m)
1235
1236static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = {
1237 { "rx_packets", DEV_STAT(rx_packets), -1 },
1238 { "tx_packets", DEV_STAT(tx_packets), -1 },
1239 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
1240 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
1241 { "rx_errors", DEV_STAT(rx_errors), -1 },
1242 { "tx_errors", DEV_STAT(tx_errors), -1 },
1243 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1244 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1245
1246 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS},
1247 { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS },
1248 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST },
1249 { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT },
1250 { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 },
1251 { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 },
1252 { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 },
1253 { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 },
1254 { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 },
1255 { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX },
1256 { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB },
1257 { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR },
1258 { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG },
1259 { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP },
1260 { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN },
1261 { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND },
1262 { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC },
1263 { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN },
1264 { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM },
1265 { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE },
1266 { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL },
1267
1268 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS },
1269 { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS },
1270 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST },
1271 { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT },
1272 { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 },
1273 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 },
1274 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 },
1275 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 },
1276 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023},
1277 { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX },
1278 { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB },
1279 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR },
1280 { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG },
1281 { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN },
1282 { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL },
1283 { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL },
1284 { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL },
1285 { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL },
1286 { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE },
1287 { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF },
1288 { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS },
1289 { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE },
1290
1291};
1292
1293#define BCM_ENET_STATS_LEN ARRAY_SIZE(bcm_enet_gstrings_stats)
1294
1295static const u32 unused_mib_regs[] = {
1296 ETH_MIB_TX_ALL_OCTETS,
1297 ETH_MIB_TX_ALL_PKTS,
1298 ETH_MIB_RX_ALL_OCTETS,
1299 ETH_MIB_RX_ALL_PKTS,
1300};
1301
1302
1303static void bcm_enet_get_drvinfo(struct net_device *netdev,
1304 struct ethtool_drvinfo *drvinfo)
1305{
1306 strlcpy(drvinfo->driver, bcm_enet_driver_name, sizeof(drvinfo->driver));
1307 strlcpy(drvinfo->version, bcm_enet_driver_version,
1308 sizeof(drvinfo->version));
1309 strlcpy(drvinfo->fw_version, "N/A", sizeof(drvinfo->fw_version));
1310 strlcpy(drvinfo->bus_info, "bcm63xx", sizeof(drvinfo->bus_info));
1311}
1312
1313static int bcm_enet_get_sset_count(struct net_device *netdev,
1314 int string_set)
1315{
1316 switch (string_set) {
1317 case ETH_SS_STATS:
1318 return BCM_ENET_STATS_LEN;
1319 default:
1320 return -EINVAL;
1321 }
1322}
1323
1324static void bcm_enet_get_strings(struct net_device *netdev,
1325 u32 stringset, u8 *data)
1326{
1327 int i;
1328
1329 switch (stringset) {
1330 case ETH_SS_STATS:
1331 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1332 memcpy(data + i * ETH_GSTRING_LEN,
1333 bcm_enet_gstrings_stats[i].stat_string,
1334 ETH_GSTRING_LEN);
1335 }
1336 break;
1337 }
1338}
1339
1340static void update_mib_counters(struct bcm_enet_priv *priv)
1341{
1342 int i;
1343
1344 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1345 const struct bcm_enet_stats *s;
1346 u32 val;
1347 char *p;
1348
1349 s = &bcm_enet_gstrings_stats[i];
1350 if (s->mib_reg == -1)
1351 continue;
1352
1353 val = enet_readl(priv, ENET_MIB_REG(s->mib_reg));
1354 p = (char *)priv + s->stat_offset;
1355
1356 if (s->sizeof_stat == sizeof(u64))
1357 *(u64 *)p += val;
1358 else
1359 *(u32 *)p += val;
1360 }
1361
1362
1363
1364 for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++)
1365 (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i]));
1366}
1367
1368static void bcm_enet_update_mib_counters_defer(struct work_struct *t)
1369{
1370 struct bcm_enet_priv *priv;
1371
1372 priv = container_of(t, struct bcm_enet_priv, mib_update_task);
1373 mutex_lock(&priv->mib_update_lock);
1374 update_mib_counters(priv);
1375 mutex_unlock(&priv->mib_update_lock);
1376
1377
1378 if (netif_running(priv->net_dev))
1379 enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG);
1380}
1381
1382static void bcm_enet_get_ethtool_stats(struct net_device *netdev,
1383 struct ethtool_stats *stats,
1384 u64 *data)
1385{
1386 struct bcm_enet_priv *priv;
1387 int i;
1388
1389 priv = netdev_priv(netdev);
1390
1391 mutex_lock(&priv->mib_update_lock);
1392 update_mib_counters(priv);
1393
1394 for (i = 0; i < BCM_ENET_STATS_LEN; i++) {
1395 const struct bcm_enet_stats *s;
1396 char *p;
1397
1398 s = &bcm_enet_gstrings_stats[i];
1399 if (s->mib_reg == -1)
1400 p = (char *)&netdev->stats;
1401 else
1402 p = (char *)priv;
1403 p += s->stat_offset;
1404 data[i] = (s->sizeof_stat == sizeof(u64)) ?
1405 *(u64 *)p : *(u32 *)p;
1406 }
1407 mutex_unlock(&priv->mib_update_lock);
1408}
1409
1410static int bcm_enet_nway_reset(struct net_device *dev)
1411{
1412 struct bcm_enet_priv *priv;
1413
1414 priv = netdev_priv(dev);
1415 if (priv->has_phy)
1416 return phy_ethtool_nway_reset(dev);
1417
1418 return -EOPNOTSUPP;
1419}
1420
1421static int bcm_enet_get_link_ksettings(struct net_device *dev,
1422 struct ethtool_link_ksettings *cmd)
1423{
1424 struct bcm_enet_priv *priv;
1425 u32 supported, advertising;
1426
1427 priv = netdev_priv(dev);
1428
1429 if (priv->has_phy) {
1430 if (!dev->phydev)
1431 return -ENODEV;
1432
1433 phy_ethtool_ksettings_get(dev->phydev, cmd);
1434
1435 return 0;
1436 } else {
1437 cmd->base.autoneg = 0;
1438 cmd->base.speed = (priv->force_speed_100) ?
1439 SPEED_100 : SPEED_10;
1440 cmd->base.duplex = (priv->force_duplex_full) ?
1441 DUPLEX_FULL : DUPLEX_HALF;
1442 supported = ADVERTISED_10baseT_Half |
1443 ADVERTISED_10baseT_Full |
1444 ADVERTISED_100baseT_Half |
1445 ADVERTISED_100baseT_Full;
1446 advertising = 0;
1447 ethtool_convert_legacy_u32_to_link_mode(
1448 cmd->link_modes.supported, supported);
1449 ethtool_convert_legacy_u32_to_link_mode(
1450 cmd->link_modes.advertising, advertising);
1451 cmd->base.port = PORT_MII;
1452 }
1453 return 0;
1454}
1455
1456static int bcm_enet_set_link_ksettings(struct net_device *dev,
1457 const struct ethtool_link_ksettings *cmd)
1458{
1459 struct bcm_enet_priv *priv;
1460
1461 priv = netdev_priv(dev);
1462 if (priv->has_phy) {
1463 if (!dev->phydev)
1464 return -ENODEV;
1465 return phy_ethtool_ksettings_set(dev->phydev, cmd);
1466 } else {
1467
1468 if (cmd->base.autoneg ||
1469 (cmd->base.speed != SPEED_100 &&
1470 cmd->base.speed != SPEED_10) ||
1471 cmd->base.port != PORT_MII)
1472 return -EINVAL;
1473
1474 priv->force_speed_100 =
1475 (cmd->base.speed == SPEED_100) ? 1 : 0;
1476 priv->force_duplex_full =
1477 (cmd->base.duplex == DUPLEX_FULL) ? 1 : 0;
1478
1479 if (netif_running(dev))
1480 bcm_enet_adjust_link(dev);
1481 return 0;
1482 }
1483}
1484
1485static void bcm_enet_get_ringparam(struct net_device *dev,
1486 struct ethtool_ringparam *ering)
1487{
1488 struct bcm_enet_priv *priv;
1489
1490 priv = netdev_priv(dev);
1491
1492
1493 ering->rx_max_pending = 8192;
1494 ering->tx_max_pending = 8192;
1495 ering->rx_pending = priv->rx_ring_size;
1496 ering->tx_pending = priv->tx_ring_size;
1497}
1498
1499static int bcm_enet_set_ringparam(struct net_device *dev,
1500 struct ethtool_ringparam *ering)
1501{
1502 struct bcm_enet_priv *priv;
1503 int was_running;
1504
1505 priv = netdev_priv(dev);
1506
1507 was_running = 0;
1508 if (netif_running(dev)) {
1509 bcm_enet_stop(dev);
1510 was_running = 1;
1511 }
1512
1513 priv->rx_ring_size = ering->rx_pending;
1514 priv->tx_ring_size = ering->tx_pending;
1515
1516 if (was_running) {
1517 int err;
1518
1519 err = bcm_enet_open(dev);
1520 if (err)
1521 dev_close(dev);
1522 else
1523 bcm_enet_set_multicast_list(dev);
1524 }
1525 return 0;
1526}
1527
1528static void bcm_enet_get_pauseparam(struct net_device *dev,
1529 struct ethtool_pauseparam *ecmd)
1530{
1531 struct bcm_enet_priv *priv;
1532
1533 priv = netdev_priv(dev);
1534 ecmd->autoneg = priv->pause_auto;
1535 ecmd->rx_pause = priv->pause_rx;
1536 ecmd->tx_pause = priv->pause_tx;
1537}
1538
1539static int bcm_enet_set_pauseparam(struct net_device *dev,
1540 struct ethtool_pauseparam *ecmd)
1541{
1542 struct bcm_enet_priv *priv;
1543
1544 priv = netdev_priv(dev);
1545
1546 if (priv->has_phy) {
1547 if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) {
1548
1549
1550
1551 return -EINVAL;
1552 }
1553 } else {
1554
1555 if (ecmd->autoneg)
1556 return -EINVAL;
1557 }
1558
1559 priv->pause_auto = ecmd->autoneg;
1560 priv->pause_rx = ecmd->rx_pause;
1561 priv->pause_tx = ecmd->tx_pause;
1562
1563 return 0;
1564}
1565
1566static const struct ethtool_ops bcm_enet_ethtool_ops = {
1567 .get_strings = bcm_enet_get_strings,
1568 .get_sset_count = bcm_enet_get_sset_count,
1569 .get_ethtool_stats = bcm_enet_get_ethtool_stats,
1570 .nway_reset = bcm_enet_nway_reset,
1571 .get_drvinfo = bcm_enet_get_drvinfo,
1572 .get_link = ethtool_op_get_link,
1573 .get_ringparam = bcm_enet_get_ringparam,
1574 .set_ringparam = bcm_enet_set_ringparam,
1575 .get_pauseparam = bcm_enet_get_pauseparam,
1576 .set_pauseparam = bcm_enet_set_pauseparam,
1577 .get_link_ksettings = bcm_enet_get_link_ksettings,
1578 .set_link_ksettings = bcm_enet_set_link_ksettings,
1579};
1580
1581static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1582{
1583 struct bcm_enet_priv *priv;
1584
1585 priv = netdev_priv(dev);
1586 if (priv->has_phy) {
1587 if (!dev->phydev)
1588 return -ENODEV;
1589 return phy_mii_ioctl(dev->phydev, rq, cmd);
1590 } else {
1591 struct mii_if_info mii;
1592
1593 mii.dev = dev;
1594 mii.mdio_read = bcm_enet_mdio_read_mii;
1595 mii.mdio_write = bcm_enet_mdio_write_mii;
1596 mii.phy_id = 0;
1597 mii.phy_id_mask = 0x3f;
1598 mii.reg_num_mask = 0x1f;
1599 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
1600 }
1601}
1602
1603
1604
1605
1606static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu)
1607{
1608 struct bcm_enet_priv *priv = netdev_priv(dev);
1609 int actual_mtu = new_mtu;
1610
1611 if (netif_running(dev))
1612 return -EBUSY;
1613
1614
1615 actual_mtu += VLAN_ETH_HLEN;
1616
1617
1618
1619
1620
1621
1622
1623 priv->hw_mtu = actual_mtu;
1624
1625
1626
1627
1628
1629 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
1630 priv->dma_maxburst * 4);
1631
1632 dev->mtu = new_mtu;
1633 return 0;
1634}
1635
1636
1637
1638
1639static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv)
1640{
1641 u32 val;
1642 int limit;
1643
1644
1645 bcm_enet_disable_mac(priv);
1646
1647
1648 val = ENET_CTL_SRESET_MASK;
1649 enet_writel(priv, val, ENET_CTL_REG);
1650 wmb();
1651
1652 limit = 1000;
1653 do {
1654 val = enet_readl(priv, ENET_CTL_REG);
1655 if (!(val & ENET_CTL_SRESET_MASK))
1656 break;
1657 udelay(1);
1658 } while (limit--);
1659
1660
1661 val = enet_readl(priv, ENET_CTL_REG);
1662 if (priv->use_external_mii)
1663 val |= ENET_CTL_EPHYSEL_MASK;
1664 else
1665 val &= ~ENET_CTL_EPHYSEL_MASK;
1666 enet_writel(priv, val, ENET_CTL_REG);
1667
1668
1669 enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) |
1670 ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG);
1671
1672
1673 val = enet_readl(priv, ENET_MIBCTL_REG);
1674 val |= ENET_MIBCTL_RDCLEAR_MASK;
1675 enet_writel(priv, val, ENET_MIBCTL_REG);
1676}
1677
1678static const struct net_device_ops bcm_enet_ops = {
1679 .ndo_open = bcm_enet_open,
1680 .ndo_stop = bcm_enet_stop,
1681 .ndo_start_xmit = bcm_enet_start_xmit,
1682 .ndo_set_mac_address = bcm_enet_set_mac_address,
1683 .ndo_set_rx_mode = bcm_enet_set_multicast_list,
1684 .ndo_do_ioctl = bcm_enet_ioctl,
1685 .ndo_change_mtu = bcm_enet_change_mtu,
1686};
1687
1688
1689
1690
1691static int bcm_enet_probe(struct platform_device *pdev)
1692{
1693 struct bcm_enet_priv *priv;
1694 struct net_device *dev;
1695 struct bcm63xx_enet_platform_data *pd;
1696 struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx;
1697 struct mii_bus *bus;
1698 int i, ret;
1699
1700 if (!bcm_enet_shared_base[0])
1701 return -EPROBE_DEFER;
1702
1703 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1704 res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
1705 res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2);
1706 if (!res_irq || !res_irq_rx || !res_irq_tx)
1707 return -ENODEV;
1708
1709 ret = 0;
1710 dev = alloc_etherdev(sizeof(*priv));
1711 if (!dev)
1712 return -ENOMEM;
1713 priv = netdev_priv(dev);
1714
1715 priv->enet_is_sw = false;
1716 priv->dma_maxburst = BCMENET_DMA_MAXBURST;
1717
1718 ret = bcm_enet_change_mtu(dev, dev->mtu);
1719 if (ret)
1720 goto out;
1721
1722 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1723 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
1724 if (IS_ERR(priv->base)) {
1725 ret = PTR_ERR(priv->base);
1726 goto out;
1727 }
1728
1729 dev->irq = priv->irq = res_irq->start;
1730 priv->irq_rx = res_irq_rx->start;
1731 priv->irq_tx = res_irq_tx->start;
1732
1733 priv->mac_clk = devm_clk_get(&pdev->dev, "enet");
1734 if (IS_ERR(priv->mac_clk)) {
1735 ret = PTR_ERR(priv->mac_clk);
1736 goto out;
1737 }
1738 ret = clk_prepare_enable(priv->mac_clk);
1739 if (ret)
1740 goto out;
1741
1742
1743 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1744 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1745
1746 pd = dev_get_platdata(&pdev->dev);
1747 if (pd) {
1748 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1749 priv->has_phy = pd->has_phy;
1750 priv->phy_id = pd->phy_id;
1751 priv->has_phy_interrupt = pd->has_phy_interrupt;
1752 priv->phy_interrupt = pd->phy_interrupt;
1753 priv->use_external_mii = !pd->use_internal_phy;
1754 priv->pause_auto = pd->pause_auto;
1755 priv->pause_rx = pd->pause_rx;
1756 priv->pause_tx = pd->pause_tx;
1757 priv->force_duplex_full = pd->force_duplex_full;
1758 priv->force_speed_100 = pd->force_speed_100;
1759 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
1760 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
1761 priv->dma_chan_width = pd->dma_chan_width;
1762 priv->dma_has_sram = pd->dma_has_sram;
1763 priv->dma_desc_shift = pd->dma_desc_shift;
1764 priv->rx_chan = pd->rx_chan;
1765 priv->tx_chan = pd->tx_chan;
1766 }
1767
1768 if (priv->has_phy && !priv->use_external_mii) {
1769
1770 priv->phy_clk = devm_clk_get(&pdev->dev, "ephy");
1771 if (IS_ERR(priv->phy_clk)) {
1772 ret = PTR_ERR(priv->phy_clk);
1773 priv->phy_clk = NULL;
1774 goto out_disable_clk_mac;
1775 }
1776 ret = clk_prepare_enable(priv->phy_clk);
1777 if (ret)
1778 goto out_disable_clk_mac;
1779 }
1780
1781
1782 bcm_enet_hw_preinit(priv);
1783
1784
1785 if (priv->has_phy) {
1786
1787 priv->mii_bus = mdiobus_alloc();
1788 if (!priv->mii_bus) {
1789 ret = -ENOMEM;
1790 goto out_uninit_hw;
1791 }
1792
1793 bus = priv->mii_bus;
1794 bus->name = "bcm63xx_enet MII bus";
1795 bus->parent = &pdev->dev;
1796 bus->priv = priv;
1797 bus->read = bcm_enet_mdio_read_phylib;
1798 bus->write = bcm_enet_mdio_write_phylib;
1799 sprintf(bus->id, "%s-%d", pdev->name, pdev->id);
1800
1801
1802
1803
1804 bus->phy_mask = ~(1 << priv->phy_id);
1805
1806 if (priv->has_phy_interrupt)
1807 bus->irq[priv->phy_id] = priv->phy_interrupt;
1808
1809 ret = mdiobus_register(bus);
1810 if (ret) {
1811 dev_err(&pdev->dev, "unable to register mdio bus\n");
1812 goto out_free_mdio;
1813 }
1814 } else {
1815
1816
1817 if (pd && pd->mii_config &&
1818 pd->mii_config(dev, 1, bcm_enet_mdio_read_mii,
1819 bcm_enet_mdio_write_mii)) {
1820 dev_err(&pdev->dev, "unable to configure mdio bus\n");
1821 goto out_uninit_hw;
1822 }
1823 }
1824
1825 spin_lock_init(&priv->rx_lock);
1826
1827
1828 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
1829
1830
1831 mutex_init(&priv->mib_update_lock);
1832 INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer);
1833
1834
1835 for (i = 0; i < ENET_MIB_REG_COUNT; i++)
1836 enet_writel(priv, 0, ENET_MIB_REG(i));
1837
1838
1839 dev->netdev_ops = &bcm_enet_ops;
1840 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1841
1842 dev->ethtool_ops = &bcm_enet_ethtool_ops;
1843
1844 dev->min_mtu = ETH_ZLEN - ETH_HLEN;
1845 dev->max_mtu = BCMENET_MAX_MTU - VLAN_ETH_HLEN;
1846 SET_NETDEV_DEV(dev, &pdev->dev);
1847
1848 ret = register_netdev(dev);
1849 if (ret)
1850 goto out_unregister_mdio;
1851
1852 netif_carrier_off(dev);
1853 platform_set_drvdata(pdev, dev);
1854 priv->pdev = pdev;
1855 priv->net_dev = dev;
1856
1857 return 0;
1858
1859out_unregister_mdio:
1860 if (priv->mii_bus)
1861 mdiobus_unregister(priv->mii_bus);
1862
1863out_free_mdio:
1864 if (priv->mii_bus)
1865 mdiobus_free(priv->mii_bus);
1866
1867out_uninit_hw:
1868
1869 enet_writel(priv, 0, ENET_MIISC_REG);
1870 clk_disable_unprepare(priv->phy_clk);
1871
1872out_disable_clk_mac:
1873 clk_disable_unprepare(priv->mac_clk);
1874out:
1875 free_netdev(dev);
1876 return ret;
1877}
1878
1879
1880
1881
1882
1883static int bcm_enet_remove(struct platform_device *pdev)
1884{
1885 struct bcm_enet_priv *priv;
1886 struct net_device *dev;
1887
1888
1889 dev = platform_get_drvdata(pdev);
1890 priv = netdev_priv(dev);
1891 unregister_netdev(dev);
1892
1893
1894 enet_writel(priv, 0, ENET_MIISC_REG);
1895
1896 if (priv->has_phy) {
1897 mdiobus_unregister(priv->mii_bus);
1898 mdiobus_free(priv->mii_bus);
1899 } else {
1900 struct bcm63xx_enet_platform_data *pd;
1901
1902 pd = dev_get_platdata(&pdev->dev);
1903 if (pd && pd->mii_config)
1904 pd->mii_config(dev, 0, bcm_enet_mdio_read_mii,
1905 bcm_enet_mdio_write_mii);
1906 }
1907
1908
1909 clk_disable_unprepare(priv->phy_clk);
1910 clk_disable_unprepare(priv->mac_clk);
1911
1912 free_netdev(dev);
1913 return 0;
1914}
1915
1916struct platform_driver bcm63xx_enet_driver = {
1917 .probe = bcm_enet_probe,
1918 .remove = bcm_enet_remove,
1919 .driver = {
1920 .name = "bcm63xx_enet",
1921 .owner = THIS_MODULE,
1922 },
1923};
1924
1925
1926
1927
1928static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
1929 int ext, int phy_id, int location)
1930{
1931 u32 reg;
1932 int ret;
1933
1934 spin_lock_bh(&priv->enetsw_mdio_lock);
1935 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1936
1937 reg = ENETSW_MDIOC_RD_MASK |
1938 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1939 (location << ENETSW_MDIOC_REG_SHIFT);
1940
1941 if (ext)
1942 reg |= ENETSW_MDIOC_EXT_MASK;
1943
1944 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1945 udelay(50);
1946 ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
1947 spin_unlock_bh(&priv->enetsw_mdio_lock);
1948 return ret;
1949}
1950
1951static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
1952 int ext, int phy_id, int location,
1953 uint16_t data)
1954{
1955 u32 reg;
1956
1957 spin_lock_bh(&priv->enetsw_mdio_lock);
1958 enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
1959
1960 reg = ENETSW_MDIOC_WR_MASK |
1961 (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
1962 (location << ENETSW_MDIOC_REG_SHIFT);
1963
1964 if (ext)
1965 reg |= ENETSW_MDIOC_EXT_MASK;
1966
1967 reg |= data;
1968
1969 enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
1970 udelay(50);
1971 spin_unlock_bh(&priv->enetsw_mdio_lock);
1972}
1973
1974static inline int bcm_enet_port_is_rgmii(int portid)
1975{
1976 return portid >= ENETSW_RGMII_PORT0;
1977}
1978
1979
1980
1981
1982static void swphy_poll_timer(struct timer_list *t)
1983{
1984 struct bcm_enet_priv *priv = from_timer(priv, t, swphy_poll);
1985 unsigned int i;
1986
1987 for (i = 0; i < priv->num_ports; i++) {
1988 struct bcm63xx_enetsw_port *port;
1989 int val, j, up, advertise, lpa, speed, duplex, media;
1990 int external_phy = bcm_enet_port_is_rgmii(i);
1991 u8 override;
1992
1993 port = &priv->used_ports[i];
1994 if (!port->used)
1995 continue;
1996
1997 if (port->bypass_link)
1998 continue;
1999
2000
2001 for (j = 0; j < 2; j++)
2002 val = bcmenet_sw_mdio_read(priv, external_phy,
2003 port->phy_id, MII_BMSR);
2004
2005 if (val == 0xffff)
2006 continue;
2007
2008 up = (val & BMSR_LSTATUS) ? 1 : 0;
2009 if (!(up ^ priv->sw_port_link[i]))
2010 continue;
2011
2012 priv->sw_port_link[i] = up;
2013
2014
2015 if (!up) {
2016 dev_info(&priv->pdev->dev, "link DOWN on %s\n",
2017 port->name);
2018 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2019 ENETSW_PORTOV_REG(i));
2020 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2021 ENETSW_PTCTRL_TXDIS_MASK,
2022 ENETSW_PTCTRL_REG(i));
2023 continue;
2024 }
2025
2026 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2027 port->phy_id, MII_ADVERTISE);
2028
2029 lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
2030 MII_LPA);
2031
2032
2033 media = mii_nway_result(lpa & advertise);
2034 duplex = (media & ADVERTISE_FULL) ? 1 : 0;
2035
2036 if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
2037 speed = 100;
2038 else
2039 speed = 10;
2040
2041 if (val & BMSR_ESTATEN) {
2042 advertise = bcmenet_sw_mdio_read(priv, external_phy,
2043 port->phy_id, MII_CTRL1000);
2044
2045 lpa = bcmenet_sw_mdio_read(priv, external_phy,
2046 port->phy_id, MII_STAT1000);
2047
2048 if (advertise & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)
2049 && lpa & (LPA_1000FULL | LPA_1000HALF)) {
2050 speed = 1000;
2051 duplex = (lpa & LPA_1000FULL);
2052 }
2053 }
2054
2055 dev_info(&priv->pdev->dev,
2056 "link UP on %s, %dMbps, %s-duplex\n",
2057 port->name, speed, duplex ? "full" : "half");
2058
2059 override = ENETSW_PORTOV_ENABLE_MASK |
2060 ENETSW_PORTOV_LINKUP_MASK;
2061
2062 if (speed == 1000)
2063 override |= ENETSW_IMPOV_1000_MASK;
2064 else if (speed == 100)
2065 override |= ENETSW_IMPOV_100_MASK;
2066 if (duplex)
2067 override |= ENETSW_IMPOV_FDX_MASK;
2068
2069 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2070 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2071 }
2072
2073 priv->swphy_poll.expires = jiffies + HZ;
2074 add_timer(&priv->swphy_poll);
2075}
2076
2077
2078
2079
2080static int bcm_enetsw_open(struct net_device *dev)
2081{
2082 struct bcm_enet_priv *priv;
2083 struct device *kdev;
2084 int i, ret;
2085 unsigned int size;
2086 void *p;
2087 u32 val;
2088
2089 priv = netdev_priv(dev);
2090 kdev = &priv->pdev->dev;
2091
2092
2093 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2094 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2095
2096 ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
2097 0, dev->name, dev);
2098 if (ret)
2099 goto out_freeirq;
2100
2101 if (priv->irq_tx != -1) {
2102 ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
2103 0, dev->name, dev);
2104 if (ret)
2105 goto out_freeirq_rx;
2106 }
2107
2108
2109 size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
2110 p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
2111 if (!p) {
2112 dev_err(kdev, "cannot allocate rx ring %u\n", size);
2113 ret = -ENOMEM;
2114 goto out_freeirq_tx;
2115 }
2116
2117 priv->rx_desc_alloc_size = size;
2118 priv->rx_desc_cpu = p;
2119
2120
2121 size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
2122 p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
2123 if (!p) {
2124 dev_err(kdev, "cannot allocate tx ring\n");
2125 ret = -ENOMEM;
2126 goto out_free_rx_ring;
2127 }
2128
2129 priv->tx_desc_alloc_size = size;
2130 priv->tx_desc_cpu = p;
2131
2132 priv->tx_skb = kcalloc(priv->tx_ring_size, sizeof(struct sk_buff *),
2133 GFP_KERNEL);
2134 if (!priv->tx_skb) {
2135 dev_err(kdev, "cannot allocate rx skb queue\n");
2136 ret = -ENOMEM;
2137 goto out_free_tx_ring;
2138 }
2139
2140 priv->tx_desc_count = priv->tx_ring_size;
2141 priv->tx_dirty_desc = 0;
2142 priv->tx_curr_desc = 0;
2143 spin_lock_init(&priv->tx_lock);
2144
2145
2146 priv->rx_skb = kcalloc(priv->rx_ring_size, sizeof(struct sk_buff *),
2147 GFP_KERNEL);
2148 if (!priv->rx_skb) {
2149 dev_err(kdev, "cannot allocate rx skb queue\n");
2150 ret = -ENOMEM;
2151 goto out_free_tx_skb;
2152 }
2153
2154 priv->rx_desc_count = 0;
2155 priv->rx_dirty_desc = 0;
2156 priv->rx_curr_desc = 0;
2157
2158
2159 for (i = 0; i < priv->num_ports; i++) {
2160 enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
2161 ENETSW_PORTOV_REG(i));
2162 enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
2163 ENETSW_PTCTRL_TXDIS_MASK,
2164 ENETSW_PTCTRL_REG(i));
2165
2166 priv->sw_port_link[i] = 0;
2167 }
2168
2169
2170 val = enetsw_readb(priv, ENETSW_GMCR_REG);
2171 val |= ENETSW_GMCR_RST_MIB_MASK;
2172 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2173 mdelay(1);
2174 val &= ~ENETSW_GMCR_RST_MIB_MASK;
2175 enetsw_writeb(priv, val, ENETSW_GMCR_REG);
2176 mdelay(1);
2177
2178
2179 val = enetsw_readb(priv, ENETSW_IMPOV_REG);
2180 val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
2181 enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
2182
2183
2184 val = enetsw_readb(priv, ENETSW_SWMODE_REG);
2185 val |= ENETSW_SWMODE_FWD_EN_MASK;
2186 enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
2187
2188
2189 enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
2190 enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
2191
2192
2193 enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
2194 ENETDMA_BUFALLOC_REG(priv->rx_chan));
2195
2196 if (bcm_enet_refill_rx(dev)) {
2197 dev_err(kdev, "cannot allocate rx skb queue\n");
2198 ret = -ENOMEM;
2199 goto out;
2200 }
2201
2202
2203 enet_dmas_writel(priv, priv->rx_desc_dma,
2204 ENETDMAS_RSTART_REG, priv->rx_chan);
2205 enet_dmas_writel(priv, priv->tx_desc_dma,
2206 ENETDMAS_RSTART_REG, priv->tx_chan);
2207
2208
2209 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->rx_chan);
2210 enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG, priv->tx_chan);
2211 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->rx_chan);
2212 enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG, priv->tx_chan);
2213 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->rx_chan);
2214 enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG, priv->tx_chan);
2215
2216
2217 enet_dmac_writel(priv, priv->dma_maxburst,
2218 ENETDMAC_MAXBURST, priv->rx_chan);
2219 enet_dmac_writel(priv, priv->dma_maxburst,
2220 ENETDMAC_MAXBURST, priv->tx_chan);
2221
2222
2223 val = priv->rx_ring_size / 3;
2224 enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
2225 val = (priv->rx_ring_size * 2) / 3;
2226 enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
2227
2228
2229
2230
2231 wmb();
2232 enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
2233 enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
2234 ENETDMAC_CHANCFG, priv->rx_chan);
2235
2236
2237 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2238 ENETDMAC_IR, priv->rx_chan);
2239 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2240 ENETDMAC_IR, priv->tx_chan);
2241
2242
2243 napi_enable(&priv->napi);
2244
2245 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2246 ENETDMAC_IRMASK, priv->rx_chan);
2247 enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
2248 ENETDMAC_IRMASK, priv->tx_chan);
2249
2250 netif_carrier_on(dev);
2251 netif_start_queue(dev);
2252
2253
2254 for (i = 0; i < priv->num_ports; i++) {
2255 struct bcm63xx_enetsw_port *port;
2256 u8 override;
2257 port = &priv->used_ports[i];
2258 if (!port->used)
2259 continue;
2260
2261 if (!port->bypass_link)
2262 continue;
2263
2264 override = ENETSW_PORTOV_ENABLE_MASK |
2265 ENETSW_PORTOV_LINKUP_MASK;
2266
2267 switch (port->force_speed) {
2268 case 1000:
2269 override |= ENETSW_IMPOV_1000_MASK;
2270 break;
2271 case 100:
2272 override |= ENETSW_IMPOV_100_MASK;
2273 break;
2274 case 10:
2275 break;
2276 default:
2277 pr_warn("invalid forced speed on port %s: assume 10\n",
2278 port->name);
2279 break;
2280 }
2281
2282 if (port->force_duplex_full)
2283 override |= ENETSW_IMPOV_FDX_MASK;
2284
2285
2286 enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
2287 enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
2288 }
2289
2290
2291 timer_setup(&priv->swphy_poll, swphy_poll_timer, 0);
2292 mod_timer(&priv->swphy_poll, jiffies);
2293 return 0;
2294
2295out:
2296 for (i = 0; i < priv->rx_ring_size; i++) {
2297 struct bcm_enet_desc *desc;
2298
2299 if (!priv->rx_skb[i])
2300 continue;
2301
2302 desc = &priv->rx_desc_cpu[i];
2303 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2304 DMA_FROM_DEVICE);
2305 kfree_skb(priv->rx_skb[i]);
2306 }
2307 kfree(priv->rx_skb);
2308
2309out_free_tx_skb:
2310 kfree(priv->tx_skb);
2311
2312out_free_tx_ring:
2313 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2314 priv->tx_desc_cpu, priv->tx_desc_dma);
2315
2316out_free_rx_ring:
2317 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2318 priv->rx_desc_cpu, priv->rx_desc_dma);
2319
2320out_freeirq_tx:
2321 if (priv->irq_tx != -1)
2322 free_irq(priv->irq_tx, dev);
2323
2324out_freeirq_rx:
2325 free_irq(priv->irq_rx, dev);
2326
2327out_freeirq:
2328 return ret;
2329}
2330
2331
2332static int bcm_enetsw_stop(struct net_device *dev)
2333{
2334 struct bcm_enet_priv *priv;
2335 struct device *kdev;
2336 int i;
2337
2338 priv = netdev_priv(dev);
2339 kdev = &priv->pdev->dev;
2340
2341 del_timer_sync(&priv->swphy_poll);
2342 netif_stop_queue(dev);
2343 napi_disable(&priv->napi);
2344 del_timer_sync(&priv->rx_timeout);
2345
2346
2347 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->rx_chan);
2348 enet_dmac_writel(priv, 0, ENETDMAC_IRMASK, priv->tx_chan);
2349
2350
2351 bcm_enet_disable_dma(priv, priv->tx_chan);
2352 bcm_enet_disable_dma(priv, priv->rx_chan);
2353
2354
2355 bcm_enet_tx_reclaim(dev, 1);
2356
2357
2358 for (i = 0; i < priv->rx_ring_size; i++) {
2359 struct bcm_enet_desc *desc;
2360
2361 if (!priv->rx_skb[i])
2362 continue;
2363
2364 desc = &priv->rx_desc_cpu[i];
2365 dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
2366 DMA_FROM_DEVICE);
2367 kfree_skb(priv->rx_skb[i]);
2368 }
2369
2370
2371 kfree(priv->rx_skb);
2372 kfree(priv->tx_skb);
2373 dma_free_coherent(kdev, priv->rx_desc_alloc_size,
2374 priv->rx_desc_cpu, priv->rx_desc_dma);
2375 dma_free_coherent(kdev, priv->tx_desc_alloc_size,
2376 priv->tx_desc_cpu, priv->tx_desc_dma);
2377 if (priv->irq_tx != -1)
2378 free_irq(priv->irq_tx, dev);
2379 free_irq(priv->irq_rx, dev);
2380
2381 return 0;
2382}
2383
2384
2385
2386
2387
2388
2389static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
2390{
2391 int i;
2392
2393 for (i = 0; i < priv->num_ports; ++i) {
2394 if (!priv->used_ports[i].used)
2395 continue;
2396 if (priv->used_ports[i].phy_id == phy_id)
2397 return bcm_enet_port_is_rgmii(i);
2398 }
2399
2400 printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
2401 phy_id);
2402 return 1;
2403}
2404
2405
2406
2407
2408static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
2409 int location)
2410{
2411 struct bcm_enet_priv *priv;
2412
2413 priv = netdev_priv(dev);
2414 return bcmenet_sw_mdio_read(priv,
2415 bcm_enetsw_phy_is_external(priv, phy_id),
2416 phy_id, location);
2417}
2418
2419
2420
2421
2422static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
2423 int location,
2424 int val)
2425{
2426 struct bcm_enet_priv *priv;
2427
2428 priv = netdev_priv(dev);
2429 bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
2430 phy_id, location, val);
2431}
2432
2433static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2434{
2435 struct mii_if_info mii;
2436
2437 mii.dev = dev;
2438 mii.mdio_read = bcm_enetsw_mii_mdio_read;
2439 mii.mdio_write = bcm_enetsw_mii_mdio_write;
2440 mii.phy_id = 0;
2441 mii.phy_id_mask = 0x3f;
2442 mii.reg_num_mask = 0x1f;
2443 return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
2444
2445}
2446
2447static const struct net_device_ops bcm_enetsw_ops = {
2448 .ndo_open = bcm_enetsw_open,
2449 .ndo_stop = bcm_enetsw_stop,
2450 .ndo_start_xmit = bcm_enet_start_xmit,
2451 .ndo_change_mtu = bcm_enet_change_mtu,
2452 .ndo_do_ioctl = bcm_enetsw_ioctl,
2453};
2454
2455
2456static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
2457 { "rx_packets", DEV_STAT(rx_packets), -1 },
2458 { "tx_packets", DEV_STAT(tx_packets), -1 },
2459 { "rx_bytes", DEV_STAT(rx_bytes), -1 },
2460 { "tx_bytes", DEV_STAT(tx_bytes), -1 },
2461 { "rx_errors", DEV_STAT(rx_errors), -1 },
2462 { "tx_errors", DEV_STAT(tx_errors), -1 },
2463 { "rx_dropped", DEV_STAT(rx_dropped), -1 },
2464 { "tx_dropped", DEV_STAT(tx_dropped), -1 },
2465
2466 { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
2467 { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
2468 { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
2469 { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
2470 { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
2471 { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
2472 { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
2473 { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
2474 { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
2475 { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
2476 ETHSW_MIB_RX_1024_1522 },
2477 { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
2478 ETHSW_MIB_RX_1523_2047 },
2479 { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
2480 ETHSW_MIB_RX_2048_4095 },
2481 { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
2482 ETHSW_MIB_RX_4096_8191 },
2483 { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
2484 ETHSW_MIB_RX_8192_9728 },
2485 { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
2486 { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
2487 { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
2488 { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
2489 { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
2490
2491 { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
2492 { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
2493 { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
2494 { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
2495 { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
2496 { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
2497
2498};
2499
2500#define BCM_ENETSW_STATS_LEN \
2501 (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
2502
2503static void bcm_enetsw_get_strings(struct net_device *netdev,
2504 u32 stringset, u8 *data)
2505{
2506 int i;
2507
2508 switch (stringset) {
2509 case ETH_SS_STATS:
2510 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2511 memcpy(data + i * ETH_GSTRING_LEN,
2512 bcm_enetsw_gstrings_stats[i].stat_string,
2513 ETH_GSTRING_LEN);
2514 }
2515 break;
2516 }
2517}
2518
2519static int bcm_enetsw_get_sset_count(struct net_device *netdev,
2520 int string_set)
2521{
2522 switch (string_set) {
2523 case ETH_SS_STATS:
2524 return BCM_ENETSW_STATS_LEN;
2525 default:
2526 return -EINVAL;
2527 }
2528}
2529
2530static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
2531 struct ethtool_drvinfo *drvinfo)
2532{
2533 strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
2534 strncpy(drvinfo->version, bcm_enet_driver_version, 32);
2535 strncpy(drvinfo->fw_version, "N/A", 32);
2536 strncpy(drvinfo->bus_info, "bcm63xx", 32);
2537}
2538
2539static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
2540 struct ethtool_stats *stats,
2541 u64 *data)
2542{
2543 struct bcm_enet_priv *priv;
2544 int i;
2545
2546 priv = netdev_priv(netdev);
2547
2548 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2549 const struct bcm_enet_stats *s;
2550 u32 lo, hi;
2551 char *p;
2552 int reg;
2553
2554 s = &bcm_enetsw_gstrings_stats[i];
2555
2556 reg = s->mib_reg;
2557 if (reg == -1)
2558 continue;
2559
2560 lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
2561 p = (char *)priv + s->stat_offset;
2562
2563 if (s->sizeof_stat == sizeof(u64)) {
2564 hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
2565 *(u64 *)p = ((u64)hi << 32 | lo);
2566 } else {
2567 *(u32 *)p = lo;
2568 }
2569 }
2570
2571 for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
2572 const struct bcm_enet_stats *s;
2573 char *p;
2574
2575 s = &bcm_enetsw_gstrings_stats[i];
2576
2577 if (s->mib_reg == -1)
2578 p = (char *)&netdev->stats + s->stat_offset;
2579 else
2580 p = (char *)priv + s->stat_offset;
2581
2582 data[i] = (s->sizeof_stat == sizeof(u64)) ?
2583 *(u64 *)p : *(u32 *)p;
2584 }
2585}
2586
2587static void bcm_enetsw_get_ringparam(struct net_device *dev,
2588 struct ethtool_ringparam *ering)
2589{
2590 struct bcm_enet_priv *priv;
2591
2592 priv = netdev_priv(dev);
2593
2594
2595 ering->rx_max_pending = 8192;
2596 ering->tx_max_pending = 8192;
2597 ering->rx_mini_max_pending = 0;
2598 ering->rx_jumbo_max_pending = 0;
2599 ering->rx_pending = priv->rx_ring_size;
2600 ering->tx_pending = priv->tx_ring_size;
2601}
2602
2603static int bcm_enetsw_set_ringparam(struct net_device *dev,
2604 struct ethtool_ringparam *ering)
2605{
2606 struct bcm_enet_priv *priv;
2607 int was_running;
2608
2609 priv = netdev_priv(dev);
2610
2611 was_running = 0;
2612 if (netif_running(dev)) {
2613 bcm_enetsw_stop(dev);
2614 was_running = 1;
2615 }
2616
2617 priv->rx_ring_size = ering->rx_pending;
2618 priv->tx_ring_size = ering->tx_pending;
2619
2620 if (was_running) {
2621 int err;
2622
2623 err = bcm_enetsw_open(dev);
2624 if (err)
2625 dev_close(dev);
2626 }
2627 return 0;
2628}
2629
2630static const struct ethtool_ops bcm_enetsw_ethtool_ops = {
2631 .get_strings = bcm_enetsw_get_strings,
2632 .get_sset_count = bcm_enetsw_get_sset_count,
2633 .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
2634 .get_drvinfo = bcm_enetsw_get_drvinfo,
2635 .get_ringparam = bcm_enetsw_get_ringparam,
2636 .set_ringparam = bcm_enetsw_set_ringparam,
2637};
2638
2639
2640static int bcm_enetsw_probe(struct platform_device *pdev)
2641{
2642 struct bcm_enet_priv *priv;
2643 struct net_device *dev;
2644 struct bcm63xx_enetsw_platform_data *pd;
2645 struct resource *res_mem;
2646 int ret, irq_rx, irq_tx;
2647
2648 if (!bcm_enet_shared_base[0])
2649 return -EPROBE_DEFER;
2650
2651 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2652 irq_rx = platform_get_irq(pdev, 0);
2653 irq_tx = platform_get_irq(pdev, 1);
2654 if (!res_mem || irq_rx < 0)
2655 return -ENODEV;
2656
2657 ret = 0;
2658 dev = alloc_etherdev(sizeof(*priv));
2659 if (!dev)
2660 return -ENOMEM;
2661 priv = netdev_priv(dev);
2662 memset(priv, 0, sizeof(*priv));
2663
2664
2665 priv->enet_is_sw = true;
2666 priv->irq_rx = irq_rx;
2667 priv->irq_tx = irq_tx;
2668 priv->rx_ring_size = BCMENET_DEF_RX_DESC;
2669 priv->tx_ring_size = BCMENET_DEF_TX_DESC;
2670 priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
2671
2672 pd = dev_get_platdata(&pdev->dev);
2673 if (pd) {
2674 memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
2675 memcpy(priv->used_ports, pd->used_ports,
2676 sizeof(pd->used_ports));
2677 priv->num_ports = pd->num_ports;
2678 priv->dma_has_sram = pd->dma_has_sram;
2679 priv->dma_chan_en_mask = pd->dma_chan_en_mask;
2680 priv->dma_chan_int_mask = pd->dma_chan_int_mask;
2681 priv->dma_chan_width = pd->dma_chan_width;
2682 }
2683
2684 ret = bcm_enet_change_mtu(dev, dev->mtu);
2685 if (ret)
2686 goto out;
2687
2688 priv->base = devm_ioremap_resource(&pdev->dev, res_mem);
2689 if (IS_ERR(priv->base)) {
2690 ret = PTR_ERR(priv->base);
2691 goto out;
2692 }
2693
2694 priv->mac_clk = devm_clk_get(&pdev->dev, "enetsw");
2695 if (IS_ERR(priv->mac_clk)) {
2696 ret = PTR_ERR(priv->mac_clk);
2697 goto out;
2698 }
2699 ret = clk_prepare_enable(priv->mac_clk);
2700 if (ret)
2701 goto out;
2702
2703 priv->rx_chan = 0;
2704 priv->tx_chan = 1;
2705 spin_lock_init(&priv->rx_lock);
2706
2707
2708 timer_setup(&priv->rx_timeout, bcm_enet_refill_rx_timer, 0);
2709
2710
2711 dev->netdev_ops = &bcm_enetsw_ops;
2712 netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
2713 dev->ethtool_ops = &bcm_enetsw_ethtool_ops;
2714 SET_NETDEV_DEV(dev, &pdev->dev);
2715
2716 spin_lock_init(&priv->enetsw_mdio_lock);
2717
2718 ret = register_netdev(dev);
2719 if (ret)
2720 goto out_disable_clk;
2721
2722 netif_carrier_off(dev);
2723 platform_set_drvdata(pdev, dev);
2724 priv->pdev = pdev;
2725 priv->net_dev = dev;
2726
2727 return 0;
2728
2729out_disable_clk:
2730 clk_disable_unprepare(priv->mac_clk);
2731out:
2732 free_netdev(dev);
2733 return ret;
2734}
2735
2736
2737
2738static int bcm_enetsw_remove(struct platform_device *pdev)
2739{
2740 struct bcm_enet_priv *priv;
2741 struct net_device *dev;
2742
2743
2744 dev = platform_get_drvdata(pdev);
2745 priv = netdev_priv(dev);
2746 unregister_netdev(dev);
2747
2748 clk_disable_unprepare(priv->mac_clk);
2749
2750 free_netdev(dev);
2751 return 0;
2752}
2753
2754struct platform_driver bcm63xx_enetsw_driver = {
2755 .probe = bcm_enetsw_probe,
2756 .remove = bcm_enetsw_remove,
2757 .driver = {
2758 .name = "bcm63xx_enetsw",
2759 .owner = THIS_MODULE,
2760 },
2761};
2762
2763
2764static int bcm_enet_shared_probe(struct platform_device *pdev)
2765{
2766 struct resource *res;
2767 void __iomem *p[3];
2768 unsigned int i;
2769
2770 memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
2771
2772 for (i = 0; i < 3; i++) {
2773 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
2774 p[i] = devm_ioremap_resource(&pdev->dev, res);
2775 if (IS_ERR(p[i]))
2776 return PTR_ERR(p[i]);
2777 }
2778
2779 memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
2780
2781 return 0;
2782}
2783
2784static int bcm_enet_shared_remove(struct platform_device *pdev)
2785{
2786 return 0;
2787}
2788
2789
2790
2791
2792struct platform_driver bcm63xx_enet_shared_driver = {
2793 .probe = bcm_enet_shared_probe,
2794 .remove = bcm_enet_shared_remove,
2795 .driver = {
2796 .name = "bcm63xx_enet_shared",
2797 .owner = THIS_MODULE,
2798 },
2799};
2800
2801static struct platform_driver * const drivers[] = {
2802 &bcm63xx_enet_shared_driver,
2803 &bcm63xx_enet_driver,
2804 &bcm63xx_enetsw_driver,
2805};
2806
2807
2808static int __init bcm_enet_init(void)
2809{
2810 return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2811}
2812
2813static void __exit bcm_enet_exit(void)
2814{
2815 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2816}
2817
2818
2819module_init(bcm_enet_init);
2820module_exit(bcm_enet_exit);
2821
2822MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver");
2823MODULE_AUTHOR("Maxime Bizon <mbizon@freebox.fr>");
2824MODULE_LICENSE("GPL");
2825