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11#ifndef BNXT_H
12#define BNXT_H
13
14#define DRV_MODULE_NAME "bnxt_en"
15#define DRV_MODULE_VERSION "1.10.0"
16
17#define DRV_VER_MAJ 1
18#define DRV_VER_MIN 10
19#define DRV_VER_UPD 0
20
21#include <linux/interrupt.h>
22#include <linux/rhashtable.h>
23#include <linux/crash_dump.h>
24#include <net/devlink.h>
25#include <net/dst_metadata.h>
26#include <net/xdp.h>
27#include <linux/net_dim.h>
28
29struct tx_bd {
30 __le32 tx_bd_len_flags_type;
31 #define TX_BD_TYPE (0x3f << 0)
32 #define TX_BD_TYPE_SHORT_TX_BD (0x00 << 0)
33 #define TX_BD_TYPE_LONG_TX_BD (0x10 << 0)
34 #define TX_BD_FLAGS_PACKET_END (1 << 6)
35 #define TX_BD_FLAGS_NO_CMPL (1 << 7)
36 #define TX_BD_FLAGS_BD_CNT (0x1f << 8)
37 #define TX_BD_FLAGS_BD_CNT_SHIFT 8
38 #define TX_BD_FLAGS_LHINT (3 << 13)
39 #define TX_BD_FLAGS_LHINT_SHIFT 13
40 #define TX_BD_FLAGS_LHINT_512_AND_SMALLER (0 << 13)
41 #define TX_BD_FLAGS_LHINT_512_TO_1023 (1 << 13)
42 #define TX_BD_FLAGS_LHINT_1024_TO_2047 (2 << 13)
43 #define TX_BD_FLAGS_LHINT_2048_AND_LARGER (3 << 13)
44 #define TX_BD_FLAGS_COAL_NOW (1 << 15)
45 #define TX_BD_LEN (0xffff << 16)
46 #define TX_BD_LEN_SHIFT 16
47
48 u32 tx_bd_opaque;
49 __le64 tx_bd_haddr;
50} __packed;
51
52struct tx_bd_ext {
53 __le32 tx_bd_hsize_lflags;
54 #define TX_BD_FLAGS_TCP_UDP_CHKSUM (1 << 0)
55 #define TX_BD_FLAGS_IP_CKSUM (1 << 1)
56 #define TX_BD_FLAGS_NO_CRC (1 << 2)
57 #define TX_BD_FLAGS_STAMP (1 << 3)
58 #define TX_BD_FLAGS_T_IP_CHKSUM (1 << 4)
59 #define TX_BD_FLAGS_LSO (1 << 5)
60 #define TX_BD_FLAGS_IPID_FMT (1 << 6)
61 #define TX_BD_FLAGS_T_IPID (1 << 7)
62 #define TX_BD_HSIZE (0xff << 16)
63 #define TX_BD_HSIZE_SHIFT 16
64
65 __le32 tx_bd_mss;
66 __le32 tx_bd_cfa_action;
67 #define TX_BD_CFA_ACTION (0xffff << 16)
68 #define TX_BD_CFA_ACTION_SHIFT 16
69
70 __le32 tx_bd_cfa_meta;
71 #define TX_BD_CFA_META_MASK 0xfffffff
72 #define TX_BD_CFA_META_VID_MASK 0xfff
73 #define TX_BD_CFA_META_PRI_MASK (0xf << 12)
74 #define TX_BD_CFA_META_PRI_SHIFT 12
75 #define TX_BD_CFA_META_TPID_MASK (3 << 16)
76 #define TX_BD_CFA_META_TPID_SHIFT 16
77 #define TX_BD_CFA_META_KEY (0xf << 28)
78 #define TX_BD_CFA_META_KEY_SHIFT 28
79 #define TX_BD_CFA_META_KEY_VLAN (1 << 28)
80};
81
82struct rx_bd {
83 __le32 rx_bd_len_flags_type;
84 #define RX_BD_TYPE (0x3f << 0)
85 #define RX_BD_TYPE_RX_PACKET_BD 0x4
86 #define RX_BD_TYPE_RX_BUFFER_BD 0x5
87 #define RX_BD_TYPE_RX_AGG_BD 0x6
88 #define RX_BD_TYPE_16B_BD_SIZE (0 << 4)
89 #define RX_BD_TYPE_32B_BD_SIZE (1 << 4)
90 #define RX_BD_TYPE_48B_BD_SIZE (2 << 4)
91 #define RX_BD_TYPE_64B_BD_SIZE (3 << 4)
92 #define RX_BD_FLAGS_SOP (1 << 6)
93 #define RX_BD_FLAGS_EOP (1 << 7)
94 #define RX_BD_FLAGS_BUFFERS (3 << 8)
95 #define RX_BD_FLAGS_1_BUFFER_PACKET (0 << 8)
96 #define RX_BD_FLAGS_2_BUFFER_PACKET (1 << 8)
97 #define RX_BD_FLAGS_3_BUFFER_PACKET (2 << 8)
98 #define RX_BD_FLAGS_4_BUFFER_PACKET (3 << 8)
99 #define RX_BD_LEN (0xffff << 16)
100 #define RX_BD_LEN_SHIFT 16
101
102 u32 rx_bd_opaque;
103 __le64 rx_bd_haddr;
104};
105
106struct tx_cmp {
107 __le32 tx_cmp_flags_type;
108 #define CMP_TYPE (0x3f << 0)
109 #define CMP_TYPE_TX_L2_CMP 0
110 #define CMP_TYPE_RX_L2_CMP 17
111 #define CMP_TYPE_RX_AGG_CMP 18
112 #define CMP_TYPE_RX_L2_TPA_START_CMP 19
113 #define CMP_TYPE_RX_L2_TPA_END_CMP 21
114 #define CMP_TYPE_STATUS_CMP 32
115 #define CMP_TYPE_REMOTE_DRIVER_REQ 34
116 #define CMP_TYPE_REMOTE_DRIVER_RESP 36
117 #define CMP_TYPE_ERROR_STATUS 48
118 #define CMPL_BASE_TYPE_STAT_EJECT 0x1aUL
119 #define CMPL_BASE_TYPE_HWRM_DONE 0x20UL
120 #define CMPL_BASE_TYPE_HWRM_FWD_REQ 0x22UL
121 #define CMPL_BASE_TYPE_HWRM_FWD_RESP 0x24UL
122 #define CMPL_BASE_TYPE_HWRM_ASYNC_EVENT 0x2eUL
123
124 #define TX_CMP_FLAGS_ERROR (1 << 6)
125 #define TX_CMP_FLAGS_PUSH (1 << 7)
126
127 u32 tx_cmp_opaque;
128 __le32 tx_cmp_errors_v;
129 #define TX_CMP_V (1 << 0)
130 #define TX_CMP_ERRORS_BUFFER_ERROR (7 << 1)
131 #define TX_CMP_ERRORS_BUFFER_ERROR_NO_ERROR 0
132 #define TX_CMP_ERRORS_BUFFER_ERROR_BAD_FORMAT 2
133 #define TX_CMP_ERRORS_BUFFER_ERROR_INVALID_STAG 4
134 #define TX_CMP_ERRORS_BUFFER_ERROR_STAG_BOUNDS 5
135 #define TX_CMP_ERRORS_ZERO_LENGTH_PKT (1 << 4)
136 #define TX_CMP_ERRORS_EXCESSIVE_BD_LEN (1 << 5)
137 #define TX_CMP_ERRORS_DMA_ERROR (1 << 6)
138 #define TX_CMP_ERRORS_HINT_TOO_SHORT (1 << 7)
139
140 __le32 tx_cmp_unsed_3;
141};
142
143struct rx_cmp {
144 __le32 rx_cmp_len_flags_type;
145 #define RX_CMP_CMP_TYPE (0x3f << 0)
146 #define RX_CMP_FLAGS_ERROR (1 << 6)
147 #define RX_CMP_FLAGS_PLACEMENT (7 << 7)
148 #define RX_CMP_FLAGS_RSS_VALID (1 << 10)
149 #define RX_CMP_FLAGS_UNUSED (1 << 11)
150 #define RX_CMP_FLAGS_ITYPES_SHIFT 12
151 #define RX_CMP_FLAGS_ITYPE_UNKNOWN (0 << 12)
152 #define RX_CMP_FLAGS_ITYPE_IP (1 << 12)
153 #define RX_CMP_FLAGS_ITYPE_TCP (2 << 12)
154 #define RX_CMP_FLAGS_ITYPE_UDP (3 << 12)
155 #define RX_CMP_FLAGS_ITYPE_FCOE (4 << 12)
156 #define RX_CMP_FLAGS_ITYPE_ROCE (5 << 12)
157 #define RX_CMP_FLAGS_ITYPE_PTP_WO_TS (8 << 12)
158 #define RX_CMP_FLAGS_ITYPE_PTP_W_TS (9 << 12)
159 #define RX_CMP_LEN (0xffff << 16)
160 #define RX_CMP_LEN_SHIFT 16
161
162 u32 rx_cmp_opaque;
163 __le32 rx_cmp_misc_v1;
164 #define RX_CMP_V1 (1 << 0)
165 #define RX_CMP_AGG_BUFS (0x1f << 1)
166 #define RX_CMP_AGG_BUFS_SHIFT 1
167 #define RX_CMP_RSS_HASH_TYPE (0x7f << 9)
168 #define RX_CMP_RSS_HASH_TYPE_SHIFT 9
169 #define RX_CMP_PAYLOAD_OFFSET (0xff << 16)
170 #define RX_CMP_PAYLOAD_OFFSET_SHIFT 16
171
172 __le32 rx_cmp_rss_hash;
173};
174
175#define RX_CMP_HASH_VALID(rxcmp) \
176 ((rxcmp)->rx_cmp_len_flags_type & cpu_to_le32(RX_CMP_FLAGS_RSS_VALID))
177
178#define RSS_PROFILE_ID_MASK 0x1f
179
180#define RX_CMP_HASH_TYPE(rxcmp) \
181 (((le32_to_cpu((rxcmp)->rx_cmp_misc_v1) & RX_CMP_RSS_HASH_TYPE) >>\
182 RX_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
183
184struct rx_cmp_ext {
185 __le32 rx_cmp_flags2;
186 #define RX_CMP_FLAGS2_IP_CS_CALC 0x1
187 #define RX_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
188 #define RX_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
189 #define RX_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
190 #define RX_CMP_FLAGS2_META_FORMAT_VLAN (0x1 << 4)
191 __le32 rx_cmp_meta_data;
192 #define RX_CMP_FLAGS2_METADATA_TCI_MASK 0xffff
193 #define RX_CMP_FLAGS2_METADATA_VID_MASK 0xfff
194 #define RX_CMP_FLAGS2_METADATA_TPID_MASK 0xffff0000
195 #define RX_CMP_FLAGS2_METADATA_TPID_SFT 16
196 __le32 rx_cmp_cfa_code_errors_v2;
197 #define RX_CMP_V (1 << 0)
198 #define RX_CMPL_ERRORS_MASK (0x7fff << 1)
199 #define RX_CMPL_ERRORS_SFT 1
200 #define RX_CMPL_ERRORS_BUFFER_ERROR_MASK (0x7 << 1)
201 #define RX_CMPL_ERRORS_BUFFER_ERROR_NO_BUFFER (0x0 << 1)
202 #define RX_CMPL_ERRORS_BUFFER_ERROR_DID_NOT_FIT (0x1 << 1)
203 #define RX_CMPL_ERRORS_BUFFER_ERROR_NOT_ON_CHIP (0x2 << 1)
204 #define RX_CMPL_ERRORS_BUFFER_ERROR_BAD_FORMAT (0x3 << 1)
205 #define RX_CMPL_ERRORS_IP_CS_ERROR (0x1 << 4)
206 #define RX_CMPL_ERRORS_L4_CS_ERROR (0x1 << 5)
207 #define RX_CMPL_ERRORS_T_IP_CS_ERROR (0x1 << 6)
208 #define RX_CMPL_ERRORS_T_L4_CS_ERROR (0x1 << 7)
209 #define RX_CMPL_ERRORS_CRC_ERROR (0x1 << 8)
210 #define RX_CMPL_ERRORS_T_PKT_ERROR_MASK (0x7 << 9)
211 #define RX_CMPL_ERRORS_T_PKT_ERROR_NO_ERROR (0x0 << 9)
212 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_VERSION (0x1 << 9)
213 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_HDR_LEN (0x2 << 9)
214 #define RX_CMPL_ERRORS_T_PKT_ERROR_TUNNEL_TOTAL_ERROR (0x3 << 9)
215 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_IP_TOTAL_ERROR (0x4 << 9)
216 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_UDP_TOTAL_ERROR (0x5 << 9)
217 #define RX_CMPL_ERRORS_T_PKT_ERROR_T_L3_BAD_TTL (0x6 << 9)
218 #define RX_CMPL_ERRORS_PKT_ERROR_MASK (0xf << 12)
219 #define RX_CMPL_ERRORS_PKT_ERROR_NO_ERROR (0x0 << 12)
220 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_VERSION (0x1 << 12)
221 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_HDR_LEN (0x2 << 12)
222 #define RX_CMPL_ERRORS_PKT_ERROR_L3_BAD_TTL (0x3 << 12)
223 #define RX_CMPL_ERRORS_PKT_ERROR_IP_TOTAL_ERROR (0x4 << 12)
224 #define RX_CMPL_ERRORS_PKT_ERROR_UDP_TOTAL_ERROR (0x5 << 12)
225 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN (0x6 << 12)
226 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_HDR_LEN_TOO_SMALL (0x7 << 12)
227 #define RX_CMPL_ERRORS_PKT_ERROR_L4_BAD_OPT_LEN (0x8 << 12)
228
229 #define RX_CMPL_CFA_CODE_MASK (0xffff << 16)
230 #define RX_CMPL_CFA_CODE_SFT 16
231
232 __le32 rx_cmp_unused3;
233};
234
235#define RX_CMP_L2_ERRORS \
236 cpu_to_le32(RX_CMPL_ERRORS_BUFFER_ERROR_MASK | RX_CMPL_ERRORS_CRC_ERROR)
237
238#define RX_CMP_L4_CS_BITS \
239 (cpu_to_le32(RX_CMP_FLAGS2_L4_CS_CALC | RX_CMP_FLAGS2_T_L4_CS_CALC))
240
241#define RX_CMP_L4_CS_ERR_BITS \
242 (cpu_to_le32(RX_CMPL_ERRORS_L4_CS_ERROR | RX_CMPL_ERRORS_T_L4_CS_ERROR))
243
244#define RX_CMP_L4_CS_OK(rxcmp1) \
245 (((rxcmp1)->rx_cmp_flags2 & RX_CMP_L4_CS_BITS) && \
246 !((rxcmp1)->rx_cmp_cfa_code_errors_v2 & RX_CMP_L4_CS_ERR_BITS))
247
248#define RX_CMP_ENCAP(rxcmp1) \
249 ((le32_to_cpu((rxcmp1)->rx_cmp_flags2) & \
250 RX_CMP_FLAGS2_T_L4_CS_CALC) >> 3)
251
252#define RX_CMP_CFA_CODE(rxcmpl1) \
253 ((le32_to_cpu((rxcmpl1)->rx_cmp_cfa_code_errors_v2) & \
254 RX_CMPL_CFA_CODE_MASK) >> RX_CMPL_CFA_CODE_SFT)
255
256struct rx_agg_cmp {
257 __le32 rx_agg_cmp_len_flags_type;
258 #define RX_AGG_CMP_TYPE (0x3f << 0)
259 #define RX_AGG_CMP_LEN (0xffff << 16)
260 #define RX_AGG_CMP_LEN_SHIFT 16
261 u32 rx_agg_cmp_opaque;
262 __le32 rx_agg_cmp_v;
263 #define RX_AGG_CMP_V (1 << 0)
264 __le32 rx_agg_cmp_unused;
265};
266
267struct rx_tpa_start_cmp {
268 __le32 rx_tpa_start_cmp_len_flags_type;
269 #define RX_TPA_START_CMP_TYPE (0x3f << 0)
270 #define RX_TPA_START_CMP_FLAGS (0x3ff << 6)
271 #define RX_TPA_START_CMP_FLAGS_SHIFT 6
272 #define RX_TPA_START_CMP_FLAGS_PLACEMENT (0x7 << 7)
273 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_SHIFT 7
274 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
275 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
276 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
277 #define RX_TPA_START_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
278 #define RX_TPA_START_CMP_FLAGS_RSS_VALID (0x1 << 10)
279 #define RX_TPA_START_CMP_FLAGS_ITYPES (0xf << 12)
280 #define RX_TPA_START_CMP_FLAGS_ITYPES_SHIFT 12
281 #define RX_TPA_START_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
282 #define RX_TPA_START_CMP_LEN (0xffff << 16)
283 #define RX_TPA_START_CMP_LEN_SHIFT 16
284
285 u32 rx_tpa_start_cmp_opaque;
286 __le32 rx_tpa_start_cmp_misc_v1;
287 #define RX_TPA_START_CMP_V1 (0x1 << 0)
288 #define RX_TPA_START_CMP_RSS_HASH_TYPE (0x7f << 9)
289 #define RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT 9
290 #define RX_TPA_START_CMP_AGG_ID (0x7f << 25)
291 #define RX_TPA_START_CMP_AGG_ID_SHIFT 25
292
293 __le32 rx_tpa_start_cmp_rss_hash;
294};
295
296#define TPA_START_HASH_VALID(rx_tpa_start) \
297 ((rx_tpa_start)->rx_tpa_start_cmp_len_flags_type & \
298 cpu_to_le32(RX_TPA_START_CMP_FLAGS_RSS_VALID))
299
300#define TPA_START_HASH_TYPE(rx_tpa_start) \
301 (((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
302 RX_TPA_START_CMP_RSS_HASH_TYPE) >> \
303 RX_TPA_START_CMP_RSS_HASH_TYPE_SHIFT) & RSS_PROFILE_ID_MASK)
304
305#define TPA_START_AGG_ID(rx_tpa_start) \
306 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_misc_v1) & \
307 RX_TPA_START_CMP_AGG_ID) >> RX_TPA_START_CMP_AGG_ID_SHIFT)
308
309struct rx_tpa_start_cmp_ext {
310 __le32 rx_tpa_start_cmp_flags2;
311 #define RX_TPA_START_CMP_FLAGS2_IP_CS_CALC (0x1 << 0)
312 #define RX_TPA_START_CMP_FLAGS2_L4_CS_CALC (0x1 << 1)
313 #define RX_TPA_START_CMP_FLAGS2_T_IP_CS_CALC (0x1 << 2)
314 #define RX_TPA_START_CMP_FLAGS2_T_L4_CS_CALC (0x1 << 3)
315 #define RX_TPA_START_CMP_FLAGS2_IP_TYPE (0x1 << 8)
316
317 __le32 rx_tpa_start_cmp_metadata;
318 __le32 rx_tpa_start_cmp_cfa_code_v2;
319 #define RX_TPA_START_CMP_V2 (0x1 << 0)
320 #define RX_TPA_START_CMP_CFA_CODE (0xffff << 16)
321 #define RX_TPA_START_CMPL_CFA_CODE_SHIFT 16
322 __le32 rx_tpa_start_cmp_hdr_info;
323};
324
325#define TPA_START_CFA_CODE(rx_tpa_start) \
326 ((le32_to_cpu((rx_tpa_start)->rx_tpa_start_cmp_cfa_code_v2) & \
327 RX_TPA_START_CMP_CFA_CODE) >> RX_TPA_START_CMPL_CFA_CODE_SHIFT)
328
329#define TPA_START_IS_IPV6(rx_tpa_start) \
330 (!!((rx_tpa_start)->rx_tpa_start_cmp_flags2 & \
331 cpu_to_le32(RX_TPA_START_CMP_FLAGS2_IP_TYPE)))
332
333struct rx_tpa_end_cmp {
334 __le32 rx_tpa_end_cmp_len_flags_type;
335 #define RX_TPA_END_CMP_TYPE (0x3f << 0)
336 #define RX_TPA_END_CMP_FLAGS (0x3ff << 6)
337 #define RX_TPA_END_CMP_FLAGS_SHIFT 6
338 #define RX_TPA_END_CMP_FLAGS_PLACEMENT (0x7 << 7)
339 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_SHIFT 7
340 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_JUMBO (0x1 << 7)
341 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_HDS (0x2 << 7)
342 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO (0x5 << 7)
343 #define RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS (0x6 << 7)
344 #define RX_TPA_END_CMP_FLAGS_RSS_VALID (0x1 << 10)
345 #define RX_TPA_END_CMP_FLAGS_ITYPES (0xf << 12)
346 #define RX_TPA_END_CMP_FLAGS_ITYPES_SHIFT 12
347 #define RX_TPA_END_CMP_FLAGS_ITYPE_TCP (0x2 << 12)
348 #define RX_TPA_END_CMP_LEN (0xffff << 16)
349 #define RX_TPA_END_CMP_LEN_SHIFT 16
350
351 u32 rx_tpa_end_cmp_opaque;
352 __le32 rx_tpa_end_cmp_misc_v1;
353 #define RX_TPA_END_CMP_V1 (0x1 << 0)
354 #define RX_TPA_END_CMP_AGG_BUFS (0x3f << 1)
355 #define RX_TPA_END_CMP_AGG_BUFS_SHIFT 1
356 #define RX_TPA_END_CMP_TPA_SEGS (0xff << 8)
357 #define RX_TPA_END_CMP_TPA_SEGS_SHIFT 8
358 #define RX_TPA_END_CMP_PAYLOAD_OFFSET (0xff << 16)
359 #define RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT 16
360 #define RX_TPA_END_CMP_AGG_ID (0x7f << 25)
361 #define RX_TPA_END_CMP_AGG_ID_SHIFT 25
362
363 __le32 rx_tpa_end_cmp_tsdelta;
364 #define RX_TPA_END_GRO_TS (0x1 << 31)
365};
366
367#define TPA_END_AGG_ID(rx_tpa_end) \
368 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
369 RX_TPA_END_CMP_AGG_ID) >> RX_TPA_END_CMP_AGG_ID_SHIFT)
370
371#define TPA_END_TPA_SEGS(rx_tpa_end) \
372 ((le32_to_cpu((rx_tpa_end)->rx_tpa_end_cmp_misc_v1) & \
373 RX_TPA_END_CMP_TPA_SEGS) >> RX_TPA_END_CMP_TPA_SEGS_SHIFT)
374
375#define RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO \
376 cpu_to_le32(RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_JUMBO & \
377 RX_TPA_END_CMP_FLAGS_PLACEMENT_GRO_HDS)
378
379#define TPA_END_GRO(rx_tpa_end) \
380 ((rx_tpa_end)->rx_tpa_end_cmp_len_flags_type & \
381 RX_TPA_END_CMP_FLAGS_PLACEMENT_ANY_GRO)
382
383#define TPA_END_GRO_TS(rx_tpa_end) \
384 (!!((rx_tpa_end)->rx_tpa_end_cmp_tsdelta & \
385 cpu_to_le32(RX_TPA_END_GRO_TS)))
386
387struct rx_tpa_end_cmp_ext {
388 __le32 rx_tpa_end_cmp_dup_acks;
389 #define RX_TPA_END_CMP_TPA_DUP_ACKS (0xf << 0)
390
391 __le32 rx_tpa_end_cmp_seg_len;
392 #define RX_TPA_END_CMP_TPA_SEG_LEN (0xffff << 0)
393
394 __le32 rx_tpa_end_cmp_errors_v2;
395 #define RX_TPA_END_CMP_V2 (0x1 << 0)
396 #define RX_TPA_END_CMP_ERRORS (0x3 << 1)
397 #define RX_TPA_END_CMPL_ERRORS_SHIFT 1
398
399 u32 rx_tpa_end_cmp_start_opaque;
400};
401
402#define TPA_END_ERRORS(rx_tpa_end_ext) \
403 ((rx_tpa_end_ext)->rx_tpa_end_cmp_errors_v2 & \
404 cpu_to_le32(RX_TPA_END_CMP_ERRORS))
405
406struct nqe_cn {
407 __le16 type;
408 #define NQ_CN_TYPE_MASK 0x3fUL
409 #define NQ_CN_TYPE_SFT 0
410 #define NQ_CN_TYPE_CQ_NOTIFICATION 0x30UL
411 #define NQ_CN_TYPE_LAST NQ_CN_TYPE_CQ_NOTIFICATION
412 __le16 reserved16;
413 __le32 cq_handle_low;
414 __le32 v;
415 #define NQ_CN_V 0x1UL
416 __le32 cq_handle_high;
417};
418
419#define DB_IDX_MASK 0xffffff
420#define DB_IDX_VALID (0x1 << 26)
421#define DB_IRQ_DIS (0x1 << 27)
422#define DB_KEY_TX (0x0 << 28)
423#define DB_KEY_RX (0x1 << 28)
424#define DB_KEY_CP (0x2 << 28)
425#define DB_KEY_ST (0x3 << 28)
426#define DB_KEY_TX_PUSH (0x4 << 28)
427#define DB_LONG_TX_PUSH (0x2 << 24)
428
429#define BNXT_MIN_ROCE_CP_RINGS 2
430#define BNXT_MIN_ROCE_STAT_CTXS 1
431
432
433#define DBR_INDEX_MASK 0x0000000000ffffffULL
434#define DBR_XID_MASK 0x000fffff00000000ULL
435#define DBR_XID_SFT 32
436#define DBR_PATH_L2 (0x1ULL << 56)
437#define DBR_TYPE_SQ (0x0ULL << 60)
438#define DBR_TYPE_RQ (0x1ULL << 60)
439#define DBR_TYPE_SRQ (0x2ULL << 60)
440#define DBR_TYPE_SRQ_ARM (0x3ULL << 60)
441#define DBR_TYPE_CQ (0x4ULL << 60)
442#define DBR_TYPE_CQ_ARMSE (0x5ULL << 60)
443#define DBR_TYPE_CQ_ARMALL (0x6ULL << 60)
444#define DBR_TYPE_CQ_ARMENA (0x7ULL << 60)
445#define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60)
446#define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60)
447#define DBR_TYPE_NQ (0xaULL << 60)
448#define DBR_TYPE_NQ_ARM (0xbULL << 60)
449#define DBR_TYPE_NULL (0xfULL << 60)
450
451#define INVALID_HW_RING_ID ((u16)-1)
452
453
454
455
456#if (PAGE_SHIFT < 12)
457#define BNXT_PAGE_SHIFT 12
458#elif (PAGE_SHIFT <= 13)
459#define BNXT_PAGE_SHIFT PAGE_SHIFT
460#elif (PAGE_SHIFT < 16)
461#define BNXT_PAGE_SHIFT 13
462#else
463#define BNXT_PAGE_SHIFT 16
464#endif
465
466#define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT)
467
468
469#if (PAGE_SHIFT > 15)
470#define BNXT_RX_PAGE_SHIFT 15
471#else
472#define BNXT_RX_PAGE_SHIFT PAGE_SHIFT
473#endif
474
475#define BNXT_RX_PAGE_SIZE (1 << BNXT_RX_PAGE_SHIFT)
476
477#define BNXT_MAX_MTU 9500
478#define BNXT_MAX_PAGE_MODE_MTU \
479 ((unsigned int)PAGE_SIZE - VLAN_ETH_HLEN - NET_IP_ALIGN - \
480 XDP_PACKET_HEADROOM)
481
482#define BNXT_MIN_PKT_SIZE 52
483
484#define BNXT_DEFAULT_RX_RING_SIZE 511
485#define BNXT_DEFAULT_TX_RING_SIZE 511
486
487#define MAX_TPA 64
488
489#if (BNXT_PAGE_SHIFT == 16)
490#define MAX_RX_PAGES 1
491#define MAX_RX_AGG_PAGES 4
492#define MAX_TX_PAGES 1
493#define MAX_CP_PAGES 8
494#else
495#define MAX_RX_PAGES 8
496#define MAX_RX_AGG_PAGES 32
497#define MAX_TX_PAGES 8
498#define MAX_CP_PAGES 64
499#endif
500
501#define RX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct rx_bd))
502#define TX_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_bd))
503#define CP_DESC_CNT (BNXT_PAGE_SIZE / sizeof(struct tx_cmp))
504
505#define SW_RXBD_RING_SIZE (sizeof(struct bnxt_sw_rx_bd) * RX_DESC_CNT)
506#define HW_RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
507
508#define SW_RXBD_AGG_RING_SIZE (sizeof(struct bnxt_sw_rx_agg_bd) * RX_DESC_CNT)
509
510#define SW_TXBD_RING_SIZE (sizeof(struct bnxt_sw_tx_bd) * TX_DESC_CNT)
511#define HW_TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
512
513#define HW_CMPD_RING_SIZE (sizeof(struct tx_cmp) * CP_DESC_CNT)
514
515#define BNXT_MAX_RX_DESC_CNT (RX_DESC_CNT * MAX_RX_PAGES - 1)
516#define BNXT_MAX_RX_JUM_DESC_CNT (RX_DESC_CNT * MAX_RX_AGG_PAGES - 1)
517#define BNXT_MAX_TX_DESC_CNT (TX_DESC_CNT * MAX_TX_PAGES - 1)
518
519#define RX_RING(x) (((x) & ~(RX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
520#define RX_IDX(x) ((x) & (RX_DESC_CNT - 1))
521
522#define TX_RING(x) (((x) & ~(TX_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
523#define TX_IDX(x) ((x) & (TX_DESC_CNT - 1))
524
525#define CP_RING(x) (((x) & ~(CP_DESC_CNT - 1)) >> (BNXT_PAGE_SHIFT - 4))
526#define CP_IDX(x) ((x) & (CP_DESC_CNT - 1))
527
528#define TX_CMP_VALID(txcmp, raw_cons) \
529 (!!((txcmp)->tx_cmp_errors_v & cpu_to_le32(TX_CMP_V)) == \
530 !((raw_cons) & bp->cp_bit))
531
532#define RX_CMP_VALID(rxcmp1, raw_cons) \
533 (!!((rxcmp1)->rx_cmp_cfa_code_errors_v2 & cpu_to_le32(RX_CMP_V)) ==\
534 !((raw_cons) & bp->cp_bit))
535
536#define RX_AGG_CMP_VALID(agg, raw_cons) \
537 (!!((agg)->rx_agg_cmp_v & cpu_to_le32(RX_AGG_CMP_V)) == \
538 !((raw_cons) & bp->cp_bit))
539
540#define NQ_CMP_VALID(nqcmp, raw_cons) \
541 (!!((nqcmp)->v & cpu_to_le32(NQ_CN_V)) == !((raw_cons) & bp->cp_bit))
542
543#define TX_CMP_TYPE(txcmp) \
544 (le32_to_cpu((txcmp)->tx_cmp_flags_type) & CMP_TYPE)
545
546#define RX_CMP_TYPE(rxcmp) \
547 (le32_to_cpu((rxcmp)->rx_cmp_len_flags_type) & RX_CMP_CMP_TYPE)
548
549#define NEXT_RX(idx) (((idx) + 1) & bp->rx_ring_mask)
550
551#define NEXT_RX_AGG(idx) (((idx) + 1) & bp->rx_agg_ring_mask)
552
553#define NEXT_TX(idx) (((idx) + 1) & bp->tx_ring_mask)
554
555#define ADV_RAW_CMP(idx, n) ((idx) + (n))
556#define NEXT_RAW_CMP(idx) ADV_RAW_CMP(idx, 1)
557#define RING_CMP(idx) ((idx) & bp->cp_ring_mask)
558#define NEXT_CMP(idx) RING_CMP(ADV_RAW_CMP(idx, 1))
559
560#define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len)
561#define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input)
562#define DFLT_HWRM_CMD_TIMEOUT 500
563#define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout)
564#define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4)
565#define HWRM_RESP_ERR_CODE_MASK 0xffff
566#define HWRM_RESP_LEN_OFFSET 4
567#define HWRM_RESP_LEN_MASK 0xffff0000
568#define HWRM_RESP_LEN_SFT 16
569#define HWRM_RESP_VALID_MASK 0xff000000
570#define BNXT_HWRM_REQ_MAX_SIZE 128
571#define BNXT_HWRM_REQS_PER_PAGE (BNXT_PAGE_SIZE / \
572 BNXT_HWRM_REQ_MAX_SIZE)
573#define HWRM_SHORT_MIN_TIMEOUT 3
574#define HWRM_SHORT_MAX_TIMEOUT 10
575#define HWRM_SHORT_TIMEOUT_COUNTER 5
576
577#define HWRM_MIN_TIMEOUT 25
578#define HWRM_MAX_TIMEOUT 40
579
580#define HWRM_TOTAL_TIMEOUT(n) (((n) <= HWRM_SHORT_TIMEOUT_COUNTER) ? \
581 ((n) * HWRM_SHORT_MIN_TIMEOUT) : \
582 (HWRM_SHORT_TIMEOUT_COUNTER * HWRM_SHORT_MIN_TIMEOUT + \
583 ((n) - HWRM_SHORT_TIMEOUT_COUNTER) * HWRM_MIN_TIMEOUT))
584
585#define HWRM_VALID_BIT_DELAY_USEC 150
586
587#define BNXT_HWRM_CHNL_CHIMP 0
588#define BNXT_HWRM_CHNL_KONG 1
589
590#define BNXT_RX_EVENT 1
591#define BNXT_AGG_EVENT 2
592#define BNXT_TX_EVENT 4
593
594struct bnxt_sw_tx_bd {
595 struct sk_buff *skb;
596 DEFINE_DMA_UNMAP_ADDR(mapping);
597 u8 is_gso;
598 u8 is_push;
599 union {
600 unsigned short nr_frags;
601 u16 rx_prod;
602 };
603};
604
605struct bnxt_sw_rx_bd {
606 void *data;
607 u8 *data_ptr;
608 dma_addr_t mapping;
609};
610
611struct bnxt_sw_rx_agg_bd {
612 struct page *page;
613 unsigned int offset;
614 dma_addr_t mapping;
615};
616
617struct bnxt_ring_mem_info {
618 int nr_pages;
619 int page_size;
620 u16 flags;
621#define BNXT_RMEM_VALID_PTE_FLAG 1
622#define BNXT_RMEM_RING_PTE_FLAG 2
623#define BNXT_RMEM_USE_FULL_PAGE_FLAG 4
624
625 u16 depth;
626
627 void **pg_arr;
628 dma_addr_t *dma_arr;
629
630 __le64 *pg_tbl;
631 dma_addr_t pg_tbl_map;
632
633 int vmem_size;
634 void **vmem;
635};
636
637struct bnxt_ring_struct {
638 struct bnxt_ring_mem_info ring_mem;
639
640 u16 fw_ring_id;
641 union {
642 u16 grp_idx;
643 u16 map_idx;
644 };
645 u32 handle;
646 u8 queue_id;
647};
648
649struct tx_push_bd {
650 __le32 doorbell;
651 __le32 tx_bd_len_flags_type;
652 u32 tx_bd_opaque;
653 struct tx_bd_ext txbd2;
654};
655
656struct tx_push_buffer {
657 struct tx_push_bd push_bd;
658 u32 data[25];
659};
660
661struct bnxt_db_info {
662 void __iomem *doorbell;
663 union {
664 u64 db_key64;
665 u32 db_key32;
666 };
667};
668
669struct bnxt_tx_ring_info {
670 struct bnxt_napi *bnapi;
671 u16 tx_prod;
672 u16 tx_cons;
673 u16 txq_index;
674 struct bnxt_db_info tx_db;
675
676 struct tx_bd *tx_desc_ring[MAX_TX_PAGES];
677 struct bnxt_sw_tx_bd *tx_buf_ring;
678
679 dma_addr_t tx_desc_mapping[MAX_TX_PAGES];
680
681 struct tx_push_buffer *tx_push;
682 dma_addr_t tx_push_mapping;
683 __le64 data_mapping;
684
685#define BNXT_DEV_STATE_CLOSING 0x1
686 u32 dev_state;
687
688 struct bnxt_ring_struct tx_ring_struct;
689};
690
691#define BNXT_LEGACY_COAL_CMPL_PARAMS \
692 (RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MIN | \
693 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_INT_LAT_TMR_MAX | \
694 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_TIMER_RESET | \
695 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_RING_IDLE | \
696 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR | \
697 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_DMA_AGGR_DURING_INT | \
698 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR | \
699 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_CMPL_AGGR_DMA_TMR_DURING_INT | \
700 RING_AGGINT_QCAPS_RESP_CMPL_PARAMS_NUM_CMPL_AGGR_INT)
701
702#define BNXT_COAL_CMPL_ENABLES \
703 (RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR | \
704 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_CMPL_AGGR_DMA_TMR | \
705 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MAX | \
706 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_AGGR_INT)
707
708#define BNXT_COAL_CMPL_MIN_TMR_ENABLE \
709 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_INT_LAT_TMR_MIN
710
711#define BNXT_COAL_CMPL_AGGR_TMR_DURING_INT_ENABLE \
712 RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_ENABLES_NUM_CMPL_DMA_AGGR_DURING_INT
713
714struct bnxt_coal_cap {
715 u32 cmpl_params;
716 u32 nq_params;
717 u16 num_cmpl_dma_aggr_max;
718 u16 num_cmpl_dma_aggr_during_int_max;
719 u16 cmpl_aggr_dma_tmr_max;
720 u16 cmpl_aggr_dma_tmr_during_int_max;
721 u16 int_lat_tmr_min_max;
722 u16 int_lat_tmr_max_max;
723 u16 num_cmpl_aggr_int_max;
724 u16 timer_units;
725};
726
727struct bnxt_coal {
728 u16 coal_ticks;
729 u16 coal_ticks_irq;
730 u16 coal_bufs;
731 u16 coal_bufs_irq;
732
733 u16 idle_thresh;
734 u8 bufs_per_record;
735 u8 budget;
736};
737
738struct bnxt_tpa_info {
739 void *data;
740 u8 *data_ptr;
741 dma_addr_t mapping;
742 u16 len;
743 unsigned short gso_type;
744 u32 flags2;
745 u32 metadata;
746 enum pkt_hash_types hash_type;
747 u32 rss_hash;
748 u32 hdr_info;
749
750#define BNXT_TPA_L4_SIZE(hdr_info) \
751 (((hdr_info) & 0xf8000000) ? ((hdr_info) >> 27) : 32)
752
753#define BNXT_TPA_INNER_L3_OFF(hdr_info) \
754 (((hdr_info) >> 18) & 0x1ff)
755
756#define BNXT_TPA_INNER_L2_OFF(hdr_info) \
757 (((hdr_info) >> 9) & 0x1ff)
758
759#define BNXT_TPA_OUTER_L3_OFF(hdr_info) \
760 ((hdr_info) & 0x1ff)
761
762 u16 cfa_code;
763};
764
765struct bnxt_rx_ring_info {
766 struct bnxt_napi *bnapi;
767 u16 rx_prod;
768 u16 rx_agg_prod;
769 u16 rx_sw_agg_prod;
770 u16 rx_next_cons;
771 struct bnxt_db_info rx_db;
772 struct bnxt_db_info rx_agg_db;
773
774 struct bpf_prog *xdp_prog;
775
776 struct rx_bd *rx_desc_ring[MAX_RX_PAGES];
777 struct bnxt_sw_rx_bd *rx_buf_ring;
778
779 struct rx_bd *rx_agg_desc_ring[MAX_RX_AGG_PAGES];
780 struct bnxt_sw_rx_agg_bd *rx_agg_ring;
781
782 unsigned long *rx_agg_bmap;
783 u16 rx_agg_bmap_size;
784
785 struct page *rx_page;
786 unsigned int rx_page_offset;
787
788 dma_addr_t rx_desc_mapping[MAX_RX_PAGES];
789 dma_addr_t rx_agg_desc_mapping[MAX_RX_AGG_PAGES];
790
791 struct bnxt_tpa_info *rx_tpa;
792
793 struct bnxt_ring_struct rx_ring_struct;
794 struct bnxt_ring_struct rx_agg_ring_struct;
795 struct xdp_rxq_info xdp_rxq;
796};
797
798struct bnxt_cp_ring_info {
799 struct bnxt_napi *bnapi;
800 u32 cp_raw_cons;
801 struct bnxt_db_info cp_db;
802
803 u8 had_work_done:1;
804 u8 has_more_work:1;
805
806 u32 last_cp_raw_cons;
807
808 struct bnxt_coal rx_ring_coal;
809 u64 rx_packets;
810 u64 rx_bytes;
811 u64 event_ctr;
812
813 struct net_dim dim;
814
815 union {
816 struct tx_cmp *cp_desc_ring[MAX_CP_PAGES];
817 struct nqe_cn *nq_desc_ring[MAX_CP_PAGES];
818 };
819
820 dma_addr_t cp_desc_mapping[MAX_CP_PAGES];
821
822 struct ctx_hw_stats *hw_stats;
823 dma_addr_t hw_stats_map;
824 u32 hw_stats_ctx_id;
825 u64 rx_l4_csum_errors;
826 u64 missed_irqs;
827
828 struct bnxt_ring_struct cp_ring_struct;
829
830 struct bnxt_cp_ring_info *cp_ring_arr[2];
831#define BNXT_RX_HDL 0
832#define BNXT_TX_HDL 1
833};
834
835struct bnxt_napi {
836 struct napi_struct napi;
837 struct bnxt *bp;
838
839 int index;
840 struct bnxt_cp_ring_info cp_ring;
841 struct bnxt_rx_ring_info *rx_ring;
842 struct bnxt_tx_ring_info *tx_ring;
843
844 void (*tx_int)(struct bnxt *, struct bnxt_napi *,
845 int);
846 int tx_pkts;
847 u8 events;
848
849 u32 flags;
850#define BNXT_NAPI_FLAG_XDP 0x1
851
852 bool in_reset;
853};
854
855struct bnxt_irq {
856 irq_handler_t handler;
857 unsigned int vector;
858 u8 requested:1;
859 u8 have_cpumask:1;
860 char name[IFNAMSIZ + 2];
861 cpumask_var_t cpu_mask;
862};
863
864#define HWRM_RING_ALLOC_TX 0x1
865#define HWRM_RING_ALLOC_RX 0x2
866#define HWRM_RING_ALLOC_AGG 0x4
867#define HWRM_RING_ALLOC_CMPL 0x8
868#define HWRM_RING_ALLOC_NQ 0x10
869
870#define INVALID_STATS_CTX_ID -1
871
872struct bnxt_ring_grp_info {
873 u16 fw_stats_ctx;
874 u16 fw_grp_id;
875 u16 rx_fw_ring_id;
876 u16 agg_fw_ring_id;
877 u16 cp_fw_ring_id;
878};
879
880struct bnxt_vnic_info {
881 u16 fw_vnic_id;
882#define BNXT_MAX_CTX_PER_VNIC 8
883 u16 fw_rss_cos_lb_ctx[BNXT_MAX_CTX_PER_VNIC];
884 u16 fw_l2_ctx_id;
885#define BNXT_MAX_UC_ADDRS 4
886 __le64 fw_l2_filter_id[BNXT_MAX_UC_ADDRS];
887
888 u16 uc_filter_count;
889 u8 *uc_list;
890
891 u16 *fw_grp_ids;
892 dma_addr_t rss_table_dma_addr;
893 __le16 *rss_table;
894 dma_addr_t rss_hash_key_dma_addr;
895 u64 *rss_hash_key;
896 u32 rx_mask;
897
898 u8 *mc_list;
899 int mc_list_size;
900 int mc_list_count;
901 dma_addr_t mc_list_mapping;
902#define BNXT_MAX_MC_ADDRS 16
903
904 u32 flags;
905#define BNXT_VNIC_RSS_FLAG 1
906#define BNXT_VNIC_RFS_FLAG 2
907#define BNXT_VNIC_MCAST_FLAG 4
908#define BNXT_VNIC_UCAST_FLAG 8
909#define BNXT_VNIC_RFS_NEW_RSS_FLAG 0x10
910};
911
912struct bnxt_hw_resc {
913 u16 min_rsscos_ctxs;
914 u16 max_rsscos_ctxs;
915 u16 min_cp_rings;
916 u16 max_cp_rings;
917 u16 resv_cp_rings;
918 u16 min_tx_rings;
919 u16 max_tx_rings;
920 u16 resv_tx_rings;
921 u16 max_tx_sch_inputs;
922 u16 min_rx_rings;
923 u16 max_rx_rings;
924 u16 resv_rx_rings;
925 u16 min_hw_ring_grps;
926 u16 max_hw_ring_grps;
927 u16 resv_hw_ring_grps;
928 u16 min_l2_ctxs;
929 u16 max_l2_ctxs;
930 u16 min_vnics;
931 u16 max_vnics;
932 u16 resv_vnics;
933 u16 min_stat_ctxs;
934 u16 max_stat_ctxs;
935 u16 resv_stat_ctxs;
936 u16 max_nqs;
937 u16 max_irqs;
938 u16 resv_irqs;
939};
940
941#if defined(CONFIG_BNXT_SRIOV)
942struct bnxt_vf_info {
943 u16 fw_fid;
944 u8 mac_addr[ETH_ALEN];
945 u8 vf_mac_addr[ETH_ALEN];
946
947
948 u16 vlan;
949 u16 func_qcfg_flags;
950 u32 flags;
951#define BNXT_VF_QOS 0x1
952#define BNXT_VF_SPOOFCHK 0x2
953#define BNXT_VF_LINK_FORCED 0x4
954#define BNXT_VF_LINK_UP 0x8
955#define BNXT_VF_TRUST 0x10
956 u32 func_flags;
957 u32 min_tx_rate;
958 u32 max_tx_rate;
959 void *hwrm_cmd_req_addr;
960 dma_addr_t hwrm_cmd_req_dma_addr;
961};
962#endif
963
964struct bnxt_pf_info {
965#define BNXT_FIRST_PF_FID 1
966#define BNXT_FIRST_VF_FID 128
967 u16 fw_fid;
968 u16 port_id;
969 u8 mac_addr[ETH_ALEN];
970 u32 first_vf_id;
971 u16 active_vfs;
972 u16 max_vfs;
973 u32 max_encap_records;
974 u32 max_decap_records;
975 u32 max_tx_em_flows;
976 u32 max_tx_wm_flows;
977 u32 max_rx_em_flows;
978 u32 max_rx_wm_flows;
979 unsigned long *vf_event_bmap;
980 u16 hwrm_cmd_req_pages;
981 u8 vf_resv_strategy;
982#define BNXT_VF_RESV_STRATEGY_MAXIMAL 0
983#define BNXT_VF_RESV_STRATEGY_MINIMAL 1
984#define BNXT_VF_RESV_STRATEGY_MINIMAL_STATIC 2
985 void *hwrm_cmd_req_addr[4];
986 dma_addr_t hwrm_cmd_req_dma_addr[4];
987 struct bnxt_vf_info *vf;
988};
989
990struct bnxt_ntuple_filter {
991 struct hlist_node hash;
992 u8 dst_mac_addr[ETH_ALEN];
993 u8 src_mac_addr[ETH_ALEN];
994 struct flow_keys fkeys;
995 __le64 filter_id;
996 u16 sw_id;
997 u8 l2_fltr_idx;
998 u16 rxq;
999 u32 flow_id;
1000 unsigned long state;
1001#define BNXT_FLTR_VALID 0
1002#define BNXT_FLTR_UPDATE 1
1003};
1004
1005struct bnxt_link_info {
1006 u8 phy_type;
1007 u8 media_type;
1008 u8 transceiver;
1009 u8 phy_addr;
1010 u8 phy_link_status;
1011#define BNXT_LINK_NO_LINK PORT_PHY_QCFG_RESP_LINK_NO_LINK
1012#define BNXT_LINK_SIGNAL PORT_PHY_QCFG_RESP_LINK_SIGNAL
1013#define BNXT_LINK_LINK PORT_PHY_QCFG_RESP_LINK_LINK
1014 u8 wire_speed;
1015 u8 loop_back;
1016 u8 link_up;
1017 u8 duplex;
1018#define BNXT_LINK_DUPLEX_HALF PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF
1019#define BNXT_LINK_DUPLEX_FULL PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL
1020 u8 pause;
1021#define BNXT_LINK_PAUSE_TX PORT_PHY_QCFG_RESP_PAUSE_TX
1022#define BNXT_LINK_PAUSE_RX PORT_PHY_QCFG_RESP_PAUSE_RX
1023#define BNXT_LINK_PAUSE_BOTH (PORT_PHY_QCFG_RESP_PAUSE_RX | \
1024 PORT_PHY_QCFG_RESP_PAUSE_TX)
1025 u8 lp_pause;
1026 u8 auto_pause_setting;
1027 u8 force_pause_setting;
1028 u8 duplex_setting;
1029 u8 auto_mode;
1030#define BNXT_AUTO_MODE(mode) ((mode) > BNXT_LINK_AUTO_NONE && \
1031 (mode) <= BNXT_LINK_AUTO_MSK)
1032#define BNXT_LINK_AUTO_NONE PORT_PHY_QCFG_RESP_AUTO_MODE_NONE
1033#define BNXT_LINK_AUTO_ALLSPDS PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS
1034#define BNXT_LINK_AUTO_ONESPD PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED
1035#define BNXT_LINK_AUTO_ONEORBELOW PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW
1036#define BNXT_LINK_AUTO_MSK PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK
1037#define PHY_VER_LEN 3
1038 u8 phy_ver[PHY_VER_LEN];
1039 u16 link_speed;
1040#define BNXT_LINK_SPEED_100MB PORT_PHY_QCFG_RESP_LINK_SPEED_100MB
1041#define BNXT_LINK_SPEED_1GB PORT_PHY_QCFG_RESP_LINK_SPEED_1GB
1042#define BNXT_LINK_SPEED_2GB PORT_PHY_QCFG_RESP_LINK_SPEED_2GB
1043#define BNXT_LINK_SPEED_2_5GB PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB
1044#define BNXT_LINK_SPEED_10GB PORT_PHY_QCFG_RESP_LINK_SPEED_10GB
1045#define BNXT_LINK_SPEED_20GB PORT_PHY_QCFG_RESP_LINK_SPEED_20GB
1046#define BNXT_LINK_SPEED_25GB PORT_PHY_QCFG_RESP_LINK_SPEED_25GB
1047#define BNXT_LINK_SPEED_40GB PORT_PHY_QCFG_RESP_LINK_SPEED_40GB
1048#define BNXT_LINK_SPEED_50GB PORT_PHY_QCFG_RESP_LINK_SPEED_50GB
1049#define BNXT_LINK_SPEED_100GB PORT_PHY_QCFG_RESP_LINK_SPEED_100GB
1050 u16 support_speeds;
1051 u16 auto_link_speeds;
1052#define BNXT_LINK_SPEED_MSK_100MB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB
1053#define BNXT_LINK_SPEED_MSK_1GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB
1054#define BNXT_LINK_SPEED_MSK_2GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB
1055#define BNXT_LINK_SPEED_MSK_10GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB
1056#define BNXT_LINK_SPEED_MSK_2_5GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB
1057#define BNXT_LINK_SPEED_MSK_20GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB
1058#define BNXT_LINK_SPEED_MSK_25GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB
1059#define BNXT_LINK_SPEED_MSK_40GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB
1060#define BNXT_LINK_SPEED_MSK_50GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB
1061#define BNXT_LINK_SPEED_MSK_100GB PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB
1062 u16 support_auto_speeds;
1063 u16 lp_auto_link_speeds;
1064 u16 force_link_speed;
1065 u32 preemphasis;
1066 u8 module_status;
1067 u16 fec_cfg;
1068#define BNXT_FEC_AUTONEG PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED
1069#define BNXT_FEC_ENC_BASE_R PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED
1070#define BNXT_FEC_ENC_RS PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED
1071
1072
1073 u8 autoneg;
1074#define BNXT_AUTONEG_SPEED 1
1075#define BNXT_AUTONEG_FLOW_CTRL 2
1076 u8 req_duplex;
1077 u8 req_flow_ctrl;
1078 u16 req_link_speed;
1079 u16 advertising;
1080 bool force_link_chng;
1081
1082 bool phy_retry;
1083 unsigned long phy_retry_expires;
1084
1085
1086
1087
1088 struct hwrm_port_phy_qcfg_output phy_qcfg_resp;
1089};
1090
1091#define BNXT_MAX_QUEUE 8
1092
1093struct bnxt_queue_info {
1094 u8 queue_id;
1095 u8 queue_profile;
1096};
1097
1098#define BNXT_MAX_LED 4
1099
1100struct bnxt_led_info {
1101 u8 led_id;
1102 u8 led_type;
1103 u8 led_group_id;
1104 u8 unused;
1105 __le16 led_state_caps;
1106#define BNXT_LED_ALT_BLINK_CAP(x) ((x) & \
1107 cpu_to_le16(PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED))
1108
1109 __le16 led_color_caps;
1110};
1111
1112#define BNXT_MAX_TEST 8
1113
1114struct bnxt_test_info {
1115 u8 offline_mask;
1116 u8 flags;
1117#define BNXT_TEST_FL_EXT_LPBK 0x1
1118 u16 timeout;
1119 char string[BNXT_MAX_TEST][ETH_GSTRING_LEN];
1120};
1121
1122#define BNXT_GRCPF_REG_CHIMP_COMM 0x0
1123#define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100
1124#define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400
1125#define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014
1126#define BNXT_CAG_REG_BASE 0x300000
1127
1128#define BNXT_GRCPF_REG_KONG_COMM 0xA00
1129#define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00
1130
1131struct bnxt_tc_flow_stats {
1132 u64 packets;
1133 u64 bytes;
1134};
1135
1136struct bnxt_tc_info {
1137 bool enabled;
1138
1139
1140 struct rhashtable flow_table;
1141 struct rhashtable_params flow_ht_params;
1142
1143
1144 struct rhashtable l2_table;
1145 struct rhashtable_params l2_ht_params;
1146
1147 struct rhashtable decap_l2_table;
1148 struct rhashtable_params decap_l2_ht_params;
1149
1150 struct rhashtable decap_table;
1151 struct rhashtable_params decap_ht_params;
1152
1153 struct rhashtable encap_table;
1154 struct rhashtable_params encap_ht_params;
1155
1156
1157
1158
1159 struct mutex lock;
1160
1161
1162 struct rhashtable_iter iter;
1163#define BNXT_FLOW_STATS_BATCH_MAX 10
1164 struct bnxt_tc_stats_batch {
1165 void *flow_node;
1166 struct bnxt_tc_flow_stats hw_stats;
1167 } stats_batch[BNXT_FLOW_STATS_BATCH_MAX];
1168
1169
1170 u64 bytes_mask;
1171 u64 packets_mask;
1172};
1173
1174struct bnxt_vf_rep_stats {
1175 u64 packets;
1176 u64 bytes;
1177 u64 dropped;
1178};
1179
1180struct bnxt_vf_rep {
1181 struct bnxt *bp;
1182 struct net_device *dev;
1183 struct metadata_dst *dst;
1184 u16 vf_idx;
1185 u16 tx_cfa_action;
1186 u16 rx_cfa_code;
1187
1188 struct bnxt_vf_rep_stats rx_stats;
1189 struct bnxt_vf_rep_stats tx_stats;
1190};
1191
1192#define PTU_PTE_VALID 0x1UL
1193#define PTU_PTE_LAST 0x2UL
1194#define PTU_PTE_NEXT_TO_LAST 0x4UL
1195
1196#define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8)
1197#define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES)
1198
1199struct bnxt_ctx_pg_info {
1200 u32 entries;
1201 u32 nr_pages;
1202 void *ctx_pg_arr[MAX_CTX_PAGES];
1203 dma_addr_t ctx_dma_arr[MAX_CTX_PAGES];
1204 struct bnxt_ring_mem_info ring_mem;
1205 struct bnxt_ctx_pg_info **ctx_pg_tbl;
1206};
1207
1208struct bnxt_ctx_mem_info {
1209 u32 qp_max_entries;
1210 u16 qp_min_qp1_entries;
1211 u16 qp_max_l2_entries;
1212 u16 qp_entry_size;
1213 u16 srq_max_l2_entries;
1214 u32 srq_max_entries;
1215 u16 srq_entry_size;
1216 u16 cq_max_l2_entries;
1217 u32 cq_max_entries;
1218 u16 cq_entry_size;
1219 u16 vnic_max_vnic_entries;
1220 u16 vnic_max_ring_table_entries;
1221 u16 vnic_entry_size;
1222 u32 stat_max_entries;
1223 u16 stat_entry_size;
1224 u16 tqm_entry_size;
1225 u32 tqm_min_entries_per_ring;
1226 u32 tqm_max_entries_per_ring;
1227 u32 mrav_max_entries;
1228 u16 mrav_entry_size;
1229 u16 tim_entry_size;
1230 u32 tim_max_entries;
1231 u16 mrav_num_entries_units;
1232 u8 tqm_entries_multiple;
1233
1234 u32 flags;
1235 #define BNXT_CTX_FLAG_INITED 0x01
1236
1237 struct bnxt_ctx_pg_info qp_mem;
1238 struct bnxt_ctx_pg_info srq_mem;
1239 struct bnxt_ctx_pg_info cq_mem;
1240 struct bnxt_ctx_pg_info vnic_mem;
1241 struct bnxt_ctx_pg_info stat_mem;
1242 struct bnxt_ctx_pg_info mrav_mem;
1243 struct bnxt_ctx_pg_info tim_mem;
1244 struct bnxt_ctx_pg_info *tqm_mem[9];
1245};
1246
1247struct bnxt {
1248 void __iomem *bar0;
1249 void __iomem *bar1;
1250 void __iomem *bar2;
1251
1252 u32 reg_base;
1253 u16 chip_num;
1254#define CHIP_NUM_57301 0x16c8
1255#define CHIP_NUM_57302 0x16c9
1256#define CHIP_NUM_57304 0x16ca
1257#define CHIP_NUM_58700 0x16cd
1258#define CHIP_NUM_57402 0x16d0
1259#define CHIP_NUM_57404 0x16d1
1260#define CHIP_NUM_57406 0x16d2
1261#define CHIP_NUM_57407 0x16d5
1262
1263#define CHIP_NUM_57311 0x16ce
1264#define CHIP_NUM_57312 0x16cf
1265#define CHIP_NUM_57314 0x16df
1266#define CHIP_NUM_57317 0x16e0
1267#define CHIP_NUM_57412 0x16d6
1268#define CHIP_NUM_57414 0x16d7
1269#define CHIP_NUM_57416 0x16d8
1270#define CHIP_NUM_57417 0x16d9
1271#define CHIP_NUM_57412L 0x16da
1272#define CHIP_NUM_57414L 0x16db
1273
1274#define CHIP_NUM_5745X 0xd730
1275
1276#define CHIP_NUM_57500 0x1750
1277
1278#define CHIP_NUM_58802 0xd802
1279#define CHIP_NUM_58804 0xd804
1280#define CHIP_NUM_58808 0xd808
1281
1282#define BNXT_CHIP_NUM_5730X(chip_num) \
1283 ((chip_num) >= CHIP_NUM_57301 && \
1284 (chip_num) <= CHIP_NUM_57304)
1285
1286#define BNXT_CHIP_NUM_5740X(chip_num) \
1287 (((chip_num) >= CHIP_NUM_57402 && \
1288 (chip_num) <= CHIP_NUM_57406) || \
1289 (chip_num) == CHIP_NUM_57407)
1290
1291#define BNXT_CHIP_NUM_5731X(chip_num) \
1292 ((chip_num) == CHIP_NUM_57311 || \
1293 (chip_num) == CHIP_NUM_57312 || \
1294 (chip_num) == CHIP_NUM_57314 || \
1295 (chip_num) == CHIP_NUM_57317)
1296
1297#define BNXT_CHIP_NUM_5741X(chip_num) \
1298 ((chip_num) >= CHIP_NUM_57412 && \
1299 (chip_num) <= CHIP_NUM_57414L)
1300
1301#define BNXT_CHIP_NUM_58700(chip_num) \
1302 ((chip_num) == CHIP_NUM_58700)
1303
1304#define BNXT_CHIP_NUM_5745X(chip_num) \
1305 ((chip_num) == CHIP_NUM_5745X)
1306
1307#define BNXT_CHIP_NUM_57X0X(chip_num) \
1308 (BNXT_CHIP_NUM_5730X(chip_num) || BNXT_CHIP_NUM_5740X(chip_num))
1309
1310#define BNXT_CHIP_NUM_57X1X(chip_num) \
1311 (BNXT_CHIP_NUM_5731X(chip_num) || BNXT_CHIP_NUM_5741X(chip_num))
1312
1313#define BNXT_CHIP_NUM_588XX(chip_num) \
1314 ((chip_num) == CHIP_NUM_58802 || \
1315 (chip_num) == CHIP_NUM_58804 || \
1316 (chip_num) == CHIP_NUM_58808)
1317
1318 struct net_device *dev;
1319 struct pci_dev *pdev;
1320
1321 atomic_t intr_sem;
1322
1323 u32 flags;
1324 #define BNXT_FLAG_CHIP_P5 0x1
1325 #define BNXT_FLAG_VF 0x2
1326 #define BNXT_FLAG_LRO 0x4
1327#ifdef CONFIG_INET
1328 #define BNXT_FLAG_GRO 0x8
1329#else
1330
1331 #define BNXT_FLAG_GRO 0x0
1332#endif
1333 #define BNXT_FLAG_TPA (BNXT_FLAG_LRO | BNXT_FLAG_GRO)
1334 #define BNXT_FLAG_JUMBO 0x10
1335 #define BNXT_FLAG_STRIP_VLAN 0x20
1336 #define BNXT_FLAG_AGG_RINGS (BNXT_FLAG_JUMBO | BNXT_FLAG_GRO | \
1337 BNXT_FLAG_LRO)
1338 #define BNXT_FLAG_USING_MSIX 0x40
1339 #define BNXT_FLAG_MSIX_CAP 0x80
1340 #define BNXT_FLAG_RFS 0x100
1341 #define BNXT_FLAG_SHARED_RINGS 0x200
1342 #define BNXT_FLAG_PORT_STATS 0x400
1343 #define BNXT_FLAG_UDP_RSS_CAP 0x800
1344 #define BNXT_FLAG_EEE_CAP 0x1000
1345 #define BNXT_FLAG_NEW_RSS_CAP 0x2000
1346 #define BNXT_FLAG_WOL_CAP 0x4000
1347 #define BNXT_FLAG_ROCEV1_CAP 0x8000
1348 #define BNXT_FLAG_ROCEV2_CAP 0x10000
1349 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | \
1350 BNXT_FLAG_ROCEV2_CAP)
1351 #define BNXT_FLAG_NO_AGG_RINGS 0x20000
1352 #define BNXT_FLAG_RX_PAGE_MODE 0x40000
1353 #define BNXT_FLAG_MULTI_HOST 0x100000
1354 #define BNXT_FLAG_DOUBLE_DB 0x400000
1355 #define BNXT_FLAG_CHIP_NITRO_A0 0x1000000
1356 #define BNXT_FLAG_DIM 0x2000000
1357 #define BNXT_FLAG_ROCE_MIRROR_CAP 0x4000000
1358 #define BNXT_FLAG_PORT_STATS_EXT 0x10000000
1359 #define BNXT_FLAG_PCIE_STATS 0x40000000
1360
1361 #define BNXT_FLAG_ALL_CONFIG_FEATS (BNXT_FLAG_TPA | \
1362 BNXT_FLAG_RFS | \
1363 BNXT_FLAG_STRIP_VLAN)
1364
1365#define BNXT_PF(bp) (!((bp)->flags & BNXT_FLAG_VF))
1366#define BNXT_VF(bp) ((bp)->flags & BNXT_FLAG_VF)
1367#define BNXT_NPAR(bp) ((bp)->port_partition_type)
1368#define BNXT_MH(bp) ((bp)->flags & BNXT_FLAG_MULTI_HOST)
1369#define BNXT_SINGLE_PF(bp) (BNXT_PF(bp) && !BNXT_NPAR(bp) && !BNXT_MH(bp))
1370#define BNXT_CHIP_TYPE_NITRO_A0(bp) ((bp)->flags & BNXT_FLAG_CHIP_NITRO_A0)
1371#define BNXT_RX_PAGE_MODE(bp) ((bp)->flags & BNXT_FLAG_RX_PAGE_MODE)
1372#define BNXT_SUPPORTS_TPA(bp) (!BNXT_CHIP_TYPE_NITRO_A0(bp) && \
1373 !(bp->flags & BNXT_FLAG_CHIP_P5) && \
1374 !is_kdump_kernel())
1375
1376
1377#define BNXT_CHIP_P5(bp) \
1378 ((bp)->chip_num == CHIP_NUM_57500)
1379
1380
1381#define BNXT_CHIP_P4(bp) \
1382 (BNXT_CHIP_NUM_57X1X((bp)->chip_num) || \
1383 BNXT_CHIP_NUM_5745X((bp)->chip_num) || \
1384 BNXT_CHIP_NUM_588XX((bp)->chip_num) || \
1385 (BNXT_CHIP_NUM_58700((bp)->chip_num) && \
1386 !BNXT_CHIP_TYPE_NITRO_A0(bp)))
1387
1388#define BNXT_CHIP_P4_PLUS(bp) \
1389 (BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))
1390
1391 struct bnxt_en_dev *edev;
1392 struct bnxt_en_dev * (*ulp_probe)(struct net_device *);
1393
1394 struct bnxt_napi **bnapi;
1395
1396 struct bnxt_rx_ring_info *rx_ring;
1397 struct bnxt_tx_ring_info *tx_ring;
1398 u16 *tx_ring_map;
1399
1400 struct sk_buff * (*gro_func)(struct bnxt_tpa_info *, int, int,
1401 struct sk_buff *);
1402
1403 struct sk_buff * (*rx_skb_func)(struct bnxt *,
1404 struct bnxt_rx_ring_info *,
1405 u16, void *, u8 *, dma_addr_t,
1406 unsigned int);
1407
1408 u32 rx_buf_size;
1409 u32 rx_buf_use_size;
1410 u16 rx_offset;
1411 u16 rx_dma_offset;
1412 enum dma_data_direction rx_dir;
1413 u32 rx_ring_size;
1414 u32 rx_agg_ring_size;
1415 u32 rx_copy_thresh;
1416 u32 rx_ring_mask;
1417 u32 rx_agg_ring_mask;
1418 int rx_nr_pages;
1419 int rx_agg_nr_pages;
1420 int rx_nr_rings;
1421 int rsscos_nr_ctxs;
1422
1423 u32 tx_ring_size;
1424 u32 tx_ring_mask;
1425 int tx_nr_pages;
1426 int tx_nr_rings;
1427 int tx_nr_rings_per_tc;
1428 int tx_nr_rings_xdp;
1429
1430 int tx_wake_thresh;
1431 int tx_push_thresh;
1432 int tx_push_size;
1433
1434 u32 cp_ring_size;
1435 u32 cp_ring_mask;
1436 u32 cp_bit;
1437 int cp_nr_pages;
1438 int cp_nr_rings;
1439
1440
1441 struct bnxt_ring_grp_info *grp_info;
1442 struct bnxt_vnic_info *vnic_info;
1443 int nr_vnics;
1444 u32 rss_hash_cfg;
1445
1446 u16 max_mtu;
1447 u8 max_tc;
1448 u8 max_lltc;
1449 struct bnxt_queue_info q_info[BNXT_MAX_QUEUE];
1450 u8 tc_to_qidx[BNXT_MAX_QUEUE];
1451 u8 q_ids[BNXT_MAX_QUEUE];
1452 u8 max_q;
1453
1454 unsigned int current_interval;
1455#define BNXT_TIMER_INTERVAL HZ
1456
1457 struct timer_list timer;
1458
1459 unsigned long state;
1460#define BNXT_STATE_OPEN 0
1461#define BNXT_STATE_IN_SP_TASK 1
1462#define BNXT_STATE_READ_STATS 2
1463
1464 struct bnxt_irq *irq_tbl;
1465 int total_irqs;
1466 u8 mac_addr[ETH_ALEN];
1467
1468#ifdef CONFIG_BNXT_DCB
1469 struct ieee_pfc *ieee_pfc;
1470 struct ieee_ets *ieee_ets;
1471 u8 dcbx_cap;
1472 u8 default_pri;
1473 u8 max_dscp_value;
1474#endif
1475
1476 u32 msg_enable;
1477
1478 u32 fw_cap;
1479 #define BNXT_FW_CAP_SHORT_CMD 0x00000001
1480 #define BNXT_FW_CAP_LLDP_AGENT 0x00000002
1481 #define BNXT_FW_CAP_DCBX_AGENT 0x00000004
1482 #define BNXT_FW_CAP_NEW_RM 0x00000008
1483 #define BNXT_FW_CAP_IF_CHANGE 0x00000010
1484 #define BNXT_FW_CAP_KONG_MB_CHNL 0x00000080
1485 #define BNXT_FW_CAP_OVS_64BIT_HANDLE 0x00000400
1486 #define BNXT_FW_CAP_TRUSTED_VF 0x00000800
1487 #define BNXT_FW_CAP_PKG_VER 0x00004000
1488 #define BNXT_FW_CAP_CFA_ADV_FLOW 0x00008000
1489 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX 0x00010000
1490 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED 0x00020000
1491 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED 0x00040000
1492
1493#define BNXT_NEW_RM(bp) ((bp)->fw_cap & BNXT_FW_CAP_NEW_RM)
1494 u32 hwrm_spec_code;
1495 u16 hwrm_cmd_seq;
1496 u16 hwrm_cmd_kong_seq;
1497 u16 hwrm_intr_seq_id;
1498 void *hwrm_short_cmd_req_addr;
1499 dma_addr_t hwrm_short_cmd_req_dma_addr;
1500 void *hwrm_cmd_resp_addr;
1501 dma_addr_t hwrm_cmd_resp_dma_addr;
1502 void *hwrm_cmd_kong_resp_addr;
1503 dma_addr_t hwrm_cmd_kong_resp_dma_addr;
1504
1505 struct rtnl_link_stats64 net_stats_prev;
1506 struct rx_port_stats *hw_rx_port_stats;
1507 struct tx_port_stats *hw_tx_port_stats;
1508 struct rx_port_stats_ext *hw_rx_port_stats_ext;
1509 struct tx_port_stats_ext *hw_tx_port_stats_ext;
1510 struct pcie_ctx_hw_stats *hw_pcie_stats;
1511 dma_addr_t hw_rx_port_stats_map;
1512 dma_addr_t hw_tx_port_stats_map;
1513 dma_addr_t hw_rx_port_stats_ext_map;
1514 dma_addr_t hw_tx_port_stats_ext_map;
1515 dma_addr_t hw_pcie_stats_map;
1516 int hw_port_stats_size;
1517 u16 fw_rx_stats_ext_size;
1518 u16 fw_tx_stats_ext_size;
1519 u8 pri2cos[8];
1520 u8 pri2cos_valid;
1521
1522 u16 hwrm_max_req_len;
1523 u16 hwrm_max_ext_req_len;
1524 int hwrm_cmd_timeout;
1525 struct mutex hwrm_cmd_lock;
1526 struct hwrm_ver_get_output ver_resp;
1527#define FW_VER_STR_LEN 32
1528#define BC_HWRM_STR_LEN 21
1529#define PHY_VER_STR_LEN (FW_VER_STR_LEN - BC_HWRM_STR_LEN)
1530 char fw_ver_str[FW_VER_STR_LEN];
1531 __be16 vxlan_port;
1532 u8 vxlan_port_cnt;
1533 __le16 vxlan_fw_dst_port_id;
1534 __be16 nge_port;
1535 u8 nge_port_cnt;
1536 __le16 nge_fw_dst_port_id;
1537 u8 port_partition_type;
1538 u8 port_count;
1539 u16 br_mode;
1540
1541 struct bnxt_coal_cap coal_cap;
1542 struct bnxt_coal rx_coal;
1543 struct bnxt_coal tx_coal;
1544
1545 u32 stats_coal_ticks;
1546#define BNXT_DEF_STATS_COAL_TICKS 1000000
1547#define BNXT_MIN_STATS_COAL_TICKS 250000
1548#define BNXT_MAX_STATS_COAL_TICKS 1000000
1549
1550 struct work_struct sp_task;
1551 unsigned long sp_event;
1552#define BNXT_RX_MASK_SP_EVENT 0
1553#define BNXT_RX_NTP_FLTR_SP_EVENT 1
1554#define BNXT_LINK_CHNG_SP_EVENT 2
1555#define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3
1556#define BNXT_VXLAN_ADD_PORT_SP_EVENT 4
1557#define BNXT_VXLAN_DEL_PORT_SP_EVENT 5
1558#define BNXT_RESET_TASK_SP_EVENT 6
1559#define BNXT_RST_RING_SP_EVENT 7
1560#define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8
1561#define BNXT_PERIODIC_STATS_SP_EVENT 9
1562#define BNXT_HWRM_PORT_MODULE_SP_EVENT 10
1563#define BNXT_RESET_TASK_SILENT_SP_EVENT 11
1564#define BNXT_GENEVE_ADD_PORT_SP_EVENT 12
1565#define BNXT_GENEVE_DEL_PORT_SP_EVENT 13
1566#define BNXT_LINK_SPEED_CHNG_SP_EVENT 14
1567#define BNXT_FLOW_STATS_SP_EVENT 15
1568#define BNXT_UPDATE_PHY_SP_EVENT 16
1569#define BNXT_RING_COAL_NOW_SP_EVENT 17
1570
1571 struct bnxt_hw_resc hw_resc;
1572 struct bnxt_pf_info pf;
1573 struct bnxt_ctx_mem_info *ctx;
1574#ifdef CONFIG_BNXT_SRIOV
1575 int nr_vfs;
1576 struct bnxt_vf_info vf;
1577 wait_queue_head_t sriov_cfg_wait;
1578 bool sriov_cfg;
1579#define BNXT_SRIOV_CFG_WAIT_TMO msecs_to_jiffies(10000)
1580
1581
1582
1583
1584
1585 struct mutex sriov_lock;
1586#endif
1587
1588#if BITS_PER_LONG == 32
1589
1590 spinlock_t db_lock;
1591#endif
1592
1593#define BNXT_NTP_FLTR_MAX_FLTR 4096
1594#define BNXT_NTP_FLTR_HASH_SIZE 512
1595#define BNXT_NTP_FLTR_HASH_MASK (BNXT_NTP_FLTR_HASH_SIZE - 1)
1596 struct hlist_head ntp_fltr_hash_tbl[BNXT_NTP_FLTR_HASH_SIZE];
1597 spinlock_t ntp_fltr_lock;
1598
1599 unsigned long *ntp_fltr_bmap;
1600 int ntp_fltr_count;
1601
1602
1603
1604
1605 struct mutex link_lock;
1606 struct bnxt_link_info link_info;
1607 struct ethtool_eee eee;
1608 u32 lpi_tmr_lo;
1609 u32 lpi_tmr_hi;
1610
1611 u8 num_tests;
1612 struct bnxt_test_info *test_info;
1613
1614 u8 wol_filter_id;
1615 u8 wol;
1616
1617 u8 num_leds;
1618 struct bnxt_led_info leds[BNXT_MAX_LED];
1619
1620 struct bpf_prog *xdp_prog;
1621
1622
1623 struct devlink *dl;
1624 struct devlink_port dl_port;
1625 enum devlink_eswitch_mode eswitch_mode;
1626 struct bnxt_vf_rep **vf_reps;
1627 u16 *cfa_code_map;
1628 u8 switch_id[8];
1629 struct bnxt_tc_info *tc_info;
1630 struct dentry *debugfs_pdev;
1631 struct dentry *debugfs_dim;
1632 struct device *hwmon_dev;
1633};
1634
1635#define BNXT_RX_STATS_OFFSET(counter) \
1636 (offsetof(struct rx_port_stats, counter) / 8)
1637
1638#define BNXT_TX_STATS_OFFSET(counter) \
1639 ((offsetof(struct tx_port_stats, counter) + \
1640 sizeof(struct rx_port_stats) + 512) / 8)
1641
1642#define BNXT_RX_STATS_EXT_OFFSET(counter) \
1643 (offsetof(struct rx_port_stats_ext, counter) / 8)
1644
1645#define BNXT_TX_STATS_EXT_OFFSET(counter) \
1646 (offsetof(struct tx_port_stats_ext, counter) / 8)
1647
1648#define BNXT_PCIE_STATS_OFFSET(counter) \
1649 (offsetof(struct pcie_ctx_hw_stats, counter) / 8)
1650
1651#define I2C_DEV_ADDR_A0 0xa0
1652#define I2C_DEV_ADDR_A2 0xa2
1653#define SFF_DIAG_SUPPORT_OFFSET 0x5c
1654#define SFF_MODULE_ID_SFP 0x3
1655#define SFF_MODULE_ID_QSFP 0xc
1656#define SFF_MODULE_ID_QSFP_PLUS 0xd
1657#define SFF_MODULE_ID_QSFP28 0x11
1658#define BNXT_MAX_PHY_I2C_RESP_SIZE 64
1659
1660static inline u32 bnxt_tx_avail(struct bnxt *bp, struct bnxt_tx_ring_info *txr)
1661{
1662
1663 barrier();
1664
1665 return bp->tx_ring_size -
1666 ((txr->tx_prod - txr->tx_cons) & bp->tx_ring_mask);
1667}
1668
1669#if BITS_PER_LONG == 32
1670#define writeq(val64, db) \
1671do { \
1672 spin_lock(&bp->db_lock); \
1673 writel((val64) & 0xffffffff, db); \
1674 writel((val64) >> 32, (db) + 4); \
1675 spin_unlock(&bp->db_lock); \
1676} while (0)
1677
1678#define writeq_relaxed writeq
1679#endif
1680
1681
1682static inline void bnxt_db_write_relaxed(struct bnxt *bp,
1683 struct bnxt_db_info *db, u32 idx)
1684{
1685 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1686 writeq_relaxed(db->db_key64 | idx, db->doorbell);
1687 } else {
1688 u32 db_val = db->db_key32 | idx;
1689
1690 writel_relaxed(db_val, db->doorbell);
1691 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1692 writel_relaxed(db_val, db->doorbell);
1693 }
1694}
1695
1696
1697static inline void bnxt_db_write(struct bnxt *bp, struct bnxt_db_info *db,
1698 u32 idx)
1699{
1700 if (bp->flags & BNXT_FLAG_CHIP_P5) {
1701 writeq(db->db_key64 | idx, db->doorbell);
1702 } else {
1703 u32 db_val = db->db_key32 | idx;
1704
1705 writel(db_val, db->doorbell);
1706 if (bp->flags & BNXT_FLAG_DOUBLE_DB)
1707 writel(db_val, db->doorbell);
1708 }
1709}
1710
1711static inline bool bnxt_cfa_hwrm_message(u16 req_type)
1712{
1713 switch (req_type) {
1714 case HWRM_CFA_ENCAP_RECORD_ALLOC:
1715 case HWRM_CFA_ENCAP_RECORD_FREE:
1716 case HWRM_CFA_DECAP_FILTER_ALLOC:
1717 case HWRM_CFA_DECAP_FILTER_FREE:
1718 case HWRM_CFA_NTUPLE_FILTER_ALLOC:
1719 case HWRM_CFA_NTUPLE_FILTER_FREE:
1720 case HWRM_CFA_NTUPLE_FILTER_CFG:
1721 case HWRM_CFA_EM_FLOW_ALLOC:
1722 case HWRM_CFA_EM_FLOW_FREE:
1723 case HWRM_CFA_EM_FLOW_CFG:
1724 case HWRM_CFA_FLOW_ALLOC:
1725 case HWRM_CFA_FLOW_FREE:
1726 case HWRM_CFA_FLOW_INFO:
1727 case HWRM_CFA_FLOW_FLUSH:
1728 case HWRM_CFA_FLOW_STATS:
1729 case HWRM_CFA_METER_PROFILE_ALLOC:
1730 case HWRM_CFA_METER_PROFILE_FREE:
1731 case HWRM_CFA_METER_PROFILE_CFG:
1732 case HWRM_CFA_METER_INSTANCE_ALLOC:
1733 case HWRM_CFA_METER_INSTANCE_FREE:
1734 return true;
1735 default:
1736 return false;
1737 }
1738}
1739
1740static inline bool bnxt_kong_hwrm_message(struct bnxt *bp, struct input *req)
1741{
1742 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1743 bnxt_cfa_hwrm_message(le16_to_cpu(req->req_type)));
1744}
1745
1746static inline bool bnxt_hwrm_kong_chnl(struct bnxt *bp, struct input *req)
1747{
1748 return (bp->fw_cap & BNXT_FW_CAP_KONG_MB_CHNL &&
1749 req->resp_addr == cpu_to_le64(bp->hwrm_cmd_kong_resp_dma_addr));
1750}
1751
1752static inline void *bnxt_get_hwrm_resp_addr(struct bnxt *bp, void *req)
1753{
1754 if (bnxt_hwrm_kong_chnl(bp, (struct input *)req))
1755 return bp->hwrm_cmd_kong_resp_addr;
1756 else
1757 return bp->hwrm_cmd_resp_addr;
1758}
1759
1760static inline u16 bnxt_get_hwrm_seq_id(struct bnxt *bp, u16 dst)
1761{
1762 u16 seq_id;
1763
1764 if (dst == BNXT_HWRM_CHNL_CHIMP)
1765 seq_id = bp->hwrm_cmd_seq++;
1766 else
1767 seq_id = bp->hwrm_cmd_kong_seq++;
1768 return seq_id;
1769}
1770
1771extern const u16 bnxt_lhint_arr[];
1772
1773int bnxt_alloc_rx_data(struct bnxt *bp, struct bnxt_rx_ring_info *rxr,
1774 u16 prod, gfp_t gfp);
1775void bnxt_reuse_rx_data(struct bnxt_rx_ring_info *rxr, u16 cons, void *data);
1776void bnxt_set_tpa_flags(struct bnxt *bp);
1777void bnxt_set_ring_params(struct bnxt *);
1778int bnxt_set_rx_skb_mode(struct bnxt *bp, bool page_mode);
1779void bnxt_hwrm_cmd_hdr_init(struct bnxt *, void *, u16, u16, u16);
1780int _hwrm_send_message(struct bnxt *, void *, u32, int);
1781int _hwrm_send_message_silent(struct bnxt *bp, void *msg, u32 len, int timeout);
1782int hwrm_send_message(struct bnxt *, void *, u32, int);
1783int hwrm_send_message_silent(struct bnxt *, void *, u32, int);
1784int bnxt_hwrm_func_rgtr_async_events(struct bnxt *bp, unsigned long *bmap,
1785 int bmap_size);
1786int bnxt_hwrm_vnic_cfg(struct bnxt *bp, u16 vnic_id);
1787int __bnxt_hwrm_get_tx_rings(struct bnxt *bp, u16 fid, int *tx_rings);
1788int bnxt_nq_rings_in_use(struct bnxt *bp);
1789int bnxt_hwrm_set_coal(struct bnxt *);
1790unsigned int bnxt_get_max_func_stat_ctxs(struct bnxt *bp);
1791unsigned int bnxt_get_avail_stat_ctxs_for_en(struct bnxt *bp);
1792unsigned int bnxt_get_max_func_cp_rings(struct bnxt *bp);
1793unsigned int bnxt_get_avail_cp_rings_for_en(struct bnxt *bp);
1794int bnxt_get_avail_msix(struct bnxt *bp, int num);
1795int bnxt_reserve_rings(struct bnxt *bp, bool irq_re_init);
1796void bnxt_tx_disable(struct bnxt *bp);
1797void bnxt_tx_enable(struct bnxt *bp);
1798int bnxt_hwrm_set_pause(struct bnxt *);
1799int bnxt_hwrm_set_link_setting(struct bnxt *, bool, bool);
1800int bnxt_hwrm_alloc_wol_fltr(struct bnxt *bp);
1801int bnxt_hwrm_free_wol_fltr(struct bnxt *bp);
1802int bnxt_hwrm_func_resc_qcaps(struct bnxt *bp, bool all);
1803int bnxt_hwrm_fw_set_time(struct bnxt *);
1804int bnxt_open_nic(struct bnxt *, bool, bool);
1805int bnxt_half_open_nic(struct bnxt *bp);
1806void bnxt_half_close_nic(struct bnxt *bp);
1807int bnxt_close_nic(struct bnxt *, bool, bool);
1808int bnxt_check_rings(struct bnxt *bp, int tx, int rx, bool sh, int tcs,
1809 int tx_xdp);
1810int bnxt_setup_mq_tc(struct net_device *dev, u8 tc);
1811int bnxt_get_max_rings(struct bnxt *, int *, int *, bool);
1812int bnxt_restore_pf_fw_resources(struct bnxt *bp);
1813int bnxt_get_port_parent_id(struct net_device *dev,
1814 struct netdev_phys_item_id *ppid);
1815void bnxt_dim_work(struct work_struct *work);
1816int bnxt_hwrm_set_ring_coal(struct bnxt *bp, struct bnxt_napi *bnapi);
1817
1818#endif
1819