1
2
3
4
5
6#include <linux/sort.h>
7
8#include "t4_regs.h"
9#include "cxgb4.h"
10#include "cxgb4_cudbg.h"
11#include "cudbg_if.h"
12#include "cudbg_lib_common.h"
13#include "cudbg_entity.h"
14#include "cudbg_lib.h"
15#include "cudbg_zlib.h"
16
17static int cudbg_do_compression(struct cudbg_init *pdbg_init,
18 struct cudbg_buffer *pin_buff,
19 struct cudbg_buffer *dbg_buff)
20{
21 struct cudbg_buffer temp_in_buff = { 0 };
22 int bytes_left, bytes_read, bytes;
23 u32 offset = dbg_buff->offset;
24 int rc;
25
26 temp_in_buff.offset = pin_buff->offset;
27 temp_in_buff.data = pin_buff->data;
28 temp_in_buff.size = pin_buff->size;
29
30 bytes_left = pin_buff->size;
31 bytes_read = 0;
32 while (bytes_left > 0) {
33
34 bytes = min_t(unsigned long, bytes_left,
35 (unsigned long)CUDBG_CHUNK_SIZE);
36 temp_in_buff.data = (char *)pin_buff->data + bytes_read;
37 temp_in_buff.size = bytes;
38 rc = cudbg_compress_buff(pdbg_init, &temp_in_buff, dbg_buff);
39 if (rc)
40 return rc;
41 bytes_left -= bytes;
42 bytes_read += bytes;
43 }
44
45 pin_buff->size = dbg_buff->offset - offset;
46 return 0;
47}
48
49static int cudbg_write_and_release_buff(struct cudbg_init *pdbg_init,
50 struct cudbg_buffer *pin_buff,
51 struct cudbg_buffer *dbg_buff)
52{
53 int rc = 0;
54
55 if (pdbg_init->compress_type == CUDBG_COMPRESSION_NONE) {
56 cudbg_update_buff(pin_buff, dbg_buff);
57 } else {
58 rc = cudbg_do_compression(pdbg_init, pin_buff, dbg_buff);
59 if (rc)
60 goto out;
61 }
62
63out:
64 cudbg_put_buff(pdbg_init, pin_buff);
65 return rc;
66}
67
68static int is_fw_attached(struct cudbg_init *pdbg_init)
69{
70 struct adapter *padap = pdbg_init->adap;
71
72 if (!(padap->flags & CXGB4_FW_OK) || padap->use_bd)
73 return 0;
74
75 return 1;
76}
77
78
79
80
81void cudbg_align_debug_buffer(struct cudbg_buffer *dbg_buff,
82 struct cudbg_entity_hdr *entity_hdr)
83{
84 u8 zero_buf[4] = {0};
85 u8 padding, remain;
86
87 remain = (dbg_buff->offset - entity_hdr->start_offset) % 4;
88 padding = 4 - remain;
89 if (remain) {
90 memcpy(((u8 *)dbg_buff->data) + dbg_buff->offset, &zero_buf,
91 padding);
92 dbg_buff->offset += padding;
93 entity_hdr->num_pad = padding;
94 }
95 entity_hdr->size = dbg_buff->offset - entity_hdr->start_offset;
96}
97
98struct cudbg_entity_hdr *cudbg_get_entity_hdr(void *outbuf, int i)
99{
100 struct cudbg_hdr *cudbg_hdr = (struct cudbg_hdr *)outbuf;
101
102 return (struct cudbg_entity_hdr *)
103 ((char *)outbuf + cudbg_hdr->hdr_len +
104 (sizeof(struct cudbg_entity_hdr) * (i - 1)));
105}
106
107static int cudbg_read_vpd_reg(struct adapter *padap, u32 addr, u32 len,
108 void *dest)
109{
110 int vaddr, rc;
111
112 vaddr = t4_eeprom_ptov(addr, padap->pf, EEPROMPFSIZE);
113 if (vaddr < 0)
114 return vaddr;
115
116 rc = pci_read_vpd(padap->pdev, vaddr, len, dest);
117 if (rc < 0)
118 return rc;
119
120 return 0;
121}
122
123static int cudbg_mem_desc_cmp(const void *a, const void *b)
124{
125 return ((const struct cudbg_mem_desc *)a)->base -
126 ((const struct cudbg_mem_desc *)b)->base;
127}
128
129int cudbg_fill_meminfo(struct adapter *padap,
130 struct cudbg_meminfo *meminfo_buff)
131{
132 struct cudbg_mem_desc *md;
133 u32 lo, hi, used, alloc;
134 int n, i;
135
136 memset(meminfo_buff->avail, 0,
137 ARRAY_SIZE(meminfo_buff->avail) *
138 sizeof(struct cudbg_mem_desc));
139 memset(meminfo_buff->mem, 0,
140 (ARRAY_SIZE(cudbg_region) + 3) * sizeof(struct cudbg_mem_desc));
141 md = meminfo_buff->mem;
142
143 for (i = 0; i < ARRAY_SIZE(meminfo_buff->mem); i++) {
144 meminfo_buff->mem[i].limit = 0;
145 meminfo_buff->mem[i].idx = i;
146 }
147
148
149 i = 0;
150 lo = t4_read_reg(padap, MA_TARGET_MEM_ENABLE_A);
151 if (lo & EDRAM0_ENABLE_F) {
152 hi = t4_read_reg(padap, MA_EDRAM0_BAR_A);
153 meminfo_buff->avail[i].base =
154 cudbg_mbytes_to_bytes(EDRAM0_BASE_G(hi));
155 meminfo_buff->avail[i].limit =
156 meminfo_buff->avail[i].base +
157 cudbg_mbytes_to_bytes(EDRAM0_SIZE_G(hi));
158 meminfo_buff->avail[i].idx = 0;
159 i++;
160 }
161
162 if (lo & EDRAM1_ENABLE_F) {
163 hi = t4_read_reg(padap, MA_EDRAM1_BAR_A);
164 meminfo_buff->avail[i].base =
165 cudbg_mbytes_to_bytes(EDRAM1_BASE_G(hi));
166 meminfo_buff->avail[i].limit =
167 meminfo_buff->avail[i].base +
168 cudbg_mbytes_to_bytes(EDRAM1_SIZE_G(hi));
169 meminfo_buff->avail[i].idx = 1;
170 i++;
171 }
172
173 if (is_t5(padap->params.chip)) {
174 if (lo & EXT_MEM0_ENABLE_F) {
175 hi = t4_read_reg(padap, MA_EXT_MEMORY0_BAR_A);
176 meminfo_buff->avail[i].base =
177 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
178 meminfo_buff->avail[i].limit =
179 meminfo_buff->avail[i].base +
180 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
181 meminfo_buff->avail[i].idx = 3;
182 i++;
183 }
184
185 if (lo & EXT_MEM1_ENABLE_F) {
186 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
187 meminfo_buff->avail[i].base =
188 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
189 meminfo_buff->avail[i].limit =
190 meminfo_buff->avail[i].base +
191 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
192 meminfo_buff->avail[i].idx = 4;
193 i++;
194 }
195 } else {
196 if (lo & EXT_MEM_ENABLE_F) {
197 hi = t4_read_reg(padap, MA_EXT_MEMORY_BAR_A);
198 meminfo_buff->avail[i].base =
199 cudbg_mbytes_to_bytes(EXT_MEM_BASE_G(hi));
200 meminfo_buff->avail[i].limit =
201 meminfo_buff->avail[i].base +
202 cudbg_mbytes_to_bytes(EXT_MEM_SIZE_G(hi));
203 meminfo_buff->avail[i].idx = 2;
204 i++;
205 }
206
207 if (lo & HMA_MUX_F) {
208 hi = t4_read_reg(padap, MA_EXT_MEMORY1_BAR_A);
209 meminfo_buff->avail[i].base =
210 cudbg_mbytes_to_bytes(EXT_MEM1_BASE_G(hi));
211 meminfo_buff->avail[i].limit =
212 meminfo_buff->avail[i].base +
213 cudbg_mbytes_to_bytes(EXT_MEM1_SIZE_G(hi));
214 meminfo_buff->avail[i].idx = 5;
215 i++;
216 }
217 }
218
219 if (!i)
220 return CUDBG_STATUS_ENTITY_NOT_FOUND;
221
222 meminfo_buff->avail_c = i;
223 sort(meminfo_buff->avail, i, sizeof(struct cudbg_mem_desc),
224 cudbg_mem_desc_cmp, NULL);
225 (md++)->base = t4_read_reg(padap, SGE_DBQ_CTXT_BADDR_A);
226 (md++)->base = t4_read_reg(padap, SGE_IMSG_CTXT_BADDR_A);
227 (md++)->base = t4_read_reg(padap, SGE_FLM_CACHE_BADDR_A);
228 (md++)->base = t4_read_reg(padap, TP_CMM_TCB_BASE_A);
229 (md++)->base = t4_read_reg(padap, TP_CMM_MM_BASE_A);
230 (md++)->base = t4_read_reg(padap, TP_CMM_TIMER_BASE_A);
231 (md++)->base = t4_read_reg(padap, TP_CMM_MM_RX_FLST_BASE_A);
232 (md++)->base = t4_read_reg(padap, TP_CMM_MM_TX_FLST_BASE_A);
233 (md++)->base = t4_read_reg(padap, TP_CMM_MM_PS_FLST_BASE_A);
234
235
236 md->base = t4_read_reg(padap, TP_PMM_TX_BASE_A);
237 md->limit = md->base - 1 +
238 t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A) *
239 PMTXMAXPAGE_G(t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A));
240 md++;
241
242 md->base = t4_read_reg(padap, TP_PMM_RX_BASE_A);
243 md->limit = md->base - 1 +
244 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) *
245 PMRXMAXPAGE_G(t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A));
246 md++;
247
248 if (t4_read_reg(padap, LE_DB_CONFIG_A) & HASHEN_F) {
249 if (CHELSIO_CHIP_VERSION(padap->params.chip) <= CHELSIO_T5) {
250 hi = t4_read_reg(padap, LE_DB_TID_HASHBASE_A) / 4;
251 md->base = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
252 } else {
253 hi = t4_read_reg(padap, LE_DB_HASH_TID_BASE_A);
254 md->base = t4_read_reg(padap,
255 LE_DB_HASH_TBL_BASE_ADDR_A);
256 }
257 md->limit = 0;
258 } else {
259 md->base = 0;
260 md->idx = ARRAY_SIZE(cudbg_region);
261 }
262 md++;
263
264#define ulp_region(reg) do { \
265 md->base = t4_read_reg(padap, ULP_ ## reg ## _LLIMIT_A);\
266 (md++)->limit = t4_read_reg(padap, ULP_ ## reg ## _ULIMIT_A);\
267} while (0)
268
269 ulp_region(RX_ISCSI);
270 ulp_region(RX_TDDP);
271 ulp_region(TX_TPT);
272 ulp_region(RX_STAG);
273 ulp_region(RX_RQ);
274 ulp_region(RX_RQUDP);
275 ulp_region(RX_PBL);
276 ulp_region(TX_PBL);
277#undef ulp_region
278 md->base = 0;
279 md->idx = ARRAY_SIZE(cudbg_region);
280 if (!is_t4(padap->params.chip)) {
281 u32 fifo_size = t4_read_reg(padap, SGE_DBVFIFO_SIZE_A);
282 u32 sge_ctrl = t4_read_reg(padap, SGE_CONTROL2_A);
283 u32 size = 0;
284
285 if (is_t5(padap->params.chip)) {
286 if (sge_ctrl & VFIFO_ENABLE_F)
287 size = DBVFIFO_SIZE_G(fifo_size);
288 } else {
289 size = T6_DBVFIFO_SIZE_G(fifo_size);
290 }
291
292 if (size) {
293 md->base = BASEADDR_G(t4_read_reg(padap,
294 SGE_DBVFIFO_BADDR_A));
295 md->limit = md->base + (size << 2) - 1;
296 }
297 }
298
299 md++;
300
301 md->base = t4_read_reg(padap, ULP_RX_CTX_BASE_A);
302 md->limit = 0;
303 md++;
304 md->base = t4_read_reg(padap, ULP_TX_ERR_TABLE_BASE_A);
305 md->limit = 0;
306 md++;
307
308 md->base = padap->vres.ocq.start;
309 if (padap->vres.ocq.size)
310 md->limit = md->base + padap->vres.ocq.size - 1;
311 else
312 md->idx = ARRAY_SIZE(cudbg_region);
313 md++;
314
315
316 for (n = 0; n < i - 1; n++)
317 if (meminfo_buff->avail[n].limit <
318 meminfo_buff->avail[n + 1].base)
319 (md++)->base = meminfo_buff->avail[n].limit;
320
321 if (meminfo_buff->avail[n].limit)
322 (md++)->base = meminfo_buff->avail[n].limit;
323
324 n = md - meminfo_buff->mem;
325 meminfo_buff->mem_c = n;
326
327 sort(meminfo_buff->mem, n, sizeof(struct cudbg_mem_desc),
328 cudbg_mem_desc_cmp, NULL);
329
330 lo = t4_read_reg(padap, CIM_SDRAM_BASE_ADDR_A);
331 hi = t4_read_reg(padap, CIM_SDRAM_ADDR_SIZE_A) + lo - 1;
332 meminfo_buff->up_ram_lo = lo;
333 meminfo_buff->up_ram_hi = hi;
334
335 lo = t4_read_reg(padap, CIM_EXTMEM2_BASE_ADDR_A);
336 hi = t4_read_reg(padap, CIM_EXTMEM2_ADDR_SIZE_A) + lo - 1;
337 meminfo_buff->up_extmem2_lo = lo;
338 meminfo_buff->up_extmem2_hi = hi;
339
340 lo = t4_read_reg(padap, TP_PMM_RX_MAX_PAGE_A);
341 for (i = 0, meminfo_buff->free_rx_cnt = 0; i < 2; i++)
342 meminfo_buff->free_rx_cnt +=
343 FREERXPAGECOUNT_G(t4_read_reg(padap,
344 TP_FLM_FREE_RX_CNT_A));
345
346 meminfo_buff->rx_pages_data[0] = PMRXMAXPAGE_G(lo);
347 meminfo_buff->rx_pages_data[1] =
348 t4_read_reg(padap, TP_PMM_RX_PAGE_SIZE_A) >> 10;
349 meminfo_buff->rx_pages_data[2] = (lo & PMRXNUMCHN_F) ? 2 : 1;
350
351 lo = t4_read_reg(padap, TP_PMM_TX_MAX_PAGE_A);
352 hi = t4_read_reg(padap, TP_PMM_TX_PAGE_SIZE_A);
353 for (i = 0, meminfo_buff->free_tx_cnt = 0; i < 4; i++)
354 meminfo_buff->free_tx_cnt +=
355 FREETXPAGECOUNT_G(t4_read_reg(padap,
356 TP_FLM_FREE_TX_CNT_A));
357
358 meminfo_buff->tx_pages_data[0] = PMTXMAXPAGE_G(lo);
359 meminfo_buff->tx_pages_data[1] =
360 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10);
361 meminfo_buff->tx_pages_data[2] =
362 hi >= (1 << 20) ? 'M' : 'K';
363 meminfo_buff->tx_pages_data[3] = 1 << PMTXNUMCHN_G(lo);
364
365 meminfo_buff->p_structs = t4_read_reg(padap, TP_CMM_MM_MAX_PSTRUCT_A);
366 meminfo_buff->p_structs_free_cnt =
367 FREEPSTRUCTCOUNT_G(t4_read_reg(padap, TP_FLM_FREE_PS_CNT_A));
368
369 for (i = 0; i < 4; i++) {
370 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
371 lo = t4_read_reg(padap,
372 MPS_RX_MAC_BG_PG_CNT0_A + i * 4);
373 else
374 lo = t4_read_reg(padap, MPS_RX_PG_RSV0_A + i * 4);
375 if (is_t5(padap->params.chip)) {
376 used = T5_USED_G(lo);
377 alloc = T5_ALLOC_G(lo);
378 } else {
379 used = USED_G(lo);
380 alloc = ALLOC_G(lo);
381 }
382 meminfo_buff->port_used[i] = used;
383 meminfo_buff->port_alloc[i] = alloc;
384 }
385
386 for (i = 0; i < padap->params.arch.nchan; i++) {
387 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5)
388 lo = t4_read_reg(padap,
389 MPS_RX_LPBK_BG_PG_CNT0_A + i * 4);
390 else
391 lo = t4_read_reg(padap, MPS_RX_PG_RSV4_A + i * 4);
392 if (is_t5(padap->params.chip)) {
393 used = T5_USED_G(lo);
394 alloc = T5_ALLOC_G(lo);
395 } else {
396 used = USED_G(lo);
397 alloc = ALLOC_G(lo);
398 }
399 meminfo_buff->loopback_used[i] = used;
400 meminfo_buff->loopback_alloc[i] = alloc;
401 }
402
403 return 0;
404}
405
406int cudbg_collect_reg_dump(struct cudbg_init *pdbg_init,
407 struct cudbg_buffer *dbg_buff,
408 struct cudbg_error *cudbg_err)
409{
410 struct adapter *padap = pdbg_init->adap;
411 struct cudbg_buffer temp_buff = { 0 };
412 u32 buf_size = 0;
413 int rc = 0;
414
415 if (is_t4(padap->params.chip))
416 buf_size = T4_REGMAP_SIZE;
417 else if (is_t5(padap->params.chip) || is_t6(padap->params.chip))
418 buf_size = T5_REGMAP_SIZE;
419
420 rc = cudbg_get_buff(pdbg_init, dbg_buff, buf_size, &temp_buff);
421 if (rc)
422 return rc;
423 t4_get_regs(padap, (void *)temp_buff.data, temp_buff.size);
424 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
425}
426
427int cudbg_collect_fw_devlog(struct cudbg_init *pdbg_init,
428 struct cudbg_buffer *dbg_buff,
429 struct cudbg_error *cudbg_err)
430{
431 struct adapter *padap = pdbg_init->adap;
432 struct cudbg_buffer temp_buff = { 0 };
433 struct devlog_params *dparams;
434 int rc = 0;
435
436 rc = t4_init_devlog_params(padap);
437 if (rc < 0) {
438 cudbg_err->sys_err = rc;
439 return rc;
440 }
441
442 dparams = &padap->params.devlog;
443 rc = cudbg_get_buff(pdbg_init, dbg_buff, dparams->size, &temp_buff);
444 if (rc)
445 return rc;
446
447
448 if (dparams->start != 0) {
449 spin_lock(&padap->win0_lock);
450 rc = t4_memory_rw(padap, padap->params.drv_memwin,
451 dparams->memtype, dparams->start,
452 dparams->size,
453 (__be32 *)(char *)temp_buff.data,
454 1);
455 spin_unlock(&padap->win0_lock);
456 if (rc) {
457 cudbg_err->sys_err = rc;
458 cudbg_put_buff(pdbg_init, &temp_buff);
459 return rc;
460 }
461 }
462 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
463}
464
465int cudbg_collect_cim_la(struct cudbg_init *pdbg_init,
466 struct cudbg_buffer *dbg_buff,
467 struct cudbg_error *cudbg_err)
468{
469 struct adapter *padap = pdbg_init->adap;
470 struct cudbg_buffer temp_buff = { 0 };
471 int size, rc;
472 u32 cfg = 0;
473
474 if (is_t6(padap->params.chip)) {
475 size = padap->params.cim_la_size / 10 + 1;
476 size *= 10 * sizeof(u32);
477 } else {
478 size = padap->params.cim_la_size / 8;
479 size *= 8 * sizeof(u32);
480 }
481
482 size += sizeof(cfg);
483 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
484 if (rc)
485 return rc;
486
487 rc = t4_cim_read(padap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
488 if (rc) {
489 cudbg_err->sys_err = rc;
490 cudbg_put_buff(pdbg_init, &temp_buff);
491 return rc;
492 }
493
494 memcpy((char *)temp_buff.data, &cfg, sizeof(cfg));
495 rc = t4_cim_read_la(padap,
496 (u32 *)((char *)temp_buff.data + sizeof(cfg)),
497 NULL);
498 if (rc < 0) {
499 cudbg_err->sys_err = rc;
500 cudbg_put_buff(pdbg_init, &temp_buff);
501 return rc;
502 }
503 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
504}
505
506int cudbg_collect_cim_ma_la(struct cudbg_init *pdbg_init,
507 struct cudbg_buffer *dbg_buff,
508 struct cudbg_error *cudbg_err)
509{
510 struct adapter *padap = pdbg_init->adap;
511 struct cudbg_buffer temp_buff = { 0 };
512 int size, rc;
513
514 size = 2 * CIM_MALA_SIZE * 5 * sizeof(u32);
515 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
516 if (rc)
517 return rc;
518
519 t4_cim_read_ma_la(padap,
520 (u32 *)temp_buff.data,
521 (u32 *)((char *)temp_buff.data +
522 5 * CIM_MALA_SIZE));
523 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
524}
525
526int cudbg_collect_cim_qcfg(struct cudbg_init *pdbg_init,
527 struct cudbg_buffer *dbg_buff,
528 struct cudbg_error *cudbg_err)
529{
530 struct adapter *padap = pdbg_init->adap;
531 struct cudbg_buffer temp_buff = { 0 };
532 struct cudbg_cim_qcfg *cim_qcfg_data;
533 int rc;
534
535 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_cim_qcfg),
536 &temp_buff);
537 if (rc)
538 return rc;
539
540 cim_qcfg_data = (struct cudbg_cim_qcfg *)temp_buff.data;
541 cim_qcfg_data->chip = padap->params.chip;
542 rc = t4_cim_read(padap, UP_IBQ_0_RDADDR_A,
543 ARRAY_SIZE(cim_qcfg_data->stat), cim_qcfg_data->stat);
544 if (rc) {
545 cudbg_err->sys_err = rc;
546 cudbg_put_buff(pdbg_init, &temp_buff);
547 return rc;
548 }
549
550 rc = t4_cim_read(padap, UP_OBQ_0_REALADDR_A,
551 ARRAY_SIZE(cim_qcfg_data->obq_wr),
552 cim_qcfg_data->obq_wr);
553 if (rc) {
554 cudbg_err->sys_err = rc;
555 cudbg_put_buff(pdbg_init, &temp_buff);
556 return rc;
557 }
558
559 t4_read_cimq_cfg(padap, cim_qcfg_data->base, cim_qcfg_data->size,
560 cim_qcfg_data->thres);
561 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
562}
563
564static int cudbg_read_cim_ibq(struct cudbg_init *pdbg_init,
565 struct cudbg_buffer *dbg_buff,
566 struct cudbg_error *cudbg_err, int qid)
567{
568 struct adapter *padap = pdbg_init->adap;
569 struct cudbg_buffer temp_buff = { 0 };
570 int no_of_read_words, rc = 0;
571 u32 qsize;
572
573
574 qsize = CIM_IBQ_SIZE * 4 * sizeof(u32);
575 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
576 if (rc)
577 return rc;
578
579
580 no_of_read_words = t4_read_cim_ibq(padap, qid,
581 (u32 *)temp_buff.data, qsize);
582
583 if (no_of_read_words <= 0) {
584 if (!no_of_read_words)
585 rc = CUDBG_SYSTEM_ERROR;
586 else
587 rc = no_of_read_words;
588 cudbg_err->sys_err = rc;
589 cudbg_put_buff(pdbg_init, &temp_buff);
590 return rc;
591 }
592 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
593}
594
595int cudbg_collect_cim_ibq_tp0(struct cudbg_init *pdbg_init,
596 struct cudbg_buffer *dbg_buff,
597 struct cudbg_error *cudbg_err)
598{
599 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 0);
600}
601
602int cudbg_collect_cim_ibq_tp1(struct cudbg_init *pdbg_init,
603 struct cudbg_buffer *dbg_buff,
604 struct cudbg_error *cudbg_err)
605{
606 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 1);
607}
608
609int cudbg_collect_cim_ibq_ulp(struct cudbg_init *pdbg_init,
610 struct cudbg_buffer *dbg_buff,
611 struct cudbg_error *cudbg_err)
612{
613 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 2);
614}
615
616int cudbg_collect_cim_ibq_sge0(struct cudbg_init *pdbg_init,
617 struct cudbg_buffer *dbg_buff,
618 struct cudbg_error *cudbg_err)
619{
620 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 3);
621}
622
623int cudbg_collect_cim_ibq_sge1(struct cudbg_init *pdbg_init,
624 struct cudbg_buffer *dbg_buff,
625 struct cudbg_error *cudbg_err)
626{
627 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 4);
628}
629
630int cudbg_collect_cim_ibq_ncsi(struct cudbg_init *pdbg_init,
631 struct cudbg_buffer *dbg_buff,
632 struct cudbg_error *cudbg_err)
633{
634 return cudbg_read_cim_ibq(pdbg_init, dbg_buff, cudbg_err, 5);
635}
636
637u32 cudbg_cim_obq_size(struct adapter *padap, int qid)
638{
639 u32 value;
640
641 t4_write_reg(padap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
642 QUENUMSELECT_V(qid));
643 value = t4_read_reg(padap, CIM_QUEUE_CONFIG_CTRL_A);
644 value = CIMQSIZE_G(value) * 64;
645 return value * sizeof(u32);
646}
647
648static int cudbg_read_cim_obq(struct cudbg_init *pdbg_init,
649 struct cudbg_buffer *dbg_buff,
650 struct cudbg_error *cudbg_err, int qid)
651{
652 struct adapter *padap = pdbg_init->adap;
653 struct cudbg_buffer temp_buff = { 0 };
654 int no_of_read_words, rc = 0;
655 u32 qsize;
656
657
658 qsize = cudbg_cim_obq_size(padap, qid);
659 rc = cudbg_get_buff(pdbg_init, dbg_buff, qsize, &temp_buff);
660 if (rc)
661 return rc;
662
663
664 no_of_read_words = t4_read_cim_obq(padap, qid,
665 (u32 *)temp_buff.data, qsize);
666
667 if (no_of_read_words <= 0) {
668 if (!no_of_read_words)
669 rc = CUDBG_SYSTEM_ERROR;
670 else
671 rc = no_of_read_words;
672 cudbg_err->sys_err = rc;
673 cudbg_put_buff(pdbg_init, &temp_buff);
674 return rc;
675 }
676 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
677}
678
679int cudbg_collect_cim_obq_ulp0(struct cudbg_init *pdbg_init,
680 struct cudbg_buffer *dbg_buff,
681 struct cudbg_error *cudbg_err)
682{
683 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 0);
684}
685
686int cudbg_collect_cim_obq_ulp1(struct cudbg_init *pdbg_init,
687 struct cudbg_buffer *dbg_buff,
688 struct cudbg_error *cudbg_err)
689{
690 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 1);
691}
692
693int cudbg_collect_cim_obq_ulp2(struct cudbg_init *pdbg_init,
694 struct cudbg_buffer *dbg_buff,
695 struct cudbg_error *cudbg_err)
696{
697 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 2);
698}
699
700int cudbg_collect_cim_obq_ulp3(struct cudbg_init *pdbg_init,
701 struct cudbg_buffer *dbg_buff,
702 struct cudbg_error *cudbg_err)
703{
704 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 3);
705}
706
707int cudbg_collect_cim_obq_sge(struct cudbg_init *pdbg_init,
708 struct cudbg_buffer *dbg_buff,
709 struct cudbg_error *cudbg_err)
710{
711 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 4);
712}
713
714int cudbg_collect_cim_obq_ncsi(struct cudbg_init *pdbg_init,
715 struct cudbg_buffer *dbg_buff,
716 struct cudbg_error *cudbg_err)
717{
718 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 5);
719}
720
721int cudbg_collect_obq_sge_rx_q0(struct cudbg_init *pdbg_init,
722 struct cudbg_buffer *dbg_buff,
723 struct cudbg_error *cudbg_err)
724{
725 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 6);
726}
727
728int cudbg_collect_obq_sge_rx_q1(struct cudbg_init *pdbg_init,
729 struct cudbg_buffer *dbg_buff,
730 struct cudbg_error *cudbg_err)
731{
732 return cudbg_read_cim_obq(pdbg_init, dbg_buff, cudbg_err, 7);
733}
734
735static int cudbg_meminfo_get_mem_index(struct adapter *padap,
736 struct cudbg_meminfo *mem_info,
737 u8 mem_type, u8 *idx)
738{
739 u8 i, flag;
740
741 switch (mem_type) {
742 case MEM_EDC0:
743 flag = EDC0_FLAG;
744 break;
745 case MEM_EDC1:
746 flag = EDC1_FLAG;
747 break;
748 case MEM_MC0:
749
750 flag = is_t5(padap->params.chip) ? MC0_FLAG : MC_FLAG;
751 break;
752 case MEM_MC1:
753 flag = MC1_FLAG;
754 break;
755 case MEM_HMA:
756 flag = HMA_FLAG;
757 break;
758 default:
759 return CUDBG_STATUS_ENTITY_NOT_FOUND;
760 }
761
762 for (i = 0; i < mem_info->avail_c; i++) {
763 if (mem_info->avail[i].idx == flag) {
764 *idx = i;
765 return 0;
766 }
767 }
768
769 return CUDBG_STATUS_ENTITY_NOT_FOUND;
770}
771
772
773static int cudbg_get_mem_region(struct adapter *padap,
774 struct cudbg_meminfo *meminfo,
775 u8 mem_type, const char *region_name,
776 struct cudbg_mem_desc *mem_desc)
777{
778 u8 mc, found = 0;
779 u32 i, idx = 0;
780 int rc;
781
782 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc);
783 if (rc)
784 return rc;
785
786 for (i = 0; i < ARRAY_SIZE(cudbg_region); i++) {
787 if (!strcmp(cudbg_region[i], region_name)) {
788 found = 1;
789 idx = i;
790 break;
791 }
792 }
793 if (!found)
794 return -EINVAL;
795
796 found = 0;
797 for (i = 0; i < meminfo->mem_c; i++) {
798 if (meminfo->mem[i].idx >= ARRAY_SIZE(cudbg_region))
799 continue;
800
801 if (!(meminfo->mem[i].limit))
802 meminfo->mem[i].limit =
803 i < meminfo->mem_c - 1 ?
804 meminfo->mem[i + 1].base - 1 : ~0;
805
806 if (meminfo->mem[i].idx == idx) {
807
808 if (meminfo->mem[i].base < meminfo->avail[mc].base &&
809 meminfo->mem[i].limit < meminfo->avail[mc].base)
810 return -EINVAL;
811
812 if (meminfo->mem[i].base > meminfo->avail[mc].limit)
813 return -EINVAL;
814
815 memcpy(mem_desc, &meminfo->mem[i],
816 sizeof(struct cudbg_mem_desc));
817 found = 1;
818 break;
819 }
820 }
821 if (!found)
822 return -EINVAL;
823
824 return 0;
825}
826
827
828
829
830static int cudbg_get_mem_relative(struct adapter *padap,
831 struct cudbg_meminfo *meminfo,
832 u8 mem_type, u32 *out_base, u32 *out_end)
833{
834 u8 mc_idx;
835 int rc;
836
837 rc = cudbg_meminfo_get_mem_index(padap, meminfo, mem_type, &mc_idx);
838 if (rc)
839 return rc;
840
841 if (*out_base < meminfo->avail[mc_idx].base)
842 *out_base = 0;
843 else
844 *out_base -= meminfo->avail[mc_idx].base;
845
846 if (*out_end > meminfo->avail[mc_idx].limit)
847 *out_end = meminfo->avail[mc_idx].limit;
848 else
849 *out_end -= meminfo->avail[mc_idx].base;
850
851 return 0;
852}
853
854
855static int cudbg_get_payload_range(struct adapter *padap, u8 mem_type,
856 const char *region_name,
857 struct cudbg_region_info *payload)
858{
859 struct cudbg_mem_desc mem_desc = { 0 };
860 struct cudbg_meminfo meminfo;
861 int rc;
862
863 rc = cudbg_fill_meminfo(padap, &meminfo);
864 if (rc)
865 return rc;
866
867 rc = cudbg_get_mem_region(padap, &meminfo, mem_type, region_name,
868 &mem_desc);
869 if (rc) {
870 payload->exist = false;
871 return 0;
872 }
873
874 payload->exist = true;
875 payload->start = mem_desc.base;
876 payload->end = mem_desc.limit;
877
878 return cudbg_get_mem_relative(padap, &meminfo, mem_type,
879 &payload->start, &payload->end);
880}
881
882static int cudbg_memory_read(struct cudbg_init *pdbg_init, int win,
883 int mtype, u32 addr, u32 len, void *hbuf)
884{
885 u32 win_pf, memoffset, mem_aperture, mem_base;
886 struct adapter *adap = pdbg_init->adap;
887 u32 pos, offset, resid;
888 u32 *res_buf;
889 u64 *buf;
890 int ret;
891
892
893
894 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
895 return -EINVAL;
896
897 buf = (u64 *)hbuf;
898
899
900 resid = len & 0x7;
901 len -= resid;
902
903 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
904 &mem_aperture);
905 if (ret)
906 return ret;
907
908 addr = addr + memoffset;
909 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
910
911 pos = addr & ~(mem_aperture - 1);
912 offset = addr - pos;
913
914
915
916
917 t4_memory_update_win(adap, win, pos | win_pf);
918
919
920 while (len > 0) {
921 *buf++ = le64_to_cpu((__force __le64)
922 t4_read_reg64(adap, mem_base + offset));
923 offset += sizeof(u64);
924 len -= sizeof(u64);
925
926
927
928
929 if (offset == mem_aperture) {
930 pos += mem_aperture;
931 offset = 0;
932 t4_memory_update_win(adap, win, pos | win_pf);
933 }
934 }
935
936 res_buf = (u32 *)buf;
937
938 while (resid > sizeof(u32)) {
939 *res_buf++ = le32_to_cpu((__force __le32)
940 t4_read_reg(adap, mem_base + offset));
941 offset += sizeof(u32);
942 resid -= sizeof(u32);
943
944
945
946
947 if (offset == mem_aperture) {
948 pos += mem_aperture;
949 offset = 0;
950 t4_memory_update_win(adap, win, pos | win_pf);
951 }
952 }
953
954
955 if (resid)
956 t4_memory_rw_residual(adap, resid, mem_base + offset,
957 (u8 *)res_buf, T4_MEMORY_READ);
958
959 return 0;
960}
961
962#define CUDBG_YIELD_ITERATION 256
963
964static int cudbg_read_fw_mem(struct cudbg_init *pdbg_init,
965 struct cudbg_buffer *dbg_buff, u8 mem_type,
966 unsigned long tot_len,
967 struct cudbg_error *cudbg_err)
968{
969 static const char * const region_name[] = { "Tx payload:",
970 "Rx payload:" };
971 unsigned long bytes, bytes_left, bytes_read = 0;
972 struct adapter *padap = pdbg_init->adap;
973 struct cudbg_buffer temp_buff = { 0 };
974 struct cudbg_region_info payload[2];
975 u32 yield_count = 0;
976 int rc = 0;
977 u8 i;
978
979
980 memset(payload, 0, sizeof(payload));
981 for (i = 0; i < ARRAY_SIZE(region_name); i++) {
982 rc = cudbg_get_payload_range(padap, mem_type, region_name[i],
983 &payload[i]);
984 if (rc)
985 return rc;
986
987 if (payload[i].exist) {
988
989 payload[i].start = roundup(payload[i].start,
990 CUDBG_CHUNK_SIZE);
991 payload[i].end = rounddown(payload[i].end,
992 CUDBG_CHUNK_SIZE);
993 }
994 }
995
996 bytes_left = tot_len;
997 while (bytes_left > 0) {
998
999
1000
1001
1002
1003 yield_count++;
1004 if (!(yield_count % CUDBG_YIELD_ITERATION))
1005 schedule();
1006
1007 bytes = min_t(unsigned long, bytes_left,
1008 (unsigned long)CUDBG_CHUNK_SIZE);
1009 rc = cudbg_get_buff(pdbg_init, dbg_buff, bytes, &temp_buff);
1010 if (rc)
1011 return rc;
1012
1013 for (i = 0; i < ARRAY_SIZE(payload); i++)
1014 if (payload[i].exist &&
1015 bytes_read >= payload[i].start &&
1016 bytes_read + bytes <= payload[i].end)
1017
1018 goto skip_read;
1019
1020 spin_lock(&padap->win0_lock);
1021 rc = cudbg_memory_read(pdbg_init, MEMWIN_NIC, mem_type,
1022 bytes_read, bytes, temp_buff.data);
1023 spin_unlock(&padap->win0_lock);
1024 if (rc) {
1025 cudbg_err->sys_err = rc;
1026 cudbg_put_buff(pdbg_init, &temp_buff);
1027 return rc;
1028 }
1029
1030skip_read:
1031 bytes_left -= bytes;
1032 bytes_read += bytes;
1033 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
1034 dbg_buff);
1035 if (rc) {
1036 cudbg_put_buff(pdbg_init, &temp_buff);
1037 return rc;
1038 }
1039 }
1040 return rc;
1041}
1042
1043static void cudbg_t4_fwcache(struct cudbg_init *pdbg_init,
1044 struct cudbg_error *cudbg_err)
1045{
1046 struct adapter *padap = pdbg_init->adap;
1047 int rc;
1048
1049 if (is_fw_attached(pdbg_init)) {
1050
1051 rc = t4_fwcache(padap, FW_PARAM_DEV_FWCACHE_FLUSH);
1052 if (rc)
1053 cudbg_err->sys_warn = rc;
1054 }
1055}
1056
1057static int cudbg_collect_mem_region(struct cudbg_init *pdbg_init,
1058 struct cudbg_buffer *dbg_buff,
1059 struct cudbg_error *cudbg_err,
1060 u8 mem_type)
1061{
1062 struct adapter *padap = pdbg_init->adap;
1063 struct cudbg_meminfo mem_info;
1064 unsigned long size;
1065 u8 mc_idx;
1066 int rc;
1067
1068 memset(&mem_info, 0, sizeof(struct cudbg_meminfo));
1069 rc = cudbg_fill_meminfo(padap, &mem_info);
1070 if (rc)
1071 return rc;
1072
1073 cudbg_t4_fwcache(pdbg_init, cudbg_err);
1074 rc = cudbg_meminfo_get_mem_index(padap, &mem_info, mem_type, &mc_idx);
1075 if (rc)
1076 return rc;
1077
1078 size = mem_info.avail[mc_idx].limit - mem_info.avail[mc_idx].base;
1079 return cudbg_read_fw_mem(pdbg_init, dbg_buff, mem_type, size,
1080 cudbg_err);
1081}
1082
1083int cudbg_collect_edc0_meminfo(struct cudbg_init *pdbg_init,
1084 struct cudbg_buffer *dbg_buff,
1085 struct cudbg_error *cudbg_err)
1086{
1087 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1088 MEM_EDC0);
1089}
1090
1091int cudbg_collect_edc1_meminfo(struct cudbg_init *pdbg_init,
1092 struct cudbg_buffer *dbg_buff,
1093 struct cudbg_error *cudbg_err)
1094{
1095 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1096 MEM_EDC1);
1097}
1098
1099int cudbg_collect_mc0_meminfo(struct cudbg_init *pdbg_init,
1100 struct cudbg_buffer *dbg_buff,
1101 struct cudbg_error *cudbg_err)
1102{
1103 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1104 MEM_MC0);
1105}
1106
1107int cudbg_collect_mc1_meminfo(struct cudbg_init *pdbg_init,
1108 struct cudbg_buffer *dbg_buff,
1109 struct cudbg_error *cudbg_err)
1110{
1111 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1112 MEM_MC1);
1113}
1114
1115int cudbg_collect_hma_meminfo(struct cudbg_init *pdbg_init,
1116 struct cudbg_buffer *dbg_buff,
1117 struct cudbg_error *cudbg_err)
1118{
1119 return cudbg_collect_mem_region(pdbg_init, dbg_buff, cudbg_err,
1120 MEM_HMA);
1121}
1122
1123int cudbg_collect_rss(struct cudbg_init *pdbg_init,
1124 struct cudbg_buffer *dbg_buff,
1125 struct cudbg_error *cudbg_err)
1126{
1127 struct adapter *padap = pdbg_init->adap;
1128 struct cudbg_buffer temp_buff = { 0 };
1129 int rc, nentries;
1130
1131 nentries = t4_chip_rss_size(padap);
1132 rc = cudbg_get_buff(pdbg_init, dbg_buff, nentries * sizeof(u16),
1133 &temp_buff);
1134 if (rc)
1135 return rc;
1136
1137 rc = t4_read_rss(padap, (u16 *)temp_buff.data);
1138 if (rc) {
1139 cudbg_err->sys_err = rc;
1140 cudbg_put_buff(pdbg_init, &temp_buff);
1141 return rc;
1142 }
1143 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1144}
1145
1146int cudbg_collect_rss_vf_config(struct cudbg_init *pdbg_init,
1147 struct cudbg_buffer *dbg_buff,
1148 struct cudbg_error *cudbg_err)
1149{
1150 struct adapter *padap = pdbg_init->adap;
1151 struct cudbg_buffer temp_buff = { 0 };
1152 struct cudbg_rss_vf_conf *vfconf;
1153 int vf, rc, vf_count;
1154
1155 vf_count = padap->params.arch.vfcount;
1156 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1157 vf_count * sizeof(struct cudbg_rss_vf_conf),
1158 &temp_buff);
1159 if (rc)
1160 return rc;
1161
1162 vfconf = (struct cudbg_rss_vf_conf *)temp_buff.data;
1163 for (vf = 0; vf < vf_count; vf++)
1164 t4_read_rss_vf_config(padap, vf, &vfconf[vf].rss_vf_vfl,
1165 &vfconf[vf].rss_vf_vfh, true);
1166 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1167}
1168
1169int cudbg_collect_path_mtu(struct cudbg_init *pdbg_init,
1170 struct cudbg_buffer *dbg_buff,
1171 struct cudbg_error *cudbg_err)
1172{
1173 struct adapter *padap = pdbg_init->adap;
1174 struct cudbg_buffer temp_buff = { 0 };
1175 int rc;
1176
1177 rc = cudbg_get_buff(pdbg_init, dbg_buff, NMTUS * sizeof(u16),
1178 &temp_buff);
1179 if (rc)
1180 return rc;
1181
1182 t4_read_mtu_tbl(padap, (u16 *)temp_buff.data, NULL);
1183 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1184}
1185
1186int cudbg_collect_pm_stats(struct cudbg_init *pdbg_init,
1187 struct cudbg_buffer *dbg_buff,
1188 struct cudbg_error *cudbg_err)
1189{
1190 struct adapter *padap = pdbg_init->adap;
1191 struct cudbg_buffer temp_buff = { 0 };
1192 struct cudbg_pm_stats *pm_stats_buff;
1193 int rc;
1194
1195 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_pm_stats),
1196 &temp_buff);
1197 if (rc)
1198 return rc;
1199
1200 pm_stats_buff = (struct cudbg_pm_stats *)temp_buff.data;
1201 t4_pmtx_get_stats(padap, pm_stats_buff->tx_cnt, pm_stats_buff->tx_cyc);
1202 t4_pmrx_get_stats(padap, pm_stats_buff->rx_cnt, pm_stats_buff->rx_cyc);
1203 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1204}
1205
1206int cudbg_collect_hw_sched(struct cudbg_init *pdbg_init,
1207 struct cudbg_buffer *dbg_buff,
1208 struct cudbg_error *cudbg_err)
1209{
1210 struct adapter *padap = pdbg_init->adap;
1211 struct cudbg_buffer temp_buff = { 0 };
1212 struct cudbg_hw_sched *hw_sched_buff;
1213 int i, rc = 0;
1214
1215 if (!padap->params.vpd.cclk)
1216 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1217
1218 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_hw_sched),
1219 &temp_buff);
1220
1221 if (rc)
1222 return rc;
1223
1224 hw_sched_buff = (struct cudbg_hw_sched *)temp_buff.data;
1225 hw_sched_buff->map = t4_read_reg(padap, TP_TX_MOD_QUEUE_REQ_MAP_A);
1226 hw_sched_buff->mode = TIMERMODE_G(t4_read_reg(padap, TP_MOD_CONFIG_A));
1227 t4_read_pace_tbl(padap, hw_sched_buff->pace_tab);
1228 for (i = 0; i < NTX_SCHED; ++i)
1229 t4_get_tx_sched(padap, i, &hw_sched_buff->kbps[i],
1230 &hw_sched_buff->ipg[i], true);
1231 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1232}
1233
1234int cudbg_collect_tp_indirect(struct cudbg_init *pdbg_init,
1235 struct cudbg_buffer *dbg_buff,
1236 struct cudbg_error *cudbg_err)
1237{
1238 struct adapter *padap = pdbg_init->adap;
1239 struct cudbg_buffer temp_buff = { 0 };
1240 struct ireg_buf *ch_tp_pio;
1241 int i, rc, n = 0;
1242 u32 size;
1243
1244 if (is_t5(padap->params.chip))
1245 n = sizeof(t5_tp_pio_array) +
1246 sizeof(t5_tp_tm_pio_array) +
1247 sizeof(t5_tp_mib_index_array);
1248 else
1249 n = sizeof(t6_tp_pio_array) +
1250 sizeof(t6_tp_tm_pio_array) +
1251 sizeof(t6_tp_mib_index_array);
1252
1253 n = n / (IREG_NUM_ELEM * sizeof(u32));
1254 size = sizeof(struct ireg_buf) * n;
1255 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1256 if (rc)
1257 return rc;
1258
1259 ch_tp_pio = (struct ireg_buf *)temp_buff.data;
1260
1261
1262 if (is_t5(padap->params.chip))
1263 n = sizeof(t5_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1264 else if (is_t6(padap->params.chip))
1265 n = sizeof(t6_tp_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1266
1267 for (i = 0; i < n; i++) {
1268 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1269 u32 *buff = ch_tp_pio->outbuf;
1270
1271 if (is_t5(padap->params.chip)) {
1272 tp_pio->ireg_addr = t5_tp_pio_array[i][0];
1273 tp_pio->ireg_data = t5_tp_pio_array[i][1];
1274 tp_pio->ireg_local_offset = t5_tp_pio_array[i][2];
1275 tp_pio->ireg_offset_range = t5_tp_pio_array[i][3];
1276 } else if (is_t6(padap->params.chip)) {
1277 tp_pio->ireg_addr = t6_tp_pio_array[i][0];
1278 tp_pio->ireg_data = t6_tp_pio_array[i][1];
1279 tp_pio->ireg_local_offset = t6_tp_pio_array[i][2];
1280 tp_pio->ireg_offset_range = t6_tp_pio_array[i][3];
1281 }
1282 t4_tp_pio_read(padap, buff, tp_pio->ireg_offset_range,
1283 tp_pio->ireg_local_offset, true);
1284 ch_tp_pio++;
1285 }
1286
1287
1288 if (is_t5(padap->params.chip))
1289 n = sizeof(t5_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1290 else if (is_t6(padap->params.chip))
1291 n = sizeof(t6_tp_tm_pio_array) / (IREG_NUM_ELEM * sizeof(u32));
1292
1293 for (i = 0; i < n; i++) {
1294 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1295 u32 *buff = ch_tp_pio->outbuf;
1296
1297 if (is_t5(padap->params.chip)) {
1298 tp_pio->ireg_addr = t5_tp_tm_pio_array[i][0];
1299 tp_pio->ireg_data = t5_tp_tm_pio_array[i][1];
1300 tp_pio->ireg_local_offset = t5_tp_tm_pio_array[i][2];
1301 tp_pio->ireg_offset_range = t5_tp_tm_pio_array[i][3];
1302 } else if (is_t6(padap->params.chip)) {
1303 tp_pio->ireg_addr = t6_tp_tm_pio_array[i][0];
1304 tp_pio->ireg_data = t6_tp_tm_pio_array[i][1];
1305 tp_pio->ireg_local_offset = t6_tp_tm_pio_array[i][2];
1306 tp_pio->ireg_offset_range = t6_tp_tm_pio_array[i][3];
1307 }
1308 t4_tp_tm_pio_read(padap, buff, tp_pio->ireg_offset_range,
1309 tp_pio->ireg_local_offset, true);
1310 ch_tp_pio++;
1311 }
1312
1313
1314 if (is_t5(padap->params.chip))
1315 n = sizeof(t5_tp_mib_index_array) /
1316 (IREG_NUM_ELEM * sizeof(u32));
1317 else if (is_t6(padap->params.chip))
1318 n = sizeof(t6_tp_mib_index_array) /
1319 (IREG_NUM_ELEM * sizeof(u32));
1320
1321 for (i = 0; i < n ; i++) {
1322 struct ireg_field *tp_pio = &ch_tp_pio->tp_pio;
1323 u32 *buff = ch_tp_pio->outbuf;
1324
1325 if (is_t5(padap->params.chip)) {
1326 tp_pio->ireg_addr = t5_tp_mib_index_array[i][0];
1327 tp_pio->ireg_data = t5_tp_mib_index_array[i][1];
1328 tp_pio->ireg_local_offset =
1329 t5_tp_mib_index_array[i][2];
1330 tp_pio->ireg_offset_range =
1331 t5_tp_mib_index_array[i][3];
1332 } else if (is_t6(padap->params.chip)) {
1333 tp_pio->ireg_addr = t6_tp_mib_index_array[i][0];
1334 tp_pio->ireg_data = t6_tp_mib_index_array[i][1];
1335 tp_pio->ireg_local_offset =
1336 t6_tp_mib_index_array[i][2];
1337 tp_pio->ireg_offset_range =
1338 t6_tp_mib_index_array[i][3];
1339 }
1340 t4_tp_mib_read(padap, buff, tp_pio->ireg_offset_range,
1341 tp_pio->ireg_local_offset, true);
1342 ch_tp_pio++;
1343 }
1344 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1345}
1346
1347static void cudbg_read_sge_qbase_indirect_reg(struct adapter *padap,
1348 struct sge_qbase_reg_field *qbase,
1349 u32 func, bool is_pf)
1350{
1351 u32 *buff, i;
1352
1353 if (is_pf) {
1354 buff = qbase->pf_data_value[func];
1355 } else {
1356 buff = qbase->vf_data_value[func];
1357
1358
1359
1360 func += 8;
1361 }
1362
1363 t4_write_reg(padap, qbase->reg_addr, func);
1364 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++, buff++)
1365 *buff = t4_read_reg(padap, qbase->reg_data[i]);
1366}
1367
1368int cudbg_collect_sge_indirect(struct cudbg_init *pdbg_init,
1369 struct cudbg_buffer *dbg_buff,
1370 struct cudbg_error *cudbg_err)
1371{
1372 struct adapter *padap = pdbg_init->adap;
1373 struct cudbg_buffer temp_buff = { 0 };
1374 struct sge_qbase_reg_field *sge_qbase;
1375 struct ireg_buf *ch_sge_dbg;
1376 int i, rc;
1377
1378 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1379 sizeof(*ch_sge_dbg) * 2 + sizeof(*sge_qbase),
1380 &temp_buff);
1381 if (rc)
1382 return rc;
1383
1384 ch_sge_dbg = (struct ireg_buf *)temp_buff.data;
1385 for (i = 0; i < 2; i++) {
1386 struct ireg_field *sge_pio = &ch_sge_dbg->tp_pio;
1387 u32 *buff = ch_sge_dbg->outbuf;
1388
1389 sge_pio->ireg_addr = t5_sge_dbg_index_array[i][0];
1390 sge_pio->ireg_data = t5_sge_dbg_index_array[i][1];
1391 sge_pio->ireg_local_offset = t5_sge_dbg_index_array[i][2];
1392 sge_pio->ireg_offset_range = t5_sge_dbg_index_array[i][3];
1393 t4_read_indirect(padap,
1394 sge_pio->ireg_addr,
1395 sge_pio->ireg_data,
1396 buff,
1397 sge_pio->ireg_offset_range,
1398 sge_pio->ireg_local_offset);
1399 ch_sge_dbg++;
1400 }
1401
1402 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
1403 sge_qbase = (struct sge_qbase_reg_field *)ch_sge_dbg;
1404
1405
1406
1407 sge_qbase->reg_addr = t6_sge_qbase_index_array[0];
1408 for (i = 0; i < SGE_QBASE_DATA_REG_NUM; i++)
1409 sge_qbase->reg_data[i] =
1410 t6_sge_qbase_index_array[i + 1];
1411
1412 for (i = 0; i <= PCIE_FW_MASTER_M; i++)
1413 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1414 i, true);
1415
1416 for (i = 0; i < padap->params.arch.vfcount; i++)
1417 cudbg_read_sge_qbase_indirect_reg(padap, sge_qbase,
1418 i, false);
1419
1420 sge_qbase->vfcount = padap->params.arch.vfcount;
1421 }
1422
1423 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1424}
1425
1426int cudbg_collect_ulprx_la(struct cudbg_init *pdbg_init,
1427 struct cudbg_buffer *dbg_buff,
1428 struct cudbg_error *cudbg_err)
1429{
1430 struct adapter *padap = pdbg_init->adap;
1431 struct cudbg_buffer temp_buff = { 0 };
1432 struct cudbg_ulprx_la *ulprx_la_buff;
1433 int rc;
1434
1435 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_ulprx_la),
1436 &temp_buff);
1437 if (rc)
1438 return rc;
1439
1440 ulprx_la_buff = (struct cudbg_ulprx_la *)temp_buff.data;
1441 t4_ulprx_read_la(padap, (u32 *)ulprx_la_buff->data);
1442 ulprx_la_buff->size = ULPRX_LA_SIZE;
1443 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1444}
1445
1446int cudbg_collect_tp_la(struct cudbg_init *pdbg_init,
1447 struct cudbg_buffer *dbg_buff,
1448 struct cudbg_error *cudbg_err)
1449{
1450 struct adapter *padap = pdbg_init->adap;
1451 struct cudbg_buffer temp_buff = { 0 };
1452 struct cudbg_tp_la *tp_la_buff;
1453 int size, rc;
1454
1455 size = sizeof(struct cudbg_tp_la) + TPLA_SIZE * sizeof(u64);
1456 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1457 if (rc)
1458 return rc;
1459
1460 tp_la_buff = (struct cudbg_tp_la *)temp_buff.data;
1461 tp_la_buff->mode = DBGLAMODE_G(t4_read_reg(padap, TP_DBG_LA_CONFIG_A));
1462 t4_tp_read_la(padap, (u64 *)tp_la_buff->data, NULL);
1463 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1464}
1465
1466int cudbg_collect_meminfo(struct cudbg_init *pdbg_init,
1467 struct cudbg_buffer *dbg_buff,
1468 struct cudbg_error *cudbg_err)
1469{
1470 struct adapter *padap = pdbg_init->adap;
1471 struct cudbg_buffer temp_buff = { 0 };
1472 struct cudbg_meminfo *meminfo_buff;
1473 struct cudbg_ver_hdr *ver_hdr;
1474 int rc;
1475
1476 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1477 sizeof(struct cudbg_ver_hdr) +
1478 sizeof(struct cudbg_meminfo),
1479 &temp_buff);
1480 if (rc)
1481 return rc;
1482
1483 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
1484 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
1485 ver_hdr->revision = CUDBG_MEMINFO_REV;
1486 ver_hdr->size = sizeof(struct cudbg_meminfo);
1487
1488 meminfo_buff = (struct cudbg_meminfo *)(temp_buff.data +
1489 sizeof(*ver_hdr));
1490 rc = cudbg_fill_meminfo(padap, meminfo_buff);
1491 if (rc) {
1492 cudbg_err->sys_err = rc;
1493 cudbg_put_buff(pdbg_init, &temp_buff);
1494 return rc;
1495 }
1496
1497 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1498}
1499
1500int cudbg_collect_cim_pif_la(struct cudbg_init *pdbg_init,
1501 struct cudbg_buffer *dbg_buff,
1502 struct cudbg_error *cudbg_err)
1503{
1504 struct cudbg_cim_pif_la *cim_pif_la_buff;
1505 struct adapter *padap = pdbg_init->adap;
1506 struct cudbg_buffer temp_buff = { 0 };
1507 int size, rc;
1508
1509 size = sizeof(struct cudbg_cim_pif_la) +
1510 2 * CIM_PIFLA_SIZE * 6 * sizeof(u32);
1511 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1512 if (rc)
1513 return rc;
1514
1515 cim_pif_la_buff = (struct cudbg_cim_pif_la *)temp_buff.data;
1516 cim_pif_la_buff->size = CIM_PIFLA_SIZE;
1517 t4_cim_read_pif_la(padap, (u32 *)cim_pif_la_buff->data,
1518 (u32 *)cim_pif_la_buff->data + 6 * CIM_PIFLA_SIZE,
1519 NULL, NULL);
1520 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1521}
1522
1523int cudbg_collect_clk_info(struct cudbg_init *pdbg_init,
1524 struct cudbg_buffer *dbg_buff,
1525 struct cudbg_error *cudbg_err)
1526{
1527 struct adapter *padap = pdbg_init->adap;
1528 struct cudbg_buffer temp_buff = { 0 };
1529 struct cudbg_clk_info *clk_info_buff;
1530 u64 tp_tick_us;
1531 int rc;
1532
1533 if (!padap->params.vpd.cclk)
1534 return CUDBG_STATUS_CCLK_NOT_DEFINED;
1535
1536 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_clk_info),
1537 &temp_buff);
1538 if (rc)
1539 return rc;
1540
1541 clk_info_buff = (struct cudbg_clk_info *)temp_buff.data;
1542 clk_info_buff->cclk_ps = 1000000000 / padap->params.vpd.cclk;
1543 clk_info_buff->res = t4_read_reg(padap, TP_TIMER_RESOLUTION_A);
1544 clk_info_buff->tre = TIMERRESOLUTION_G(clk_info_buff->res);
1545 clk_info_buff->dack_re = DELAYEDACKRESOLUTION_G(clk_info_buff->res);
1546 tp_tick_us = (clk_info_buff->cclk_ps << clk_info_buff->tre) / 1000000;
1547
1548 clk_info_buff->dack_timer =
1549 (clk_info_buff->cclk_ps << clk_info_buff->dack_re) / 1000000 *
1550 t4_read_reg(padap, TP_DACK_TIMER_A);
1551 clk_info_buff->retransmit_min =
1552 tp_tick_us * t4_read_reg(padap, TP_RXT_MIN_A);
1553 clk_info_buff->retransmit_max =
1554 tp_tick_us * t4_read_reg(padap, TP_RXT_MAX_A);
1555 clk_info_buff->persist_timer_min =
1556 tp_tick_us * t4_read_reg(padap, TP_PERS_MIN_A);
1557 clk_info_buff->persist_timer_max =
1558 tp_tick_us * t4_read_reg(padap, TP_PERS_MAX_A);
1559 clk_info_buff->keepalive_idle_timer =
1560 tp_tick_us * t4_read_reg(padap, TP_KEEP_IDLE_A);
1561 clk_info_buff->keepalive_interval =
1562 tp_tick_us * t4_read_reg(padap, TP_KEEP_INTVL_A);
1563 clk_info_buff->initial_srtt =
1564 tp_tick_us * INITSRTT_G(t4_read_reg(padap, TP_INIT_SRTT_A));
1565 clk_info_buff->finwait2_timer =
1566 tp_tick_us * t4_read_reg(padap, TP_FINWAIT2_TIMER_A);
1567
1568 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1569}
1570
1571int cudbg_collect_pcie_indirect(struct cudbg_init *pdbg_init,
1572 struct cudbg_buffer *dbg_buff,
1573 struct cudbg_error *cudbg_err)
1574{
1575 struct adapter *padap = pdbg_init->adap;
1576 struct cudbg_buffer temp_buff = { 0 };
1577 struct ireg_buf *ch_pcie;
1578 int i, rc, n;
1579 u32 size;
1580
1581 n = sizeof(t5_pcie_pdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1582 size = sizeof(struct ireg_buf) * n * 2;
1583 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1584 if (rc)
1585 return rc;
1586
1587 ch_pcie = (struct ireg_buf *)temp_buff.data;
1588
1589 for (i = 0; i < n; i++) {
1590 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1591 u32 *buff = ch_pcie->outbuf;
1592
1593 pcie_pio->ireg_addr = t5_pcie_pdbg_array[i][0];
1594 pcie_pio->ireg_data = t5_pcie_pdbg_array[i][1];
1595 pcie_pio->ireg_local_offset = t5_pcie_pdbg_array[i][2];
1596 pcie_pio->ireg_offset_range = t5_pcie_pdbg_array[i][3];
1597 t4_read_indirect(padap,
1598 pcie_pio->ireg_addr,
1599 pcie_pio->ireg_data,
1600 buff,
1601 pcie_pio->ireg_offset_range,
1602 pcie_pio->ireg_local_offset);
1603 ch_pcie++;
1604 }
1605
1606
1607 n = sizeof(t5_pcie_cdbg_array) / (IREG_NUM_ELEM * sizeof(u32));
1608 for (i = 0; i < n; i++) {
1609 struct ireg_field *pcie_pio = &ch_pcie->tp_pio;
1610 u32 *buff = ch_pcie->outbuf;
1611
1612 pcie_pio->ireg_addr = t5_pcie_cdbg_array[i][0];
1613 pcie_pio->ireg_data = t5_pcie_cdbg_array[i][1];
1614 pcie_pio->ireg_local_offset = t5_pcie_cdbg_array[i][2];
1615 pcie_pio->ireg_offset_range = t5_pcie_cdbg_array[i][3];
1616 t4_read_indirect(padap,
1617 pcie_pio->ireg_addr,
1618 pcie_pio->ireg_data,
1619 buff,
1620 pcie_pio->ireg_offset_range,
1621 pcie_pio->ireg_local_offset);
1622 ch_pcie++;
1623 }
1624 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1625}
1626
1627int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
1628 struct cudbg_buffer *dbg_buff,
1629 struct cudbg_error *cudbg_err)
1630{
1631 struct adapter *padap = pdbg_init->adap;
1632 struct cudbg_buffer temp_buff = { 0 };
1633 struct ireg_buf *ch_pm;
1634 int i, rc, n;
1635 u32 size;
1636
1637 n = sizeof(t5_pm_rx_array) / (IREG_NUM_ELEM * sizeof(u32));
1638 size = sizeof(struct ireg_buf) * n * 2;
1639 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1640 if (rc)
1641 return rc;
1642
1643 ch_pm = (struct ireg_buf *)temp_buff.data;
1644
1645 for (i = 0; i < n; i++) {
1646 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1647 u32 *buff = ch_pm->outbuf;
1648
1649 pm_pio->ireg_addr = t5_pm_rx_array[i][0];
1650 pm_pio->ireg_data = t5_pm_rx_array[i][1];
1651 pm_pio->ireg_local_offset = t5_pm_rx_array[i][2];
1652 pm_pio->ireg_offset_range = t5_pm_rx_array[i][3];
1653 t4_read_indirect(padap,
1654 pm_pio->ireg_addr,
1655 pm_pio->ireg_data,
1656 buff,
1657 pm_pio->ireg_offset_range,
1658 pm_pio->ireg_local_offset);
1659 ch_pm++;
1660 }
1661
1662
1663 n = sizeof(t5_pm_tx_array) / (IREG_NUM_ELEM * sizeof(u32));
1664 for (i = 0; i < n; i++) {
1665 struct ireg_field *pm_pio = &ch_pm->tp_pio;
1666 u32 *buff = ch_pm->outbuf;
1667
1668 pm_pio->ireg_addr = t5_pm_tx_array[i][0];
1669 pm_pio->ireg_data = t5_pm_tx_array[i][1];
1670 pm_pio->ireg_local_offset = t5_pm_tx_array[i][2];
1671 pm_pio->ireg_offset_range = t5_pm_tx_array[i][3];
1672 t4_read_indirect(padap,
1673 pm_pio->ireg_addr,
1674 pm_pio->ireg_data,
1675 buff,
1676 pm_pio->ireg_offset_range,
1677 pm_pio->ireg_local_offset);
1678 ch_pm++;
1679 }
1680 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1681}
1682
1683int cudbg_collect_tid(struct cudbg_init *pdbg_init,
1684 struct cudbg_buffer *dbg_buff,
1685 struct cudbg_error *cudbg_err)
1686{
1687 struct adapter *padap = pdbg_init->adap;
1688 struct cudbg_tid_info_region_rev1 *tid1;
1689 struct cudbg_buffer temp_buff = { 0 };
1690 struct cudbg_tid_info_region *tid;
1691 u32 para[2], val[2];
1692 int rc;
1693
1694 rc = cudbg_get_buff(pdbg_init, dbg_buff,
1695 sizeof(struct cudbg_tid_info_region_rev1),
1696 &temp_buff);
1697 if (rc)
1698 return rc;
1699
1700 tid1 = (struct cudbg_tid_info_region_rev1 *)temp_buff.data;
1701 tid = &tid1->tid;
1702 tid1->ver_hdr.signature = CUDBG_ENTITY_SIGNATURE;
1703 tid1->ver_hdr.revision = CUDBG_TID_INFO_REV;
1704 tid1->ver_hdr.size = sizeof(struct cudbg_tid_info_region_rev1) -
1705 sizeof(struct cudbg_ver_hdr);
1706
1707
1708
1709
1710 if (!is_fw_attached(pdbg_init))
1711 goto fill_tid;
1712
1713#define FW_PARAM_PFVF_A(param) \
1714 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) | \
1715 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_##param) | \
1716 FW_PARAMS_PARAM_Y_V(0) | \
1717 FW_PARAMS_PARAM_Z_V(0))
1718
1719 para[0] = FW_PARAM_PFVF_A(ETHOFLD_START);
1720 para[1] = FW_PARAM_PFVF_A(ETHOFLD_END);
1721 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2, para, val);
1722 if (rc < 0) {
1723 cudbg_err->sys_err = rc;
1724 cudbg_put_buff(pdbg_init, &temp_buff);
1725 return rc;
1726 }
1727 tid->uotid_base = val[0];
1728 tid->nuotids = val[1] - val[0] + 1;
1729
1730 if (is_t5(padap->params.chip)) {
1731 tid->sb = t4_read_reg(padap, LE_DB_SERVER_INDEX_A) / 4;
1732 } else if (is_t6(padap->params.chip)) {
1733 tid1->tid_start =
1734 t4_read_reg(padap, LE_DB_ACTIVE_TABLE_START_INDEX_A);
1735 tid->sb = t4_read_reg(padap, LE_DB_SRVR_START_INDEX_A);
1736
1737 para[0] = FW_PARAM_PFVF_A(HPFILTER_START);
1738 para[1] = FW_PARAM_PFVF_A(HPFILTER_END);
1739 rc = t4_query_params(padap, padap->mbox, padap->pf, 0, 2,
1740 para, val);
1741 if (rc < 0) {
1742 cudbg_err->sys_err = rc;
1743 cudbg_put_buff(pdbg_init, &temp_buff);
1744 return rc;
1745 }
1746 tid->hpftid_base = val[0];
1747 tid->nhpftids = val[1] - val[0] + 1;
1748 }
1749
1750#undef FW_PARAM_PFVF_A
1751
1752fill_tid:
1753 tid->ntids = padap->tids.ntids;
1754 tid->nstids = padap->tids.nstids;
1755 tid->stid_base = padap->tids.stid_base;
1756 tid->hash_base = padap->tids.hash_base;
1757
1758 tid->natids = padap->tids.natids;
1759 tid->nftids = padap->tids.nftids;
1760 tid->ftid_base = padap->tids.ftid_base;
1761 tid->aftid_base = padap->tids.aftid_base;
1762 tid->aftid_end = padap->tids.aftid_end;
1763
1764 tid->sftid_base = padap->tids.sftid_base;
1765 tid->nsftids = padap->tids.nsftids;
1766
1767 tid->flags = padap->flags;
1768 tid->le_db_conf = t4_read_reg(padap, LE_DB_CONFIG_A);
1769 tid->ip_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV4_A);
1770 tid->ipv6_users = t4_read_reg(padap, LE_DB_ACT_CNT_IPV6_A);
1771
1772 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1773}
1774
1775int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,
1776 struct cudbg_buffer *dbg_buff,
1777 struct cudbg_error *cudbg_err)
1778{
1779 struct adapter *padap = pdbg_init->adap;
1780 struct cudbg_buffer temp_buff = { 0 };
1781 u32 size, *value, j;
1782 int i, rc, n;
1783
1784 size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;
1785 n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));
1786 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1787 if (rc)
1788 return rc;
1789
1790 value = (u32 *)temp_buff.data;
1791 for (i = 0; i < n; i++) {
1792 for (j = t5_pcie_config_array[i][0];
1793 j <= t5_pcie_config_array[i][1]; j += 4) {
1794 t4_hw_pci_read_cfg4(padap, j, value);
1795 value++;
1796 }
1797 }
1798 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
1799}
1800
1801static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)
1802{
1803 int index, bit, bit_pos = 0;
1804
1805 switch (type) {
1806 case CTXT_EGRESS:
1807 bit_pos = 176;
1808 break;
1809 case CTXT_INGRESS:
1810 bit_pos = 141;
1811 break;
1812 case CTXT_FLM:
1813 bit_pos = 89;
1814 break;
1815 }
1816 index = bit_pos / 32;
1817 bit = bit_pos % 32;
1818 return buf[index] & (1U << bit);
1819}
1820
1821static int cudbg_get_ctxt_region_info(struct adapter *padap,
1822 struct cudbg_region_info *ctx_info,
1823 u8 *mem_type)
1824{
1825 struct cudbg_mem_desc mem_desc;
1826 struct cudbg_meminfo meminfo;
1827 u32 i, j, value, found;
1828 u8 flq;
1829 int rc;
1830
1831 rc = cudbg_fill_meminfo(padap, &meminfo);
1832 if (rc)
1833 return rc;
1834
1835
1836 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
1837 found = 0;
1838 memset(&mem_desc, 0, sizeof(struct cudbg_mem_desc));
1839 for (j = 0; j < ARRAY_SIZE(meminfo.avail); j++) {
1840 rc = cudbg_get_mem_region(padap, &meminfo, j,
1841 cudbg_region[i],
1842 &mem_desc);
1843 if (!rc) {
1844 found = 1;
1845 rc = cudbg_get_mem_relative(padap, &meminfo, j,
1846 &mem_desc.base,
1847 &mem_desc.limit);
1848 if (rc) {
1849 ctx_info[i].exist = false;
1850 break;
1851 }
1852 ctx_info[i].exist = true;
1853 ctx_info[i].start = mem_desc.base;
1854 ctx_info[i].end = mem_desc.limit;
1855 mem_type[i] = j;
1856 break;
1857 }
1858 }
1859 if (!found)
1860 ctx_info[i].exist = false;
1861 }
1862
1863
1864 value = t4_read_reg(padap, SGE_FLM_CFG_A);
1865
1866
1867 flq = HDRSTARTFLQ_G(value);
1868 ctx_info[CTXT_FLM].exist = true;
1869 ctx_info[CTXT_FLM].end = (CUDBG_MAX_FL_QIDS >> flq) * SGE_CTXT_SIZE;
1870
1871
1872
1873
1874 ctx_info[CTXT_CNM].exist = true;
1875 ctx_info[CTXT_CNM].end = ctx_info[CTXT_FLM].end;
1876
1877 return 0;
1878}
1879
1880int cudbg_dump_context_size(struct adapter *padap)
1881{
1882 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1883 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1884 u32 i, size = 0;
1885 int rc;
1886
1887
1888 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1889 if (rc)
1890 return rc;
1891
1892 for (i = 0; i < CTXT_CNM; i++) {
1893 if (!region_info[i].exist) {
1894 if (i == CTXT_EGRESS || i == CTXT_INGRESS)
1895 size += CUDBG_LOWMEM_MAX_CTXT_QIDS *
1896 SGE_CTXT_SIZE;
1897 continue;
1898 }
1899
1900 size += (region_info[i].end - region_info[i].start + 1) /
1901 SGE_CTXT_SIZE;
1902 }
1903 return size * sizeof(struct cudbg_ch_cntxt);
1904}
1905
1906static void cudbg_read_sge_ctxt(struct cudbg_init *pdbg_init, u32 cid,
1907 enum ctxt_type ctype, u32 *data)
1908{
1909 struct adapter *padap = pdbg_init->adap;
1910 int rc = -1;
1911
1912
1913
1914
1915
1916
1917
1918
1919 if (is_fw_attached(pdbg_init))
1920 rc = t4_sge_ctxt_rd(padap, padap->mbox, cid, ctype, data);
1921 if (rc)
1922 t4_sge_ctxt_rd_bd(padap, cid, ctype, data);
1923}
1924
1925static void cudbg_get_sge_ctxt_fw(struct cudbg_init *pdbg_init, u32 max_qid,
1926 u8 ctxt_type,
1927 struct cudbg_ch_cntxt **out_buff)
1928{
1929 struct cudbg_ch_cntxt *buff = *out_buff;
1930 int rc;
1931 u32 j;
1932
1933 for (j = 0; j < max_qid; j++) {
1934 cudbg_read_sge_ctxt(pdbg_init, j, ctxt_type, buff->data);
1935 rc = cudbg_sge_ctxt_check_valid(buff->data, ctxt_type);
1936 if (!rc)
1937 continue;
1938
1939 buff->cntxt_type = ctxt_type;
1940 buff->cntxt_id = j;
1941 buff++;
1942 if (ctxt_type == CTXT_FLM) {
1943 cudbg_read_sge_ctxt(pdbg_init, j, CTXT_CNM, buff->data);
1944 buff->cntxt_type = CTXT_CNM;
1945 buff->cntxt_id = j;
1946 buff++;
1947 }
1948 }
1949
1950 *out_buff = buff;
1951}
1952
1953int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,
1954 struct cudbg_buffer *dbg_buff,
1955 struct cudbg_error *cudbg_err)
1956{
1957 struct cudbg_region_info region_info[CTXT_CNM + 1] = { {0} };
1958 struct adapter *padap = pdbg_init->adap;
1959 u32 j, size, max_ctx_size, max_ctx_qid;
1960 u8 mem_type[CTXT_INGRESS + 1] = { 0 };
1961 struct cudbg_buffer temp_buff = { 0 };
1962 struct cudbg_ch_cntxt *buff;
1963 u64 *dst_off, *src_off;
1964 u8 *ctx_buf;
1965 u8 i, k;
1966 int rc;
1967
1968
1969 rc = cudbg_get_ctxt_region_info(padap, region_info, mem_type);
1970 if (rc)
1971 return rc;
1972
1973 rc = cudbg_dump_context_size(padap);
1974 if (rc <= 0)
1975 return CUDBG_STATUS_ENTITY_NOT_FOUND;
1976
1977 size = rc;
1978 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
1979 if (rc)
1980 return rc;
1981
1982
1983
1984
1985 max_ctx_size = max(region_info[CTXT_EGRESS].end -
1986 region_info[CTXT_EGRESS].start + 1,
1987 region_info[CTXT_INGRESS].end -
1988 region_info[CTXT_INGRESS].start + 1);
1989
1990 ctx_buf = kvzalloc(max_ctx_size, GFP_KERNEL);
1991 if (!ctx_buf) {
1992 cudbg_put_buff(pdbg_init, &temp_buff);
1993 return -ENOMEM;
1994 }
1995
1996 buff = (struct cudbg_ch_cntxt *)temp_buff.data;
1997
1998
1999
2000
2001
2002 for (i = CTXT_EGRESS; i <= CTXT_INGRESS; i++) {
2003 if (!region_info[i].exist) {
2004 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2005 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2006 &buff);
2007 continue;
2008 }
2009
2010 max_ctx_size = region_info[i].end - region_info[i].start + 1;
2011 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2012
2013
2014
2015
2016 if (is_fw_attached(pdbg_init)) {
2017 t4_sge_ctxt_flush(padap, padap->mbox, i);
2018
2019 rc = t4_memory_rw(padap, MEMWIN_NIC, mem_type[i],
2020 region_info[i].start, max_ctx_size,
2021 (__be32 *)ctx_buf, 1);
2022 }
2023
2024 if (rc || !is_fw_attached(pdbg_init)) {
2025 max_ctx_qid = CUDBG_LOWMEM_MAX_CTXT_QIDS;
2026 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, i,
2027 &buff);
2028 continue;
2029 }
2030
2031 for (j = 0; j < max_ctx_qid; j++) {
2032 src_off = (u64 *)(ctx_buf + j * SGE_CTXT_SIZE);
2033 dst_off = (u64 *)buff->data;
2034
2035
2036
2037
2038 for (k = 0; k < SGE_CTXT_SIZE / sizeof(u64); k++)
2039 dst_off[k] = cpu_to_be64(src_off[k]);
2040
2041 rc = cudbg_sge_ctxt_check_valid(buff->data, i);
2042 if (!rc)
2043 continue;
2044
2045 buff->cntxt_type = i;
2046 buff->cntxt_id = j;
2047 buff++;
2048 }
2049 }
2050
2051 kvfree(ctx_buf);
2052
2053
2054 max_ctx_size = region_info[CTXT_FLM].end -
2055 region_info[CTXT_FLM].start + 1;
2056 max_ctx_qid = max_ctx_size / SGE_CTXT_SIZE;
2057
2058
2059
2060 cudbg_get_sge_ctxt_fw(pdbg_init, max_ctx_qid, CTXT_FLM, &buff);
2061
2062 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2063}
2064
2065static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
2066{
2067 *mask = x | y;
2068 y = (__force u64)cpu_to_be64(y);
2069 memcpy(addr, (char *)&y + 2, ETH_ALEN);
2070}
2071
2072static void cudbg_mps_rpl_backdoor(struct adapter *padap,
2073 struct fw_ldst_mps_rplc *mps_rplc)
2074{
2075 if (is_t5(padap->params.chip)) {
2076 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2077 MPS_VF_RPLCT_MAP3_A));
2078 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2079 MPS_VF_RPLCT_MAP2_A));
2080 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2081 MPS_VF_RPLCT_MAP1_A));
2082 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2083 MPS_VF_RPLCT_MAP0_A));
2084 } else {
2085 mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
2086 MPS_VF_RPLCT_MAP7_A));
2087 mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
2088 MPS_VF_RPLCT_MAP6_A));
2089 mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
2090 MPS_VF_RPLCT_MAP5_A));
2091 mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
2092 MPS_VF_RPLCT_MAP4_A));
2093 }
2094 mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
2095 mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
2096 mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
2097 mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
2098}
2099
2100static int cudbg_collect_tcam_index(struct cudbg_init *pdbg_init,
2101 struct cudbg_mps_tcam *tcam, u32 idx)
2102{
2103 struct adapter *padap = pdbg_init->adap;
2104 u64 tcamy, tcamx, val;
2105 u32 ctl, data2;
2106 int rc = 0;
2107
2108 if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
2109
2110
2111
2112
2113
2114
2115
2116 ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
2117 if (idx < 256)
2118 ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
2119 else
2120 ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
2121
2122 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2123 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2124 tcamy = DMACH_G(val) << 32;
2125 tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2126 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2127 tcam->lookup_type = DATALKPTYPE_G(data2);
2128
2129
2130
2131
2132
2133 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2134
2135 tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2136 tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
2137 tcam->dip_hit = data2 & DATADIPHIT_F;
2138 } else {
2139 tcam->vlan_vld = data2 & DATAVIDH2_F;
2140 tcam->ivlan = VIDL_G(val);
2141 }
2142
2143 tcam->port_num = DATAPORTNUM_G(data2);
2144
2145
2146 ctl |= CTLXYBITSEL_V(1);
2147 t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
2148 val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
2149 tcamx = DMACH_G(val) << 32;
2150 tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
2151 data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
2152 if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
2153
2154 tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
2155 tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
2156 }
2157 } else {
2158 tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
2159 tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
2160 }
2161
2162
2163 if (tcamx & tcamy)
2164 return rc;
2165
2166 tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
2167 tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
2168
2169 if (is_t5(padap->params.chip))
2170 tcam->repli = (tcam->cls_lo & REPLICATE_F);
2171 else if (is_t6(padap->params.chip))
2172 tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
2173
2174 if (tcam->repli) {
2175 struct fw_ldst_cmd ldst_cmd;
2176 struct fw_ldst_mps_rplc mps_rplc;
2177
2178 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
2179 ldst_cmd.op_to_addrspace =
2180 htonl(FW_CMD_OP_V(FW_LDST_CMD) |
2181 FW_CMD_REQUEST_F | FW_CMD_READ_F |
2182 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
2183 ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
2184 ldst_cmd.u.mps.rplc.fid_idx =
2185 htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
2186 FW_LDST_CMD_IDX_V(idx));
2187
2188
2189
2190
2191 if (is_fw_attached(pdbg_init))
2192 rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd,
2193 sizeof(ldst_cmd), &ldst_cmd);
2194
2195 if (rc || !is_fw_attached(pdbg_init)) {
2196 cudbg_mps_rpl_backdoor(padap, &mps_rplc);
2197
2198
2199
2200 rc = 0;
2201 } else {
2202 mps_rplc = ldst_cmd.u.mps.rplc;
2203 }
2204
2205 tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
2206 tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
2207 tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
2208 tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
2209 if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
2210 tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
2211 tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
2212 tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
2213 tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
2214 }
2215 }
2216 cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
2217 tcam->idx = idx;
2218 tcam->rplc_size = padap->params.arch.mps_rplc_size;
2219 return rc;
2220}
2221
2222int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
2223 struct cudbg_buffer *dbg_buff,
2224 struct cudbg_error *cudbg_err)
2225{
2226 struct adapter *padap = pdbg_init->adap;
2227 struct cudbg_buffer temp_buff = { 0 };
2228 u32 size = 0, i, n, total_size = 0;
2229 struct cudbg_mps_tcam *tcam;
2230 int rc;
2231
2232 n = padap->params.arch.mps_tcam_size;
2233 size = sizeof(struct cudbg_mps_tcam) * n;
2234 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2235 if (rc)
2236 return rc;
2237
2238 tcam = (struct cudbg_mps_tcam *)temp_buff.data;
2239 for (i = 0; i < n; i++) {
2240 rc = cudbg_collect_tcam_index(pdbg_init, tcam, i);
2241 if (rc) {
2242 cudbg_err->sys_err = rc;
2243 cudbg_put_buff(pdbg_init, &temp_buff);
2244 return rc;
2245 }
2246 total_size += sizeof(struct cudbg_mps_tcam);
2247 tcam++;
2248 }
2249
2250 if (!total_size) {
2251 rc = CUDBG_SYSTEM_ERROR;
2252 cudbg_err->sys_err = rc;
2253 cudbg_put_buff(pdbg_init, &temp_buff);
2254 return rc;
2255 }
2256 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2257}
2258
2259int cudbg_collect_vpd_data(struct cudbg_init *pdbg_init,
2260 struct cudbg_buffer *dbg_buff,
2261 struct cudbg_error *cudbg_err)
2262{
2263 struct adapter *padap = pdbg_init->adap;
2264 struct cudbg_buffer temp_buff = { 0 };
2265 char vpd_str[CUDBG_VPD_VER_LEN + 1];
2266 u32 scfg_vers, vpd_vers, fw_vers;
2267 struct cudbg_vpd_data *vpd_data;
2268 struct vpd_params vpd = { 0 };
2269 int rc, ret;
2270
2271 rc = t4_get_raw_vpd_params(padap, &vpd);
2272 if (rc)
2273 return rc;
2274
2275 rc = t4_get_fw_version(padap, &fw_vers);
2276 if (rc)
2277 return rc;
2278
2279
2280
2281
2282 rc = pci_set_vpd_size(padap->pdev, EEPROMVSIZE);
2283 if (rc < 0)
2284 return rc;
2285
2286 ret = cudbg_read_vpd_reg(padap, CUDBG_SCFG_VER_ADDR, CUDBG_SCFG_VER_LEN,
2287 &scfg_vers);
2288
2289
2290 rc = pci_set_vpd_size(padap->pdev, CUDBG_VPD_PF_SIZE);
2291 if (rc < 0)
2292 return rc;
2293
2294 if (ret)
2295 return ret;
2296
2297 rc = cudbg_read_vpd_reg(padap, CUDBG_VPD_VER_ADDR, CUDBG_VPD_VER_LEN,
2298 vpd_str);
2299 if (rc)
2300 return rc;
2301
2302 vpd_str[CUDBG_VPD_VER_LEN] = '\0';
2303 rc = kstrtouint(vpd_str, 0, &vpd_vers);
2304 if (rc)
2305 return rc;
2306
2307 rc = cudbg_get_buff(pdbg_init, dbg_buff, sizeof(struct cudbg_vpd_data),
2308 &temp_buff);
2309 if (rc)
2310 return rc;
2311
2312 vpd_data = (struct cudbg_vpd_data *)temp_buff.data;
2313 memcpy(vpd_data->sn, vpd.sn, SERNUM_LEN + 1);
2314 memcpy(vpd_data->bn, vpd.pn, PN_LEN + 1);
2315 memcpy(vpd_data->na, vpd.na, MACADDR_LEN + 1);
2316 memcpy(vpd_data->mn, vpd.id, ID_LEN + 1);
2317 vpd_data->scfg_vers = scfg_vers;
2318 vpd_data->vpd_vers = vpd_vers;
2319 vpd_data->fw_major = FW_HDR_FW_VER_MAJOR_G(fw_vers);
2320 vpd_data->fw_minor = FW_HDR_FW_VER_MINOR_G(fw_vers);
2321 vpd_data->fw_micro = FW_HDR_FW_VER_MICRO_G(fw_vers);
2322 vpd_data->fw_build = FW_HDR_FW_VER_BUILD_G(fw_vers);
2323 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2324}
2325
2326static int cudbg_read_tid(struct cudbg_init *pdbg_init, u32 tid,
2327 struct cudbg_tid_data *tid_data)
2328{
2329 struct adapter *padap = pdbg_init->adap;
2330 int i, cmd_retry = 8;
2331 u32 val;
2332
2333
2334 for (i = 0; i < NUM_LE_DB_DBGI_REQ_DATA_INSTANCES; i++)
2335 t4_write_reg(padap, LE_DB_DBGI_REQ_DATA_A + (i << 2), 0);
2336
2337
2338 val = DBGICMD_V(4) | DBGITID_V(tid);
2339 t4_write_reg(padap, LE_DB_DBGI_REQ_TCAM_CMD_A, val);
2340 tid_data->dbig_cmd = val;
2341
2342 val = DBGICMDSTRT_F | DBGICMDMODE_V(1);
2343 t4_write_reg(padap, LE_DB_DBGI_CONFIG_A, val);
2344 tid_data->dbig_conf = val;
2345
2346
2347 val = 1;
2348 while (val) {
2349 val = t4_read_reg(padap, LE_DB_DBGI_CONFIG_A);
2350 val = val & DBGICMDBUSY_F;
2351 cmd_retry--;
2352 if (!cmd_retry)
2353 return CUDBG_SYSTEM_ERROR;
2354 }
2355
2356
2357 val = t4_read_reg(padap, LE_DB_DBGI_RSP_STATUS_A);
2358 tid_data->dbig_rsp_stat = val;
2359 if (!(val & 1))
2360 return CUDBG_SYSTEM_ERROR;
2361
2362
2363 for (i = 0; i < NUM_LE_DB_DBGI_RSP_DATA_INSTANCES; i++)
2364 tid_data->data[i] = t4_read_reg(padap,
2365 LE_DB_DBGI_RSP_DATA_A +
2366 (i << 2));
2367 tid_data->tid = tid;
2368 return 0;
2369}
2370
2371static int cudbg_get_le_type(u32 tid, struct cudbg_tcam tcam_region)
2372{
2373 int type = LE_ET_UNKNOWN;
2374
2375 if (tid < tcam_region.server_start)
2376 type = LE_ET_TCAM_CON;
2377 else if (tid < tcam_region.filter_start)
2378 type = LE_ET_TCAM_SERVER;
2379 else if (tid < tcam_region.clip_start)
2380 type = LE_ET_TCAM_FILTER;
2381 else if (tid < tcam_region.routing_start)
2382 type = LE_ET_TCAM_CLIP;
2383 else if (tid < tcam_region.tid_hash_base)
2384 type = LE_ET_TCAM_ROUTING;
2385 else if (tid < tcam_region.max_tid)
2386 type = LE_ET_HASH_CON;
2387 else
2388 type = LE_ET_INVALID_TID;
2389
2390 return type;
2391}
2392
2393static int cudbg_is_ipv6_entry(struct cudbg_tid_data *tid_data,
2394 struct cudbg_tcam tcam_region)
2395{
2396 int ipv6 = 0;
2397 int le_type;
2398
2399 le_type = cudbg_get_le_type(tid_data->tid, tcam_region);
2400 if (tid_data->tid & 1)
2401 return 0;
2402
2403 if (le_type == LE_ET_HASH_CON) {
2404 ipv6 = tid_data->data[16] & 0x8000;
2405 } else if (le_type == LE_ET_TCAM_CON) {
2406 ipv6 = tid_data->data[16] & 0x8000;
2407 if (ipv6)
2408 ipv6 = tid_data->data[9] == 0x00C00000;
2409 } else {
2410 ipv6 = 0;
2411 }
2412 return ipv6;
2413}
2414
2415void cudbg_fill_le_tcam_info(struct adapter *padap,
2416 struct cudbg_tcam *tcam_region)
2417{
2418 u32 value;
2419
2420
2421 value = t4_read_reg(padap, LE_DB_TID_HASHBASE_A);
2422 tcam_region->tid_hash_base = value;
2423
2424
2425 value = t4_read_reg(padap, LE_DB_ROUTING_TABLE_INDEX_A);
2426 tcam_region->routing_start = value;
2427
2428
2429 if (is_t6(padap->params.chip))
2430 value = t4_read_reg(padap, LE_DB_CLCAM_TID_BASE_A);
2431 else
2432 value = t4_read_reg(padap, LE_DB_CLIP_TABLE_INDEX_A);
2433 tcam_region->clip_start = value;
2434
2435
2436 value = t4_read_reg(padap, LE_DB_FILTER_TABLE_INDEX_A);
2437 tcam_region->filter_start = value;
2438
2439
2440 value = t4_read_reg(padap, LE_DB_SERVER_INDEX_A);
2441 tcam_region->server_start = value;
2442
2443
2444 value = t4_read_reg(padap, LE_DB_CONFIG_A);
2445 if ((value >> HASHEN_S) & 1) {
2446 value = t4_read_reg(padap, LE_DB_HASH_CONFIG_A);
2447 if (CHELSIO_CHIP_VERSION(padap->params.chip) > CHELSIO_T5) {
2448 tcam_region->max_tid = (value & 0xFFFFF) +
2449 tcam_region->tid_hash_base;
2450 } else {
2451 value = HASHTIDSIZE_G(value);
2452 value = 1 << value;
2453 tcam_region->max_tid = value +
2454 tcam_region->tid_hash_base;
2455 }
2456 } else {
2457 if (is_t6(padap->params.chip))
2458 tcam_region->max_tid = (value & ASLIPCOMPEN_F) ?
2459 CUDBG_MAX_TID_COMP_EN :
2460 CUDBG_MAX_TID_COMP_DIS;
2461 else
2462 tcam_region->max_tid = CUDBG_MAX_TCAM_TID;
2463 }
2464
2465 if (is_t6(padap->params.chip))
2466 tcam_region->max_tid += CUDBG_T6_CLIP;
2467}
2468
2469int cudbg_collect_le_tcam(struct cudbg_init *pdbg_init,
2470 struct cudbg_buffer *dbg_buff,
2471 struct cudbg_error *cudbg_err)
2472{
2473 struct adapter *padap = pdbg_init->adap;
2474 struct cudbg_buffer temp_buff = { 0 };
2475 struct cudbg_tcam tcam_region = { 0 };
2476 struct cudbg_tid_data *tid_data;
2477 u32 bytes = 0;
2478 int rc, size;
2479 u32 i;
2480
2481 cudbg_fill_le_tcam_info(padap, &tcam_region);
2482
2483 size = sizeof(struct cudbg_tid_data) * tcam_region.max_tid;
2484 size += sizeof(struct cudbg_tcam);
2485 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2486 if (rc)
2487 return rc;
2488
2489 memcpy(temp_buff.data, &tcam_region, sizeof(struct cudbg_tcam));
2490 bytes = sizeof(struct cudbg_tcam);
2491 tid_data = (struct cudbg_tid_data *)(temp_buff.data + bytes);
2492
2493 for (i = 0; i < tcam_region.max_tid; ) {
2494 rc = cudbg_read_tid(pdbg_init, i, tid_data);
2495 if (rc) {
2496 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
2497
2498 tcam_region.max_tid = i;
2499 memcpy(temp_buff.data, &tcam_region,
2500 sizeof(struct cudbg_tcam));
2501 goto out;
2502 }
2503
2504 if (cudbg_is_ipv6_entry(tid_data, tcam_region)) {
2505
2506 if (is_t6(padap->params.chip) &&
2507 i >= tcam_region.clip_start &&
2508 i < tcam_region.clip_start + CUDBG_T6_CLIP)
2509 i += 4;
2510 else
2511 i += 2;
2512 } else {
2513 i++;
2514 }
2515
2516 tid_data++;
2517 bytes += sizeof(struct cudbg_tid_data);
2518 }
2519
2520out:
2521 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2522}
2523
2524int cudbg_collect_cctrl(struct cudbg_init *pdbg_init,
2525 struct cudbg_buffer *dbg_buff,
2526 struct cudbg_error *cudbg_err)
2527{
2528 struct adapter *padap = pdbg_init->adap;
2529 struct cudbg_buffer temp_buff = { 0 };
2530 u32 size;
2531 int rc;
2532
2533 size = sizeof(u16) * NMTUS * NCCTRL_WIN;
2534 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2535 if (rc)
2536 return rc;
2537
2538 t4_read_cong_tbl(padap, (void *)temp_buff.data);
2539 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2540}
2541
2542int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
2543 struct cudbg_buffer *dbg_buff,
2544 struct cudbg_error *cudbg_err)
2545{
2546 struct adapter *padap = pdbg_init->adap;
2547 struct cudbg_buffer temp_buff = { 0 };
2548 struct ireg_buf *ma_indr;
2549 int i, rc, n;
2550 u32 size, j;
2551
2552 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2553 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2554
2555 n = sizeof(t6_ma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2556 size = sizeof(struct ireg_buf) * n * 2;
2557 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2558 if (rc)
2559 return rc;
2560
2561 ma_indr = (struct ireg_buf *)temp_buff.data;
2562 for (i = 0; i < n; i++) {
2563 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2564 u32 *buff = ma_indr->outbuf;
2565
2566 ma_fli->ireg_addr = t6_ma_ireg_array[i][0];
2567 ma_fli->ireg_data = t6_ma_ireg_array[i][1];
2568 ma_fli->ireg_local_offset = t6_ma_ireg_array[i][2];
2569 ma_fli->ireg_offset_range = t6_ma_ireg_array[i][3];
2570 t4_read_indirect(padap, ma_fli->ireg_addr, ma_fli->ireg_data,
2571 buff, ma_fli->ireg_offset_range,
2572 ma_fli->ireg_local_offset);
2573 ma_indr++;
2574 }
2575
2576 n = sizeof(t6_ma_ireg_array2) / (IREG_NUM_ELEM * sizeof(u32));
2577 for (i = 0; i < n; i++) {
2578 struct ireg_field *ma_fli = &ma_indr->tp_pio;
2579 u32 *buff = ma_indr->outbuf;
2580
2581 ma_fli->ireg_addr = t6_ma_ireg_array2[i][0];
2582 ma_fli->ireg_data = t6_ma_ireg_array2[i][1];
2583 ma_fli->ireg_local_offset = t6_ma_ireg_array2[i][2];
2584 for (j = 0; j < t6_ma_ireg_array2[i][3]; j++) {
2585 t4_read_indirect(padap, ma_fli->ireg_addr,
2586 ma_fli->ireg_data, buff, 1,
2587 ma_fli->ireg_local_offset);
2588 buff++;
2589 ma_fli->ireg_local_offset += 0x20;
2590 }
2591 ma_indr++;
2592 }
2593 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2594}
2595
2596int cudbg_collect_ulptx_la(struct cudbg_init *pdbg_init,
2597 struct cudbg_buffer *dbg_buff,
2598 struct cudbg_error *cudbg_err)
2599{
2600 struct adapter *padap = pdbg_init->adap;
2601 struct cudbg_buffer temp_buff = { 0 };
2602 struct cudbg_ulptx_la *ulptx_la_buff;
2603 struct cudbg_ver_hdr *ver_hdr;
2604 u32 i, j;
2605 int rc;
2606
2607 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2608 sizeof(struct cudbg_ver_hdr) +
2609 sizeof(struct cudbg_ulptx_la),
2610 &temp_buff);
2611 if (rc)
2612 return rc;
2613
2614 ver_hdr = (struct cudbg_ver_hdr *)temp_buff.data;
2615 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2616 ver_hdr->revision = CUDBG_ULPTX_LA_REV;
2617 ver_hdr->size = sizeof(struct cudbg_ulptx_la);
2618
2619 ulptx_la_buff = (struct cudbg_ulptx_la *)(temp_buff.data +
2620 sizeof(*ver_hdr));
2621 for (i = 0; i < CUDBG_NUM_ULPTX; i++) {
2622 ulptx_la_buff->rdptr[i] = t4_read_reg(padap,
2623 ULP_TX_LA_RDPTR_0_A +
2624 0x10 * i);
2625 ulptx_la_buff->wrptr[i] = t4_read_reg(padap,
2626 ULP_TX_LA_WRPTR_0_A +
2627 0x10 * i);
2628 ulptx_la_buff->rddata[i] = t4_read_reg(padap,
2629 ULP_TX_LA_RDDATA_0_A +
2630 0x10 * i);
2631 for (j = 0; j < CUDBG_NUM_ULPTX_READ; j++)
2632 ulptx_la_buff->rd_data[i][j] =
2633 t4_read_reg(padap,
2634 ULP_TX_LA_RDDATA_0_A + 0x10 * i);
2635 }
2636
2637 for (i = 0; i < CUDBG_NUM_ULPTX_ASIC_READ; i++) {
2638 t4_write_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A, 0x1);
2639 ulptx_la_buff->rdptr_asic[i] =
2640 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_CTRL_A);
2641 ulptx_la_buff->rddata_asic[i][0] =
2642 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_0_A);
2643 ulptx_la_buff->rddata_asic[i][1] =
2644 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_1_A);
2645 ulptx_la_buff->rddata_asic[i][2] =
2646 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_2_A);
2647 ulptx_la_buff->rddata_asic[i][3] =
2648 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_3_A);
2649 ulptx_la_buff->rddata_asic[i][4] =
2650 t4_read_reg(padap, ULP_TX_ASIC_DEBUG_4_A);
2651 ulptx_la_buff->rddata_asic[i][5] =
2652 t4_read_reg(padap, PM_RX_BASE_ADDR);
2653 }
2654
2655 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2656}
2657
2658int cudbg_collect_up_cim_indirect(struct cudbg_init *pdbg_init,
2659 struct cudbg_buffer *dbg_buff,
2660 struct cudbg_error *cudbg_err)
2661{
2662 struct adapter *padap = pdbg_init->adap;
2663 struct cudbg_buffer temp_buff = { 0 };
2664 u32 local_offset, local_range;
2665 struct ireg_buf *up_cim;
2666 u32 size, j, iter;
2667 u32 instance = 0;
2668 int i, rc, n;
2669
2670 if (is_t5(padap->params.chip))
2671 n = sizeof(t5_up_cim_reg_array) /
2672 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2673 else if (is_t6(padap->params.chip))
2674 n = sizeof(t6_up_cim_reg_array) /
2675 ((IREG_NUM_ELEM + 1) * sizeof(u32));
2676 else
2677 return CUDBG_STATUS_NOT_IMPLEMENTED;
2678
2679 size = sizeof(struct ireg_buf) * n;
2680 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2681 if (rc)
2682 return rc;
2683
2684 up_cim = (struct ireg_buf *)temp_buff.data;
2685 for (i = 0; i < n; i++) {
2686 struct ireg_field *up_cim_reg = &up_cim->tp_pio;
2687 u32 *buff = up_cim->outbuf;
2688
2689 if (is_t5(padap->params.chip)) {
2690 up_cim_reg->ireg_addr = t5_up_cim_reg_array[i][0];
2691 up_cim_reg->ireg_data = t5_up_cim_reg_array[i][1];
2692 up_cim_reg->ireg_local_offset =
2693 t5_up_cim_reg_array[i][2];
2694 up_cim_reg->ireg_offset_range =
2695 t5_up_cim_reg_array[i][3];
2696 instance = t5_up_cim_reg_array[i][4];
2697 } else if (is_t6(padap->params.chip)) {
2698 up_cim_reg->ireg_addr = t6_up_cim_reg_array[i][0];
2699 up_cim_reg->ireg_data = t6_up_cim_reg_array[i][1];
2700 up_cim_reg->ireg_local_offset =
2701 t6_up_cim_reg_array[i][2];
2702 up_cim_reg->ireg_offset_range =
2703 t6_up_cim_reg_array[i][3];
2704 instance = t6_up_cim_reg_array[i][4];
2705 }
2706
2707 switch (instance) {
2708 case NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES:
2709 iter = up_cim_reg->ireg_offset_range;
2710 local_offset = 0x120;
2711 local_range = 1;
2712 break;
2713 case NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES:
2714 iter = up_cim_reg->ireg_offset_range;
2715 local_offset = 0x10;
2716 local_range = 1;
2717 break;
2718 default:
2719 iter = 1;
2720 local_offset = 0;
2721 local_range = up_cim_reg->ireg_offset_range;
2722 break;
2723 }
2724
2725 for (j = 0; j < iter; j++, buff++) {
2726 rc = t4_cim_read(padap,
2727 up_cim_reg->ireg_local_offset +
2728 (j * local_offset), local_range, buff);
2729 if (rc) {
2730 cudbg_put_buff(pdbg_init, &temp_buff);
2731 return rc;
2732 }
2733 }
2734 up_cim++;
2735 }
2736 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2737}
2738
2739int cudbg_collect_pbt_tables(struct cudbg_init *pdbg_init,
2740 struct cudbg_buffer *dbg_buff,
2741 struct cudbg_error *cudbg_err)
2742{
2743 struct adapter *padap = pdbg_init->adap;
2744 struct cudbg_buffer temp_buff = { 0 };
2745 struct cudbg_pbt_tables *pbt;
2746 int i, rc;
2747 u32 addr;
2748
2749 rc = cudbg_get_buff(pdbg_init, dbg_buff,
2750 sizeof(struct cudbg_pbt_tables),
2751 &temp_buff);
2752 if (rc)
2753 return rc;
2754
2755 pbt = (struct cudbg_pbt_tables *)temp_buff.data;
2756
2757 addr = CUDBG_CHAC_PBT_ADDR;
2758 for (i = 0; i < CUDBG_PBT_DYNAMIC_ENTRIES; i++) {
2759 rc = t4_cim_read(padap, addr + (i * 4), 1,
2760 &pbt->pbt_dynamic[i]);
2761 if (rc) {
2762 cudbg_err->sys_err = rc;
2763 cudbg_put_buff(pdbg_init, &temp_buff);
2764 return rc;
2765 }
2766 }
2767
2768
2769
2770 addr = CUDBG_CHAC_PBT_ADDR + (1 << 6);
2771 for (i = 0; i < CUDBG_PBT_STATIC_ENTRIES; i++) {
2772 rc = t4_cim_read(padap, addr + (i * 4), 1,
2773 &pbt->pbt_static[i]);
2774 if (rc) {
2775 cudbg_err->sys_err = rc;
2776 cudbg_put_buff(pdbg_init, &temp_buff);
2777 return rc;
2778 }
2779 }
2780
2781
2782 addr = CUDBG_CHAC_PBT_LRF;
2783 for (i = 0; i < CUDBG_LRF_ENTRIES; i++) {
2784 rc = t4_cim_read(padap, addr + (i * 4), 1,
2785 &pbt->lrf_table[i]);
2786 if (rc) {
2787 cudbg_err->sys_err = rc;
2788 cudbg_put_buff(pdbg_init, &temp_buff);
2789 return rc;
2790 }
2791 }
2792
2793
2794 addr = CUDBG_CHAC_PBT_DATA;
2795 for (i = 0; i < CUDBG_PBT_DATA_ENTRIES; i++) {
2796 rc = t4_cim_read(padap, addr + (i * 4), 1,
2797 &pbt->pbt_data[i]);
2798 if (rc) {
2799 cudbg_err->sys_err = rc;
2800 cudbg_put_buff(pdbg_init, &temp_buff);
2801 return rc;
2802 }
2803 }
2804 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2805}
2806
2807int cudbg_collect_mbox_log(struct cudbg_init *pdbg_init,
2808 struct cudbg_buffer *dbg_buff,
2809 struct cudbg_error *cudbg_err)
2810{
2811 struct adapter *padap = pdbg_init->adap;
2812 struct cudbg_mbox_log *mboxlog = NULL;
2813 struct cudbg_buffer temp_buff = { 0 };
2814 struct mbox_cmd_log *log = NULL;
2815 struct mbox_cmd *entry;
2816 unsigned int entry_idx;
2817 u16 mbox_cmds;
2818 int i, k, rc;
2819 u64 flit;
2820 u32 size;
2821
2822 log = padap->mbox_log;
2823 mbox_cmds = padap->mbox_log->size;
2824 size = sizeof(struct cudbg_mbox_log) * mbox_cmds;
2825 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2826 if (rc)
2827 return rc;
2828
2829 mboxlog = (struct cudbg_mbox_log *)temp_buff.data;
2830 for (k = 0; k < mbox_cmds; k++) {
2831 entry_idx = log->cursor + k;
2832 if (entry_idx >= log->size)
2833 entry_idx -= log->size;
2834
2835 entry = mbox_cmd_log_entry(log, entry_idx);
2836
2837 if (entry->timestamp == 0)
2838 continue;
2839
2840 memcpy(&mboxlog->entry, entry, sizeof(struct mbox_cmd));
2841 for (i = 0; i < MBOX_LEN / 8; i++) {
2842 flit = entry->cmd[i];
2843 mboxlog->hi[i] = (u32)(flit >> 32);
2844 mboxlog->lo[i] = (u32)flit;
2845 }
2846 mboxlog++;
2847 }
2848 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2849}
2850
2851int cudbg_collect_hma_indirect(struct cudbg_init *pdbg_init,
2852 struct cudbg_buffer *dbg_buff,
2853 struct cudbg_error *cudbg_err)
2854{
2855 struct adapter *padap = pdbg_init->adap;
2856 struct cudbg_buffer temp_buff = { 0 };
2857 struct ireg_buf *hma_indr;
2858 int i, rc, n;
2859 u32 size;
2860
2861 if (CHELSIO_CHIP_VERSION(padap->params.chip) < CHELSIO_T6)
2862 return CUDBG_STATUS_ENTITY_NOT_FOUND;
2863
2864 n = sizeof(t6_hma_ireg_array) / (IREG_NUM_ELEM * sizeof(u32));
2865 size = sizeof(struct ireg_buf) * n;
2866 rc = cudbg_get_buff(pdbg_init, dbg_buff, size, &temp_buff);
2867 if (rc)
2868 return rc;
2869
2870 hma_indr = (struct ireg_buf *)temp_buff.data;
2871 for (i = 0; i < n; i++) {
2872 struct ireg_field *hma_fli = &hma_indr->tp_pio;
2873 u32 *buff = hma_indr->outbuf;
2874
2875 hma_fli->ireg_addr = t6_hma_ireg_array[i][0];
2876 hma_fli->ireg_data = t6_hma_ireg_array[i][1];
2877 hma_fli->ireg_local_offset = t6_hma_ireg_array[i][2];
2878 hma_fli->ireg_offset_range = t6_hma_ireg_array[i][3];
2879 t4_read_indirect(padap, hma_fli->ireg_addr, hma_fli->ireg_data,
2880 buff, hma_fli->ireg_offset_range,
2881 hma_fli->ireg_local_offset);
2882 hma_indr++;
2883 }
2884 return cudbg_write_and_release_buff(pdbg_init, &temp_buff, dbg_buff);
2885}
2886
2887void cudbg_fill_qdesc_num_and_size(const struct adapter *padap,
2888 u32 *num, u32 *size)
2889{
2890 u32 tot_entries = 0, tot_size = 0;
2891
2892
2893 tot_entries += MAX_ETH_QSETS * 3;
2894 tot_entries += MAX_CTRL_QUEUES;
2895
2896 tot_size += MAX_ETH_QSETS * MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2897 tot_size += MAX_ETH_QSETS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2898 tot_size += MAX_ETH_QSETS * MAX_RX_BUFFERS * MAX_FL_DESC_SIZE;
2899 tot_size += MAX_CTRL_QUEUES * MAX_CTRL_TXQ_ENTRIES *
2900 MAX_CTRL_TXQ_DESC_SIZE;
2901
2902
2903 tot_entries += INGQ_EXTRAS;
2904 tot_size += INGQ_EXTRAS * MAX_RSPQ_ENTRIES * MAX_RXQ_DESC_SIZE;
2905
2906
2907 tot_entries += 1;
2908 tot_size += MAX_TXQ_ENTRIES * MAX_TXQ_DESC_SIZE;
2909
2910
2911 tot_entries += CXGB4_TX_MAX * MAX_OFLD_QSETS;
2912 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS * 2;
2913
2914 tot_size += CXGB4_TX_MAX * MAX_OFLD_QSETS * MAX_TXQ_ENTRIES *
2915 MAX_TXQ_DESC_SIZE;
2916 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RSPQ_ENTRIES *
2917 MAX_RXQ_DESC_SIZE;
2918 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * MAX_RX_BUFFERS *
2919 MAX_FL_DESC_SIZE;
2920
2921
2922 tot_entries += CXGB4_ULD_MAX * MAX_ULD_QSETS;
2923 tot_size += CXGB4_ULD_MAX * MAX_ULD_QSETS * SGE_MAX_IQ_SIZE *
2924 MAX_RXQ_DESC_SIZE;
2925
2926 tot_size += sizeof(struct cudbg_ver_hdr) +
2927 sizeof(struct cudbg_qdesc_info) +
2928 sizeof(struct cudbg_qdesc_entry) * tot_entries;
2929
2930 if (num)
2931 *num = tot_entries;
2932
2933 if (size)
2934 *size = tot_size;
2935}
2936
2937int cudbg_collect_qdesc(struct cudbg_init *pdbg_init,
2938 struct cudbg_buffer *dbg_buff,
2939 struct cudbg_error *cudbg_err)
2940{
2941 u32 num_queues = 0, tot_entries = 0, size = 0;
2942 struct adapter *padap = pdbg_init->adap;
2943 struct cudbg_buffer temp_buff = { 0 };
2944 struct cudbg_qdesc_entry *qdesc_entry;
2945 struct cudbg_qdesc_info *qdesc_info;
2946 struct cudbg_ver_hdr *ver_hdr;
2947 struct sge *s = &padap->sge;
2948 u32 i, j, cur_off, tot_len;
2949 u8 *data;
2950 int rc;
2951
2952 cudbg_fill_qdesc_num_and_size(padap, &tot_entries, &size);
2953 size = min_t(u32, size, CUDBG_DUMP_BUFF_SIZE);
2954 tot_len = size;
2955 data = kvzalloc(size, GFP_KERNEL);
2956 if (!data)
2957 return -ENOMEM;
2958
2959 ver_hdr = (struct cudbg_ver_hdr *)data;
2960 ver_hdr->signature = CUDBG_ENTITY_SIGNATURE;
2961 ver_hdr->revision = CUDBG_QDESC_REV;
2962 ver_hdr->size = sizeof(struct cudbg_qdesc_info);
2963 size -= sizeof(*ver_hdr);
2964
2965 qdesc_info = (struct cudbg_qdesc_info *)(data +
2966 sizeof(*ver_hdr));
2967 size -= sizeof(*qdesc_info);
2968 qdesc_entry = (struct cudbg_qdesc_entry *)qdesc_info->data;
2969
2970#define QDESC_GET(q, desc, type, label) do { \
2971 if (size <= 0) { \
2972 goto label; \
2973 } \
2974 if (desc) { \
2975 cudbg_fill_qdesc_##q(q, type, qdesc_entry); \
2976 size -= sizeof(*qdesc_entry) + qdesc_entry->data_size; \
2977 num_queues++; \
2978 qdesc_entry = cudbg_next_qdesc(qdesc_entry); \
2979 } \
2980} while (0)
2981
2982#define QDESC_GET_TXQ(q, type, label) do { \
2983 struct sge_txq *txq = (struct sge_txq *)q; \
2984 QDESC_GET(txq, txq->desc, type, label); \
2985} while (0)
2986
2987#define QDESC_GET_RXQ(q, type, label) do { \
2988 struct sge_rspq *rxq = (struct sge_rspq *)q; \
2989 QDESC_GET(rxq, rxq->desc, type, label); \
2990} while (0)
2991
2992#define QDESC_GET_FLQ(q, type, label) do { \
2993 struct sge_fl *flq = (struct sge_fl *)q; \
2994 QDESC_GET(flq, flq->desc, type, label); \
2995} while (0)
2996
2997
2998 for (i = 0; i < s->ethqsets; i++)
2999 QDESC_GET_TXQ(&s->ethtxq[i].q, CUDBG_QTYPE_NIC_TXQ, out);
3000
3001
3002 for (i = 0; i < s->ethqsets; i++)
3003 QDESC_GET_RXQ(&s->ethrxq[i].rspq, CUDBG_QTYPE_NIC_RXQ, out);
3004
3005
3006 for (i = 0; i < s->ethqsets; i++)
3007 QDESC_GET_FLQ(&s->ethrxq[i].fl, CUDBG_QTYPE_NIC_FLQ, out);
3008
3009
3010 for (i = 0; i < padap->params.nports; i++)
3011 QDESC_GET_TXQ(&s->ctrlq[i].q, CUDBG_QTYPE_CTRLQ, out);
3012
3013
3014 QDESC_GET_RXQ(&s->fw_evtq, CUDBG_QTYPE_FWEVTQ, out);
3015
3016
3017 QDESC_GET_RXQ(&s->intrq, CUDBG_QTYPE_INTRQ, out);
3018
3019
3020 QDESC_GET_TXQ(&s->ptptxq.q, CUDBG_QTYPE_PTP_TXQ, out);
3021
3022
3023 mutex_lock(&uld_mutex);
3024
3025 if (s->uld_txq_info) {
3026 struct sge_uld_txq_info *utxq;
3027
3028
3029 for (j = 0; j < CXGB4_TX_MAX; j++) {
3030 if (!s->uld_txq_info[j])
3031 continue;
3032
3033 utxq = s->uld_txq_info[j];
3034 for (i = 0; i < utxq->ntxq; i++)
3035 QDESC_GET_TXQ(&utxq->uldtxq[i].q,
3036 cudbg_uld_txq_to_qtype(j),
3037 out_unlock);
3038 }
3039 }
3040
3041 if (s->uld_rxq_info) {
3042 struct sge_uld_rxq_info *urxq;
3043 u32 base;
3044
3045
3046 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3047 if (!s->uld_rxq_info[j])
3048 continue;
3049
3050 urxq = s->uld_rxq_info[j];
3051 for (i = 0; i < urxq->nrxq; i++)
3052 QDESC_GET_RXQ(&urxq->uldrxq[i].rspq,
3053 cudbg_uld_rxq_to_qtype(j),
3054 out_unlock);
3055 }
3056
3057
3058 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3059 if (!s->uld_rxq_info[j])
3060 continue;
3061
3062 urxq = s->uld_rxq_info[j];
3063 for (i = 0; i < urxq->nrxq; i++)
3064 QDESC_GET_FLQ(&urxq->uldrxq[i].fl,
3065 cudbg_uld_flq_to_qtype(j),
3066 out_unlock);
3067 }
3068
3069
3070 for (j = 0; j < CXGB4_ULD_MAX; j++) {
3071 if (!s->uld_rxq_info[j])
3072 continue;
3073
3074 urxq = s->uld_rxq_info[j];
3075 base = urxq->nrxq;
3076 for (i = 0; i < urxq->nciq; i++)
3077 QDESC_GET_RXQ(&urxq->uldrxq[base + i].rspq,
3078 cudbg_uld_ciq_to_qtype(j),
3079 out_unlock);
3080 }
3081 }
3082
3083out_unlock:
3084 mutex_unlock(&uld_mutex);
3085
3086out:
3087 qdesc_info->qdesc_entry_size = sizeof(*qdesc_entry);
3088 qdesc_info->num_queues = num_queues;
3089 cur_off = 0;
3090 while (tot_len) {
3091 u32 chunk_size = min_t(u32, tot_len, CUDBG_CHUNK_SIZE);
3092
3093 rc = cudbg_get_buff(pdbg_init, dbg_buff, chunk_size,
3094 &temp_buff);
3095 if (rc) {
3096 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3097 goto out_free;
3098 }
3099
3100 memcpy(temp_buff.data, data + cur_off, chunk_size);
3101 tot_len -= chunk_size;
3102 cur_off += chunk_size;
3103 rc = cudbg_write_and_release_buff(pdbg_init, &temp_buff,
3104 dbg_buff);
3105 if (rc) {
3106 cudbg_put_buff(pdbg_init, &temp_buff);
3107 cudbg_err->sys_warn = CUDBG_STATUS_PARTIAL_DATA;
3108 goto out_free;
3109 }
3110 }
3111
3112out_free:
3113 if (data)
3114 kvfree(data);
3115
3116#undef QDESC_GET_FLQ
3117#undef QDESC_GET_RXQ
3118#undef QDESC_GET_TXQ
3119#undef QDESC_GET
3120
3121 return rc;
3122}
3123