LXR linux/drivers/net/ethernet/intel/iavf/i40e_adminq

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright(c) 2013 - 2018 Intel Corporation. */
   3
   4#ifndef _I40E_ADMINQ_CMD_H_
   5#define _I40E_ADMINQ_CMD_H_
   6
   7/* This header file defines the i40e Admin Queue commands and is shared between
   8 * i40e Firmware and Software.  Do not change the names in this file to IAVF
   9 * because this file should be diff-able against the i40e version, even
  10 * though many parts have been removed in this VF version.
  11 *
  12 * This file needs to comply with the Linux Kernel coding style.
  13 */
  14
  15#define I40E_FW_API_VERSION_MAJOR       0x0001
  16#define I40E_FW_API_VERSION_MINOR_X722  0x0005
  17#define I40E_FW_API_VERSION_MINOR_X710  0x0008
  18
  19#define I40E_FW_MINOR_VERSION(_h) ((_h)->mac.type == I40E_MAC_XL710 ? \
  20                                        I40E_FW_API_VERSION_MINOR_X710 : \
  21                                        I40E_FW_API_VERSION_MINOR_X722)
  22
  23/* API version 1.7 implements additional link and PHY-specific APIs  */
  24#define I40E_MINOR_VER_GET_LINK_INFO_XL710 0x0007
  25
  26struct i40e_aq_desc {
  27        __le16 flags;
  28        __le16 opcode;
  29        __le16 datalen;
  30        __le16 retval;
  31        __le32 cookie_high;
  32        __le32 cookie_low;
  33        union {
  34                struct {
  35                        __le32 param0;
  36                        __le32 param1;
  37                        __le32 param2;
  38                        __le32 param3;
  39                } internal;
  40                struct {
  41                        __le32 param0;
  42                        __le32 param1;
  43                        __le32 addr_high;
  44                        __le32 addr_low;
  45                } external;
  46                u8 raw[16];
  47        } params;
  48};
  49
  50/* Flags sub-structure
  51 * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  52 * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  53 */
  54
  55/* command flags and offsets*/
  56#define I40E_AQ_FLAG_DD_SHIFT   0
  57#define I40E_AQ_FLAG_CMP_SHIFT  1
  58#define I40E_AQ_FLAG_ERR_SHIFT  2
  59#define I40E_AQ_FLAG_VFE_SHIFT  3
  60#define I40E_AQ_FLAG_LB_SHIFT   9
  61#define I40E_AQ_FLAG_RD_SHIFT   10
  62#define I40E_AQ_FLAG_VFC_SHIFT  11
  63#define I40E_AQ_FLAG_BUF_SHIFT  12
  64#define I40E_AQ_FLAG_SI_SHIFT   13
  65#define I40E_AQ_FLAG_EI_SHIFT   14
  66#define I40E_AQ_FLAG_FE_SHIFT   15
  67
  68#define I40E_AQ_FLAG_DD         BIT(I40E_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  69#define I40E_AQ_FLAG_CMP        BIT(I40E_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  70#define I40E_AQ_FLAG_ERR        BIT(I40E_AQ_FLAG_ERR_SHIFT) /* 0x4    */
  71#define I40E_AQ_FLAG_VFE        BIT(I40E_AQ_FLAG_VFE_SHIFT) /* 0x8    */
  72#define I40E_AQ_FLAG_LB         BIT(I40E_AQ_FLAG_LB_SHIFT)  /* 0x200  */
  73#define I40E_AQ_FLAG_RD         BIT(I40E_AQ_FLAG_RD_SHIFT)  /* 0x400  */
  74#define I40E_AQ_FLAG_VFC        BIT(I40E_AQ_FLAG_VFC_SHIFT) /* 0x800  */
  75#define I40E_AQ_FLAG_BUF        BIT(I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
  76#define I40E_AQ_FLAG_SI         BIT(I40E_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
  77#define I40E_AQ_FLAG_EI         BIT(I40E_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
  78#define I40E_AQ_FLAG_FE         BIT(I40E_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
  79
  80/* error codes */
  81enum i40e_admin_queue_err {
  82        I40E_AQ_RC_OK           = 0,  /* success */
  83        I40E_AQ_RC_EPERM        = 1,  /* Operation not permitted */
  84        I40E_AQ_RC_ENOENT       = 2,  /* No such element */
  85        I40E_AQ_RC_ESRCH        = 3,  /* Bad opcode */
  86        I40E_AQ_RC_EINTR        = 4,  /* operation interrupted */
  87        I40E_AQ_RC_EIO          = 5,  /* I/O error */
  88        I40E_AQ_RC_ENXIO        = 6,  /* No such resource */
  89        I40E_AQ_RC_E2BIG        = 7,  /* Arg too long */
  90        I40E_AQ_RC_EAGAIN       = 8,  /* Try again */
  91        I40E_AQ_RC_ENOMEM       = 9,  /* Out of memory */
  92        I40E_AQ_RC_EACCES       = 10, /* Permission denied */
  93        I40E_AQ_RC_EFAULT       = 11, /* Bad address */
  94        I40E_AQ_RC_EBUSY        = 12, /* Device or resource busy */
  95        I40E_AQ_RC_EEXIST       = 13, /* object already exists */
  96        I40E_AQ_RC_EINVAL       = 14, /* Invalid argument */
  97        I40E_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
  98        I40E_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
  99        I40E_AQ_RC_ENOSYS       = 17, /* Function not implemented */
 100        I40E_AQ_RC_ERANGE       = 18, /* Parameter out of range */
 101        I40E_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 102        I40E_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 103        I40E_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 104        I40E_AQ_RC_EFBIG        = 22, /* File too large */
 105};
 106
 107/* Admin Queue command opcodes */
 108enum i40e_admin_queue_opc {
 109        /* aq commands */
 110        i40e_aqc_opc_get_version        = 0x0001,
 111        i40e_aqc_opc_driver_version     = 0x0002,
 112        i40e_aqc_opc_queue_shutdown     = 0x0003,
 113        i40e_aqc_opc_set_pf_context     = 0x0004,
 114
 115        /* resource ownership */
 116        i40e_aqc_opc_request_resource   = 0x0008,
 117        i40e_aqc_opc_release_resource   = 0x0009,
 118
 119        i40e_aqc_opc_list_func_capabilities     = 0x000A,
 120        i40e_aqc_opc_list_dev_capabilities      = 0x000B,
 121
 122        /* Proxy commands */
 123        i40e_aqc_opc_set_proxy_config           = 0x0104,
 124        i40e_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
 125
 126        /* LAA */
 127        i40e_aqc_opc_mac_address_read   = 0x0107,
 128        i40e_aqc_opc_mac_address_write  = 0x0108,
 129
 130        /* PXE */
 131        i40e_aqc_opc_clear_pxe_mode     = 0x0110,
 132
 133        /* WoL commands */
 134        i40e_aqc_opc_set_wol_filter     = 0x0120,
 135        i40e_aqc_opc_get_wake_reason    = 0x0121,
 136
 137        /* internal switch commands */
 138        i40e_aqc_opc_get_switch_config          = 0x0200,
 139        i40e_aqc_opc_add_statistics             = 0x0201,
 140        i40e_aqc_opc_remove_statistics          = 0x0202,
 141        i40e_aqc_opc_set_port_parameters        = 0x0203,
 142        i40e_aqc_opc_get_switch_resource_alloc  = 0x0204,
 143        i40e_aqc_opc_set_switch_config          = 0x0205,
 144        i40e_aqc_opc_rx_ctl_reg_read            = 0x0206,
 145        i40e_aqc_opc_rx_ctl_reg_write           = 0x0207,
 146
 147        i40e_aqc_opc_add_vsi                    = 0x0210,
 148        i40e_aqc_opc_update_vsi_parameters      = 0x0211,
 149        i40e_aqc_opc_get_vsi_parameters         = 0x0212,
 150
 151        i40e_aqc_opc_add_pv                     = 0x0220,
 152        i40e_aqc_opc_update_pv_parameters       = 0x0221,
 153        i40e_aqc_opc_get_pv_parameters          = 0x0222,
 154
 155        i40e_aqc_opc_add_veb                    = 0x0230,
 156        i40e_aqc_opc_update_veb_parameters      = 0x0231,
 157        i40e_aqc_opc_get_veb_parameters         = 0x0232,
 158
 159        i40e_aqc_opc_delete_element             = 0x0243,
 160
 161        i40e_aqc_opc_add_macvlan                = 0x0250,
 162        i40e_aqc_opc_remove_macvlan             = 0x0251,
 163        i40e_aqc_opc_add_vlan                   = 0x0252,
 164        i40e_aqc_opc_remove_vlan                = 0x0253,
 165        i40e_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 166        i40e_aqc_opc_add_tag                    = 0x0255,
 167        i40e_aqc_opc_remove_tag                 = 0x0256,
 168        i40e_aqc_opc_add_multicast_etag         = 0x0257,
 169        i40e_aqc_opc_remove_multicast_etag      = 0x0258,
 170        i40e_aqc_opc_update_tag                 = 0x0259,
 171        i40e_aqc_opc_add_control_packet_filter  = 0x025A,
 172        i40e_aqc_opc_remove_control_packet_filter       = 0x025B,
 173        i40e_aqc_opc_add_cloud_filters          = 0x025C,
 174        i40e_aqc_opc_remove_cloud_filters       = 0x025D,
 175        i40e_aqc_opc_clear_wol_switch_filters   = 0x025E,
 176
 177        i40e_aqc_opc_add_mirror_rule    = 0x0260,
 178        i40e_aqc_opc_delete_mirror_rule = 0x0261,
 179
 180        /* Dynamic Device Personalization */
 181        i40e_aqc_opc_write_personalization_profile      = 0x0270,
 182        i40e_aqc_opc_get_personalization_profile_list   = 0x0271,
 183
 184        /* DCB commands */
 185        i40e_aqc_opc_dcb_ignore_pfc     = 0x0301,
 186        i40e_aqc_opc_dcb_updated        = 0x0302,
 187        i40e_aqc_opc_set_dcb_parameters = 0x0303,
 188
 189        /* TX scheduler */
 190        i40e_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 191        i40e_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 192        i40e_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 193        i40e_aqc_opc_query_vsi_bw_config                = 0x0408,
 194        i40e_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 195        i40e_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 196
 197        i40e_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 198        i40e_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 199        i40e_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 200        i40e_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 201        i40e_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 202        i40e_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 203        i40e_aqc_opc_query_port_ets_config                      = 0x0419,
 204        i40e_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 205        i40e_aqc_opc_suspend_port_tx                            = 0x041B,
 206        i40e_aqc_opc_resume_port_tx                             = 0x041C,
 207        i40e_aqc_opc_configure_partition_bw                     = 0x041D,
 208        /* hmc */
 209        i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
 210        i40e_aqc_opc_set_hmc_resource_profile   = 0x0501,
 211
 212        /* phy commands*/
 213        i40e_aqc_opc_get_phy_abilities          = 0x0600,
 214        i40e_aqc_opc_set_phy_config             = 0x0601,
 215        i40e_aqc_opc_set_mac_config             = 0x0603,
 216        i40e_aqc_opc_set_link_restart_an        = 0x0605,
 217        i40e_aqc_opc_get_link_status            = 0x0607,
 218        i40e_aqc_opc_set_phy_int_mask           = 0x0613,
 219        i40e_aqc_opc_get_local_advt_reg         = 0x0614,
 220        i40e_aqc_opc_set_local_advt_reg         = 0x0615,
 221        i40e_aqc_opc_get_partner_advt           = 0x0616,
 222        i40e_aqc_opc_set_lb_modes               = 0x0618,
 223        i40e_aqc_opc_get_phy_wol_caps           = 0x0621,
 224        i40e_aqc_opc_set_phy_debug              = 0x0622,
 225        i40e_aqc_opc_upload_ext_phy_fm          = 0x0625,
 226        i40e_aqc_opc_run_phy_activity           = 0x0626,
 227        i40e_aqc_opc_set_phy_register           = 0x0628,
 228        i40e_aqc_opc_get_phy_register           = 0x0629,
 229
 230        /* NVM commands */
 231        i40e_aqc_opc_nvm_read                   = 0x0701,
 232        i40e_aqc_opc_nvm_erase                  = 0x0702,
 233        i40e_aqc_opc_nvm_update                 = 0x0703,
 234        i40e_aqc_opc_nvm_config_read            = 0x0704,
 235        i40e_aqc_opc_nvm_config_write           = 0x0705,
 236        i40e_aqc_opc_oem_post_update            = 0x0720,
 237        i40e_aqc_opc_thermal_sensor             = 0x0721,
 238
 239        /* virtualization commands */
 240        i40e_aqc_opc_send_msg_to_pf             = 0x0801,
 241        i40e_aqc_opc_send_msg_to_vf             = 0x0802,
 242        i40e_aqc_opc_send_msg_to_peer           = 0x0803,
 243
 244        /* alternate structure */
 245        i40e_aqc_opc_alternate_write            = 0x0900,
 246        i40e_aqc_opc_alternate_write_indirect   = 0x0901,
 247        i40e_aqc_opc_alternate_read             = 0x0902,
 248        i40e_aqc_opc_alternate_read_indirect    = 0x0903,
 249        i40e_aqc_opc_alternate_write_done       = 0x0904,
 250        i40e_aqc_opc_alternate_set_mode         = 0x0905,
 251        i40e_aqc_opc_alternate_clear_port       = 0x0906,
 252
 253        /* LLDP commands */
 254        i40e_aqc_opc_lldp_get_mib       = 0x0A00,
 255        i40e_aqc_opc_lldp_update_mib    = 0x0A01,
 256        i40e_aqc_opc_lldp_add_tlv       = 0x0A02,
 257        i40e_aqc_opc_lldp_update_tlv    = 0x0A03,
 258        i40e_aqc_opc_lldp_delete_tlv    = 0x0A04,
 259        i40e_aqc_opc_lldp_stop          = 0x0A05,
 260        i40e_aqc_opc_lldp_start         = 0x0A06,
 261
 262        /* Tunnel commands */
 263        i40e_aqc_opc_add_udp_tunnel     = 0x0B00,
 264        i40e_aqc_opc_del_udp_tunnel     = 0x0B01,
 265        i40e_aqc_opc_set_rss_key        = 0x0B02,
 266        i40e_aqc_opc_set_rss_lut        = 0x0B03,
 267        i40e_aqc_opc_get_rss_key        = 0x0B04,
 268        i40e_aqc_opc_get_rss_lut        = 0x0B05,
 269
 270        /* Async Events */
 271        i40e_aqc_opc_event_lan_overflow         = 0x1001,
 272
 273        /* OEM commands */
 274        i40e_aqc_opc_oem_parameter_change       = 0xFE00,
 275        i40e_aqc_opc_oem_device_status_change   = 0xFE01,
 276        i40e_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 277        i40e_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 278
 279        /* debug commands */
 280        i40e_aqc_opc_debug_read_reg             = 0xFF03,
 281        i40e_aqc_opc_debug_write_reg            = 0xFF04,
 282        i40e_aqc_opc_debug_modify_reg           = 0xFF07,
 283        i40e_aqc_opc_debug_dump_internals       = 0xFF08,
 284};
 285
 286/* command structures and indirect data structures */
 287
 288/* Structure naming conventions:
 289 * - no suffix for direct command descriptor structures
 290 * - _data for indirect sent data
 291 * - _resp for indirect return data (data which is both will use _data)
 292 * - _completion for direct return data
 293 * - _element_ for repeated elements (may also be _data or _resp)
 294 *
 295 * Command structures are expected to overlay the params.raw member of the basic
 296 * descriptor, and as such cannot exceed 16 bytes in length.
 297 */
 298
 299/* This macro is used to generate a compilation error if a structure
 300 * is not exactly the correct length. It gives a divide by zero error if the
 301 * structure is not of the correct size, otherwise it creates an enum that is
 302 * never used.
 303 */
 304#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
 305        { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 306
 307/* This macro is used extensively to ensure that command structures are 16
 308 * bytes in length as they have to map to the raw array of that size.
 309 */
 310#define I40E_CHECK_CMD_LENGTH(X)        I40E_CHECK_STRUCT_LEN(16, X)
 311
 312/* Queue Shutdown (direct 0x0003) */
 313struct i40e_aqc_queue_shutdown {
 314        __le32  driver_unloading;
 315#define I40E_AQ_DRIVER_UNLOADING        0x1
 316        u8      reserved[12];
 317};
 318
 319I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
 320
 321struct i40e_aqc_vsi_properties_data {
 322        /* first 96 byte are written by SW */
 323        __le16  valid_sections;
 324#define I40E_AQ_VSI_PROP_SWITCH_VALID           0x0001
 325#define I40E_AQ_VSI_PROP_SECURITY_VALID         0x0002
 326#define I40E_AQ_VSI_PROP_VLAN_VALID             0x0004
 327#define I40E_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 328#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 329#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 330#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 331#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 332#define I40E_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 333#define I40E_AQ_VSI_PROP_SCHED_VALID            0x0200
 334        /* switch section */
 335        __le16  switch_id; /* 12bit id combined with flags below */
 336#define I40E_AQ_VSI_SW_ID_SHIFT         0x0000
 337#define I40E_AQ_VSI_SW_ID_MASK          (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
 338#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 339#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 340#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 341        u8      sw_reserved[2];
 342        /* security section */
 343        u8      sec_flags;
 344#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 345#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 346#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 347        u8      sec_reserved;
 348        /* VLAN section */
 349        __le16  pvid; /* VLANS include priority bits */
 350        __le16  fcoe_pvid;
 351        u8      port_vlan_flags;
 352#define I40E_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 353#define I40E_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 354                                         I40E_AQ_VSI_PVLAN_MODE_SHIFT)
 355#define I40E_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 356#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 357#define I40E_AQ_VSI_PVLAN_MODE_ALL      0x03
 358#define I40E_AQ_VSI_PVLAN_INSERT_PVID   0x04
 359#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 360#define I40E_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 361                                         I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
 362#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 363#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 364#define I40E_AQ_VSI_PVLAN_EMOD_STR      0x10
 365#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 366        u8      pvlan_reserved[3];
 367        /* ingress egress up sections */
 368        __le32  ingress_table; /* bitmap, 3 bits per up */
 369#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 370#define I40E_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 371                                         I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
 372#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 373#define I40E_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 374                                         I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
 375#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 376#define I40E_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 377                                         I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
 378#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 379#define I40E_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 380                                         I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
 381#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 382#define I40E_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 383                                         I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
 384#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 385#define I40E_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 386                                         I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
 387#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 388#define I40E_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 389                                         I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
 390#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 391#define I40E_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 392                                         I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
 393        __le32  egress_table;   /* same defines as for ingress table */
 394        /* cascaded PV section */
 395        __le16  cas_pv_tag;
 396        u8      cas_pv_flags;
 397#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 398#define I40E_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 399                                                 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
 400#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 401#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 402#define I40E_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 403#define I40E_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 404#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 405#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 406        u8      cas_pv_reserved;
 407        /* queue mapping section */
 408        __le16  mapping_flags;
 409#define I40E_AQ_VSI_QUE_MAP_CONTIG      0x0
 410#define I40E_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 411        __le16  queue_mapping[16];
 412#define I40E_AQ_VSI_QUEUE_SHIFT         0x0
 413#define I40E_AQ_VSI_QUEUE_MASK          (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
 414        __le16  tc_mapping[8];
 415#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 416#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 417                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 418#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 419#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 420                                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 421        /* queueing option section */
 422        u8      queueing_opt_flags;
 423#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 424#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 425#define I40E_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 426#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 427#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 428#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 429        u8      queueing_opt_reserved[3];
 430        /* scheduler section */
 431        u8      up_enable_bits;
 432        u8      sched_reserved;
 433        /* outer up section */
 434        __le32  outer_up_table; /* same structure and defines as ingress tbl */
 435        u8      cmd_reserved[8];
 436        /* last 32 bytes are written by FW */
 437        __le16  qs_handle[8];
 438#define I40E_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 439        __le16  stat_counter_idx;
 440        __le16  sched_id;
 441        u8      resp_reserved[12];
 442};
 443
 444I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
 445
 446/* Get VEB Parameters (direct 0x0232)
 447 * uses i40e_aqc_switch_seid for the descriptor
 448 */
 449struct i40e_aqc_get_veb_parameters_completion {
 450        __le16  seid;
 451        __le16  switch_id;
 452        __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
 453        __le16  statistic_index;
 454        __le16  vebs_used;
 455        __le16  vebs_free;
 456        u8      reserved[4];
 457};
 458
 459I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
 460
 461#define I40E_LINK_SPEED_100MB_SHIFT     0x1
 462#define I40E_LINK_SPEED_1000MB_SHIFT    0x2
 463#define I40E_LINK_SPEED_10GB_SHIFT      0x3
 464#define I40E_LINK_SPEED_40GB_SHIFT      0x4
 465#define I40E_LINK_SPEED_20GB_SHIFT      0x5
 466#define I40E_LINK_SPEED_25GB_SHIFT      0x6
 467
 468enum i40e_aq_link_speed {
 469        I40E_LINK_SPEED_UNKNOWN = 0,
 470        I40E_LINK_SPEED_100MB   = BIT(I40E_LINK_SPEED_100MB_SHIFT),
 471        I40E_LINK_SPEED_1GB     = BIT(I40E_LINK_SPEED_1000MB_SHIFT),
 472        I40E_LINK_SPEED_10GB    = BIT(I40E_LINK_SPEED_10GB_SHIFT),
 473        I40E_LINK_SPEED_40GB    = BIT(I40E_LINK_SPEED_40GB_SHIFT),
 474        I40E_LINK_SPEED_20GB    = BIT(I40E_LINK_SPEED_20GB_SHIFT),
 475        I40E_LINK_SPEED_25GB    = BIT(I40E_LINK_SPEED_25GB_SHIFT),
 476};
 477
 478/* Send to PF command (indirect 0x0801) id is only used by PF
 479 * Send to VF command (indirect 0x0802) id is only used by PF
 480 * Send to Peer PF command (indirect 0x0803)
 481 */
 482struct i40e_aqc_pf_vf_message {
 483        __le32  id;
 484        u8      reserved[4];
 485        __le32  addr_high;
 486        __le32  addr_low;
 487};
 488
 489I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
 490
 491struct i40e_aqc_get_set_rss_key {
 492#define I40E_AQC_SET_RSS_KEY_VSI_VALID          BIT(15)
 493#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
 494#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
 495                                        I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
 496        __le16  vsi_id;
 497        u8      reserved[6];
 498        __le32  addr_high;
 499        __le32  addr_low;
 500};
 501
 502I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
 503
 504struct i40e_aqc_get_set_rss_key_data {
 505        u8 standard_rss_key[0x28];
 506        u8 extended_hash_key[0xc];
 507};
 508
 509I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
 510
 511struct  i40e_aqc_get_set_rss_lut {
 512#define I40E_AQC_SET_RSS_LUT_VSI_VALID          BIT(15)
 513#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
 514#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
 515                                        I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
 516        __le16  vsi_id;
 517#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
 518#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
 519                                BIT(I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
 520
 521#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
 522#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
 523        __le16  flags;
 524        u8      reserved[4];
 525        __le32  addr_high;
 526        __le32  addr_low;
 527};
 528
 529I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
 530#endif /* _I40E_ADMINQ_CMD_H_ */
 531