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33#ifndef __MLX5_ESWITCH_H__
34#define __MLX5_ESWITCH_H__
35
36#include <linux/if_ether.h>
37#include <linux/if_link.h>
38#include <net/devlink.h>
39#include <linux/mlx5/device.h>
40#include <linux/mlx5/eswitch.h>
41#include <linux/mlx5/vport.h>
42#include <linux/mlx5/fs.h>
43#include "lib/mpfs.h"
44
45#ifdef CONFIG_MLX5_ESWITCH
46
47#define MLX5_MAX_UC_PER_VPORT(dev) \
48 (1 << MLX5_CAP_GEN(dev, log_max_current_uc_list))
49
50#define MLX5_MAX_MC_PER_VPORT(dev) \
51 (1 << MLX5_CAP_GEN(dev, log_max_current_mc_list))
52
53#define MLX5_MIN_BW_SHARE 1
54
55#define MLX5_RATE_TO_BW_SHARE(rate, divider, limit) \
56 min_t(u32, max_t(u32, (rate) / (divider), MLX5_MIN_BW_SHARE), limit)
57
58#define mlx5_esw_has_fwd_fdb(dev) \
59 MLX5_CAP_ESW_FLOWTABLE(dev, fdb_multi_path_to_table)
60
61#define FDB_MAX_CHAIN 3
62#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
63#define FDB_MAX_PRIO 16
64
65struct vport_ingress {
66 struct mlx5_flow_table *acl;
67 struct mlx5_flow_group *allow_untagged_spoofchk_grp;
68 struct mlx5_flow_group *allow_spoofchk_only_grp;
69 struct mlx5_flow_group *allow_untagged_only_grp;
70 struct mlx5_flow_group *drop_grp;
71 struct mlx5_flow_handle *allow_rule;
72 struct mlx5_flow_handle *drop_rule;
73 struct mlx5_fc *drop_counter;
74};
75
76struct vport_egress {
77 struct mlx5_flow_table *acl;
78 struct mlx5_flow_group *allowed_vlans_grp;
79 struct mlx5_flow_group *drop_grp;
80 struct mlx5_flow_handle *allowed_vlan;
81 struct mlx5_flow_handle *drop_rule;
82 struct mlx5_fc *drop_counter;
83};
84
85struct mlx5_vport_drop_stats {
86 u64 rx_dropped;
87 u64 tx_dropped;
88};
89
90struct mlx5_vport_info {
91 u8 mac[ETH_ALEN];
92 u16 vlan;
93 u8 qos;
94 u64 node_guid;
95 int link_state;
96 u32 min_rate;
97 u32 max_rate;
98 bool spoofchk;
99 bool trusted;
100};
101
102struct mlx5_vport {
103 struct mlx5_core_dev *dev;
104 int vport;
105 struct hlist_head uc_list[MLX5_L2_ADDR_HASH_SIZE];
106 struct hlist_head mc_list[MLX5_L2_ADDR_HASH_SIZE];
107 struct mlx5_flow_handle *promisc_rule;
108 struct mlx5_flow_handle *allmulti_rule;
109 struct work_struct vport_change_handler;
110
111 struct vport_ingress ingress;
112 struct vport_egress egress;
113
114 struct mlx5_vport_info info;
115
116 struct {
117 bool enabled;
118 u32 esw_tsar_ix;
119 u32 bw_share;
120 } qos;
121
122 bool enabled;
123 u16 enabled_events;
124};
125
126enum offloads_fdb_flags {
127 ESW_FDB_CHAINS_AND_PRIOS_SUPPORTED = BIT(0),
128};
129
130extern const unsigned int ESW_POOLS[4];
131
132#define PRIO_LEVELS 2
133struct mlx5_eswitch_fdb {
134 union {
135 struct legacy_fdb {
136 struct mlx5_flow_table *fdb;
137 struct mlx5_flow_group *addr_grp;
138 struct mlx5_flow_group *allmulti_grp;
139 struct mlx5_flow_group *promisc_grp;
140 struct mlx5_flow_table *vepa_fdb;
141 struct mlx5_flow_handle *vepa_uplink_rule;
142 struct mlx5_flow_handle *vepa_star_rule;
143 } legacy;
144
145 struct offloads_fdb {
146 struct mlx5_flow_table *slow_fdb;
147 struct mlx5_flow_group *send_to_vport_grp;
148 struct mlx5_flow_group *peer_miss_grp;
149 struct mlx5_flow_handle **peer_miss_rules;
150 struct mlx5_flow_group *miss_grp;
151 struct mlx5_flow_handle *miss_rule_uni;
152 struct mlx5_flow_handle *miss_rule_multi;
153 int vlan_push_pop_refcount;
154
155 struct {
156 struct mlx5_flow_table *fdb;
157 u32 num_rules;
158 } fdb_prio[FDB_MAX_CHAIN + 1][FDB_MAX_PRIO + 1][PRIO_LEVELS];
159
160 struct mutex fdb_prio_lock;
161
162 int fdb_left[ARRAY_SIZE(ESW_POOLS)];
163 } offloads;
164 };
165 u32 flags;
166};
167
168struct mlx5_esw_offload {
169 struct mlx5_flow_table *ft_offloads;
170 struct mlx5_flow_group *vport_rx_group;
171 struct mlx5_eswitch_rep *vport_reps;
172 struct list_head peer_flows;
173 struct mutex peer_mutex;
174 DECLARE_HASHTABLE(encap_tbl, 8);
175 DECLARE_HASHTABLE(mod_hdr_tbl, 8);
176 u8 inline_mode;
177 u64 num_flows;
178 u8 encap;
179};
180
181
182struct esw_mc_addr {
183 struct l2addr_node node;
184 struct mlx5_flow_handle *uplink_rule;
185 u32 refcnt;
186};
187
188struct mlx5_host_work {
189 struct work_struct work;
190 struct mlx5_eswitch *esw;
191};
192
193struct mlx5_host_info {
194 struct mlx5_nb nb;
195 u16 num_vfs;
196};
197
198struct mlx5_eswitch {
199 struct mlx5_core_dev *dev;
200 struct mlx5_nb nb;
201 struct mlx5_eswitch_fdb fdb_table;
202 struct hlist_head mc_table[MLX5_L2_ADDR_HASH_SIZE];
203 struct workqueue_struct *work_queue;
204 struct mlx5_vport *vports;
205 int total_vports;
206 int enabled_vports;
207
208
209
210 struct mutex state_lock;
211 struct esw_mc_addr mc_promisc;
212
213 struct {
214 bool enabled;
215 u32 root_tsar_id;
216 } qos;
217
218 struct mlx5_esw_offload offloads;
219 int mode;
220 int nvports;
221 u16 manager_vport;
222 struct mlx5_host_info host_info;
223};
224
225void esw_offloads_cleanup(struct mlx5_eswitch *esw);
226int esw_offloads_init(struct mlx5_eswitch *esw, int vf_nvports,
227 int total_nvports);
228void esw_offloads_cleanup_reps(struct mlx5_eswitch *esw);
229int esw_offloads_init_reps(struct mlx5_eswitch *esw);
230void esw_vport_cleanup_ingress_rules(struct mlx5_eswitch *esw,
231 struct mlx5_vport *vport);
232int esw_vport_enable_ingress_acl(struct mlx5_eswitch *esw,
233 struct mlx5_vport *vport);
234void esw_vport_cleanup_egress_rules(struct mlx5_eswitch *esw,
235 struct mlx5_vport *vport);
236int esw_vport_enable_egress_acl(struct mlx5_eswitch *esw,
237 struct mlx5_vport *vport);
238void esw_vport_disable_egress_acl(struct mlx5_eswitch *esw,
239 struct mlx5_vport *vport);
240void esw_vport_disable_ingress_acl(struct mlx5_eswitch *esw,
241 struct mlx5_vport *vport);
242
243
244int mlx5_eswitch_init(struct mlx5_core_dev *dev);
245void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw);
246int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode);
247void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw);
248int mlx5_eswitch_set_vport_mac(struct mlx5_eswitch *esw,
249 u16 vport, u8 mac[ETH_ALEN]);
250int mlx5_eswitch_set_vport_state(struct mlx5_eswitch *esw,
251 u16 vport, int link_state);
252int mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
253 u16 vport, u16 vlan, u8 qos);
254int mlx5_eswitch_set_vport_spoofchk(struct mlx5_eswitch *esw,
255 u16 vport, bool spoofchk);
256int mlx5_eswitch_set_vport_trust(struct mlx5_eswitch *esw,
257 u16 vport_num, bool setting);
258int mlx5_eswitch_set_vport_rate(struct mlx5_eswitch *esw, u16 vport,
259 u32 max_rate, u32 min_rate);
260int mlx5_eswitch_set_vepa(struct mlx5_eswitch *esw, u8 setting);
261int mlx5_eswitch_get_vepa(struct mlx5_eswitch *esw, u8 *setting);
262int mlx5_eswitch_get_vport_config(struct mlx5_eswitch *esw,
263 u16 vport, struct ifla_vf_info *ivi);
264int mlx5_eswitch_get_vport_stats(struct mlx5_eswitch *esw,
265 u16 vport,
266 struct ifla_vf_stats *vf_stats);
267void mlx5_eswitch_del_send_to_vport_rule(struct mlx5_flow_handle *rule);
268
269struct mlx5_flow_spec;
270struct mlx5_esw_flow_attr;
271
272struct mlx5_flow_handle *
273mlx5_eswitch_add_offloaded_rule(struct mlx5_eswitch *esw,
274 struct mlx5_flow_spec *spec,
275 struct mlx5_esw_flow_attr *attr);
276struct mlx5_flow_handle *
277mlx5_eswitch_add_fwd_rule(struct mlx5_eswitch *esw,
278 struct mlx5_flow_spec *spec,
279 struct mlx5_esw_flow_attr *attr);
280void
281mlx5_eswitch_del_offloaded_rule(struct mlx5_eswitch *esw,
282 struct mlx5_flow_handle *rule,
283 struct mlx5_esw_flow_attr *attr);
284void
285mlx5_eswitch_del_fwd_rule(struct mlx5_eswitch *esw,
286 struct mlx5_flow_handle *rule,
287 struct mlx5_esw_flow_attr *attr);
288
289bool
290mlx5_eswitch_prios_supported(struct mlx5_eswitch *esw);
291
292u16
293mlx5_eswitch_get_prio_range(struct mlx5_eswitch *esw);
294
295u32
296mlx5_eswitch_get_chain_range(struct mlx5_eswitch *esw);
297
298struct mlx5_flow_handle *
299mlx5_eswitch_create_vport_rx_rule(struct mlx5_eswitch *esw, u16 vport,
300 struct mlx5_flow_destination *dest);
301
302enum {
303 SET_VLAN_STRIP = BIT(0),
304 SET_VLAN_INSERT = BIT(1)
305};
306
307enum mlx5_flow_match_level {
308 MLX5_MATCH_NONE = MLX5_INLINE_MODE_NONE,
309 MLX5_MATCH_L2 = MLX5_INLINE_MODE_L2,
310 MLX5_MATCH_L3 = MLX5_INLINE_MODE_IP,
311 MLX5_MATCH_L4 = MLX5_INLINE_MODE_TCP_UDP,
312};
313
314
315#define MLX5_MAX_FLOW_FWD_VPORTS 2
316
317enum {
318 MLX5_ESW_DEST_ENCAP = BIT(0),
319 MLX5_ESW_DEST_ENCAP_VALID = BIT(1),
320};
321
322struct mlx5_esw_flow_attr {
323 struct mlx5_eswitch_rep *in_rep;
324 struct mlx5_core_dev *in_mdev;
325 struct mlx5_core_dev *counter_dev;
326
327 int split_count;
328 int out_count;
329
330 int action;
331 __be16 vlan_proto[MLX5_FS_VLAN_DEPTH];
332 u16 vlan_vid[MLX5_FS_VLAN_DEPTH];
333 u8 vlan_prio[MLX5_FS_VLAN_DEPTH];
334 u8 total_vlan;
335 bool vlan_handled;
336 struct {
337 u32 flags;
338 struct mlx5_eswitch_rep *rep;
339 struct mlx5_core_dev *mdev;
340 u32 encap_id;
341 } dests[MLX5_MAX_FLOW_FWD_VPORTS];
342 u32 mod_hdr_id;
343 u8 match_level;
344 u8 tunnel_match_level;
345 struct mlx5_fc *counter;
346 u32 chain;
347 u16 prio;
348 u32 dest_chain;
349 struct mlx5e_tc_flow_parse_attr *parse_attr;
350};
351
352int mlx5_devlink_eswitch_mode_set(struct devlink *devlink, u16 mode,
353 struct netlink_ext_ack *extack);
354int mlx5_devlink_eswitch_mode_get(struct devlink *devlink, u16 *mode);
355int mlx5_devlink_eswitch_inline_mode_set(struct devlink *devlink, u8 mode,
356 struct netlink_ext_ack *extack);
357int mlx5_devlink_eswitch_inline_mode_get(struct devlink *devlink, u8 *mode);
358int mlx5_eswitch_inline_mode_get(struct mlx5_eswitch *esw, int nvfs, u8 *mode);
359int mlx5_devlink_eswitch_encap_mode_set(struct devlink *devlink, u8 encap,
360 struct netlink_ext_ack *extack);
361int mlx5_devlink_eswitch_encap_mode_get(struct devlink *devlink, u8 *encap);
362void *mlx5_eswitch_get_uplink_priv(struct mlx5_eswitch *esw, u8 rep_type);
363
364int mlx5_eswitch_add_vlan_action(struct mlx5_eswitch *esw,
365 struct mlx5_esw_flow_attr *attr);
366int mlx5_eswitch_del_vlan_action(struct mlx5_eswitch *esw,
367 struct mlx5_esw_flow_attr *attr);
368int __mlx5_eswitch_set_vport_vlan(struct mlx5_eswitch *esw,
369 u16 vport, u16 vlan, u8 qos, u8 set_flags);
370
371static inline bool mlx5_eswitch_vlan_actions_supported(struct mlx5_core_dev *dev,
372 u8 vlan_depth)
373{
374 bool ret = MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan) &&
375 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan);
376
377 if (vlan_depth == 1)
378 return ret;
379
380 return ret && MLX5_CAP_ESW_FLOWTABLE_FDB(dev, pop_vlan_2) &&
381 MLX5_CAP_ESW_FLOWTABLE_FDB(dev, push_vlan_2);
382}
383
384bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0,
385 struct mlx5_core_dev *dev1);
386bool mlx5_esw_multipath_prereq(struct mlx5_core_dev *dev0,
387 struct mlx5_core_dev *dev1);
388
389#define MLX5_DEBUG_ESWITCH_MASK BIT(3)
390
391#define esw_info(__dev, format, ...) \
392 dev_info((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
393
394#define esw_warn(__dev, format, ...) \
395 dev_warn((__dev)->device, "E-Switch: " format, ##__VA_ARGS__)
396
397#define esw_debug(dev, format, ...) \
398 mlx5_core_dbg_mask(dev, MLX5_DEBUG_ESWITCH_MASK, format, ##__VA_ARGS__)
399
400
401static inline u16 mlx5_eswitch_manager_vport(struct mlx5_core_dev *dev)
402{
403 return mlx5_core_is_ecpf_esw_manager(dev) ?
404 MLX5_VPORT_ECPF : MLX5_VPORT_PF;
405}
406
407static inline int mlx5_eswitch_uplink_idx(struct mlx5_eswitch *esw)
408{
409
410 return esw->total_vports - 1;
411}
412
413static inline int mlx5_eswitch_ecpf_idx(struct mlx5_eswitch *esw)
414{
415 return esw->total_vports - 2;
416}
417
418static inline int mlx5_eswitch_vport_num_to_index(struct mlx5_eswitch *esw,
419 u16 vport_num)
420{
421 if (vport_num == MLX5_VPORT_ECPF) {
422 if (!mlx5_ecpf_vport_exists(esw->dev))
423 esw_warn(esw->dev, "ECPF vport doesn't exist!\n");
424 return mlx5_eswitch_ecpf_idx(esw);
425 }
426
427 if (vport_num == MLX5_VPORT_UPLINK)
428 return mlx5_eswitch_uplink_idx(esw);
429
430 return vport_num;
431}
432
433static inline u16 mlx5_eswitch_index_to_vport_num(struct mlx5_eswitch *esw,
434 int index)
435{
436 if (index == mlx5_eswitch_ecpf_idx(esw) &&
437 mlx5_ecpf_vport_exists(esw->dev))
438 return MLX5_VPORT_ECPF;
439
440 if (index == mlx5_eswitch_uplink_idx(esw))
441 return MLX5_VPORT_UPLINK;
442
443 return index;
444}
445
446
447void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw);
448
449
450
451
452#define mlx5_esw_for_all_vports(esw, i, vport) \
453 for ((i) = MLX5_VPORT_PF; \
454 (vport) = &(esw)->vports[i], \
455 (i) < (esw)->total_vports; (i)++)
456
457#define mlx5_esw_for_each_vf_vport(esw, i, vport, nvfs) \
458 for ((i) = MLX5_VPORT_FIRST_VF; \
459 (vport) = &(esw)->vports[(i)], \
460 (i) <= (nvfs); (i)++)
461
462#define mlx5_esw_for_each_vf_vport_reverse(esw, i, vport, nvfs) \
463 for ((i) = (nvfs); \
464 (vport) = &(esw)->vports[(i)], \
465 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
466
467
468
469
470#define mlx5_esw_for_all_reps(esw, i, rep) \
471 for ((i) = MLX5_VPORT_PF; \
472 (rep) = &(esw)->offloads.vport_reps[i], \
473 (i) < (esw)->total_vports; (i)++)
474
475#define mlx5_esw_for_each_vf_rep(esw, i, rep, nvfs) \
476 for ((i) = MLX5_VPORT_FIRST_VF; \
477 (rep) = &(esw)->offloads.vport_reps[i], \
478 (i) <= (nvfs); (i)++)
479
480#define mlx5_esw_for_each_vf_rep_reverse(esw, i, rep, nvfs) \
481 for ((i) = (nvfs); \
482 (rep) = &(esw)->offloads.vport_reps[i], \
483 (i) >= MLX5_VPORT_FIRST_VF; (i)--)
484
485#define mlx5_esw_for_each_vf_vport_num(esw, vport, nvfs) \
486 for ((vport) = MLX5_VPORT_FIRST_VF; (vport) <= (nvfs); (vport)++)
487
488#define mlx5_esw_for_each_vf_vport_num_reverse(esw, vport, nvfs) \
489 for ((vport) = (nvfs); (vport) >= MLX5_VPORT_FIRST_VF; (vport)--)
490
491struct mlx5_vport *__must_check
492mlx5_eswitch_get_vport(struct mlx5_eswitch *esw, u16 vport_num);
493
494#else
495
496static inline int mlx5_eswitch_init(struct mlx5_core_dev *dev) { return 0; }
497static inline void mlx5_eswitch_cleanup(struct mlx5_eswitch *esw) {}
498static inline int mlx5_eswitch_enable_sriov(struct mlx5_eswitch *esw, int nvfs, int mode) { return 0; }
499static inline void mlx5_eswitch_disable_sriov(struct mlx5_eswitch *esw) {}
500static inline bool mlx5_esw_lag_prereq(struct mlx5_core_dev *dev0, struct mlx5_core_dev *dev1) { return true; }
501
502#define FDB_MAX_CHAIN 1
503#define FDB_SLOW_PATH_CHAIN (FDB_MAX_CHAIN + 1)
504#define FDB_MAX_PRIO 1
505
506#endif
507
508#endif
509
