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33#ifndef _QED_H
34#define _QED_H
35
36#include <linux/types.h>
37#include <linux/io.h>
38#include <linux/delay.h>
39#include <linux/firmware.h>
40#include <linux/interrupt.h>
41#include <linux/list.h>
42#include <linux/mutex.h>
43#include <linux/pci.h>
44#include <linux/slab.h>
45#include <linux/string.h>
46#include <linux/workqueue.h>
47#include <linux/zlib.h>
48#include <linux/hashtable.h>
49#include <linux/qed/qed_if.h>
50#include "qed_debug.h"
51#include "qed_hsi.h"
52
53extern const struct qed_common_ops qed_common_ops_pass;
54
55#define QED_MAJOR_VERSION 8
56#define QED_MINOR_VERSION 37
57#define QED_REVISION_VERSION 0
58#define QED_ENGINEERING_VERSION 20
59
60#define QED_VERSION \
61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \
62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION)
63
64#define STORM_FW_VERSION \
65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
67
68#define MAX_HWFNS_PER_DEVICE (4)
69#define NAME_SIZE 16
70#define VER_SIZE 16
71
72#define QED_WFQ_UNIT 100
73
74#define QED_WID_SIZE (1024)
75#define QED_MIN_WIDS (4)
76#define QED_PF_DEMS_SIZE (4)
77
78
79enum qed_coalescing_mode {
80 QED_COAL_MODE_DISABLE,
81 QED_COAL_MODE_ENABLE
82};
83
84enum qed_nvm_cmd {
85 QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
86 QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
87 QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
88 QED_GET_MCP_NVM_RESP = 0xFFFFFF00
89};
90
91struct qed_eth_cb_ops;
92struct qed_dev_info;
93union qed_mcp_protocol_stats;
94enum qed_mcp_protocol_type;
95enum qed_mfw_tlv_type;
96union qed_mfw_tlv_data;
97
98
99#define QED_MFW_GET_FIELD(name, field) \
100 (((name) & (field ## _MASK)) >> (field ## _SHIFT))
101
102#define QED_MFW_SET_FIELD(name, field, value) \
103 do { \
104 (name) &= ~(field ## _MASK); \
105 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
106 } while (0)
107
108static inline u32 qed_db_addr(u32 cid, u32 DEMS)
109{
110 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
111 (cid * QED_PF_DEMS_SIZE);
112
113 return db_addr;
114}
115
116static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
117{
118 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
119 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
120
121 return db_addr;
122}
123
124#define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
125 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \
126 ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
127
128#define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++)
129
130#define D_TRINE(val, cond1, cond2, true1, true2, def) \
131 (val == (cond1) ? true1 : \
132 (val == (cond2) ? true2 : def))
133
134
135struct qed_ptt_pool;
136struct qed_spq;
137struct qed_sb_info;
138struct qed_sb_attn_info;
139struct qed_cxt_mngr;
140struct qed_sb_sp_info;
141struct qed_ll2_info;
142struct qed_mcp_info;
143
144struct qed_rt_data {
145 u32 *init_val;
146 bool *b_valid;
147};
148
149enum qed_tunn_mode {
150 QED_MODE_L2GENEVE_TUNN,
151 QED_MODE_IPGENEVE_TUNN,
152 QED_MODE_L2GRE_TUNN,
153 QED_MODE_IPGRE_TUNN,
154 QED_MODE_VXLAN_TUNN,
155};
156
157enum qed_tunn_clss {
158 QED_TUNN_CLSS_MAC_VLAN,
159 QED_TUNN_CLSS_MAC_VNI,
160 QED_TUNN_CLSS_INNER_MAC_VLAN,
161 QED_TUNN_CLSS_INNER_MAC_VNI,
162 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
163 MAX_QED_TUNN_CLSS,
164};
165
166struct qed_tunn_update_type {
167 bool b_update_mode;
168 bool b_mode_enabled;
169 enum qed_tunn_clss tun_cls;
170};
171
172struct qed_tunn_update_udp_port {
173 bool b_update_port;
174 u16 port;
175};
176
177struct qed_tunnel_info {
178 struct qed_tunn_update_type vxlan;
179 struct qed_tunn_update_type l2_geneve;
180 struct qed_tunn_update_type ip_geneve;
181 struct qed_tunn_update_type l2_gre;
182 struct qed_tunn_update_type ip_gre;
183
184 struct qed_tunn_update_udp_port vxlan_port;
185 struct qed_tunn_update_udp_port geneve_port;
186
187 bool b_update_rx_cls;
188 bool b_update_tx_cls;
189};
190
191struct qed_tunn_start_params {
192 unsigned long tunn_mode;
193 u16 vxlan_udp_port;
194 u16 geneve_udp_port;
195 u8 update_vxlan_udp_port;
196 u8 update_geneve_udp_port;
197 u8 tunn_clss_vxlan;
198 u8 tunn_clss_l2geneve;
199 u8 tunn_clss_ipgeneve;
200 u8 tunn_clss_l2gre;
201 u8 tunn_clss_ipgre;
202};
203
204struct qed_tunn_update_params {
205 unsigned long tunn_mode_update_mask;
206 unsigned long tunn_mode;
207 u16 vxlan_udp_port;
208 u16 geneve_udp_port;
209 u8 update_rx_pf_clss;
210 u8 update_tx_pf_clss;
211 u8 update_vxlan_udp_port;
212 u8 update_geneve_udp_port;
213 u8 tunn_clss_vxlan;
214 u8 tunn_clss_l2geneve;
215 u8 tunn_clss_ipgeneve;
216 u8 tunn_clss_l2gre;
217 u8 tunn_clss_ipgre;
218};
219
220
221
222
223
224enum qed_pci_personality {
225 QED_PCI_ETH,
226 QED_PCI_FCOE,
227 QED_PCI_ISCSI,
228 QED_PCI_ETH_ROCE,
229 QED_PCI_ETH_IWARP,
230 QED_PCI_ETH_RDMA,
231 QED_PCI_DEFAULT,
232};
233
234
235struct qed_qm_iids {
236 u32 cids;
237 u32 vf_cids;
238 u32 tids;
239};
240
241
242
243
244enum qed_resources {
245 QED_SB,
246 QED_L2_QUEUE,
247 QED_VPORT,
248 QED_RSS_ENG,
249 QED_PQ,
250 QED_RL,
251 QED_MAC,
252 QED_VLAN,
253 QED_RDMA_CNQ_RAM,
254 QED_ILT,
255 QED_LL2_QUEUE,
256 QED_CMDQS_CQS,
257 QED_RDMA_STATS_QUEUE,
258 QED_BDQ,
259 QED_MAX_RESC,
260};
261
262enum QED_FEATURE {
263 QED_PF_L2_QUE,
264 QED_VF,
265 QED_RDMA_CNQ,
266 QED_ISCSI_CQ,
267 QED_FCOE_CQ,
268 QED_VF_L2_QUE,
269 QED_MAX_FEATURES,
270};
271
272enum QED_PORT_MODE {
273 QED_PORT_MODE_DE_2X40G,
274 QED_PORT_MODE_DE_2X50G,
275 QED_PORT_MODE_DE_1X100G,
276 QED_PORT_MODE_DE_4X10G_F,
277 QED_PORT_MODE_DE_4X10G_E,
278 QED_PORT_MODE_DE_4X20G,
279 QED_PORT_MODE_DE_1X40G,
280 QED_PORT_MODE_DE_2X25G,
281 QED_PORT_MODE_DE_1X25G,
282 QED_PORT_MODE_DE_4X25G,
283 QED_PORT_MODE_DE_2X10G,
284};
285
286enum qed_dev_cap {
287 QED_DEV_CAP_ETH,
288 QED_DEV_CAP_FCOE,
289 QED_DEV_CAP_ISCSI,
290 QED_DEV_CAP_ROCE,
291 QED_DEV_CAP_IWARP,
292};
293
294enum qed_wol_support {
295 QED_WOL_SUPPORT_NONE,
296 QED_WOL_SUPPORT_PME,
297};
298
299enum qed_db_rec_exec {
300 DB_REC_DRY_RUN,
301 DB_REC_REAL_DEAL,
302 DB_REC_ONCE,
303};
304
305struct qed_hw_info {
306
307 enum qed_pci_personality personality;
308#define QED_IS_RDMA_PERSONALITY(dev) \
309 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
310 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
311 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
312#define QED_IS_ROCE_PERSONALITY(dev) \
313 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
314 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
315#define QED_IS_IWARP_PERSONALITY(dev) \
316 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
317 (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
318#define QED_IS_L2_PERSONALITY(dev) \
319 ((dev)->hw_info.personality == QED_PCI_ETH || \
320 QED_IS_RDMA_PERSONALITY(dev))
321#define QED_IS_FCOE_PERSONALITY(dev) \
322 ((dev)->hw_info.personality == QED_PCI_FCOE)
323#define QED_IS_ISCSI_PERSONALITY(dev) \
324 ((dev)->hw_info.personality == QED_PCI_ISCSI)
325
326
327 u32 resc_start[QED_MAX_RESC];
328 u32 resc_num[QED_MAX_RESC];
329 u32 feat_num[QED_MAX_FEATURES];
330
331#define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
332#define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
333#define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
334 RESC_NUM(_p_hwfn, resc))
335#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
336
337
338 u8 num_hw_tc;
339
340
341
342
343 u8 num_active_tc;
344 u8 offload_tc;
345 bool offload_tc_set;
346
347 bool multi_tc_roce_en;
348#define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en))
349
350 u32 concrete_fid;
351 u16 opaque_fid;
352 u16 ovlan;
353 u32 part_num[4];
354
355 unsigned char hw_mac_addr[ETH_ALEN];
356 u64 node_wwn;
357 u64 port_wwn;
358
359 u16 num_fcoe_conns;
360
361 struct qed_igu_info *p_igu_info;
362
363 u32 port_mode;
364 u32 hw_mode;
365 unsigned long device_capabilities;
366 u16 mtu;
367
368 enum qed_wol_support b_wol_support;
369};
370
371
372#define DMAE_MAX_RW_SIZE 0x2000
373
374struct qed_dmae_info {
375
376 struct mutex mutex;
377
378 u8 channel;
379
380 dma_addr_t completion_word_phys_addr;
381
382
383
384
385 u32 *p_completion_word;
386
387 dma_addr_t intermediate_buffer_phys_addr;
388
389
390
391
392
393 u32 *p_intermediate_buffer;
394
395 dma_addr_t dmae_cmd_phys_addr;
396 struct dmae_cmd *p_dmae_cmd;
397};
398
399struct qed_wfq_data {
400
401 u32 min_speed;
402 bool configured;
403};
404
405struct qed_qm_info {
406 struct init_qm_pq_params *qm_pq_params;
407 struct init_qm_vport_params *qm_vport_params;
408 struct init_qm_port_params *qm_port_params;
409 u16 start_pq;
410 u8 start_vport;
411 u16 pure_lb_pq;
412 u16 first_ofld_pq;
413 u16 first_llt_pq;
414 u16 pure_ack_pq;
415 u16 ooo_pq;
416 u16 first_vf_pq;
417 u16 first_mcos_pq;
418 u16 first_rl_pq;
419 u16 num_pqs;
420 u16 num_vf_pqs;
421 u8 num_vports;
422 u8 max_phys_tcs_per_port;
423 u8 ooo_tc;
424 bool pf_rl_en;
425 bool pf_wfq_en;
426 bool vport_rl_en;
427 bool vport_wfq_en;
428 u8 pf_wfq;
429 u32 pf_rl;
430 struct qed_wfq_data *wfq_data;
431 u8 num_pf_rls;
432};
433
434#define QED_OVERFLOW_BIT 1
435
436struct qed_db_recovery_info {
437 struct list_head list;
438
439
440 spinlock_t lock;
441 bool dorq_attn;
442 u32 db_recovery_counter;
443 unsigned long overflow;
444};
445
446struct storm_stats {
447 u32 address;
448 u32 len;
449};
450
451struct qed_storm_stats {
452 struct storm_stats mstats;
453 struct storm_stats pstats;
454 struct storm_stats tstats;
455 struct storm_stats ustats;
456};
457
458struct qed_fw_data {
459 struct fw_ver_info *fw_ver_info;
460 const u8 *modes_tree_buf;
461 union init_op *init_ops;
462 const u32 *arr_data;
463 u32 init_ops_size;
464};
465
466enum qed_mf_mode_bit {
467
468 QED_MF_OVLAN_CLSS,
469
470
471 QED_MF_LLH_MAC_CLSS,
472
473
474 QED_MF_LLH_PROTO_CLSS,
475
476
477 QED_MF_NEED_DEF_PF,
478
479
480 QED_MF_LL2_NON_UNICAST,
481
482
483 QED_MF_INTER_PF_SWITCH,
484
485
486 QED_MF_UFP_SPECIFIC,
487
488
489 QED_MF_DISABLE_ARFS,
490
491
492 QED_MF_8021Q_TAGGING,
493
494
495 QED_MF_8021AD_TAGGING,
496
497
498 QED_MF_DSCP_TO_TC_MAP,
499
500
501 QED_MF_DONT_ADD_VLAN0_TAG,
502};
503
504enum qed_ufp_mode {
505 QED_UFP_MODE_ETS,
506 QED_UFP_MODE_VNIC_BW,
507 QED_UFP_MODE_UNKNOWN
508};
509
510enum qed_ufp_pri_type {
511 QED_UFP_PRI_OS,
512 QED_UFP_PRI_VNIC,
513 QED_UFP_PRI_UNKNOWN
514};
515
516struct qed_ufp_info {
517 enum qed_ufp_pri_type pri_type;
518 enum qed_ufp_mode mode;
519 u8 tc;
520};
521
522enum BAR_ID {
523 BAR_ID_0,
524 BAR_ID_1
525};
526
527struct qed_nvm_image_info {
528 u32 num_images;
529 struct bist_nvm_image_att *image_att;
530 bool valid;
531};
532
533#define DRV_MODULE_VERSION \
534 __stringify(QED_MAJOR_VERSION) "." \
535 __stringify(QED_MINOR_VERSION) "." \
536 __stringify(QED_REVISION_VERSION) "." \
537 __stringify(QED_ENGINEERING_VERSION)
538
539struct qed_simd_fp_handler {
540 void *token;
541 void (*func)(void *);
542};
543
544enum qed_slowpath_wq_flag {
545 QED_SLOWPATH_MFW_TLV_REQ,
546 QED_SLOWPATH_PERIODIC_DB_REC,
547};
548
549struct qed_hwfn {
550 struct qed_dev *cdev;
551 u8 my_id;
552#define IS_LEAD_HWFN(edev) (!((edev)->my_id))
553 u8 rel_pf_id;
554 u8 abs_pf_id;
555#define QED_PATH_ID(_p_hwfn) \
556 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
557 u8 port_id;
558 bool b_active;
559
560 u32 dp_module;
561 u8 dp_level;
562 char name[NAME_SIZE];
563
564 bool hw_init_done;
565
566 u8 num_funcs_on_engine;
567 u8 enabled_func_idx;
568
569
570 void __iomem *regview;
571 void __iomem *doorbells;
572 u64 db_phys_addr;
573 unsigned long db_size;
574
575
576 struct qed_ptt_pool *p_ptt_pool;
577
578
579 struct qed_hw_info hw_info;
580
581
582 struct qed_rt_data rt_data;
583
584
585 struct qed_spq *p_spq;
586
587
588 struct qed_eq *p_eq;
589
590
591 struct qed_consq *p_consq;
592
593
594 struct tasklet_struct *sp_dpc;
595 bool b_sp_dpc_enabled;
596
597 struct qed_ptt *p_main_ptt;
598 struct qed_ptt *p_dpc_ptt;
599
600
601
602
603 struct qed_ptt *p_ptp_ptt;
604
605 struct qed_sb_sp_info *p_sp_sb;
606 struct qed_sb_attn_info *p_sb_attn;
607
608
609 bool using_ll2;
610 struct qed_ll2_info *p_ll2_info;
611 struct qed_ooo_info *p_ooo_info;
612 struct qed_rdma_info *p_rdma_info;
613 struct qed_iscsi_info *p_iscsi_info;
614 struct qed_fcoe_info *p_fcoe_info;
615 struct qed_pf_params pf_params;
616
617 bool b_rdma_enabled_in_prs;
618 u32 rdma_prs_search_reg;
619
620 struct qed_cxt_mngr *p_cxt_mngr;
621
622
623 bool b_int_enabled;
624 bool b_int_requested;
625
626
627 bool b_drv_link_init;
628
629 struct qed_vf_iov *vf_iov_info;
630 struct qed_pf_iov *pf_iov_info;
631 struct qed_mcp_info *mcp_info;
632
633 struct qed_dcbx_info *p_dcbx_info;
634
635 struct qed_ufp_info ufp_info;
636
637 struct qed_dmae_info dmae_info;
638
639
640 struct qed_qm_info qm_info;
641 struct qed_storm_stats storm_stats;
642
643
644 void *unzip_buf;
645
646 struct dbg_tools_data dbg_info;
647 void *dbg_user_info;
648
649
650 u16 wid_count;
651 u32 dpi_size;
652 u32 dpi_count;
653
654
655 u32 dpi_start_offset;
656
657
658 u8 dcbx_no_edpm;
659 u8 db_bar_no_edpm;
660
661
662 struct qed_l2_info *p_l2_info;
663
664
665 struct qed_db_recovery_info db_recovery_info;
666
667
668 struct qed_nvm_image_info nvm_info;
669
670 struct qed_ptt *p_arfs_ptt;
671
672 struct qed_simd_fp_handler simd_proto_handler[64];
673
674#ifdef CONFIG_QED_SRIOV
675 struct workqueue_struct *iov_wq;
676 struct delayed_work iov_task;
677 unsigned long iov_task_flags;
678#endif
679 struct z_stream_s *stream;
680 bool slowpath_wq_active;
681 struct workqueue_struct *slowpath_wq;
682 struct delayed_work slowpath_task;
683 unsigned long slowpath_task_flags;
684 u32 periodic_db_rec_count;
685};
686
687struct pci_params {
688 int pm_cap;
689
690 unsigned long mem_start;
691 unsigned long mem_end;
692 unsigned int irq;
693 u8 pf_num;
694};
695
696struct qed_int_param {
697 u32 int_mode;
698 u8 num_vectors;
699 u8 min_msix_cnt;
700};
701
702struct qed_int_params {
703 struct qed_int_param in;
704 struct qed_int_param out;
705 struct msix_entry *msix_table;
706 bool fp_initialized;
707 u8 fp_msix_base;
708 u8 fp_msix_cnt;
709 u8 rdma_msix_base;
710 u8 rdma_msix_cnt;
711};
712
713struct qed_dbg_feature {
714 struct dentry *dentry;
715 u8 *dump_buf;
716 u32 buf_size;
717 u32 dumped_dwords;
718};
719
720struct qed_dbg_params {
721 struct qed_dbg_feature features[DBG_FEATURE_NUM];
722 u8 engine_for_debug;
723 bool print_data;
724};
725
726struct qed_dev {
727 u32 dp_module;
728 u8 dp_level;
729 char name[NAME_SIZE];
730
731 enum qed_dev_type type;
732
733#define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
734#define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \
735 CHIP_REV_IS_B0(dev))
736#define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
737#define QED_IS_K2(dev) QED_IS_AH(dev)
738
739 u16 vendor_id;
740 u16 device_id;
741#define QED_DEV_ID_MASK 0xff00
742#define QED_DEV_ID_MASK_BB 0x1600
743#define QED_DEV_ID_MASK_AH 0x8000
744
745 u16 chip_num;
746#define CHIP_NUM_MASK 0xffff
747#define CHIP_NUM_SHIFT 16
748
749 u16 chip_rev;
750#define CHIP_REV_MASK 0xf
751#define CHIP_REV_SHIFT 12
752#define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
753
754 u16 chip_metal;
755#define CHIP_METAL_MASK 0xff
756#define CHIP_METAL_SHIFT 4
757
758 u16 chip_bond_id;
759#define CHIP_BOND_ID_MASK 0xf
760#define CHIP_BOND_ID_SHIFT 0
761
762 u8 num_engines;
763 u8 num_ports;
764 u8 num_ports_in_engine;
765 u8 num_funcs_in_port;
766
767 u8 path_id;
768
769 unsigned long mf_bits;
770
771 int pcie_width;
772 int pcie_speed;
773
774
775 u8 mcp_rev;
776 u8 boot_mode;
777
778
779 u8 wol_config;
780 u8 wol_mac[ETH_ALEN];
781
782 u32 int_mode;
783 enum qed_coalescing_mode int_coalescing_mode;
784 u16 rx_coalesce_usecs;
785 u16 tx_coalesce_usecs;
786
787
788 void __iomem *regview;
789 void __iomem *doorbells;
790 u64 db_phys_addr;
791 unsigned long db_size;
792
793
794 u8 cache_shift;
795
796
797 const struct iro *iro_arr;
798#define IRO (p_hwfn->cdev->iro_arr)
799
800
801 u8 num_hwfns;
802 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
803
804
805 struct qed_hw_sriov_info *p_iov_info;
806#define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
807 struct qed_tunnel_info tunnel;
808 bool b_is_vf;
809 u32 drv_type;
810 struct qed_eth_stats *reset_stats;
811 struct qed_fw_data *fw_data;
812
813 u32 mcp_nvm_resp;
814
815
816 bool recov_in_prog;
817
818
819 struct qede_dev *edev;
820 struct pci_dev *pdev;
821 u32 flags;
822#define QED_FLAG_STORAGE_STARTED (BIT(0))
823 int msg_enable;
824
825 struct pci_params pci_params;
826
827 struct qed_int_params int_params;
828
829 u8 protocol;
830#define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
831#define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
832
833
834 union {
835 struct qed_common_cb_ops *common;
836 struct qed_eth_cb_ops *eth;
837 struct qed_fcoe_cb_ops *fcoe;
838 struct qed_iscsi_cb_ops *iscsi;
839 } protocol_ops;
840 void *ops_cookie;
841
842 struct qed_dbg_params dbg_params;
843
844#ifdef CONFIG_QED_LL2
845 struct qed_cb_ll2_info *ll2;
846 u8 ll2_mac_address[ETH_ALEN];
847#endif
848 DECLARE_HASHTABLE(connections, 10);
849 const struct firmware *firmware;
850
851 u32 rdma_max_sge;
852 u32 rdma_max_inline;
853 u32 rdma_max_srq_sge;
854 u16 tunn_feature_mask;
855};
856
857#define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
858 : MAX_NUM_VFS_K2)
859#define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
860 : MAX_NUM_L2_QUEUES_K2)
861#define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
862 : MAX_NUM_PORTS_K2)
863#define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
864 : MAX_SB_PER_PATH_K2)
865#define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
866 : MAX_NUM_PFS_K2)
867
868
869
870
871
872
873
874
875
876static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
877 u32 concrete_fid)
878{
879 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
880 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
881 u8 vf_valid = GET_FIELD(concrete_fid,
882 PXP_CONCRETE_FID_VFVALID);
883 u8 sw_fid;
884
885 if (vf_valid)
886 sw_fid = vfid + MAX_NUM_PFS;
887 else
888 sw_fid = pfid;
889
890 return sw_fid;
891}
892
893#define PKT_LB_TC 9
894#define MAX_NUM_VOQS_E4 20
895
896int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
897void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
898 struct qed_ptt *p_ptt,
899 u32 min_pf_rate);
900
901void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
902int qed_device_num_engines(struct qed_dev *cdev);
903void qed_set_fw_mac_addr(__le16 *fw_msb,
904 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
905
906#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
907
908
909#define PQ_FLAGS_RLS (BIT(0))
910#define PQ_FLAGS_MCOS (BIT(1))
911#define PQ_FLAGS_LB (BIT(2))
912#define PQ_FLAGS_OOO (BIT(3))
913#define PQ_FLAGS_ACK (BIT(4))
914#define PQ_FLAGS_OFLD (BIT(5))
915#define PQ_FLAGS_VFS (BIT(6))
916#define PQ_FLAGS_LLT (BIT(7))
917#define PQ_FLAGS_MTC (BIT(8))
918
919
920u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
921u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
922u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
923u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
924u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
925
926#define QED_LEADING_HWFN(dev) (&dev->hwfns[0])
927
928
929void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
930void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
931bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
932
933
934#define DP_NAME(cdev) ((cdev)->name)
935
936#define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\
937 (cdev->regview) + \
938 (offset))
939
940#define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
941#define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
942#define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
943
944#define DOORBELL(cdev, db_addr, val) \
945 writel((u32)val, (void __iomem *)((u8 __iomem *)\
946 (cdev->doorbells) + (db_addr)))
947
948#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
949 qed_device_num_ports((_p_hwfn)->cdev))
950int qed_device_num_ports(struct qed_dev *cdev);
951
952
953int qed_fill_dev_info(struct qed_dev *cdev,
954 struct qed_dev_info *dev_info);
955void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
956u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
957 u32 input_len, u8 *input_buf,
958 u32 max_size, u8 *unzip_buf);
959void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
960void qed_get_protocol_stats(struct qed_dev *cdev,
961 enum qed_mcp_protocol_type type,
962 union qed_mcp_protocol_stats *stats);
963int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
964void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
965int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
966
967int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
968 enum qed_mfw_tlv_type type,
969 union qed_mfw_tlv_data *tlv_data);
970
971void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
972
973void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
974#endif
975