1/* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver 2 * 3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) 4 * 5 * This program is dual-licensed; you may select either version 2 of 6 * the GNU General Public License ("GPL") or BSD license ("BSD"). 7 * 8 * This Synopsys DWC XLGMAC software driver and associated documentation 9 * (hereinafter the "Software") is an unsupported proprietary work of 10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between 11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a 12 * Licensed Product under any End User Software License Agreement or 13 * Agreement for Licensed Products with Synopsys or any supplement thereto. 14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included 15 * in the SOFTWARE may be the trademarks of their respective owners. 16 */ 17 18#ifndef __DWC_XLGMAC_REG_H__ 19#define __DWC_XLGMAC_REG_H__ 20 21/* MAC register offsets */ 22#define MAC_TCR 0x0000 23#define MAC_RCR 0x0004 24#define MAC_PFR 0x0008 25#define MAC_HTR0 0x0010 26#define MAC_VLANTR 0x0050 27#define MAC_VLANHTR 0x0058 28#define MAC_VLANIR 0x0060 29#define MAC_Q0TFCR 0x0070 30#define MAC_RFCR 0x0090 31#define MAC_RQC0R 0x00a0 32#define MAC_RQC1R 0x00a4 33#define MAC_RQC2R 0x00a8 34#define MAC_RQC3R 0x00ac 35#define MAC_ISR 0x00b0 36#define MAC_IER 0x00b4 37#define MAC_VR 0x0110 38#define MAC_HWF0R 0x011c 39#define MAC_HWF1R 0x0120 40#define MAC_HWF2R 0x0124 41#define MAC_MACA0HR 0x0300 42#define MAC_MACA0LR 0x0304 43#define MAC_MACA1HR 0x0308 44#define MAC_MACA1LR 0x030c 45#define MAC_RSSCR 0x0c80 46#define MAC_RSSAR 0x0c88 47#define MAC_RSSDR 0x0c8c 48 49#define MAC_QTFCR_INC 4 50#define MAC_MACA_INC 4 51#define MAC_HTR_INC 4 52#define MAC_RQC2_INC 4 53#define MAC_RQC2_Q_PER_REG 4 54 55/* MAC register entry bit positions and sizes */ 56#define MAC_HWF0R_ADDMACADRSEL_POS 18 57#define MAC_HWF0R_ADDMACADRSEL_LEN 5 58#define MAC_HWF0R_ARPOFFSEL_POS 9 59#define MAC_HWF0R_ARPOFFSEL_LEN 1 60#define MAC_HWF0R_EEESEL_POS 13 61#define MAC_HWF0R_EEESEL_LEN 1 62#define MAC_HWF0R_PHYIFSEL_POS 1 63#define MAC_HWF0R_PHYIFSEL_LEN 2 64#define MAC_HWF0R_MGKSEL_POS 7 65#define MAC_HWF0R_MGKSEL_LEN 1 66#define MAC_HWF0R_MMCSEL_POS 8 67#define MAC_HWF0R_MMCSEL_LEN 1 68#define MAC_HWF0R_RWKSEL_POS 6 69#define MAC_HWF0R_RWKSEL_LEN 1 70#define MAC_HWF0R_RXCOESEL_POS 16 71#define MAC_HWF0R_RXCOESEL_LEN 1 72#define MAC_HWF0R_SAVLANINS_POS 27 73#define MAC_HWF0R_SAVLANINS_LEN 1 74#define MAC_HWF0R_SMASEL_POS 5 75#define MAC_HWF0R_SMASEL_LEN 1 76#define MAC_HWF0R_TSSEL_POS 12 77#define MAC_HWF0R_TSSEL_LEN 1 78#define MAC_HWF0R_TSSTSSEL_POS 25 79#define MAC_HWF0R_TSSTSSEL_LEN 2 80#define MAC_HWF0R_TXCOESEL_POS 14 81#define MAC_HWF0R_TXCOESEL_LEN 1 82#define MAC_HWF0R_VLHASH_POS 4 83#define MAC_HWF0R_VLHASH_LEN 1 84#define MAC_HWF1R_ADDR64_POS 14 85#define MAC_HWF1R_ADDR64_LEN 2 86#define MAC_HWF1R_ADVTHWORD_POS 13 87#define MAC_HWF1R_ADVTHWORD_LEN 1 88#define MAC_HWF1R_DBGMEMA_POS 19 89#define MAC_HWF1R_DBGMEMA_LEN 1 90#define MAC_HWF1R_DCBEN_POS 16 91#define MAC_HWF1R_DCBEN_LEN 1 92#define MAC_HWF1R_HASHTBLSZ_POS 24 93#define MAC_HWF1R_HASHTBLSZ_LEN 3 94#define MAC_HWF1R_L3L4FNUM_POS 27 95#define MAC_HWF1R_L3L4FNUM_LEN 4 96#define MAC_HWF1R_NUMTC_POS 21 97#define MAC_HWF1R_NUMTC_LEN 3 98#define MAC_HWF1R_RSSEN_POS 20 99#define MAC_HWF1R_RSSEN_LEN 1 100#define MAC_HWF1R_RXFIFOSIZE_POS 0 101#define MAC_HWF1R_RXFIFOSIZE_LEN 5 102#define MAC_HWF1R_SPHEN_POS 17 103#define MAC_HWF1R_SPHEN_LEN 1 104#define MAC_HWF1R_TSOEN_POS 18 105#define MAC_HWF1R_TSOEN_LEN 1 106#define MAC_HWF1R_TXFIFOSIZE_POS 6 107#define MAC_HWF1R_TXFIFOSIZE_LEN 5 108#define MAC_HWF2R_AUXSNAPNUM_POS 28 109#define MAC_HWF2R_AUXSNAPNUM_LEN 3 110#define MAC_HWF2R_PPSOUTNUM_POS 24 111#define MAC_HWF2R_PPSOUTNUM_LEN 3 112#define MAC_HWF2R_RXCHCNT_POS 12 113#define MAC_HWF2R_RXCHCNT_LEN 4 114#define MAC_HWF2R_RXQCNT_POS 0 115#define MAC_HWF2R_RXQCNT_LEN 4 116#define MAC_HWF2R_TXCHCNT_POS 18 117#define MAC_HWF2R_TXCHCNT_LEN 4 118#define MAC_HWF2R_TXQCNT_POS 6 119#define MAC_HWF2R_TXQCNT_LEN 4 120#define MAC_IER_TSIE_POS 12 121#define MAC_IER_TSIE_LEN 1 122#define MAC_ISR_MMCRXIS_POS 9 123#define MAC_ISR_MMCRXIS_LEN 1 124#define MAC_ISR_MMCTXIS_POS 10 125#define MAC_ISR_MMCTXIS_LEN 1 126#define MAC_ISR_PMTIS_POS 4 127#define MAC_ISR_PMTIS_LEN 1 128#define MAC_ISR_TSIS_POS 12 129#define MAC_ISR_TSIS_LEN 1 130#define MAC_MACA1HR_AE_POS 31 131#define MAC_MACA1HR_AE_LEN 1 132#define MAC_PFR_HMC_POS 2 133#define MAC_PFR_HMC_LEN 1 134#define MAC_PFR_HPF_POS 10 135#define MAC_PFR_HPF_LEN 1 136#define MAC_PFR_HUC_POS 1 137#define MAC_PFR_HUC_LEN 1 138#define MAC_PFR_PM_POS 4 139#define MAC_PFR_PM_LEN 1 140#define MAC_PFR_PR_POS 0 141#define MAC_PFR_PR_LEN 1 142#define MAC_PFR_VTFE_POS 16 143#define MAC_PFR_VTFE_LEN 1 144#define MAC_Q0TFCR_PT_POS 16 145#define MAC_Q0TFCR_PT_LEN 16 146#define MAC_Q0TFCR_TFE_POS 1 147#define MAC_Q0TFCR_TFE_LEN 1 148#define MAC_RCR_ACS_POS 1 149#define MAC_RCR_ACS_LEN 1 150#define MAC_RCR_CST_POS 2 151#define MAC_RCR_CST_LEN 1 152#define MAC_RCR_DCRCC_POS 3 153#define MAC_RCR_DCRCC_LEN 1 154#define MAC_RCR_HDSMS_POS 12 155#define MAC_RCR_HDSMS_LEN 3 156#define MAC_RCR_IPC_POS 9 157#define MAC_RCR_IPC_LEN 1 158#define MAC_RCR_JE_POS 8 159#define MAC_RCR_JE_LEN 1 160#define MAC_RCR_LM_POS 10 161#define MAC_RCR_LM_LEN 1 162#define MAC_RCR_RE_POS 0 163#define MAC_RCR_RE_LEN 1 164#define MAC_RFCR_PFCE_POS 8 165#define MAC_RFCR_PFCE_LEN 1 166#define MAC_RFCR_RFE_POS 0 167#define MAC_RFCR_RFE_LEN 1 168#define MAC_RFCR_UP_POS 1 169#define MAC_RFCR_UP_LEN 1 170#define MAC_RQC0R_RXQ0EN_POS 0 171#define MAC_RQC0R_RXQ0EN_LEN 2 172#define MAC_RSSAR_ADDRT_POS 2 173#define MAC_RSSAR_ADDRT_LEN 1 174#define MAC_RSSAR_CT_POS 1 175#define MAC_RSSAR_CT_LEN 1 176#define MAC_RSSAR_OB_POS 0 177#define MAC_RSSAR_OB_LEN 1 178#define MAC_RSSAR_RSSIA_POS 8 179#define MAC_RSSAR_RSSIA_LEN 8 180#define MAC_RSSCR_IP2TE_POS 1 181#define MAC_RSSCR_IP2TE_LEN 1 182#define MAC_RSSCR_RSSE_POS 0 183#define MAC_RSSCR_RSSE_LEN 1 184#define MAC_RSSCR_TCP4TE_POS 2 185#define MAC_RSSCR_TCP4TE_LEN 1 186#define MAC_RSSCR_UDP4TE_POS 3 187#define MAC_RSSCR_UDP4TE_LEN 1 188#define MAC_RSSDR_DMCH_POS 0 189#define MAC_RSSDR_DMCH_LEN 4 190#define MAC_TCR_SS_POS 28 191#define MAC_TCR_SS_LEN 3 192#define MAC_TCR_TE_POS 0 193#define MAC_TCR_TE_LEN 1 194#define MAC_VLANHTR_VLHT_POS 0 195#define MAC_VLANHTR_VLHT_LEN 16 196#define MAC_VLANIR_VLTI_POS 20 197#define MAC_VLANIR_VLTI_LEN 1 198#define MAC_VLANIR_CSVL_POS 19 199#define MAC_VLANIR_CSVL_LEN 1 200#define MAC_VLANTR_DOVLTC_POS 20 201#define MAC_VLANTR_DOVLTC_LEN 1 202#define MAC_VLANTR_ERSVLM_POS 19 203#define MAC_VLANTR_ERSVLM_LEN 1 204#define MAC_VLANTR_ESVL_POS 18 205#define MAC_VLANTR_ESVL_LEN 1 206#define MAC_VLANTR_ETV_POS 16 207#define MAC_VLANTR_ETV_LEN 1 208#define MAC_VLANTR_EVLS_POS 21 209#define MAC_VLANTR_EVLS_LEN 2 210#define MAC_VLANTR_EVLRXS_POS 24 211#define MAC_VLANTR_EVLRXS_LEN 1 212#define MAC_VLANTR_VL_POS 0 213#define MAC_VLANTR_VL_LEN 16 214#define MAC_VLANTR_VTHM_POS 25 215#define MAC_VLANTR_VTHM_LEN 1 216#define MAC_VLANTR_VTIM_POS 17 217#define MAC_VLANTR_VTIM_LEN 1 218#define MAC_VR_DEVID_POS 8 219#define MAC_VR_DEVID_LEN 8 220#define MAC_VR_SNPSVER_POS 0 221#define MAC_VR_SNPSVER_LEN 8 222#define MAC_VR_USERVER_POS 16 223#define MAC_VR_USERVER_LEN 8 224 225/* MMC register offsets */ 226#define MMC_CR 0x0800 227#define MMC_RISR 0x0804 228#define MMC_TISR 0x0808 229#define MMC_RIER 0x080c 230#define MMC_TIER 0x0810 231#define MMC_TXOCTETCOUNT_GB_LO 0x0814 232#define MMC_TXFRAMECOUNT_GB_LO 0x081c 233#define MMC_TXBROADCASTFRAMES_G_LO 0x0824 234#define MMC_TXMULTICASTFRAMES_G_LO 0x082c 235#define MMC_TX64OCTETS_GB_LO 0x0834 236#define MMC_TX65TO127OCTETS_GB_LO 0x083c 237#define MMC_TX128TO255OCTETS_GB_LO 0x0844 238#define MMC_TX256TO511OCTETS_GB_LO 0x084c 239#define MMC_TX512TO1023OCTETS_GB_LO 0x0854 240#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c 241#define MMC_TXUNICASTFRAMES_GB_LO 0x0864 242#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c 243#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874 244#define MMC_TXUNDERFLOWERROR_LO 0x087c 245#define MMC_TXOCTETCOUNT_G_LO 0x0884 246#define MMC_TXFRAMECOUNT_G_LO 0x088c 247#define MMC_TXPAUSEFRAMES_LO 0x0894 248#define MMC_TXVLANFRAMES_G_LO 0x089c 249#define MMC_RXFRAMECOUNT_GB_LO 0x0900 250#define MMC_RXOCTETCOUNT_GB_LO 0x0908 251#define MMC_RXOCTETCOUNT_G_LO 0x0910 252#define MMC_RXBROADCASTFRAMES_G_LO 0x0918 253#define MMC_RXMULTICASTFRAMES_G_LO 0x0920 254#define MMC_RXCRCERROR_LO 0x0928 255#define MMC_RXRUNTERROR 0x0930 256#define MMC_RXJABBERERROR 0x0934 257#define MMC_RXUNDERSIZE_G 0x0938 258#define MMC_RXOVERSIZE_G 0x093c 259#define MMC_RX64OCTETS_GB_LO 0x0940 260#define MMC_RX65TO127OCTETS_GB_LO 0x0948 261#define MMC_RX128TO255OCTETS_GB_LO 0x0950 262#define MMC_RX256TO511OCTETS_GB_LO 0x0958 263#define MMC_RX512TO1023OCTETS_GB_LO 0x0960 264#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968 265#define MMC_RXUNICASTFRAMES_G_LO 0x0970 266#define MMC_RXLENGTHERROR_LO 0x0978 267#define MMC_RXOUTOFRANGETYPE_LO 0x0980 268#define MMC_RXPAUSEFRAMES_LO 0x0988 269#define MMC_RXFIFOOVERFLOW_LO 0x0990 270#define MMC_RXVLANFRAMES_GB_LO 0x0998 271#define MMC_RXWATCHDOGERROR 0x09a0 272 273/* MMC register entry bit positions and sizes */ 274#define MMC_CR_CR_POS 0 275#define MMC_CR_CR_LEN 1 276#define MMC_CR_CSR_POS 1 277#define MMC_CR_CSR_LEN 1 278#define MMC_CR_ROR_POS 2 279#define MMC_CR_ROR_LEN 1 280#define MMC_CR_MCF_POS 3 281#define MMC_CR_MCF_LEN 1 282#define MMC_CR_MCT_POS 4 283#define MMC_CR_MCT_LEN 2 284#define MMC_RIER_ALL_INTERRUPTS_POS 0 285#define MMC_RIER_ALL_INTERRUPTS_LEN 23 286#define MMC_RISR_RXFRAMECOUNT_GB_POS 0 287#define MMC_RISR_RXFRAMECOUNT_GB_LEN 1 288#define MMC_RISR_RXOCTETCOUNT_GB_POS 1 289#define MMC_RISR_RXOCTETCOUNT_GB_LEN 1 290#define MMC_RISR_RXOCTETCOUNT_G_POS 2 291#define MMC_RISR_RXOCTETCOUNT_G_LEN 1 292#define MMC_RISR_RXBROADCASTFRAMES_G_POS 3 293#define MMC_RISR_RXBROADCASTFRAMES_G_LEN 1 294#define MMC_RISR_RXMULTICASTFRAMES_G_POS 4 295#define MMC_RISR_RXMULTICASTFRAMES_G_LEN 1 296#define MMC_RISR_RXCRCERROR_POS 5 297#define MMC_RISR_RXCRCERROR_LEN 1 298#define MMC_RISR_RXRUNTERROR_POS 6 299#define MMC_RISR_RXRUNTERROR_LEN 1 300#define MMC_RISR_RXJABBERERROR_POS 7 301#define MMC_RISR_RXJABBERERROR_LEN 1 302#define MMC_RISR_RXUNDERSIZE_G_POS 8 303#define MMC_RISR_RXUNDERSIZE_G_LEN 1 304#define MMC_RISR_RXOVERSIZE_G_POS 9 305#define MMC_RISR_RXOVERSIZE_G_LEN 1 306#define MMC_RISR_RX64OCTETS_GB_POS 10 307#define MMC_RISR_RX64OCTETS_GB_LEN 1 308#define MMC_RISR_RX65TO127OCTETS_GB_POS 11 309#define MMC_RISR_RX65TO127OCTETS_GB_LEN 1 310#define MMC_RISR_RX128TO255OCTETS_GB_POS 12 311#define MMC_RISR_RX128TO255OCTETS_GB_LEN 1 312#define MMC_RISR_RX256TO511OCTETS_GB_POS 13 313#define MMC_RISR_RX256TO511OCTETS_GB_LEN 1 314#define MMC_RISR_RX512TO1023OCTETS_GB_POS 14 315#define MMC_RISR_RX512TO1023OCTETS_GB_LEN 1 316#define MMC_RISR_RX1024TOMAXOCTETS_GB_POS 15 317#define MMC_RISR_RX1024TOMAXOCTETS_GB_LEN 1 318#define MMC_RISR_RXUNICASTFRAMES_G_POS 16 319#define MMC_RISR_RXUNICASTFRAMES_G_LEN 1 320#define MMC_RISR_RXLENGTHERROR_POS 17 321#define MMC_RISR_RXLENGTHERROR_LEN 1 322#define MMC_RISR_RXOUTOFRANGETYPE_POS 18 323#define MMC_RISR_RXOUTOFRANGETYPE_LEN 1 324#define MMC_RISR_RXPAUSEFRAMES_POS 19 325#define MMC_RISR_RXPAUSEFRAMES_LEN 1 326#define MMC_RISR_RXFIFOOVERFLOW_POS 20 327#define MMC_RISR_RXFIFOOVERFLOW_LEN 1 328#define MMC_RISR_RXVLANFRAMES_GB_POS 21 329#define MMC_RISR_RXVLANFRAMES_GB_LEN 1 330#define MMC_RISR_RXWATCHDOGERROR_POS 22 331#define MMC_RISR_RXWATCHDOGERROR_LEN 1 332#define MMC_TIER_ALL_INTERRUPTS_POS 0 333#define MMC_TIER_ALL_INTERRUPTS_LEN 18 334#define MMC_TISR_TXOCTETCOUNT_GB_POS 0 335#define MMC_TISR_TXOCTETCOUNT_GB_LEN 1 336#define MMC_TISR_TXFRAMECOUNT_GB_POS 1 337#define MMC_TISR_TXFRAMECOUNT_GB_LEN 1 338#define MMC_TISR_TXBROADCASTFRAMES_G_POS 2 339#define MMC_TISR_TXBROADCASTFRAMES_G_LEN 1 340#define MMC_TISR_TXMULTICASTFRAMES_G_POS 3 341#define MMC_TISR_TXMULTICASTFRAMES_G_LEN 1 342#define MMC_TISR_TX64OCTETS_GB_POS 4 343#define MMC_TISR_TX64OCTETS_GB_LEN 1 344#define MMC_TISR_TX65TO127OCTETS_GB_POS 5 345#define MMC_TISR_TX65TO127OCTETS_GB_LEN 1 346#define MMC_TISR_TX128TO255OCTETS_GB_POS 6 347#define MMC_TISR_TX128TO255OCTETS_GB_LEN 1 348#define MMC_TISR_TX256TO511OCTETS_GB_POS 7 349#define MMC_TISR_TX256TO511OCTETS_GB_LEN 1 350#define MMC_TISR_TX512TO1023OCTETS_GB_POS 8 351#define MMC_TISR_TX512TO1023OCTETS_GB_LEN 1 352#define MMC_TISR_TX1024TOMAXOCTETS_GB_POS 9 353#define MMC_TISR_TX1024TOMAXOCTETS_GB_LEN 1 354#define MMC_TISR_TXUNICASTFRAMES_GB_POS 10 355#define MMC_TISR_TXUNICASTFRAMES_GB_LEN 1 356#define MMC_TISR_TXMULTICASTFRAMES_GB_POS 11 357#define MMC_TISR_TXMULTICASTFRAMES_GB_LEN 1 358#define MMC_TISR_TXBROADCASTFRAMES_GB_POS 12 359#define MMC_TISR_TXBROADCASTFRAMES_GB_LEN 1 360#define MMC_TISR_TXUNDERFLOWERROR_POS 13 361#define MMC_TISR_TXUNDERFLOWERROR_LEN 1 362#define MMC_TISR_TXOCTETCOUNT_G_POS 14 363#define MMC_TISR_TXOCTETCOUNT_G_LEN 1 364#define MMC_TISR_TXFRAMECOUNT_G_POS 15 365#define MMC_TISR_TXFRAMECOUNT_G_LEN 1 366#define MMC_TISR_TXPAUSEFRAMES_POS 16 367#define MMC_TISR_TXPAUSEFRAMES_LEN 1 368#define MMC_TISR_TXVLANFRAMES_G_POS 17 369#define MMC_TISR_TXVLANFRAMES_G_LEN 1 370 371/* MTL register offsets */ 372#define MTL_OMR 0x1000 373#define MTL_FDDR 0x1010 374#define MTL_RQDCM0R 0x1030 375 376#define MTL_RQDCM_INC 4 377#define MTL_RQDCM_Q_PER_REG 4 378 379/* MTL register entry bit positions and sizes */ 380#define MTL_OMR_ETSALG_POS 5 381#define MTL_OMR_ETSALG_LEN 2 382#define MTL_OMR_RAA_POS 2 383#define MTL_OMR_RAA_LEN 1 384 385/* MTL queue register offsets 386 * Multiple queues can be active. The first queue has registers 387 * that begin at 0x1100. Each subsequent queue has registers that 388 * are accessed using an offset of 0x80 from the previous queue. 389 */ 390#define MTL_Q_BASE 0x1100 391#define MTL_Q_INC 0x80 392 393#define MTL_Q_TQOMR 0x00 394#define MTL_Q_RQOMR 0x40 395#define MTL_Q_RQDR 0x48 396#define MTL_Q_RQFCR 0x50 397#define MTL_Q_IER 0x70 398#define MTL_Q_ISR 0x74 399 400/* MTL queue register entry bit positions and sizes */ 401#define MTL_Q_RQDR_PRXQ_POS 16 402#define MTL_Q_RQDR_PRXQ_LEN 14 403#define MTL_Q_RQDR_RXQSTS_POS 4 404#define MTL_Q_RQDR_RXQSTS_LEN 2 405#define MTL_Q_RQFCR_RFA_POS 1 406#define MTL_Q_RQFCR_RFA_LEN 6 407#define MTL_Q_RQFCR_RFD_POS 17 408#define MTL_Q_RQFCR_RFD_LEN 6 409#define MTL_Q_RQOMR_EHFC_POS 7 410#define MTL_Q_RQOMR_EHFC_LEN 1 411#define MTL_Q_RQOMR_RQS_POS 16 412#define MTL_Q_RQOMR_RQS_LEN 9 413#define MTL_Q_RQOMR_RSF_POS 5 414#define MTL_Q_RQOMR_RSF_LEN 1 415#define MTL_Q_RQOMR_FEP_POS 4 416#define MTL_Q_RQOMR_FEP_LEN 1 417#define MTL_Q_RQOMR_FUP_POS 3 418#define MTL_Q_RQOMR_FUP_LEN 1 419#define MTL_Q_RQOMR_RTC_POS 0 420#define MTL_Q_RQOMR_RTC_LEN 2 421#define MTL_Q_TQOMR_FTQ_POS 0 422#define MTL_Q_TQOMR_FTQ_LEN 1 423#define MTL_Q_TQOMR_Q2TCMAP_POS 8 424#define MTL_Q_TQOMR_Q2TCMAP_LEN 3 425#define MTL_Q_TQOMR_TQS_POS 16 426#define MTL_Q_TQOMR_TQS_LEN 10 427#define MTL_Q_TQOMR_TSF_POS 1 428#define MTL_Q_TQOMR_TSF_LEN 1 429#define MTL_Q_TQOMR_TTC_POS 4 430#define MTL_Q_TQOMR_TTC_LEN 3 431#define MTL_Q_TQOMR_TXQEN_POS 2 432#define MTL_Q_TQOMR_TXQEN_LEN 2 433 434/* MTL queue register value */ 435#define MTL_RSF_DISABLE 0x00 436#define MTL_RSF_ENABLE 0x01 437#define MTL_TSF_DISABLE 0x00 438#define MTL_TSF_ENABLE 0x01 439 440#define MTL_RX_THRESHOLD_64 0x00 441#define MTL_RX_THRESHOLD_96 0x02 442#define MTL_RX_THRESHOLD_128 0x03 443#define MTL_TX_THRESHOLD_64 0x00 444#define MTL_TX_THRESHOLD_96 0x02 445#define MTL_TX_THRESHOLD_128 0x03 446#define MTL_TX_THRESHOLD_192 0x04 447#define MTL_TX_THRESHOLD_256 0x05 448#define MTL_TX_THRESHOLD_384 0x06 449#define MTL_TX_THRESHOLD_512 0x07 450 451#define MTL_ETSALG_WRR 0x00 452#define MTL_ETSALG_WFQ 0x01 453#define MTL_ETSALG_DWRR 0x02 454#define MTL_RAA_SP 0x00 455#define MTL_RAA_WSP 0x01 456 457#define MTL_Q_DISABLED 0x00 458#define MTL_Q_ENABLED 0x02 459 460#define MTL_RQDCM0R_Q0MDMACH 0x0 461#define MTL_RQDCM0R_Q1MDMACH 0x00000100 462#define MTL_RQDCM0R_Q2MDMACH 0x00020000 463#define MTL_RQDCM0R_Q3MDMACH 0x03000000 464#define MTL_RQDCM1R_Q4MDMACH 0x00000004 465#define MTL_RQDCM1R_Q5MDMACH 0x00000500 466#define MTL_RQDCM1R_Q6MDMACH 0x00060000 467#define MTL_RQDCM1R_Q7MDMACH 0x07000000 468#define MTL_RQDCM2R_Q8MDMACH 0x00000008 469#define MTL_RQDCM2R_Q9MDMACH 0x00000900 470#define MTL_RQDCM2R_Q10MDMACH 0x000A0000 471#define MTL_RQDCM2R_Q11MDMACH 0x0B000000 472 473/* MTL traffic class register offsets 474 * Multiple traffic classes can be active. The first class has registers 475 * that begin at 0x1100. Each subsequent queue has registers that 476 * are accessed using an offset of 0x80 from the previous queue. 477 */ 478#define MTL_TC_BASE MTL_Q_BASE 479#define MTL_TC_INC MTL_Q_INC 480 481#define MTL_TC_ETSCR 0x10 482#define MTL_TC_ETSSR 0x14 483#define MTL_TC_QWR 0x18 484 485/* MTL traffic class register entry bit positions and sizes */ 486#define MTL_TC_ETSCR_TSA_POS 0 487#define MTL_TC_ETSCR_TSA_LEN 2 488#define MTL_TC_QWR_QW_POS 0 489#define MTL_TC_QWR_QW_LEN 21 490 491/* MTL traffic class register value */ 492#define MTL_TSA_SP 0x00 493#define MTL_TSA_ETS 0x02 494 495/* DMA register offsets */ 496#define DMA_MR 0x3000 497#define DMA_SBMR 0x3004 498#define DMA_ISR 0x3008 499#define DMA_DSR0 0x3020 500#define DMA_DSR1 0x3024 501 502/* DMA register entry bit positions and sizes */ 503#define DMA_ISR_MACIS_POS 17 504#define DMA_ISR_MACIS_LEN 1 505#define DMA_ISR_MTLIS_POS 16 506#define DMA_ISR_MTLIS_LEN 1 507#define DMA_MR_SWR_POS 0 508#define DMA_MR_SWR_LEN 1 509#define DMA_SBMR_EAME_POS 11 510#define DMA_SBMR_EAME_LEN 1 511#define DMA_SBMR_BLEN_64_POS 5 512#define DMA_SBMR_BLEN_64_LEN 1 513#define DMA_SBMR_BLEN_128_POS 6 514#define DMA_SBMR_BLEN_128_LEN 1 515#define DMA_SBMR_BLEN_256_POS 7 516#define DMA_SBMR_BLEN_256_LEN 1 517#define DMA_SBMR_UNDEF_POS 0 518#define DMA_SBMR_UNDEF_LEN 1 519 520/* DMA register values */ 521#define DMA_DSR_RPS_LEN 4 522#define DMA_DSR_TPS_LEN 4 523#define DMA_DSR_Q_LEN (DMA_DSR_RPS_LEN + DMA_DSR_TPS_LEN) 524#define DMA_DSR0_TPS_START 12 525#define DMA_DSRX_FIRST_QUEUE 3 526#define DMA_DSRX_INC 4 527#define DMA_DSRX_QPR 4 528#define DMA_DSRX_TPS_START 4 529#define DMA_TPS_STOPPED 0x00 530#define DMA_TPS_SUSPENDED 0x06 531 532/* DMA channel register offsets 533 * Multiple channels can be active. The first channel has registers 534 * that begin at 0x3100. Each subsequent channel has registers that 535 * are accessed using an offset of 0x80 from the previous channel. 536 */ 537#define DMA_CH_BASE 0x3100 538#define DMA_CH_INC 0x80 539 540#define DMA_CH_CR 0x00 541#define DMA_CH_TCR 0x04 542#define DMA_CH_RCR 0x08 543#define DMA_CH_TDLR_HI 0x10 544#define DMA_CH_TDLR_LO 0x14 545#define DMA_CH_RDLR_HI 0x18 546#define DMA_CH_RDLR_LO 0x1c 547#define DMA_CH_TDTR_LO 0x24 548#define DMA_CH_RDTR_LO 0x2c 549#define DMA_CH_TDRLR 0x30 550#define DMA_CH_RDRLR 0x34 551#define DMA_CH_IER 0x38 552#define DMA_CH_RIWT 0x3c 553#define DMA_CH_SR 0x60 554 555/* DMA channel register entry bit positions and sizes */ 556#define DMA_CH_CR_PBLX8_POS 16 557#define DMA_CH_CR_PBLX8_LEN 1 558#define DMA_CH_CR_SPH_POS 24 559#define DMA_CH_CR_SPH_LEN 1 560#define DMA_CH_IER_AIE_POS 15 561#define DMA_CH_IER_AIE_LEN 1 562#define DMA_CH_IER_FBEE_POS 12 563#define DMA_CH_IER_FBEE_LEN 1 564#define DMA_CH_IER_NIE_POS 16 565#define DMA_CH_IER_NIE_LEN 1 566#define DMA_CH_IER_RBUE_POS 7 567#define DMA_CH_IER_RBUE_LEN 1 568#define DMA_CH_IER_RIE_POS 6 569#define DMA_CH_IER_RIE_LEN 1 570#define DMA_CH_IER_RSE_POS 8 571#define DMA_CH_IER_RSE_LEN 1 572#define DMA_CH_IER_TBUE_POS 2 573#define DMA_CH_IER_TBUE_LEN 1 574#define DMA_CH_IER_TIE_POS 0 575#define DMA_CH_IER_TIE_LEN 1 576#define DMA_CH_IER_TXSE_POS 1 577#define DMA_CH_IER_TXSE_LEN 1 578#define DMA_CH_RCR_PBL_POS 16 579#define DMA_CH_RCR_PBL_LEN 6 580#define DMA_CH_RCR_RBSZ_POS 1 581#define DMA_CH_RCR_RBSZ_LEN 14 582#define DMA_CH_RCR_SR_POS 0 583#define DMA_CH_RCR_SR_LEN 1 584#define DMA_CH_RIWT_RWT_POS 0 585#define DMA_CH_RIWT_RWT_LEN 8 586#define DMA_CH_SR_FBE_POS 12 587#define DMA_CH_SR_FBE_LEN 1 588#define DMA_CH_SR_RBU_POS 7 589#define DMA_CH_SR_RBU_LEN 1 590#define DMA_CH_SR_RI_POS 6 591#define DMA_CH_SR_RI_LEN 1 592#define DMA_CH_SR_RPS_POS 8 593#define DMA_CH_SR_RPS_LEN 1 594#define DMA_CH_SR_TBU_POS 2 595#define DMA_CH_SR_TBU_LEN 1 596#define DMA_CH_SR_TI_POS 0 597#define DMA_CH_SR_TI_LEN 1 598#define DMA_CH_SR_TPS_POS 1 599#define DMA_CH_SR_TPS_LEN 1 600#define DMA_CH_TCR_OSP_POS 4 601#define DMA_CH_TCR_OSP_LEN 1 602#define DMA_CH_TCR_PBL_POS 16 603#define DMA_CH_TCR_PBL_LEN 6 604#define DMA_CH_TCR_ST_POS 0 605#define DMA_CH_TCR_ST_LEN 1 606#define DMA_CH_TCR_TSE_POS 12 607#define DMA_CH_TCR_TSE_LEN 1 608 609/* DMA channel register values */ 610#define DMA_OSP_DISABLE 0x00 611#define DMA_OSP_ENABLE 0x01 612#define DMA_PBL_1 1 613#define DMA_PBL_2 2 614#define DMA_PBL_4 4 615#define DMA_PBL_8 8 616#define DMA_PBL_16 16 617#define DMA_PBL_32 32 618#define DMA_PBL_64 64 619#define DMA_PBL_128 128 620#define DMA_PBL_256 256 621#define DMA_PBL_X8_DISABLE 0x00 622#define DMA_PBL_X8_ENABLE 0x01 623 624/* Descriptor/Packet entry bit positions and sizes */ 625#define RX_PACKET_ERRORS_CRC_POS 2 626#define RX_PACKET_ERRORS_CRC_LEN 1 627#define RX_PACKET_ERRORS_FRAME_POS 3 628#define RX_PACKET_ERRORS_FRAME_LEN 1 629#define RX_PACKET_ERRORS_LENGTH_POS 0 630#define RX_PACKET_ERRORS_LENGTH_LEN 1 631#define RX_PACKET_ERRORS_OVERRUN_POS 1 632#define RX_PACKET_ERRORS_OVERRUN_LEN 1 633 634#define RX_PACKET_ATTRIBUTES_CSUM_DONE_POS 0 635#define RX_PACKET_ATTRIBUTES_CSUM_DONE_LEN 1 636#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 1 637#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1 638#define RX_PACKET_ATTRIBUTES_INCOMPLETE_POS 2 639#define RX_PACKET_ATTRIBUTES_INCOMPLETE_LEN 1 640#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_POS 3 641#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_LEN 1 642#define RX_PACKET_ATTRIBUTES_CONTEXT_POS 4 643#define RX_PACKET_ATTRIBUTES_CONTEXT_LEN 1 644#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_POS 5 645#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_LEN 1 646#define RX_PACKET_ATTRIBUTES_RSS_HASH_POS 6 647#define RX_PACKET_ATTRIBUTES_RSS_HASH_LEN 1 648 649#define RX_NORMAL_DESC0_OVT_POS 0 650#define RX_NORMAL_DESC0_OVT_LEN 16 651#define RX_NORMAL_DESC2_HL_POS 0 652#define RX_NORMAL_DESC2_HL_LEN 10 653#define RX_NORMAL_DESC3_CDA_POS 27 654#define RX_NORMAL_DESC3_CDA_LEN 1 655#define RX_NORMAL_DESC3_CTXT_POS 30 656#define RX_NORMAL_DESC3_CTXT_LEN 1 657#define RX_NORMAL_DESC3_ES_POS 15 658#define RX_NORMAL_DESC3_ES_LEN 1 659#define RX_NORMAL_DESC3_ETLT_POS 16 660#define RX_NORMAL_DESC3_ETLT_LEN 4 661#define RX_NORMAL_DESC3_FD_POS 29 662#define RX_NORMAL_DESC3_FD_LEN 1 663#define RX_NORMAL_DESC3_INTE_POS 30 664#define RX_NORMAL_DESC3_INTE_LEN 1 665#define RX_NORMAL_DESC3_L34T_POS 20 666#define RX_NORMAL_DESC3_L34T_LEN 4 667#define RX_NORMAL_DESC3_LD_POS 28 668#define RX_NORMAL_DESC3_LD_LEN 1 669#define RX_NORMAL_DESC3_OWN_POS 31 670#define RX_NORMAL_DESC3_OWN_LEN 1 671#define RX_NORMAL_DESC3_PL_POS 0 672#define RX_NORMAL_DESC3_PL_LEN 14 673#define RX_NORMAL_DESC3_RSV_POS 26 674#define RX_NORMAL_DESC3_RSV_LEN 1 675 676#define RX_DESC3_L34T_IPV4_TCP 1 677#define RX_DESC3_L34T_IPV4_UDP 2 678#define RX_DESC3_L34T_IPV4_ICMP 3 679#define RX_DESC3_L34T_IPV6_TCP 9 680#define RX_DESC3_L34T_IPV6_UDP 10 681#define RX_DESC3_L34T_IPV6_ICMP 11 682 683#define RX_CONTEXT_DESC3_TSA_POS 4 684#define RX_CONTEXT_DESC3_TSA_LEN 1 685#define RX_CONTEXT_DESC3_TSD_POS 6 686#define RX_CONTEXT_DESC3_TSD_LEN 1 687 688#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_POS 0 689#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_LEN 1 690#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_POS 1 691#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_LEN 1 692#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_POS 2 693#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_LEN 1 694#define TX_PACKET_ATTRIBUTES_PTP_POS 3 695#define TX_PACKET_ATTRIBUTES_PTP_LEN 1 696 697#define TX_CONTEXT_DESC2_MSS_POS 0 698#define TX_CONTEXT_DESC2_MSS_LEN 15 699#define TX_CONTEXT_DESC3_CTXT_POS 30 700#define TX_CONTEXT_DESC3_CTXT_LEN 1 701#define TX_CONTEXT_DESC3_TCMSSV_POS 26 702#define TX_CONTEXT_DESC3_TCMSSV_LEN 1 703#define TX_CONTEXT_DESC3_VLTV_POS 16 704#define TX_CONTEXT_DESC3_VLTV_LEN 1 705#define TX_CONTEXT_DESC3_VT_POS 0 706#define TX_CONTEXT_DESC3_VT_LEN 16 707 708#define TX_NORMAL_DESC2_HL_B1L_POS 0 709#define TX_NORMAL_DESC2_HL_B1L_LEN 14 710#define TX_NORMAL_DESC2_IC_POS 31 711#define TX_NORMAL_DESC2_IC_LEN 1 712#define TX_NORMAL_DESC2_TTSE_POS 30 713#define TX_NORMAL_DESC2_TTSE_LEN 1 714#define TX_NORMAL_DESC2_VTIR_POS 14 715#define TX_NORMAL_DESC2_VTIR_LEN 2 716#define TX_NORMAL_DESC3_CIC_POS 16 717#define TX_NORMAL_DESC3_CIC_LEN 2 718#define TX_NORMAL_DESC3_CPC_POS 26 719#define TX_NORMAL_DESC3_CPC_LEN 2 720#define TX_NORMAL_DESC3_CTXT_POS 30 721#define TX_NORMAL_DESC3_CTXT_LEN 1 722#define TX_NORMAL_DESC3_FD_POS 29 723#define TX_NORMAL_DESC3_FD_LEN 1 724#define TX_NORMAL_DESC3_FL_POS 0 725#define TX_NORMAL_DESC3_FL_LEN 15 726#define TX_NORMAL_DESC3_LD_POS 28 727#define TX_NORMAL_DESC3_LD_LEN 1 728#define TX_NORMAL_DESC3_OWN_POS 31 729#define TX_NORMAL_DESC3_OWN_LEN 1 730#define TX_NORMAL_DESC3_TCPHDRLEN_POS 19 731#define TX_NORMAL_DESC3_TCPHDRLEN_LEN 4 732#define TX_NORMAL_DESC3_TCPPL_POS 0 733#define TX_NORMAL_DESC3_TCPPL_LEN 18 734#define TX_NORMAL_DESC3_TSE_POS 18 735#define TX_NORMAL_DESC3_TSE_LEN 1 736 737#define TX_NORMAL_DESC2_VLAN_INSERT 0x2 738 739#define XLGMAC_MTL_REG(pdata, n, reg) \ 740 ((pdata)->mac_regs + MTL_Q_BASE + ((n) * MTL_Q_INC) + (reg)) 741 742#define XLGMAC_DMA_REG(channel, reg) ((channel)->dma_regs + (reg)) 743 744#endif /* __DWC_XLGMAC_REG_H__ */ 745