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28#include <linux/crc-ccitt.h>
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/init.h>
32#include <linux/sched.h>
33#include <linux/string.h>
34#include <linux/workqueue.h>
35#include <linux/fs.h>
36#include <linux/parport.h>
37#include <linux/if_arp.h>
38#include <linux/hdlcdrv.h>
39#include <linux/baycom.h>
40#include <linux/jiffies.h>
41#include <linux/random.h>
42#include <net/ax25.h>
43#include <linux/uaccess.h>
44
45
46
47#define BAYCOM_DEBUG
48#define BAYCOM_MAGIC 19730510
49
50
51
52static const char paranoia_str[] = KERN_ERR
53 "baycom_epp: bad magic number for hdlcdrv_state struct in routine %s\n";
54
55static const char bc_drvname[] = "baycom_epp";
56static const char bc_drvinfo[] = KERN_INFO "baycom_epp: (C) 1998-2000 Thomas Sailer, HB9JNX/AE4WA\n"
57"baycom_epp: version 0.7\n";
58
59
60
61#define NR_PORTS 4
62
63static struct net_device *baycom_device[NR_PORTS];
64
65
66
67
68#define EPP_DCDBIT 0x80
69#define EPP_PTTBIT 0x08
70#define EPP_NREF 0x01
71#define EPP_NRAEF 0x02
72#define EPP_NRHF 0x04
73#define EPP_NTHF 0x20
74#define EPP_NTAEF 0x10
75#define EPP_NTEF EPP_PTTBIT
76
77
78#define EPP_TX_FIFO_ENABLE 0x10
79#define EPP_RX_FIFO_ENABLE 0x08
80#define EPP_MODEM_ENABLE 0x20
81#define EPP_LEDS 0xC0
82#define EPP_IRQ_ENABLE 0x10
83
84
85#define LPTREG_ECONTROL 0x402
86#define LPTREG_CONFIGB 0x401
87#define LPTREG_CONFIGA 0x400
88#define LPTREG_EPPDATA 0x004
89#define LPTREG_EPPADDR 0x003
90#define LPTREG_CONTROL 0x002
91#define LPTREG_STATUS 0x001
92#define LPTREG_DATA 0x000
93
94
95#define LPTCTRL_PROGRAM 0x04
96#define LPTCTRL_WRITE 0x01
97#define LPTCTRL_ADDRSTB 0x08
98#define LPTCTRL_DATASTB 0x02
99#define LPTCTRL_INTEN 0x10
100
101
102#define LPTSTAT_SHIFT_NINTR 6
103#define LPTSTAT_WAIT 0x80
104#define LPTSTAT_NINTR (1<<LPTSTAT_SHIFT_NINTR)
105#define LPTSTAT_PE 0x20
106#define LPTSTAT_DONE 0x10
107#define LPTSTAT_NERROR 0x08
108#define LPTSTAT_EPPTIMEOUT 0x01
109
110
111#define LPTDATA_SHIFT_TDI 0
112#define LPTDATA_SHIFT_TMS 2
113#define LPTDATA_TDI (1<<LPTDATA_SHIFT_TDI)
114#define LPTDATA_TCK 0x02
115#define LPTDATA_TMS (1<<LPTDATA_SHIFT_TMS)
116#define LPTDATA_INITBIAS 0x80
117
118
119
120#define EPP_DCDBIT 0x80
121#define EPP_PTTBIT 0x08
122#define EPP_RXEBIT 0x01
123#define EPP_RXAEBIT 0x02
124#define EPP_RXHFULL 0x04
125
126#define EPP_NTHF 0x20
127#define EPP_NTAEF 0x10
128#define EPP_NTEF EPP_PTTBIT
129
130#define EPP_TX_FIFO_ENABLE 0x10
131#define EPP_RX_FIFO_ENABLE 0x08
132#define EPP_MODEM_ENABLE 0x20
133#define EPP_LEDS 0xC0
134#define EPP_IRQ_ENABLE 0x10
135
136
137#define XC4K_IRLENGTH 3
138#define XC4K_EXTEST 0
139#define XC4K_PRELOAD 1
140#define XC4K_CONFIGURE 5
141#define XC4K_BYPASS 7
142
143#define EPP_CONVENTIONAL 0
144#define EPP_FPGA 1
145#define EPP_FPGAEXTSTATUS 2
146
147#define TXBUFFER_SIZE ((HDLCDRV_MAXFLEN*6/5)+8)
148
149
150
151
152
153
154struct baycom_state {
155 int magic;
156
157 struct pardevice *pdev;
158 struct net_device *dev;
159 unsigned int work_running;
160 struct delayed_work run_work;
161 unsigned int modem;
162 unsigned int bitrate;
163 unsigned char stat;
164
165 struct {
166 unsigned int intclk;
167 unsigned int fclk;
168 unsigned int bps;
169 unsigned int extmodem;
170 unsigned int loopback;
171 } cfg;
172
173 struct hdlcdrv_channel_params ch_params;
174
175 struct {
176 unsigned int bitbuf, bitstream, numbits, state;
177 unsigned char *bufptr;
178 int bufcnt;
179 unsigned char buf[TXBUFFER_SIZE];
180 } hdlcrx;
181
182 struct {
183 int calibrate;
184 int slotcnt;
185 int flags;
186 enum { tx_idle = 0, tx_keyup, tx_data, tx_tail } state;
187 unsigned char *bufptr;
188 int bufcnt;
189 unsigned char buf[TXBUFFER_SIZE];
190 } hdlctx;
191
192 unsigned int ptt_keyed;
193 struct sk_buff *skb;
194
195#ifdef BAYCOM_DEBUG
196 struct debug_vals {
197 unsigned long last_jiffies;
198 unsigned cur_intcnt;
199 unsigned last_intcnt;
200 int cur_pllcorr;
201 int last_pllcorr;
202 unsigned int mod_cycles;
203 unsigned int demod_cycles;
204 } debug_vals;
205#endif
206};
207
208
209
210#define KISS_VERBOSE
211
212
213
214#define PARAM_TXDELAY 1
215#define PARAM_PERSIST 2
216#define PARAM_SLOTTIME 3
217#define PARAM_TXTAIL 4
218#define PARAM_FULLDUP 5
219#define PARAM_HARDWARE 6
220#define PARAM_RETURN 255
221
222
223
224
225
226
227
228
229
230
231#if 0
232static inline void append_crc_ccitt(unsigned char *buffer, int len)
233{
234 unsigned int crc = 0xffff;
235
236 for (;len>0;len--)
237 crc = (crc >> 8) ^ crc_ccitt_table[(crc ^ *buffer++) & 0xff];
238 crc ^= 0xffff;
239 *buffer++ = crc;
240 *buffer++ = crc >> 8;
241}
242#endif
243
244
245
246static inline int check_crc_ccitt(const unsigned char *buf, int cnt)
247{
248 return (crc_ccitt(0xffff, buf, cnt) & 0xffff) == 0xf0b8;
249}
250
251
252
253static inline int calc_crc_ccitt(const unsigned char *buf, int cnt)
254{
255 return (crc_ccitt(0xffff, buf, cnt) ^ 0xffff) & 0xffff;
256}
257
258
259
260#define tenms_to_flags(bc,tenms) ((tenms * bc->bitrate) / 800)
261
262
263
264static inline void baycom_int_freq(struct baycom_state *bc)
265{
266#ifdef BAYCOM_DEBUG
267 unsigned long cur_jiffies = jiffies;
268
269
270
271 bc->debug_vals.cur_intcnt++;
272 if (time_after_eq(cur_jiffies, bc->debug_vals.last_jiffies + HZ)) {
273 bc->debug_vals.last_jiffies = cur_jiffies;
274 bc->debug_vals.last_intcnt = bc->debug_vals.cur_intcnt;
275 bc->debug_vals.cur_intcnt = 0;
276 bc->debug_vals.last_pllcorr = bc->debug_vals.cur_pllcorr;
277 bc->debug_vals.cur_pllcorr = 0;
278 }
279#endif
280}
281
282
283
284
285
286
287static char const eppconfig_path[] = "/usr/sbin/eppfpga";
288
289static char *envp[] = { "HOME=/", "TERM=linux", "PATH=/usr/bin:/bin", NULL };
290
291
292static int eppconfig(struct baycom_state *bc)
293{
294 char modearg[256];
295 char portarg[16];
296 char *argv[] = {
297 (char *)eppconfig_path,
298 "-s",
299 "-p", portarg,
300 "-m", modearg,
301 NULL };
302
303
304 sprintf(modearg, "%sclk,%smodem,fclk=%d,bps=%d,divider=%d%s,extstat",
305 bc->cfg.intclk ? "int" : "ext",
306 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
307 (bc->cfg.fclk + 8 * bc->cfg.bps) / (16 * bc->cfg.bps),
308 bc->cfg.loopback ? ",loopback" : "");
309 sprintf(portarg, "%ld", bc->pdev->port->base);
310 printk(KERN_DEBUG "%s: %s -s -p %s -m %s\n", bc_drvname, eppconfig_path, portarg, modearg);
311
312 return call_usermodehelper(eppconfig_path, argv, envp, UMH_WAIT_PROC);
313}
314
315
316
317static inline void do_kiss_params(struct baycom_state *bc,
318 unsigned char *data, unsigned long len)
319{
320
321#ifdef KISS_VERBOSE
322#define PKP(a,b) printk(KERN_INFO "baycomm_epp: channel params: " a "\n", b)
323#else
324#define PKP(a,b)
325#endif
326
327 if (len < 2)
328 return;
329 switch(data[0]) {
330 case PARAM_TXDELAY:
331 bc->ch_params.tx_delay = data[1];
332 PKP("TX delay = %ums", 10 * bc->ch_params.tx_delay);
333 break;
334 case PARAM_PERSIST:
335 bc->ch_params.ppersist = data[1];
336 PKP("p persistence = %u", bc->ch_params.ppersist);
337 break;
338 case PARAM_SLOTTIME:
339 bc->ch_params.slottime = data[1];
340 PKP("slot time = %ums", bc->ch_params.slottime);
341 break;
342 case PARAM_TXTAIL:
343 bc->ch_params.tx_tail = data[1];
344 PKP("TX tail = %ums", bc->ch_params.tx_tail);
345 break;
346 case PARAM_FULLDUP:
347 bc->ch_params.fulldup = !!data[1];
348 PKP("%s duplex", bc->ch_params.fulldup ? "full" : "half");
349 break;
350 default:
351 break;
352 }
353#undef PKP
354}
355
356
357
358static void encode_hdlc(struct baycom_state *bc)
359{
360 struct sk_buff *skb;
361 unsigned char *wp, *bp;
362 int pkt_len;
363 unsigned bitstream, notbitstream, bitbuf, numbit, crc;
364 unsigned char crcarr[2];
365 int j;
366
367 if (bc->hdlctx.bufcnt > 0)
368 return;
369 skb = bc->skb;
370 if (!skb)
371 return;
372 bc->skb = NULL;
373 pkt_len = skb->len-1;
374 wp = bc->hdlctx.buf;
375 bp = skb->data+1;
376 crc = calc_crc_ccitt(bp, pkt_len);
377 crcarr[0] = crc;
378 crcarr[1] = crc >> 8;
379 *wp++ = 0x7e;
380 bitstream = bitbuf = numbit = 0;
381 while (pkt_len > -2) {
382 bitstream >>= 8;
383 bitstream |= ((unsigned int)*bp) << 8;
384 bitbuf |= ((unsigned int)*bp) << numbit;
385 notbitstream = ~bitstream;
386 bp++;
387 pkt_len--;
388 if (!pkt_len)
389 bp = crcarr;
390 for (j = 0; j < 8; j++)
391 if (unlikely(!(notbitstream & (0x1f0 << j)))) {
392 bitstream &= ~(0x100 << j);
393 bitbuf = (bitbuf & (((2 << j) << numbit) - 1)) |
394 ((bitbuf & ~(((2 << j) << numbit) - 1)) << 1);
395 numbit++;
396 notbitstream = ~bitstream;
397 }
398 numbit += 8;
399 while (numbit >= 8) {
400 *wp++ = bitbuf;
401 bitbuf >>= 8;
402 numbit -= 8;
403 }
404 }
405 bitbuf |= 0x7e7e << numbit;
406 numbit += 16;
407 while (numbit >= 8) {
408 *wp++ = bitbuf;
409 bitbuf >>= 8;
410 numbit -= 8;
411 }
412 bc->hdlctx.bufptr = bc->hdlctx.buf;
413 bc->hdlctx.bufcnt = wp - bc->hdlctx.buf;
414 dev_kfree_skb(skb);
415 bc->dev->stats.tx_packets++;
416}
417
418
419
420static int transmit(struct baycom_state *bc, int cnt, unsigned char stat)
421{
422 struct parport *pp = bc->pdev->port;
423 unsigned char tmp[128];
424 int i, j;
425
426 if (bc->hdlctx.state == tx_tail && !(stat & EPP_PTTBIT))
427 bc->hdlctx.state = tx_idle;
428 if (bc->hdlctx.state == tx_idle && bc->hdlctx.calibrate <= 0) {
429 if (bc->hdlctx.bufcnt <= 0)
430 encode_hdlc(bc);
431 if (bc->hdlctx.bufcnt <= 0)
432 return 0;
433 if (!bc->ch_params.fulldup) {
434 if (!(stat & EPP_DCDBIT)) {
435 bc->hdlctx.slotcnt = bc->ch_params.slottime;
436 return 0;
437 }
438 if ((--bc->hdlctx.slotcnt) > 0)
439 return 0;
440 bc->hdlctx.slotcnt = bc->ch_params.slottime;
441 if ((prandom_u32() % 256) > bc->ch_params.ppersist)
442 return 0;
443 }
444 }
445 if (bc->hdlctx.state == tx_idle && bc->hdlctx.bufcnt > 0) {
446 bc->hdlctx.state = tx_keyup;
447 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_delay);
448 bc->ptt_keyed++;
449 }
450 while (cnt > 0) {
451 switch (bc->hdlctx.state) {
452 case tx_keyup:
453 i = min_t(int, cnt, bc->hdlctx.flags);
454 cnt -= i;
455 bc->hdlctx.flags -= i;
456 if (bc->hdlctx.flags <= 0)
457 bc->hdlctx.state = tx_data;
458 memset(tmp, 0x7e, sizeof(tmp));
459 while (i > 0) {
460 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
461 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
462 return -1;
463 i -= j;
464 }
465 break;
466
467 case tx_data:
468 if (bc->hdlctx.bufcnt <= 0) {
469 encode_hdlc(bc);
470 if (bc->hdlctx.bufcnt <= 0) {
471 bc->hdlctx.state = tx_tail;
472 bc->hdlctx.flags = tenms_to_flags(bc, bc->ch_params.tx_tail);
473 break;
474 }
475 }
476 i = min_t(int, cnt, bc->hdlctx.bufcnt);
477 bc->hdlctx.bufcnt -= i;
478 cnt -= i;
479 if (i != pp->ops->epp_write_data(pp, bc->hdlctx.bufptr, i, 0))
480 return -1;
481 bc->hdlctx.bufptr += i;
482 break;
483
484 case tx_tail:
485 encode_hdlc(bc);
486 if (bc->hdlctx.bufcnt > 0) {
487 bc->hdlctx.state = tx_data;
488 break;
489 }
490 i = min_t(int, cnt, bc->hdlctx.flags);
491 if (i) {
492 cnt -= i;
493 bc->hdlctx.flags -= i;
494 memset(tmp, 0x7e, sizeof(tmp));
495 while (i > 0) {
496 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
497 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
498 return -1;
499 i -= j;
500 }
501 break;
502 }
503
504 default:
505 if (bc->hdlctx.calibrate <= 0)
506 return 0;
507 i = min_t(int, cnt, bc->hdlctx.calibrate);
508 cnt -= i;
509 bc->hdlctx.calibrate -= i;
510 memset(tmp, 0, sizeof(tmp));
511 while (i > 0) {
512 j = (i > sizeof(tmp)) ? sizeof(tmp) : i;
513 if (j != pp->ops->epp_write_data(pp, tmp, j, 0))
514 return -1;
515 i -= j;
516 }
517 break;
518 }
519 }
520 return 0;
521}
522
523
524
525static void do_rxpacket(struct net_device *dev)
526{
527 struct baycom_state *bc = netdev_priv(dev);
528 struct sk_buff *skb;
529 unsigned char *cp;
530 unsigned pktlen;
531
532 if (bc->hdlcrx.bufcnt < 4)
533 return;
534 if (!check_crc_ccitt(bc->hdlcrx.buf, bc->hdlcrx.bufcnt))
535 return;
536 pktlen = bc->hdlcrx.bufcnt-2+1;
537 if (!(skb = dev_alloc_skb(pktlen))) {
538 printk("%s: memory squeeze, dropping packet\n", dev->name);
539 dev->stats.rx_dropped++;
540 return;
541 }
542 cp = skb_put(skb, pktlen);
543 *cp++ = 0;
544 memcpy(cp, bc->hdlcrx.buf, pktlen - 1);
545 skb->protocol = ax25_type_trans(skb, dev);
546 netif_rx(skb);
547 dev->stats.rx_packets++;
548}
549
550static int receive(struct net_device *dev, int cnt)
551{
552 struct baycom_state *bc = netdev_priv(dev);
553 struct parport *pp = bc->pdev->port;
554 unsigned int bitbuf, notbitstream, bitstream, numbits, state;
555 unsigned char tmp[128];
556 unsigned char *cp;
557 int cnt2, ret = 0;
558 int j;
559
560 numbits = bc->hdlcrx.numbits;
561 state = bc->hdlcrx.state;
562 bitstream = bc->hdlcrx.bitstream;
563 bitbuf = bc->hdlcrx.bitbuf;
564 while (cnt > 0) {
565 cnt2 = (cnt > sizeof(tmp)) ? sizeof(tmp) : cnt;
566 cnt -= cnt2;
567 if (cnt2 != pp->ops->epp_read_data(pp, tmp, cnt2, 0)) {
568 ret = -1;
569 break;
570 }
571 cp = tmp;
572 for (; cnt2 > 0; cnt2--, cp++) {
573 bitstream >>= 8;
574 bitstream |= (*cp) << 8;
575 bitbuf >>= 8;
576 bitbuf |= (*cp) << 8;
577 numbits += 8;
578 notbitstream = ~bitstream;
579 for (j = 0; j < 8; j++) {
580
581
582 if (unlikely(!(notbitstream & (0x0fc << j)))) {
583
584
585 if (!(notbitstream & (0x1fc << j)))
586 state = 0;
587
588
589 else if ((bitstream & (0x1fe << j)) == (0x0fc << j)) {
590 if (state)
591 do_rxpacket(dev);
592 bc->hdlcrx.bufcnt = 0;
593 bc->hdlcrx.bufptr = bc->hdlcrx.buf;
594 state = 1;
595 numbits = 7-j;
596 }
597 }
598
599
600 else if (unlikely((bitstream & (0x1f8 << j)) == (0xf8 << j))) {
601 numbits--;
602 bitbuf = (bitbuf & ((~0xff) << j)) | ((bitbuf & ~((~0xff) << j)) << 1);
603 }
604 }
605 while (state && numbits >= 8) {
606 if (bc->hdlcrx.bufcnt >= TXBUFFER_SIZE) {
607 state = 0;
608 } else {
609 *(bc->hdlcrx.bufptr)++ = bitbuf >> (16-numbits);
610 bc->hdlcrx.bufcnt++;
611 numbits -= 8;
612 }
613 }
614 }
615 }
616 bc->hdlcrx.numbits = numbits;
617 bc->hdlcrx.state = state;
618 bc->hdlcrx.bitstream = bitstream;
619 bc->hdlcrx.bitbuf = bitbuf;
620 return ret;
621}
622
623
624
625#ifdef __i386__
626#include <asm/msr.h>
627#define GETTICK(x) \
628({ \
629 if (boot_cpu_has(X86_FEATURE_TSC)) \
630 x = (unsigned int)rdtsc(); \
631})
632#else
633#define GETTICK(x)
634#endif
635
636static void epp_bh(struct work_struct *work)
637{
638 struct net_device *dev;
639 struct baycom_state *bc;
640 struct parport *pp;
641 unsigned char stat;
642 unsigned char tmp[2];
643 unsigned int time1 = 0, time2 = 0, time3 = 0;
644 int cnt, cnt2;
645
646 bc = container_of(work, struct baycom_state, run_work.work);
647 dev = bc->dev;
648 if (!bc->work_running)
649 return;
650 baycom_int_freq(bc);
651 pp = bc->pdev->port;
652
653 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
654 goto epptimeout;
655 bc->stat = stat;
656 bc->debug_vals.last_pllcorr = stat;
657 GETTICK(time1);
658 if (bc->modem == EPP_FPGAEXTSTATUS) {
659
660 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|1;
661 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
662 goto epptimeout;
663 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
664 goto epptimeout;
665 cnt = tmp[0] | (tmp[1] << 8);
666 cnt &= 0x7fff;
667
668 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE|2;
669 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
670 goto epptimeout;
671 if (pp->ops->epp_read_addr(pp, tmp, 2, 0) != 2)
672 goto epptimeout;
673 cnt2 = tmp[0] | (tmp[1] << 8);
674 cnt2 = 16384 - (cnt2 & 0x7fff);
675
676 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
677 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
678 goto epptimeout;
679 if (transmit(bc, cnt2, stat))
680 goto epptimeout;
681 GETTICK(time2);
682 if (receive(dev, cnt))
683 goto epptimeout;
684 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
685 goto epptimeout;
686 bc->stat = stat;
687 } else {
688
689 switch (stat & (EPP_NTAEF|EPP_NTHF)) {
690 case EPP_NTHF:
691 cnt = 2048 - 256;
692 break;
693
694 case EPP_NTAEF:
695 cnt = 2048 - 1793;
696 break;
697
698 case 0:
699 cnt = 0;
700 break;
701
702 default:
703 cnt = 2048 - 1025;
704 break;
705 }
706 if (transmit(bc, cnt, stat))
707 goto epptimeout;
708 GETTICK(time2);
709
710 while ((stat & (EPP_NRAEF|EPP_NRHF)) != EPP_NRHF) {
711 switch (stat & (EPP_NRAEF|EPP_NRHF)) {
712 case EPP_NRAEF:
713 cnt = 1025;
714 break;
715
716 case 0:
717 cnt = 1793;
718 break;
719
720 default:
721 cnt = 256;
722 break;
723 }
724 if (receive(dev, cnt))
725 goto epptimeout;
726 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
727 goto epptimeout;
728 }
729 cnt = 0;
730 if (bc->bitrate < 50000)
731 cnt = 256;
732 else if (bc->bitrate < 100000)
733 cnt = 128;
734 while (cnt > 0 && stat & EPP_NREF) {
735 if (receive(dev, 1))
736 goto epptimeout;
737 cnt--;
738 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
739 goto epptimeout;
740 }
741 }
742 GETTICK(time3);
743#ifdef BAYCOM_DEBUG
744 bc->debug_vals.mod_cycles = time2 - time1;
745 bc->debug_vals.demod_cycles = time3 - time2;
746#endif
747 schedule_delayed_work(&bc->run_work, 1);
748 if (!bc->skb)
749 netif_wake_queue(dev);
750 return;
751 epptimeout:
752 printk(KERN_ERR "%s: EPP timeout!\n", bc_drvname);
753}
754
755
756
757
758
759
760static int baycom_send_packet(struct sk_buff *skb, struct net_device *dev)
761{
762 struct baycom_state *bc = netdev_priv(dev);
763
764 if (skb->protocol == htons(ETH_P_IP))
765 return ax25_ip_xmit(skb);
766
767 if (skb->data[0] != 0) {
768 do_kiss_params(bc, skb->data, skb->len);
769 dev_kfree_skb(skb);
770 return NETDEV_TX_OK;
771 }
772 if (bc->skb) {
773 dev_kfree_skb(skb);
774 return NETDEV_TX_OK;
775 }
776
777 if (skb->len >= HDLCDRV_MAXFLEN+1 || skb->len < 3) {
778 dev_kfree_skb(skb);
779 return NETDEV_TX_OK;
780 }
781 netif_stop_queue(dev);
782 bc->skb = skb;
783 return NETDEV_TX_OK;
784}
785
786
787
788static int baycom_set_mac_address(struct net_device *dev, void *addr)
789{
790 struct sockaddr *sa = (struct sockaddr *)addr;
791
792
793 memcpy(dev->dev_addr, sa->sa_data, dev->addr_len);
794 return 0;
795}
796
797
798
799static void epp_wakeup(void *handle)
800{
801 struct net_device *dev = (struct net_device *)handle;
802 struct baycom_state *bc = netdev_priv(dev);
803
804 printk(KERN_DEBUG "baycom_epp: %s: why am I being woken up?\n", dev->name);
805 if (!parport_claim(bc->pdev))
806 printk(KERN_DEBUG "baycom_epp: %s: I'm broken.\n", dev->name);
807}
808
809
810
811
812
813
814
815
816
817
818
819
820static int epp_open(struct net_device *dev)
821{
822 struct baycom_state *bc = netdev_priv(dev);
823 struct parport *pp = parport_find_base(dev->base_addr);
824 unsigned int i, j;
825 unsigned char tmp[128];
826 unsigned char stat;
827 unsigned long tstart;
828 struct pardev_cb par_cb;
829
830 if (!pp) {
831 printk(KERN_ERR "%s: parport at 0x%lx unknown\n", bc_drvname, dev->base_addr);
832 return -ENXIO;
833 }
834#if 0
835 if (pp->irq < 0) {
836 printk(KERN_ERR "%s: parport at 0x%lx has no irq\n", bc_drvname, pp->base);
837 parport_put_port(pp);
838 return -ENXIO;
839 }
840#endif
841 if ((~pp->modes) & (PARPORT_MODE_TRISTATE | PARPORT_MODE_PCSPP | PARPORT_MODE_SAFEININT)) {
842 printk(KERN_ERR "%s: parport at 0x%lx cannot be used\n",
843 bc_drvname, pp->base);
844 parport_put_port(pp);
845 return -EIO;
846 }
847 memset(&bc->modem, 0, sizeof(bc->modem));
848 memset(&par_cb, 0, sizeof(par_cb));
849 par_cb.wakeup = epp_wakeup;
850 par_cb.private = (void *)dev;
851 par_cb.flags = PARPORT_DEV_EXCL;
852 for (i = 0; i < NR_PORTS; i++)
853 if (baycom_device[i] == dev)
854 break;
855
856 if (i == NR_PORTS) {
857 pr_err("%s: no device found\n", bc_drvname);
858 parport_put_port(pp);
859 return -ENODEV;
860 }
861
862 bc->pdev = parport_register_dev_model(pp, dev->name, &par_cb, i);
863 parport_put_port(pp);
864 if (!bc->pdev) {
865 printk(KERN_ERR "%s: cannot register parport at 0x%lx\n", bc_drvname, pp->base);
866 return -ENXIO;
867 }
868 if (parport_claim(bc->pdev)) {
869 printk(KERN_ERR "%s: parport at 0x%lx busy\n", bc_drvname, pp->base);
870 parport_unregister_device(bc->pdev);
871 return -EBUSY;
872 }
873 dev->irq = 0;
874 INIT_DELAYED_WORK(&bc->run_work, epp_bh);
875 bc->work_running = 1;
876 bc->modem = EPP_CONVENTIONAL;
877 if (eppconfig(bc))
878 printk(KERN_INFO "%s: no FPGA detected, assuming conventional EPP modem\n", bc_drvname);
879 else
880 bc->modem = EPP_FPGAEXTSTATUS;
881 parport_write_control(pp, LPTCTRL_PROGRAM);
882
883 tmp[0] = 0;
884 tmp[1] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
885 if (pp->ops->epp_write_addr(pp, tmp, 2, 0) != 2)
886 goto epptimeout;
887
888 tstart = jiffies;
889 i = 0;
890 while (time_before(jiffies, tstart + HZ/3)) {
891 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
892 goto epptimeout;
893 if ((stat & (EPP_NRAEF|EPP_NRHF)) == EPP_NRHF) {
894 schedule();
895 continue;
896 }
897 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
898 goto epptimeout;
899 if (pp->ops->epp_read_data(pp, tmp, 128, 0) != 128)
900 goto epptimeout;
901 i += 256;
902 }
903 for (j = 0; j < 256; j++) {
904 if (pp->ops->epp_read_addr(pp, &stat, 1, 0) != 1)
905 goto epptimeout;
906 if (!(stat & EPP_NREF))
907 break;
908 if (pp->ops->epp_read_data(pp, tmp, 1, 0) != 1)
909 goto epptimeout;
910 i++;
911 }
912 tstart = jiffies - tstart;
913 bc->bitrate = i * (8 * HZ) / tstart;
914 j = 1;
915 i = bc->bitrate >> 3;
916 while (j < 7 && i > 150) {
917 j++;
918 i >>= 1;
919 }
920 printk(KERN_INFO "%s: autoprobed bitrate: %d int divider: %d int rate: %d\n",
921 bc_drvname, bc->bitrate, j, bc->bitrate >> (j+2));
922 tmp[0] = EPP_TX_FIFO_ENABLE|EPP_RX_FIFO_ENABLE|EPP_MODEM_ENABLE;
923 if (pp->ops->epp_write_addr(pp, tmp, 1, 0) != 1)
924 goto epptimeout;
925
926
927
928 bc->hdlcrx.state = 0;
929 bc->hdlcrx.numbits = 0;
930 bc->hdlctx.state = tx_idle;
931 bc->hdlctx.bufcnt = 0;
932 bc->hdlctx.slotcnt = bc->ch_params.slottime;
933 bc->hdlctx.calibrate = 0;
934
935 schedule_delayed_work(&bc->run_work, 1);
936 netif_start_queue(dev);
937 return 0;
938
939 epptimeout:
940 printk(KERN_ERR "%s: epp timeout during bitrate probe\n", bc_drvname);
941 parport_write_control(pp, 0);
942 parport_release(bc->pdev);
943 parport_unregister_device(bc->pdev);
944 return -EIO;
945}
946
947
948
949static int epp_close(struct net_device *dev)
950{
951 struct baycom_state *bc = netdev_priv(dev);
952 struct parport *pp = bc->pdev->port;
953 unsigned char tmp[1];
954
955 bc->work_running = 0;
956 cancel_delayed_work_sync(&bc->run_work);
957 bc->stat = EPP_DCDBIT;
958 tmp[0] = 0;
959 pp->ops->epp_write_addr(pp, tmp, 1, 0);
960 parport_write_control(pp, 0);
961 parport_release(bc->pdev);
962 parport_unregister_device(bc->pdev);
963 if (bc->skb)
964 dev_kfree_skb(bc->skb);
965 bc->skb = NULL;
966 printk(KERN_INFO "%s: close epp at iobase 0x%lx irq %u\n",
967 bc_drvname, dev->base_addr, dev->irq);
968 return 0;
969}
970
971
972
973static int baycom_setmode(struct baycom_state *bc, const char *modestr)
974{
975 const char *cp;
976
977 if (strstr(modestr,"intclk"))
978 bc->cfg.intclk = 1;
979 if (strstr(modestr,"extclk"))
980 bc->cfg.intclk = 0;
981 if (strstr(modestr,"intmodem"))
982 bc->cfg.extmodem = 0;
983 if (strstr(modestr,"extmodem"))
984 bc->cfg.extmodem = 1;
985 if (strstr(modestr,"noloopback"))
986 bc->cfg.loopback = 0;
987 if (strstr(modestr,"loopback"))
988 bc->cfg.loopback = 1;
989 if ((cp = strstr(modestr,"fclk="))) {
990 bc->cfg.fclk = simple_strtoul(cp+5, NULL, 0);
991 if (bc->cfg.fclk < 1000000)
992 bc->cfg.fclk = 1000000;
993 if (bc->cfg.fclk > 25000000)
994 bc->cfg.fclk = 25000000;
995 }
996 if ((cp = strstr(modestr,"bps="))) {
997 bc->cfg.bps = simple_strtoul(cp+4, NULL, 0);
998 if (bc->cfg.bps < 1000)
999 bc->cfg.bps = 1000;
1000 if (bc->cfg.bps > 1500000)
1001 bc->cfg.bps = 1500000;
1002 }
1003 return 0;
1004}
1005
1006
1007
1008static int baycom_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1009{
1010 struct baycom_state *bc = netdev_priv(dev);
1011 struct hdlcdrv_ioctl hi;
1012
1013 if (cmd != SIOCDEVPRIVATE)
1014 return -ENOIOCTLCMD;
1015
1016 if (copy_from_user(&hi, ifr->ifr_data, sizeof(hi)))
1017 return -EFAULT;
1018 switch (hi.cmd) {
1019 default:
1020 return -ENOIOCTLCMD;
1021
1022 case HDLCDRVCTL_GETCHANNELPAR:
1023 hi.data.cp.tx_delay = bc->ch_params.tx_delay;
1024 hi.data.cp.tx_tail = bc->ch_params.tx_tail;
1025 hi.data.cp.slottime = bc->ch_params.slottime;
1026 hi.data.cp.ppersist = bc->ch_params.ppersist;
1027 hi.data.cp.fulldup = bc->ch_params.fulldup;
1028 break;
1029
1030 case HDLCDRVCTL_SETCHANNELPAR:
1031 if (!capable(CAP_NET_ADMIN))
1032 return -EACCES;
1033 bc->ch_params.tx_delay = hi.data.cp.tx_delay;
1034 bc->ch_params.tx_tail = hi.data.cp.tx_tail;
1035 bc->ch_params.slottime = hi.data.cp.slottime;
1036 bc->ch_params.ppersist = hi.data.cp.ppersist;
1037 bc->ch_params.fulldup = hi.data.cp.fulldup;
1038 bc->hdlctx.slotcnt = 1;
1039 return 0;
1040
1041 case HDLCDRVCTL_GETMODEMPAR:
1042 hi.data.mp.iobase = dev->base_addr;
1043 hi.data.mp.irq = dev->irq;
1044 hi.data.mp.dma = dev->dma;
1045 hi.data.mp.dma2 = 0;
1046 hi.data.mp.seriobase = 0;
1047 hi.data.mp.pariobase = 0;
1048 hi.data.mp.midiiobase = 0;
1049 break;
1050
1051 case HDLCDRVCTL_SETMODEMPAR:
1052 if ((!capable(CAP_SYS_RAWIO)) || netif_running(dev))
1053 return -EACCES;
1054 dev->base_addr = hi.data.mp.iobase;
1055 dev->irq = 0;
1056 dev->dma = 0;
1057 return 0;
1058
1059 case HDLCDRVCTL_GETSTAT:
1060 hi.data.cs.ptt = !!(bc->stat & EPP_PTTBIT);
1061 hi.data.cs.dcd = !(bc->stat & EPP_DCDBIT);
1062 hi.data.cs.ptt_keyed = bc->ptt_keyed;
1063 hi.data.cs.tx_packets = dev->stats.tx_packets;
1064 hi.data.cs.tx_errors = dev->stats.tx_errors;
1065 hi.data.cs.rx_packets = dev->stats.rx_packets;
1066 hi.data.cs.rx_errors = dev->stats.rx_errors;
1067 break;
1068
1069 case HDLCDRVCTL_OLDGETSTAT:
1070 hi.data.ocs.ptt = !!(bc->stat & EPP_PTTBIT);
1071 hi.data.ocs.dcd = !(bc->stat & EPP_DCDBIT);
1072 hi.data.ocs.ptt_keyed = bc->ptt_keyed;
1073 break;
1074
1075 case HDLCDRVCTL_CALIBRATE:
1076 if (!capable(CAP_SYS_RAWIO))
1077 return -EACCES;
1078 bc->hdlctx.calibrate = hi.data.calibrate * bc->bitrate / 8;
1079 return 0;
1080
1081 case HDLCDRVCTL_DRIVERNAME:
1082 strncpy(hi.data.drivername, "baycom_epp", sizeof(hi.data.drivername));
1083 break;
1084
1085 case HDLCDRVCTL_GETMODE:
1086 sprintf(hi.data.modename, "%sclk,%smodem,fclk=%d,bps=%d%s",
1087 bc->cfg.intclk ? "int" : "ext",
1088 bc->cfg.extmodem ? "ext" : "int", bc->cfg.fclk, bc->cfg.bps,
1089 bc->cfg.loopback ? ",loopback" : "");
1090 break;
1091
1092 case HDLCDRVCTL_SETMODE:
1093 if (!capable(CAP_NET_ADMIN) || netif_running(dev))
1094 return -EACCES;
1095 hi.data.modename[sizeof(hi.data.modename)-1] = '\0';
1096 return baycom_setmode(bc, hi.data.modename);
1097
1098 case HDLCDRVCTL_MODELIST:
1099 strncpy(hi.data.modename, "intclk,extclk,intmodem,extmodem,divider=x",
1100 sizeof(hi.data.modename));
1101 break;
1102
1103 case HDLCDRVCTL_MODEMPARMASK:
1104 return HDLCDRV_PARMASK_IOBASE;
1105
1106 }
1107 if (copy_to_user(ifr->ifr_data, &hi, sizeof(hi)))
1108 return -EFAULT;
1109 return 0;
1110}
1111
1112
1113
1114static const struct net_device_ops baycom_netdev_ops = {
1115 .ndo_open = epp_open,
1116 .ndo_stop = epp_close,
1117 .ndo_do_ioctl = baycom_ioctl,
1118 .ndo_start_xmit = baycom_send_packet,
1119 .ndo_set_mac_address = baycom_set_mac_address,
1120};
1121
1122
1123
1124
1125
1126
1127
1128
1129static void baycom_probe(struct net_device *dev)
1130{
1131 const struct hdlcdrv_channel_params dflt_ch_params = {
1132 20, 2, 10, 40, 0
1133 };
1134 struct baycom_state *bc;
1135
1136
1137
1138
1139 bc = netdev_priv(dev);
1140
1141
1142
1143 bc->ch_params = dflt_ch_params;
1144 bc->ptt_keyed = 0;
1145
1146
1147
1148
1149
1150
1151 bc->skb = NULL;
1152
1153 dev->netdev_ops = &baycom_netdev_ops;
1154 dev->header_ops = &ax25_header_ops;
1155
1156 dev->type = ARPHRD_AX25;
1157 dev->hard_header_len = AX25_MAX_HEADER_LEN + AX25_BPQ_HEADER_LEN;
1158 dev->mtu = AX25_DEF_PACLEN;
1159 dev->addr_len = AX25_ADDR_LEN;
1160 memcpy(dev->broadcast, &ax25_bcast, AX25_ADDR_LEN);
1161 memcpy(dev->dev_addr, &null_ax25_address, AX25_ADDR_LEN);
1162 dev->tx_queue_len = 16;
1163
1164
1165 dev->flags = 0;
1166}
1167
1168
1169
1170
1171
1172
1173static char *mode[NR_PORTS] = { "", };
1174static int iobase[NR_PORTS] = { 0x378, };
1175
1176module_param_array(mode, charp, NULL, 0);
1177MODULE_PARM_DESC(mode, "baycom operating mode");
1178module_param_hw_array(iobase, int, ioport, NULL, 0);
1179MODULE_PARM_DESC(iobase, "baycom io base address");
1180
1181MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
1182MODULE_DESCRIPTION("Baycom epp amateur radio modem driver");
1183MODULE_LICENSE("GPL");
1184
1185
1186
1187static int baycom_epp_par_probe(struct pardevice *par_dev)
1188{
1189 struct device_driver *drv = par_dev->dev.driver;
1190 int len = strlen(drv->name);
1191
1192 if (strncmp(par_dev->name, drv->name, len))
1193 return -ENODEV;
1194
1195 return 0;
1196}
1197
1198static struct parport_driver baycom_epp_par_driver = {
1199 .name = "bce",
1200 .probe = baycom_epp_par_probe,
1201 .devmodel = true,
1202};
1203
1204static void __init baycom_epp_dev_setup(struct net_device *dev)
1205{
1206 struct baycom_state *bc = netdev_priv(dev);
1207
1208
1209
1210
1211 bc->dev = dev;
1212 bc->magic = BAYCOM_MAGIC;
1213 bc->cfg.fclk = 19666600;
1214 bc->cfg.bps = 9600;
1215
1216
1217
1218 baycom_probe(dev);
1219}
1220
1221static int __init init_baycomepp(void)
1222{
1223 int i, found = 0, ret;
1224 char set_hw = 1;
1225
1226 printk(bc_drvinfo);
1227
1228 ret = parport_register_driver(&baycom_epp_par_driver);
1229 if (ret)
1230 return ret;
1231
1232
1233
1234
1235 for (i = 0; i < NR_PORTS; i++) {
1236 struct net_device *dev;
1237
1238 dev = alloc_netdev(sizeof(struct baycom_state), "bce%d",
1239 NET_NAME_UNKNOWN, baycom_epp_dev_setup);
1240
1241 if (!dev) {
1242 printk(KERN_WARNING "bce%d : out of memory\n", i);
1243 return found ? 0 : -ENOMEM;
1244 }
1245
1246 sprintf(dev->name, "bce%d", i);
1247 dev->base_addr = iobase[i];
1248
1249 if (!mode[i])
1250 set_hw = 0;
1251 if (!set_hw)
1252 iobase[i] = 0;
1253
1254 if (register_netdev(dev)) {
1255 printk(KERN_WARNING "%s: cannot register net device %s\n", bc_drvname, dev->name);
1256 free_netdev(dev);
1257 break;
1258 }
1259 if (set_hw && baycom_setmode(netdev_priv(dev), mode[i]))
1260 set_hw = 0;
1261 baycom_device[i] = dev;
1262 found++;
1263 }
1264
1265 if (found == 0) {
1266 parport_unregister_driver(&baycom_epp_par_driver);
1267 return -ENXIO;
1268 }
1269
1270 return 0;
1271}
1272
1273static void __exit cleanup_baycomepp(void)
1274{
1275 int i;
1276
1277 for(i = 0; i < NR_PORTS; i++) {
1278 struct net_device *dev = baycom_device[i];
1279
1280 if (dev) {
1281 struct baycom_state *bc = netdev_priv(dev);
1282 if (bc->magic == BAYCOM_MAGIC) {
1283 unregister_netdev(dev);
1284 free_netdev(dev);
1285 } else
1286 printk(paranoia_str, "cleanup_module");
1287 }
1288 }
1289 parport_unregister_driver(&baycom_epp_par_driver);
1290}
1291
1292module_init(init_baycomepp);
1293module_exit(cleanup_baycomepp);
1294
1295
1296
1297#ifndef MODULE
1298
1299
1300
1301
1302
1303
1304static int __init baycom_epp_setup(char *str)
1305{
1306 static unsigned __initdata nr_dev = 0;
1307 int ints[2];
1308
1309 if (nr_dev >= NR_PORTS)
1310 return 0;
1311 str = get_options(str, 2, ints);
1312 if (ints[0] < 1)
1313 return 0;
1314 mode[nr_dev] = str;
1315 iobase[nr_dev] = ints[1];
1316 nr_dev++;
1317 return 1;
1318}
1319
1320__setup("baycom_epp=", baycom_epp_setup);
1321
1322#endif
1323
1324
