1
2
3
4#include "wifi.h"
5#include "core.h"
6#include "pci.h"
7#include "base.h"
8#include "ps.h"
9#include "efuse.h"
10#include <linux/interrupt.h>
11#include <linux/export.h>
12#include <linux/module.h>
13
14MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
15MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
16MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
17MODULE_LICENSE("GPL");
18MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
19
20static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
21 INTEL_VENDOR_ID,
22 ATI_VENDOR_ID,
23 AMD_VENDOR_ID,
24 SIS_VENDOR_ID
25};
26
27static const u8 ac_to_hwq[] = {
28 VO_QUEUE,
29 VI_QUEUE,
30 BE_QUEUE,
31 BK_QUEUE
32};
33
34static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
35{
36 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
37 __le16 fc = rtl_get_fc(skb);
38 u8 queue_index = skb_get_queue_mapping(skb);
39 struct ieee80211_hdr *hdr;
40
41 if (unlikely(ieee80211_is_beacon(fc)))
42 return BEACON_QUEUE;
43 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
44 return MGNT_QUEUE;
45 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
46 if (ieee80211_is_nullfunc(fc))
47 return HIGH_QUEUE;
48 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
49 hdr = rtl_get_hdr(skb);
50
51 if (is_multicast_ether_addr(hdr->addr1) ||
52 is_broadcast_ether_addr(hdr->addr1))
53 return HIGH_QUEUE;
54 }
55
56 return ac_to_hwq[queue_index];
57}
58
59
60static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
61{
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
64 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
65 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
66 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
67 u8 init_aspm;
68
69 ppsc->reg_rfps_level = 0;
70 ppsc->support_aspm = false;
71
72
73 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
74 switch (rtlpci->const_pci_aspm) {
75 case 0:
76
77 break;
78
79 case 1:
80
81 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
82 break;
83
84 case 2:
85
86 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
87 RT_RF_OFF_LEVL_CLK_REQ);
88 break;
89
90 case 3:
91
92
93
94 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
95 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
96 RT_RF_OFF_LEVL_CLK_REQ);
97 break;
98
99 case 4:
100
101
102
103 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
104 RT_RF_OFF_LEVL_CLK_REQ);
105 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
106 break;
107 }
108
109 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
110
111
112 switch (rtlpci->const_hwsw_rfoff_d3) {
113 case 1:
114 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
115 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
116 break;
117
118 case 2:
119 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
120 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
121 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
122 break;
123
124 case 3:
125 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
126 break;
127 }
128
129
130 switch (rtlpci->const_support_pciaspm) {
131 case 0:
132
133 ppsc->support_aspm = false;
134 break;
135 case 1:
136
137 ppsc->support_aspm = true;
138 ppsc->support_backdoor = true;
139 break;
140 case 2:
141
142 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
143 ppsc->support_aspm = true;
144 break;
145 default:
146 pr_err("switch case %#x not processed\n",
147 rtlpci->const_support_pciaspm);
148 break;
149 }
150
151
152
153
154 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
155 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
156 init_aspm == 0x43)
157 ppsc->support_aspm = false;
158}
159
160static bool _rtl_pci_platform_switch_device_pci_aspm(
161 struct ieee80211_hw *hw,
162 u8 value)
163{
164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
166
167 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
168 value |= 0x40;
169
170 pci_write_config_byte(rtlpci->pdev, 0x80, value);
171
172 return false;
173}
174
175
176static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
177{
178 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180
181 pci_write_config_byte(rtlpci->pdev, 0x81, value);
182
183 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
184 udelay(100);
185}
186
187
188static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
189{
190 struct rtl_priv *rtlpriv = rtl_priv(hw);
191 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
192 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
193 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
194 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
195 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
196
197 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
198 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
199 pcibridge_linkctrlreg;
200 u16 aspmlevel = 0;
201 u8 tmp_u1b = 0;
202
203 if (!ppsc->support_aspm)
204 return;
205
206 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
207 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
208 "PCI(Bridge) UNKNOWN\n");
209
210 return;
211 }
212
213 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
214 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
215 _rtl_pci_switch_clk_req(hw, 0x0);
216 }
217
218
219 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
220
221
222 aspmlevel |= BIT(0) | BIT(1);
223 linkctrl_reg &= ~aspmlevel;
224 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
225
226 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
227 udelay(50);
228
229
230 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
231 pcibridge_linkctrlreg);
232
233 udelay(50);
234}
235
236
237
238
239
240
241static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
242{
243 struct rtl_priv *rtlpriv = rtl_priv(hw);
244 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
245 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
246 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
247 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
248 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
249 u16 aspmlevel;
250 u8 u_pcibridge_aspmsetting;
251 u8 u_device_aspmsetting;
252
253 if (!ppsc->support_aspm)
254 return;
255
256 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
257 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
258 "PCI(Bridge) UNKNOWN\n");
259 return;
260 }
261
262
263
264 u_pcibridge_aspmsetting =
265 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
266 rtlpci->const_hostpci_aspm_setting;
267
268 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
269 u_pcibridge_aspmsetting &= ~BIT(0);
270
271 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
272 u_pcibridge_aspmsetting);
273
274 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
275 "PlatformEnableASPM(): Write reg[%x] = %x\n",
276 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
277 u_pcibridge_aspmsetting);
278
279 udelay(50);
280
281
282 aspmlevel = rtlpci->const_devicepci_aspm_setting;
283 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
284
285
286
287
288 u_device_aspmsetting |= aspmlevel;
289
290 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
291
292 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
293 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
294 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
295 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
296 }
297 udelay(100);
298}
299
300static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
301{
302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
303
304 bool status = false;
305 u8 offset_e0;
306 unsigned int offset_e4;
307
308 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
309
310 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
311
312 if (offset_e0 == 0xA0) {
313 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
314 if (offset_e4 & BIT(23))
315 status = true;
316 }
317
318 return status;
319}
320
321static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
322 struct rtl_priv **buddy_priv)
323{
324 struct rtl_priv *rtlpriv = rtl_priv(hw);
325 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
326 bool find_buddy_priv = false;
327 struct rtl_priv *tpriv;
328 struct rtl_pci_priv *tpcipriv = NULL;
329
330 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
331 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
332 list) {
333 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
334 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
335 "pcipriv->ndis_adapter.funcnumber %x\n",
336 pcipriv->ndis_adapter.funcnumber);
337 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
338 "tpcipriv->ndis_adapter.funcnumber %x\n",
339 tpcipriv->ndis_adapter.funcnumber);
340
341 if (pcipriv->ndis_adapter.busnumber ==
342 tpcipriv->ndis_adapter.busnumber &&
343 pcipriv->ndis_adapter.devnumber ==
344 tpcipriv->ndis_adapter.devnumber &&
345 pcipriv->ndis_adapter.funcnumber !=
346 tpcipriv->ndis_adapter.funcnumber) {
347 find_buddy_priv = true;
348 break;
349 }
350 }
351 }
352
353 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
354 "find_buddy_priv %d\n", find_buddy_priv);
355
356 if (find_buddy_priv)
357 *buddy_priv = tpriv;
358
359 return find_buddy_priv;
360}
361
362static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
363{
364 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
365 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
366 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
367 u8 linkctrl_reg;
368 u8 num4bbytes;
369
370 num4bbytes = (capabilityoffset + 0x10) / 4;
371
372
373 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
374
375 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
376}
377
378static void rtl_pci_parse_configuration(struct pci_dev *pdev,
379 struct ieee80211_hw *hw)
380{
381 struct rtl_priv *rtlpriv = rtl_priv(hw);
382 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
383
384 u8 tmp;
385 u16 linkctrl_reg;
386
387
388 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
389 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
390
391 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
392 pcipriv->ndis_adapter.linkctrl_reg);
393
394 pci_read_config_byte(pdev, 0x98, &tmp);
395 tmp |= BIT(4);
396 pci_write_config_byte(pdev, 0x98, tmp);
397
398 tmp = 0x17;
399 pci_write_config_byte(pdev, 0x70f, tmp);
400}
401
402static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
403{
404 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
405
406 _rtl_pci_update_default_setting(hw);
407
408 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
409
410 rtl_pci_enable_aspm(hw);
411 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
412 }
413}
414
415static void _rtl_pci_io_handler_init(struct device *dev,
416 struct ieee80211_hw *hw)
417{
418 struct rtl_priv *rtlpriv = rtl_priv(hw);
419
420 rtlpriv->io.dev = dev;
421
422 rtlpriv->io.write8_async = pci_write8_async;
423 rtlpriv->io.write16_async = pci_write16_async;
424 rtlpriv->io.write32_async = pci_write32_async;
425
426 rtlpriv->io.read8_sync = pci_read8_sync;
427 rtlpriv->io.read16_sync = pci_read16_sync;
428 rtlpriv->io.read32_sync = pci_read32_sync;
429}
430
431static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
432 struct sk_buff *skb,
433 struct rtl_tcb_desc *tcb_desc, u8 tid)
434{
435 struct rtl_priv *rtlpriv = rtl_priv(hw);
436 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
437 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
438 struct sk_buff *next_skb;
439 u8 additionlen = FCS_LEN;
440
441
442 if (info->control.hw_key)
443 additionlen += info->control.hw_key->icv_len;
444
445
446 tcb_desc->empkt_num = 0;
447 spin_lock_bh(&rtlpriv->locks.waitq_lock);
448 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
449 struct ieee80211_tx_info *next_info;
450
451 next_info = IEEE80211_SKB_CB(next_skb);
452 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
453 tcb_desc->empkt_len[tcb_desc->empkt_num] =
454 next_skb->len + additionlen;
455 tcb_desc->empkt_num++;
456 } else {
457 break;
458 }
459
460 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
461 next_skb))
462 break;
463
464 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
465 break;
466 }
467 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
468
469 return true;
470}
471
472
473static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
474{
475 struct rtl_priv *rtlpriv = rtl_priv(hw);
476 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
477 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
478 struct sk_buff *skb = NULL;
479 struct ieee80211_tx_info *info = NULL;
480 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
481 int tid;
482
483 if (!rtlpriv->rtlhal.earlymode_enable)
484 return;
485
486 if (rtlpriv->dm.supp_phymode_switch &&
487 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
488 (rtlpriv->buddy_priv &&
489 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
490 return;
491
492 for (tid = 7; tid >= 0; tid--) {
493 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
494 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
495
496 while (!mac->act_scanning &&
497 rtlpriv->psc.rfpwr_state == ERFON) {
498 struct rtl_tcb_desc tcb_desc;
499
500 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
501
502 spin_lock(&rtlpriv->locks.waitq_lock);
503 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
504 (ring->entries - skb_queue_len(&ring->queue) >
505 rtlhal->max_earlymode_num)) {
506 skb = skb_dequeue(&mac->skb_waitq[tid]);
507 } else {
508 spin_unlock(&rtlpriv->locks.waitq_lock);
509 break;
510 }
511 spin_unlock(&rtlpriv->locks.waitq_lock);
512
513
514
515
516 info = IEEE80211_SKB_CB(skb);
517 if (info->flags & IEEE80211_TX_CTL_AMPDU)
518 _rtl_update_earlymode_info(hw, skb,
519 &tcb_desc, tid);
520
521 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
522 }
523 }
524}
525
526static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
527{
528 struct rtl_priv *rtlpriv = rtl_priv(hw);
529 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
530
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
532
533 while (skb_queue_len(&ring->queue)) {
534 struct sk_buff *skb;
535 struct ieee80211_tx_info *info;
536 __le16 fc;
537 u8 tid;
538 u8 *entry;
539
540 if (rtlpriv->use_new_trx_flow)
541 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
542 else
543 entry = (u8 *)(&ring->desc[ring->idx]);
544
545 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
546 return;
547 ring->idx = (ring->idx + 1) % ring->entries;
548
549 skb = __skb_dequeue(&ring->queue);
550 pci_unmap_single(rtlpci->pdev,
551 rtlpriv->cfg->ops->
552 get_desc(hw, (u8 *)entry, true,
553 HW_DESC_TXBUFF_ADDR),
554 skb->len, PCI_DMA_TODEVICE);
555
556
557 if (rtlpriv->rtlhal.earlymode_enable)
558 skb_pull(skb, EM_HDR_LEN);
559
560 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
561 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
562 ring->idx,
563 skb_queue_len(&ring->queue),
564 *(u16 *)(skb->data + 22));
565
566 if (prio == TXCMD_QUEUE) {
567 dev_kfree_skb(skb);
568 goto tx_status_ok;
569 }
570
571
572
573
574
575 fc = rtl_get_fc(skb);
576 if (ieee80211_is_nullfunc(fc)) {
577 if (ieee80211_has_pm(fc)) {
578 rtlpriv->mac80211.offchan_delay = true;
579 rtlpriv->psc.state_inap = true;
580 } else {
581 rtlpriv->psc.state_inap = false;
582 }
583 }
584 if (ieee80211_is_action(fc)) {
585 struct ieee80211_mgmt *action_frame =
586 (struct ieee80211_mgmt *)skb->data;
587 if (action_frame->u.action.u.ht_smps.action ==
588 WLAN_HT_ACTION_SMPS) {
589 dev_kfree_skb(skb);
590 goto tx_status_ok;
591 }
592 }
593
594
595 tid = rtl_get_tid(skb);
596 if (tid <= 7)
597 rtlpriv->link_info.tidtx_inperiod[tid]++;
598
599 info = IEEE80211_SKB_CB(skb);
600
601 if (likely(!ieee80211_is_nullfunc(fc))) {
602 ieee80211_tx_info_clear_status(info);
603 info->flags |= IEEE80211_TX_STAT_ACK;
604
605 ieee80211_tx_status_irqsafe(hw, skb);
606 } else {
607 rtl_tx_ackqueue(hw, skb);
608 }
609
610 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
611 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
612 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
613 prio, ring->idx,
614 skb_queue_len(&ring->queue));
615
616 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
617 }
618tx_status_ok:
619 skb = NULL;
620 }
621
622 if (((rtlpriv->link_info.num_rx_inperiod +
623 rtlpriv->link_info.num_tx_inperiod) > 8) ||
624 rtlpriv->link_info.num_rx_inperiod > 2)
625 rtl_lps_leave(hw);
626}
627
628static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
629 struct sk_buff *new_skb, u8 *entry,
630 int rxring_idx, int desc_idx)
631{
632 struct rtl_priv *rtlpriv = rtl_priv(hw);
633 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
634 u32 bufferaddress;
635 u8 tmp_one = 1;
636 struct sk_buff *skb;
637
638 if (likely(new_skb)) {
639 skb = new_skb;
640 goto remap;
641 }
642 skb = dev_alloc_skb(rtlpci->rxbuffersize);
643 if (!skb)
644 return 0;
645
646remap:
647
648 *((dma_addr_t *)skb->cb) =
649 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
650 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
651 bufferaddress = *((dma_addr_t *)skb->cb);
652 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
653 return 0;
654 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
655 if (rtlpriv->use_new_trx_flow) {
656
657 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
658 HW_DESC_RX_PREPARE,
659 (u8 *)(dma_addr_t *)skb->cb);
660 } else {
661 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
662 HW_DESC_RXBUFF_ADDR,
663 (u8 *)&bufferaddress);
664 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
665 HW_DESC_RXPKT_LEN,
666 (u8 *)&rtlpci->rxbuffersize);
667 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
668 HW_DESC_RXOWN,
669 (u8 *)&tmp_one);
670 }
671 return 1;
672}
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
688 struct sk_buff *skb,
689 struct ieee80211_rx_status rx_status)
690{
691 if (unlikely(!rtl_action_proc(hw, skb, false))) {
692 dev_kfree_skb_any(skb);
693 } else {
694 struct sk_buff *uskb = NULL;
695
696 uskb = dev_alloc_skb(skb->len + 128);
697 if (likely(uskb)) {
698 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
699 sizeof(rx_status));
700 skb_put_data(uskb, skb->data, skb->len);
701 dev_kfree_skb_any(skb);
702 ieee80211_rx_irqsafe(hw, uskb);
703 } else {
704 ieee80211_rx_irqsafe(hw, skb);
705 }
706 }
707}
708
709
710static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
711{
712 struct rtl_priv *rtlpriv = rtl_priv(hw);
713 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
714
715 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
716 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
717 rtlpci->sys_irq_mask);
718}
719
720static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
721{
722 struct rtl_priv *rtlpriv = rtl_priv(hw);
723 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
724 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
725 struct ieee80211_rx_status rx_status = { 0 };
726 unsigned int count = rtlpci->rxringcount;
727 u8 own;
728 u8 tmp_one;
729 bool unicast = false;
730 u8 hw_queue = 0;
731 unsigned int rx_remained_cnt = 0;
732 struct rtl_stats stats = {
733 .signal = 0,
734 .rate = 0,
735 };
736
737
738 while (count--) {
739 struct ieee80211_hdr *hdr;
740 __le16 fc;
741 u16 len;
742
743 struct rtl_rx_buffer_desc *buffer_desc = NULL;
744
745 struct rtl_rx_desc *pdesc = NULL;
746
747 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
748 rtlpci->rx_ring[rxring_idx].idx];
749 struct sk_buff *new_skb;
750
751 if (rtlpriv->use_new_trx_flow) {
752 if (rx_remained_cnt == 0)
753 rx_remained_cnt =
754 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
755 hw_queue);
756 if (rx_remained_cnt == 0)
757 return;
758 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
759 rtlpci->rx_ring[rxring_idx].idx];
760 pdesc = (struct rtl_rx_desc *)skb->data;
761 } else {
762 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
763 rtlpci->rx_ring[rxring_idx].idx];
764
765 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
766 false,
767 HW_DESC_OWN);
768 if (own)
769 return;
770 }
771
772
773
774
775
776 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
777 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
778
779
780 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
781 if (unlikely(!new_skb))
782 goto no_new;
783 memset(&rx_status, 0, sizeof(rx_status));
784 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
785 &rx_status, (u8 *)pdesc, skb);
786
787 if (rtlpriv->use_new_trx_flow)
788 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
789 (u8 *)buffer_desc,
790 hw_queue);
791
792 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
793 HW_DESC_RXPKT_LEN);
794
795 if (skb->end - skb->tail > len) {
796 skb_put(skb, len);
797 if (rtlpriv->use_new_trx_flow)
798 skb_reserve(skb, stats.rx_drvinfo_size +
799 stats.rx_bufshift + 24);
800 else
801 skb_reserve(skb, stats.rx_drvinfo_size +
802 stats.rx_bufshift);
803 } else {
804 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
805 "skb->end - skb->tail = %d, len is %d\n",
806 skb->end - skb->tail, len);
807 dev_kfree_skb_any(skb);
808 goto new_trx_end;
809 }
810
811 if (stats.packet_report_type == C2H_PACKET) {
812 rtl_c2hcmd_enqueue(hw, skb);
813 goto new_trx_end;
814 }
815
816
817
818
819
820
821
822 hdr = rtl_get_hdr(skb);
823 fc = rtl_get_fc(skb);
824
825 if (!stats.crc && !stats.hwerror) {
826 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
827 sizeof(rx_status));
828
829 if (is_broadcast_ether_addr(hdr->addr1)) {
830 ;
831 } else if (is_multicast_ether_addr(hdr->addr1)) {
832 ;
833 } else {
834 unicast = true;
835 rtlpriv->stats.rxbytesunicast += skb->len;
836 }
837 rtl_is_special_data(hw, skb, false, true);
838
839 if (ieee80211_is_data(fc)) {
840 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
841 if (unicast)
842 rtlpriv->link_info.num_rx_inperiod++;
843 }
844
845 rtl_collect_scan_list(hw, skb);
846
847
848 rtl_beacon_statistic(hw, skb);
849 rtl_p2p_info(hw, (void *)skb->data, skb->len);
850
851 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
852 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
853 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
854 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
855 (ieee80211_is_beacon(fc) ||
856 ieee80211_is_probe_resp(fc))) {
857 dev_kfree_skb_any(skb);
858 } else {
859 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
860 }
861 } else {
862 dev_kfree_skb_any(skb);
863 }
864new_trx_end:
865 if (rtlpriv->use_new_trx_flow) {
866 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
867 rtlpci->rx_ring[hw_queue].next_rx_rp %=
868 RTL_PCI_MAX_RX_COUNT;
869
870 rx_remained_cnt--;
871 rtl_write_word(rtlpriv, 0x3B4,
872 rtlpci->rx_ring[hw_queue].next_rx_rp);
873 }
874 if (((rtlpriv->link_info.num_rx_inperiod +
875 rtlpriv->link_info.num_tx_inperiod) > 8) ||
876 rtlpriv->link_info.num_rx_inperiod > 2)
877 rtl_lps_leave(hw);
878 skb = new_skb;
879no_new:
880 if (rtlpriv->use_new_trx_flow) {
881 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
882 rxring_idx,
883 rtlpci->rx_ring[rxring_idx].idx);
884 } else {
885 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
886 rxring_idx,
887 rtlpci->rx_ring[rxring_idx].idx);
888 if (rtlpci->rx_ring[rxring_idx].idx ==
889 rtlpci->rxringcount - 1)
890 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
891 false,
892 HW_DESC_RXERO,
893 (u8 *)&tmp_one);
894 }
895 rtlpci->rx_ring[rxring_idx].idx =
896 (rtlpci->rx_ring[rxring_idx].idx + 1) %
897 rtlpci->rxringcount;
898 }
899}
900
901static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
902{
903 struct ieee80211_hw *hw = dev_id;
904 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
905 struct rtl_priv *rtlpriv = rtl_priv(hw);
906 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
907 unsigned long flags;
908 struct rtl_int intvec = {0};
909
910 irqreturn_t ret = IRQ_HANDLED;
911
912 if (rtlpci->irq_enabled == 0)
913 return ret;
914
915 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
916 rtlpriv->cfg->ops->disable_interrupt(hw);
917
918
919 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
920
921
922 if (!intvec.inta || intvec.inta == 0xffff)
923 goto done;
924
925
926 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
927 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
928 "beacon ok interrupt!\n");
929
930 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
931 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
932 "beacon err interrupt!\n");
933
934 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
935 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
936
937 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
938 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
939 "prepare beacon for interrupt!\n");
940 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
941 }
942
943
944 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
945 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
946
947 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
948 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
949 "Manage ok interrupt!\n");
950 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
951 }
952
953 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
954 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
955 "HIGH_QUEUE ok interrupt!\n");
956 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
957 }
958
959 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
960 rtlpriv->link_info.num_tx_inperiod++;
961
962 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
963 "BK Tx OK interrupt!\n");
964 _rtl_pci_tx_isr(hw, BK_QUEUE);
965 }
966
967 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
968 rtlpriv->link_info.num_tx_inperiod++;
969
970 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
971 "BE TX OK interrupt!\n");
972 _rtl_pci_tx_isr(hw, BE_QUEUE);
973 }
974
975 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
976 rtlpriv->link_info.num_tx_inperiod++;
977
978 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
979 "VI TX OK interrupt!\n");
980 _rtl_pci_tx_isr(hw, VI_QUEUE);
981 }
982
983 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
984 rtlpriv->link_info.num_tx_inperiod++;
985
986 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
987 "Vo TX OK interrupt!\n");
988 _rtl_pci_tx_isr(hw, VO_QUEUE);
989 }
990
991 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
992 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
993 rtlpriv->link_info.num_tx_inperiod++;
994
995 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
996 "H2C TX OK interrupt!\n");
997 _rtl_pci_tx_isr(hw, H2C_QUEUE);
998 }
999 }
1000
1001 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1002 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1003 rtlpriv->link_info.num_tx_inperiod++;
1004
1005 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1006 "CMD TX OK interrupt!\n");
1007 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1008 }
1009 }
1010
1011
1012 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1013 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1014 _rtl_pci_rx_interrupt(hw);
1015 }
1016
1017 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1018 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1019 "rx descriptor unavailable!\n");
1020 _rtl_pci_rx_interrupt(hw);
1021 }
1022
1023 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1024 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1025 _rtl_pci_rx_interrupt(hw);
1026 }
1027
1028
1029 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1030 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1031 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1032 "firmware interrupt!\n");
1033 queue_delayed_work(rtlpriv->works.rtl_wq,
1034 &rtlpriv->works.fwevt_wq, 0);
1035 }
1036 }
1037
1038
1039
1040
1041
1042
1043
1044 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1045 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1046 if (unlikely(intvec.inta &
1047 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1048 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1049 "hsisr interrupt!\n");
1050 _rtl_pci_hs_interrupt(hw);
1051 }
1052 }
1053
1054 if (rtlpriv->rtlhal.earlymode_enable)
1055 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1056
1057done:
1058 rtlpriv->cfg->ops->enable_interrupt(hw);
1059 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1060 return ret;
1061}
1062
1063static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
1064{
1065 _rtl_pci_tx_chk_waitq(hw);
1066}
1067
1068static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
1069{
1070 struct rtl_priv *rtlpriv = rtl_priv(hw);
1071 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1072 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1073 struct rtl8192_tx_ring *ring = NULL;
1074 struct ieee80211_hdr *hdr = NULL;
1075 struct ieee80211_tx_info *info = NULL;
1076 struct sk_buff *pskb = NULL;
1077 struct rtl_tx_desc *pdesc = NULL;
1078 struct rtl_tcb_desc tcb_desc;
1079
1080 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1081 u8 temp_one = 1;
1082 u8 *entry;
1083
1084 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1085 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1086 pskb = __skb_dequeue(&ring->queue);
1087 if (rtlpriv->use_new_trx_flow)
1088 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1089 else
1090 entry = (u8 *)(&ring->desc[ring->idx]);
1091 if (pskb) {
1092 pci_unmap_single(rtlpci->pdev,
1093 rtlpriv->cfg->ops->get_desc(
1094 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1095 pskb->len, PCI_DMA_TODEVICE);
1096 kfree_skb(pskb);
1097 }
1098
1099
1100 pskb = ieee80211_beacon_get(hw, mac->vif);
1101 if (!pskb)
1102 return;
1103 hdr = rtl_get_hdr(pskb);
1104 info = IEEE80211_SKB_CB(pskb);
1105 pdesc = &ring->desc[0];
1106 if (rtlpriv->use_new_trx_flow)
1107 pbuffer_desc = &ring->buffer_desc[0];
1108
1109 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1110 (u8 *)pbuffer_desc, info, NULL, pskb,
1111 BEACON_QUEUE, &tcb_desc);
1112
1113 __skb_queue_tail(&ring->queue, pskb);
1114
1115 if (rtlpriv->use_new_trx_flow) {
1116 temp_one = 4;
1117 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1118 HW_DESC_OWN, (u8 *)&temp_one);
1119 } else {
1120 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1121 &temp_one);
1122 }
1123}
1124
1125static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1126{
1127 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1128 struct rtl_priv *rtlpriv = rtl_priv(hw);
1129 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1130 u8 i;
1131 u16 desc_num;
1132
1133 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1134 desc_num = TX_DESC_NUM_92E;
1135 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1136 desc_num = TX_DESC_NUM_8822B;
1137 else
1138 desc_num = RT_TXDESC_NUM;
1139
1140 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1141 rtlpci->txringcount[i] = desc_num;
1142
1143
1144
1145
1146 rtlpci->txringcount[BEACON_QUEUE] = 2;
1147
1148
1149
1150
1151
1152 if (!rtl_priv(hw)->use_new_trx_flow)
1153 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1154
1155 rtlpci->rxbuffersize = 9100;
1156 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT;
1157}
1158
1159static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1160 struct pci_dev *pdev)
1161{
1162 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1164 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1165 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1166
1167 rtlpci->up_first_time = true;
1168 rtlpci->being_init_adapter = false;
1169
1170 rtlhal->hw = hw;
1171 rtlpci->pdev = pdev;
1172
1173
1174 _rtl_pci_init_trx_var(hw);
1175
1176
1177 mac->beacon_interval = 100;
1178
1179
1180 mac->min_space_cfg = 0;
1181 mac->max_mss_density = 0;
1182
1183 mac->current_ampdu_density = 7;
1184 mac->current_ampdu_factor = 3;
1185
1186
1187 mac->retry_short = 7;
1188 mac->retry_long = 7;
1189
1190
1191 rtlpci->acm_method = EACMWAY2_SW;
1192
1193
1194 tasklet_init(&rtlpriv->works.irq_tasklet,
1195 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1196 (unsigned long)hw);
1197 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1198 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1199 (unsigned long)hw);
1200 INIT_WORK(&rtlpriv->works.lps_change_work,
1201 rtl_lps_change_work_callback);
1202}
1203
1204static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1205 unsigned int prio, unsigned int entries)
1206{
1207 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1208 struct rtl_priv *rtlpriv = rtl_priv(hw);
1209 struct rtl_tx_buffer_desc *buffer_desc;
1210 struct rtl_tx_desc *desc;
1211 dma_addr_t buffer_desc_dma, desc_dma;
1212 u32 nextdescaddress;
1213 int i;
1214
1215
1216 if (rtlpriv->use_new_trx_flow) {
1217 buffer_desc =
1218 pci_zalloc_consistent(rtlpci->pdev,
1219 sizeof(*buffer_desc) * entries,
1220 &buffer_desc_dma);
1221
1222 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1223 pr_err("Cannot allocate TX ring (prio = %d)\n",
1224 prio);
1225 return -ENOMEM;
1226 }
1227
1228 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1229 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1230
1231 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1232 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1233 }
1234
1235
1236 desc = pci_zalloc_consistent(rtlpci->pdev,
1237 sizeof(*desc) * entries, &desc_dma);
1238
1239 if (!desc || (unsigned long)desc & 0xFF) {
1240 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1241 return -ENOMEM;
1242 }
1243
1244 rtlpci->tx_ring[prio].desc = desc;
1245 rtlpci->tx_ring[prio].dma = desc_dma;
1246
1247 rtlpci->tx_ring[prio].idx = 0;
1248 rtlpci->tx_ring[prio].entries = entries;
1249 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1250
1251 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1252 prio, desc);
1253
1254
1255 if (!rtlpriv->use_new_trx_flow) {
1256 for (i = 0; i < entries; i++) {
1257 nextdescaddress = (u32)desc_dma +
1258 ((i + 1) % entries) *
1259 sizeof(*desc);
1260
1261 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1262 true,
1263 HW_DESC_TX_NEXTDESC_ADDR,
1264 (u8 *)&nextdescaddress);
1265 }
1266 }
1267 return 0;
1268}
1269
1270static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1271{
1272 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1273 struct rtl_priv *rtlpriv = rtl_priv(hw);
1274 int i;
1275
1276 if (rtlpriv->use_new_trx_flow) {
1277 struct rtl_rx_buffer_desc *entry = NULL;
1278
1279 rtlpci->rx_ring[rxring_idx].buffer_desc =
1280 pci_zalloc_consistent(rtlpci->pdev,
1281 sizeof(*rtlpci->rx_ring[rxring_idx].
1282 buffer_desc) *
1283 rtlpci->rxringcount,
1284 &rtlpci->rx_ring[rxring_idx].dma);
1285 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1286 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1287 pr_err("Cannot allocate RX ring\n");
1288 return -ENOMEM;
1289 }
1290
1291
1292 rtlpci->rx_ring[rxring_idx].idx = 0;
1293 for (i = 0; i < rtlpci->rxringcount; i++) {
1294 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1295 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1296 rxring_idx, i))
1297 return -ENOMEM;
1298 }
1299 } else {
1300 struct rtl_rx_desc *entry = NULL;
1301 u8 tmp_one = 1;
1302
1303 rtlpci->rx_ring[rxring_idx].desc =
1304 pci_zalloc_consistent(rtlpci->pdev,
1305 sizeof(*rtlpci->rx_ring[rxring_idx].
1306 desc) * rtlpci->rxringcount,
1307 &rtlpci->rx_ring[rxring_idx].dma);
1308 if (!rtlpci->rx_ring[rxring_idx].desc ||
1309 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1310 pr_err("Cannot allocate RX ring\n");
1311 return -ENOMEM;
1312 }
1313
1314
1315 rtlpci->rx_ring[rxring_idx].idx = 0;
1316
1317 for (i = 0; i < rtlpci->rxringcount; i++) {
1318 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1319 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1320 rxring_idx, i))
1321 return -ENOMEM;
1322 }
1323
1324 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1325 HW_DESC_RXERO, &tmp_one);
1326 }
1327 return 0;
1328}
1329
1330static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1331 unsigned int prio)
1332{
1333 struct rtl_priv *rtlpriv = rtl_priv(hw);
1334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1335 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1336
1337
1338 while (skb_queue_len(&ring->queue)) {
1339 u8 *entry;
1340 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1341
1342 if (rtlpriv->use_new_trx_flow)
1343 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1344 else
1345 entry = (u8 *)(&ring->desc[ring->idx]);
1346
1347 pci_unmap_single(rtlpci->pdev,
1348 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1349 true,
1350 HW_DESC_TXBUFF_ADDR),
1351 skb->len, PCI_DMA_TODEVICE);
1352 kfree_skb(skb);
1353 ring->idx = (ring->idx + 1) % ring->entries;
1354 }
1355
1356
1357 pci_free_consistent(rtlpci->pdev,
1358 sizeof(*ring->desc) * ring->entries,
1359 ring->desc, ring->dma);
1360 ring->desc = NULL;
1361 if (rtlpriv->use_new_trx_flow) {
1362 pci_free_consistent(rtlpci->pdev,
1363 sizeof(*ring->buffer_desc) * ring->entries,
1364 ring->buffer_desc, ring->buffer_desc_dma);
1365 ring->buffer_desc = NULL;
1366 }
1367}
1368
1369static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1370{
1371 struct rtl_priv *rtlpriv = rtl_priv(hw);
1372 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1373 int i;
1374
1375
1376 for (i = 0; i < rtlpci->rxringcount; i++) {
1377 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1378
1379 if (!skb)
1380 continue;
1381 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1382 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1383 kfree_skb(skb);
1384 }
1385
1386
1387 if (rtlpriv->use_new_trx_flow) {
1388 pci_free_consistent(rtlpci->pdev,
1389 sizeof(*rtlpci->rx_ring[rxring_idx].
1390 buffer_desc) * rtlpci->rxringcount,
1391 rtlpci->rx_ring[rxring_idx].buffer_desc,
1392 rtlpci->rx_ring[rxring_idx].dma);
1393 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1394 } else {
1395 pci_free_consistent(rtlpci->pdev,
1396 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1397 rtlpci->rxringcount,
1398 rtlpci->rx_ring[rxring_idx].desc,
1399 rtlpci->rx_ring[rxring_idx].dma);
1400 rtlpci->rx_ring[rxring_idx].desc = NULL;
1401 }
1402}
1403
1404static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1405{
1406 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1407 int ret;
1408 int i, rxring_idx;
1409
1410
1411
1412
1413 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1414 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1415 if (ret)
1416 return ret;
1417 }
1418
1419 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1420 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1421 if (ret)
1422 goto err_free_rings;
1423 }
1424
1425 return 0;
1426
1427err_free_rings:
1428 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1429 _rtl_pci_free_rx_ring(hw, rxring_idx);
1430
1431 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1432 if (rtlpci->tx_ring[i].desc ||
1433 rtlpci->tx_ring[i].buffer_desc)
1434 _rtl_pci_free_tx_ring(hw, i);
1435
1436 return 1;
1437}
1438
1439static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1440{
1441 u32 i, rxring_idx;
1442
1443
1444 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1445 _rtl_pci_free_rx_ring(hw, rxring_idx);
1446
1447
1448 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1449 _rtl_pci_free_tx_ring(hw, i);
1450
1451 return 0;
1452}
1453
1454int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1455{
1456 struct rtl_priv *rtlpriv = rtl_priv(hw);
1457 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1458 int i, rxring_idx;
1459 unsigned long flags;
1460 u8 tmp_one = 1;
1461 u32 bufferaddress;
1462
1463
1464 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1465
1466
1467
1468
1469 if (!rtlpriv->use_new_trx_flow &&
1470 rtlpci->rx_ring[rxring_idx].desc) {
1471 struct rtl_rx_desc *entry = NULL;
1472
1473 rtlpci->rx_ring[rxring_idx].idx = 0;
1474 for (i = 0; i < rtlpci->rxringcount; i++) {
1475 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1476 bufferaddress =
1477 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1478 false, HW_DESC_RXBUFF_ADDR);
1479 memset((u8 *)entry, 0,
1480 sizeof(*rtlpci->rx_ring
1481 [rxring_idx].desc));
1482 if (rtlpriv->use_new_trx_flow) {
1483 rtlpriv->cfg->ops->set_desc(hw,
1484 (u8 *)entry, false,
1485 HW_DESC_RX_PREPARE,
1486 (u8 *)&bufferaddress);
1487 } else {
1488 rtlpriv->cfg->ops->set_desc(hw,
1489 (u8 *)entry, false,
1490 HW_DESC_RXBUFF_ADDR,
1491 (u8 *)&bufferaddress);
1492 rtlpriv->cfg->ops->set_desc(hw,
1493 (u8 *)entry, false,
1494 HW_DESC_RXPKT_LEN,
1495 (u8 *)&rtlpci->rxbuffersize);
1496 rtlpriv->cfg->ops->set_desc(hw,
1497 (u8 *)entry, false,
1498 HW_DESC_RXOWN,
1499 (u8 *)&tmp_one);
1500 }
1501 }
1502 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1503 HW_DESC_RXERO, (u8 *)&tmp_one);
1504 }
1505 rtlpci->rx_ring[rxring_idx].idx = 0;
1506 }
1507
1508
1509
1510
1511 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1512 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1513 if (rtlpci->tx_ring[i].desc ||
1514 rtlpci->tx_ring[i].buffer_desc) {
1515 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1516
1517 while (skb_queue_len(&ring->queue)) {
1518 u8 *entry;
1519 struct sk_buff *skb =
1520 __skb_dequeue(&ring->queue);
1521 if (rtlpriv->use_new_trx_flow)
1522 entry = (u8 *)(&ring->buffer_desc
1523 [ring->idx]);
1524 else
1525 entry = (u8 *)(&ring->desc[ring->idx]);
1526
1527 pci_unmap_single(rtlpci->pdev,
1528 rtlpriv->cfg->ops->
1529 get_desc(hw, (u8 *)
1530 entry,
1531 true,
1532 HW_DESC_TXBUFF_ADDR),
1533 skb->len, PCI_DMA_TODEVICE);
1534 dev_kfree_skb_irq(skb);
1535 ring->idx = (ring->idx + 1) % ring->entries;
1536 }
1537
1538 if (rtlpriv->use_new_trx_flow) {
1539 rtlpci->tx_ring[i].cur_tx_rp = 0;
1540 rtlpci->tx_ring[i].cur_tx_wp = 0;
1541 }
1542
1543 ring->idx = 0;
1544 ring->entries = rtlpci->txringcount[i];
1545 }
1546 }
1547 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1548
1549 return 0;
1550}
1551
1552static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1553 struct ieee80211_sta *sta,
1554 struct sk_buff *skb)
1555{
1556 struct rtl_priv *rtlpriv = rtl_priv(hw);
1557 struct rtl_sta_info *sta_entry = NULL;
1558 u8 tid = rtl_get_tid(skb);
1559 __le16 fc = rtl_get_fc(skb);
1560
1561 if (!sta)
1562 return false;
1563 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1564
1565 if (!rtlpriv->rtlhal.earlymode_enable)
1566 return false;
1567 if (ieee80211_is_nullfunc(fc))
1568 return false;
1569 if (ieee80211_is_qos_nullfunc(fc))
1570 return false;
1571 if (ieee80211_is_pspoll(fc))
1572 return false;
1573 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1574 return false;
1575 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1576 return false;
1577 if (tid > 7)
1578 return false;
1579
1580
1581 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1582 return false;
1583
1584 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1585 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1586 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1587
1588 return true;
1589}
1590
1591static int rtl_pci_tx(struct ieee80211_hw *hw,
1592 struct ieee80211_sta *sta,
1593 struct sk_buff *skb,
1594 struct rtl_tcb_desc *ptcb_desc)
1595{
1596 struct rtl_priv *rtlpriv = rtl_priv(hw);
1597 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1598 struct rtl8192_tx_ring *ring;
1599 struct rtl_tx_desc *pdesc;
1600 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1601 u16 idx;
1602 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1603 unsigned long flags;
1604 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1605 __le16 fc = rtl_get_fc(skb);
1606 u8 *pda_addr = hdr->addr1;
1607 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1608 u8 own;
1609 u8 temp_one = 1;
1610
1611 if (ieee80211_is_mgmt(fc))
1612 rtl_tx_mgmt_proc(hw, skb);
1613
1614 if (rtlpriv->psc.sw_ps_enabled) {
1615 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1616 !ieee80211_has_pm(fc))
1617 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1618 }
1619
1620 rtl_action_proc(hw, skb, true);
1621
1622 if (is_multicast_ether_addr(pda_addr))
1623 rtlpriv->stats.txbytesmulticast += skb->len;
1624 else if (is_broadcast_ether_addr(pda_addr))
1625 rtlpriv->stats.txbytesbroadcast += skb->len;
1626 else
1627 rtlpriv->stats.txbytesunicast += skb->len;
1628
1629 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1630 ring = &rtlpci->tx_ring[hw_queue];
1631 if (hw_queue != BEACON_QUEUE) {
1632 if (rtlpriv->use_new_trx_flow)
1633 idx = ring->cur_tx_wp;
1634 else
1635 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1636 ring->entries;
1637 } else {
1638 idx = 0;
1639 }
1640
1641 pdesc = &ring->desc[idx];
1642 if (rtlpriv->use_new_trx_flow) {
1643 ptx_bd_desc = &ring->buffer_desc[idx];
1644 } else {
1645 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1646 true, HW_DESC_OWN);
1647
1648 if (own == 1 && hw_queue != BEACON_QUEUE) {
1649 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1650 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1651 hw_queue, ring->idx, idx,
1652 skb_queue_len(&ring->queue));
1653
1654 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1655 flags);
1656 return skb->len;
1657 }
1658 }
1659
1660 if (rtlpriv->cfg->ops->get_available_desc &&
1661 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1662 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1663 "get_available_desc fail\n");
1664 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1665 return skb->len;
1666 }
1667
1668 if (ieee80211_is_data(fc))
1669 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1670
1671 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1672 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1673
1674 __skb_queue_tail(&ring->queue, skb);
1675
1676 if (rtlpriv->use_new_trx_flow) {
1677 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1678 HW_DESC_OWN, &hw_queue);
1679 } else {
1680 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1681 HW_DESC_OWN, &temp_one);
1682 }
1683
1684 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1685 hw_queue != BEACON_QUEUE) {
1686 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1687 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1688 hw_queue, ring->idx, idx,
1689 skb_queue_len(&ring->queue));
1690
1691 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1692 }
1693
1694 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1695
1696 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1697
1698 return 0;
1699}
1700
1701static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1702{
1703 struct rtl_priv *rtlpriv = rtl_priv(hw);
1704 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1705 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1706 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1707 u16 i = 0;
1708 int queue_id;
1709 struct rtl8192_tx_ring *ring;
1710
1711 if (mac->skip_scan)
1712 return;
1713
1714 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1715 u32 queue_len;
1716
1717 if (((queues >> queue_id) & 0x1) == 0) {
1718 queue_id--;
1719 continue;
1720 }
1721 ring = &pcipriv->dev.tx_ring[queue_id];
1722 queue_len = skb_queue_len(&ring->queue);
1723 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1724 queue_id == TXCMD_QUEUE) {
1725 queue_id--;
1726 continue;
1727 } else {
1728 msleep(20);
1729 i++;
1730 }
1731
1732
1733 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1734 is_hal_stop(rtlhal) || i >= 200)
1735 return;
1736 }
1737}
1738
1739static void rtl_pci_deinit(struct ieee80211_hw *hw)
1740{
1741 struct rtl_priv *rtlpriv = rtl_priv(hw);
1742 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1743
1744 _rtl_pci_deinit_trx_ring(hw);
1745
1746 synchronize_irq(rtlpci->pdev->irq);
1747 tasklet_kill(&rtlpriv->works.irq_tasklet);
1748 cancel_work_sync(&rtlpriv->works.lps_change_work);
1749
1750 flush_workqueue(rtlpriv->works.rtl_wq);
1751 destroy_workqueue(rtlpriv->works.rtl_wq);
1752}
1753
1754static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1755{
1756 int err;
1757
1758 _rtl_pci_init_struct(hw, pdev);
1759
1760 err = _rtl_pci_init_trx_ring(hw);
1761 if (err) {
1762 pr_err("tx ring initialization failed\n");
1763 return err;
1764 }
1765
1766 return 0;
1767}
1768
1769static int rtl_pci_start(struct ieee80211_hw *hw)
1770{
1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1772 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1773 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1774 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1775 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1776 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1777
1778 int err;
1779
1780 rtl_pci_reset_trx_ring(hw);
1781
1782 rtlpci->driver_is_goingto_unload = false;
1783 if (rtlpriv->cfg->ops->get_btc_status &&
1784 rtlpriv->cfg->ops->get_btc_status()) {
1785 rtlpriv->btcoexist.btc_info.ap_num = 36;
1786 btc_ops->btc_init_variables(rtlpriv);
1787 btc_ops->btc_init_hal_vars(rtlpriv);
1788 } else if (btc_ops) {
1789 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1790 }
1791
1792 err = rtlpriv->cfg->ops->hw_init(hw);
1793 if (err) {
1794 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1795 "Failed to config hardware!\n");
1796 return err;
1797 }
1798 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1799 &rtlmac->retry_long);
1800
1801 rtlpriv->cfg->ops->enable_interrupt(hw);
1802 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1803
1804 rtl_init_rx_config(hw);
1805
1806
1807 set_hal_start(rtlhal);
1808
1809 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1810
1811 rtlpci->up_first_time = false;
1812
1813 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1814 return 0;
1815}
1816
1817static void rtl_pci_stop(struct ieee80211_hw *hw)
1818{
1819 struct rtl_priv *rtlpriv = rtl_priv(hw);
1820 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1821 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1822 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1823 unsigned long flags;
1824 u8 rf_timeout = 0;
1825
1826 if (rtlpriv->cfg->ops->get_btc_status())
1827 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1828
1829 if (rtlpriv->btcoexist.btc_ops)
1830 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1831
1832
1833
1834
1835 set_hal_stop(rtlhal);
1836
1837 rtlpci->driver_is_goingto_unload = true;
1838 rtlpriv->cfg->ops->disable_interrupt(hw);
1839 cancel_work_sync(&rtlpriv->works.lps_change_work);
1840
1841 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1842 while (ppsc->rfchange_inprogress) {
1843 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1844 if (rf_timeout > 100) {
1845 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1846 break;
1847 }
1848 mdelay(1);
1849 rf_timeout++;
1850 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1851 }
1852 ppsc->rfchange_inprogress = true;
1853 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1854
1855 rtlpriv->cfg->ops->hw_disable(hw);
1856
1857 if (!rtlpriv->max_fw_size)
1858 return;
1859 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1860
1861 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1862 ppsc->rfchange_inprogress = false;
1863 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1864
1865 rtl_pci_enable_aspm(hw);
1866}
1867
1868static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1869 struct ieee80211_hw *hw)
1870{
1871 struct rtl_priv *rtlpriv = rtl_priv(hw);
1872 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1873 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1874 struct pci_dev *bridge_pdev = pdev->bus->self;
1875 u16 venderid;
1876 u16 deviceid;
1877 u8 revisionid;
1878 u16 irqline;
1879 u8 tmp;
1880
1881 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1882 venderid = pdev->vendor;
1883 deviceid = pdev->device;
1884 pci_read_config_byte(pdev, 0x8, &revisionid);
1885 pci_read_config_word(pdev, 0x3C, &irqline);
1886
1887
1888
1889
1890
1891
1892
1893 if (deviceid == RTL_PCI_8192SE_DID &&
1894 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1895 return false;
1896
1897 if (deviceid == RTL_PCI_8192_DID ||
1898 deviceid == RTL_PCI_0044_DID ||
1899 deviceid == RTL_PCI_0047_DID ||
1900 deviceid == RTL_PCI_8192SE_DID ||
1901 deviceid == RTL_PCI_8174_DID ||
1902 deviceid == RTL_PCI_8173_DID ||
1903 deviceid == RTL_PCI_8172_DID ||
1904 deviceid == RTL_PCI_8171_DID) {
1905 switch (revisionid) {
1906 case RTL_PCI_REVISION_ID_8192PCIE:
1907 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1908 "8192 PCI-E is found - vid/did=%x/%x\n",
1909 venderid, deviceid);
1910 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1911 return false;
1912 case RTL_PCI_REVISION_ID_8192SE:
1913 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1914 "8192SE is found - vid/did=%x/%x\n",
1915 venderid, deviceid);
1916 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1917 break;
1918 default:
1919 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1920 "Err: Unknown device - vid/did=%x/%x\n",
1921 venderid, deviceid);
1922 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1923 break;
1924 }
1925 } else if (deviceid == RTL_PCI_8723AE_DID) {
1926 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1927 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1928 "8723AE PCI-E is found - vid/did=%x/%x\n",
1929 venderid, deviceid);
1930 } else if (deviceid == RTL_PCI_8192CET_DID ||
1931 deviceid == RTL_PCI_8192CE_DID ||
1932 deviceid == RTL_PCI_8191CE_DID ||
1933 deviceid == RTL_PCI_8188CE_DID) {
1934 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1935 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1936 "8192C PCI-E is found - vid/did=%x/%x\n",
1937 venderid, deviceid);
1938 } else if (deviceid == RTL_PCI_8192DE_DID ||
1939 deviceid == RTL_PCI_8192DE_DID2) {
1940 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1941 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1942 "8192D PCI-E is found - vid/did=%x/%x\n",
1943 venderid, deviceid);
1944 } else if (deviceid == RTL_PCI_8188EE_DID) {
1945 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1946 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1947 "Find adapter, Hardware type is 8188EE\n");
1948 } else if (deviceid == RTL_PCI_8723BE_DID) {
1949 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1950 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1951 "Find adapter, Hardware type is 8723BE\n");
1952 } else if (deviceid == RTL_PCI_8192EE_DID) {
1953 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1954 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1955 "Find adapter, Hardware type is 8192EE\n");
1956 } else if (deviceid == RTL_PCI_8821AE_DID) {
1957 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1958 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1959 "Find adapter, Hardware type is 8821AE\n");
1960 } else if (deviceid == RTL_PCI_8812AE_DID) {
1961 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1962 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1963 "Find adapter, Hardware type is 8812AE\n");
1964 } else if (deviceid == RTL_PCI_8822BE_DID) {
1965 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1966 rtlhal->bandset = BAND_ON_BOTH;
1967 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1968 "Find adapter, Hardware type is 8822BE\n");
1969 } else {
1970 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1971 "Err: Unknown device - vid/did=%x/%x\n",
1972 venderid, deviceid);
1973
1974 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1975 }
1976
1977 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1978 if (revisionid == 0 || revisionid == 1) {
1979 if (revisionid == 0) {
1980 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1981 "Find 92DE MAC0\n");
1982 rtlhal->interfaceindex = 0;
1983 } else if (revisionid == 1) {
1984 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1985 "Find 92DE MAC1\n");
1986 rtlhal->interfaceindex = 1;
1987 }
1988 } else {
1989 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1990 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1991 venderid, deviceid, revisionid);
1992 rtlhal->interfaceindex = 0;
1993 }
1994 }
1995
1996 switch (rtlhal->hw_type) {
1997 case HARDWARE_TYPE_RTL8192EE:
1998 case HARDWARE_TYPE_RTL8822BE:
1999
2000 rtlpriv->use_new_trx_flow = true;
2001 break;
2002
2003 default:
2004 rtlpriv->use_new_trx_flow = false;
2005 break;
2006 }
2007
2008
2009 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2010 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2011 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2012
2013
2014 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2015
2016
2017
2018 if (bridge_pdev) {
2019
2020 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2021 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2022 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2023 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2024 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2025 "Pci Bridge Vendor is found index: %d\n",
2026 tmp);
2027 break;
2028 }
2029 }
2030 }
2031
2032 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2033 PCI_BRIDGE_VENDOR_UNKNOWN) {
2034 pcipriv->ndis_adapter.pcibridge_busnum =
2035 bridge_pdev->bus->number;
2036 pcipriv->ndis_adapter.pcibridge_devnum =
2037 PCI_SLOT(bridge_pdev->devfn);
2038 pcipriv->ndis_adapter.pcibridge_funcnum =
2039 PCI_FUNC(bridge_pdev->devfn);
2040 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2041 pci_pcie_cap(bridge_pdev);
2042 pcipriv->ndis_adapter.num4bytes =
2043 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2044
2045 rtl_pci_get_linkcontrol_field(hw);
2046
2047 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2048 PCI_BRIDGE_VENDOR_AMD) {
2049 pcipriv->ndis_adapter.amd_l1_patch =
2050 rtl_pci_get_amd_l1_patch(hw);
2051 }
2052 }
2053
2054 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2055 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2056 pcipriv->ndis_adapter.busnumber,
2057 pcipriv->ndis_adapter.devnumber,
2058 pcipriv->ndis_adapter.funcnumber,
2059 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2060
2061 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2062 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2063 pcipriv->ndis_adapter.pcibridge_busnum,
2064 pcipriv->ndis_adapter.pcibridge_devnum,
2065 pcipriv->ndis_adapter.pcibridge_funcnum,
2066 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2067 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2068 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2069 pcipriv->ndis_adapter.amd_l1_patch);
2070
2071 rtl_pci_parse_configuration(pdev, hw);
2072 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2073
2074 return true;
2075}
2076
2077static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2078{
2079 struct rtl_priv *rtlpriv = rtl_priv(hw);
2080 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2081 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2082 int ret;
2083
2084 ret = pci_enable_msi(rtlpci->pdev);
2085 if (ret < 0)
2086 return ret;
2087
2088 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2089 IRQF_SHARED, KBUILD_MODNAME, hw);
2090 if (ret < 0) {
2091 pci_disable_msi(rtlpci->pdev);
2092 return ret;
2093 }
2094
2095 rtlpci->using_msi = true;
2096
2097 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2098 "MSI Interrupt Mode!\n");
2099 return 0;
2100}
2101
2102static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2103{
2104 struct rtl_priv *rtlpriv = rtl_priv(hw);
2105 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2106 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2107 int ret;
2108
2109 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2110 IRQF_SHARED, KBUILD_MODNAME, hw);
2111 if (ret < 0)
2112 return ret;
2113
2114 rtlpci->using_msi = false;
2115 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2116 "Pin-based Interrupt Mode!\n");
2117 return 0;
2118}
2119
2120static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2121{
2122 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2123 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2124 int ret;
2125
2126 if (rtlpci->msi_support) {
2127 ret = rtl_pci_intr_mode_msi(hw);
2128 if (ret < 0)
2129 ret = rtl_pci_intr_mode_legacy(hw);
2130 } else {
2131 ret = rtl_pci_intr_mode_legacy(hw);
2132 }
2133 return ret;
2134}
2135
2136static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2137{
2138 u8 value;
2139
2140 pci_read_config_byte(pdev, 0x719, &value);
2141
2142
2143 if (dma64)
2144 value |= BIT(5);
2145 else
2146 value &= ~BIT(5);
2147
2148 pci_write_config_byte(pdev, 0x719, value);
2149}
2150
2151int rtl_pci_probe(struct pci_dev *pdev,
2152 const struct pci_device_id *id)
2153{
2154 struct ieee80211_hw *hw = NULL;
2155
2156 struct rtl_priv *rtlpriv = NULL;
2157 struct rtl_pci_priv *pcipriv = NULL;
2158 struct rtl_pci *rtlpci;
2159 unsigned long pmem_start, pmem_len, pmem_flags;
2160 int err;
2161
2162 err = pci_enable_device(pdev);
2163 if (err) {
2164 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2165 pci_name(pdev));
2166 return err;
2167 }
2168
2169 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2170 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2171 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2172 WARN_ONCE(true,
2173 "Unable to obtain 64bit DMA for consistent allocations\n");
2174 err = -ENOMEM;
2175 goto fail1;
2176 }
2177
2178 platform_enable_dma64(pdev, true);
2179 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2180 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2181 WARN_ONCE(true,
2182 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2183 err = -ENOMEM;
2184 goto fail1;
2185 }
2186
2187 platform_enable_dma64(pdev, false);
2188 }
2189
2190 pci_set_master(pdev);
2191
2192 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2193 sizeof(struct rtl_priv), &rtl_ops);
2194 if (!hw) {
2195 WARN_ONCE(true,
2196 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2197 err = -ENOMEM;
2198 goto fail1;
2199 }
2200
2201 SET_IEEE80211_DEV(hw, &pdev->dev);
2202 pci_set_drvdata(pdev, hw);
2203
2204 rtlpriv = hw->priv;
2205 rtlpriv->hw = hw;
2206 pcipriv = (void *)rtlpriv->priv;
2207 pcipriv->dev.pdev = pdev;
2208 init_completion(&rtlpriv->firmware_loading_complete);
2209
2210 rtlpriv->proximity.proxim_on = false;
2211
2212 pcipriv = (void *)rtlpriv->priv;
2213 pcipriv->dev.pdev = pdev;
2214
2215
2216 rtlpriv->rtlhal.interface = INTF_PCI;
2217 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2218 rtlpriv->intf_ops = &rtl_pci_ops;
2219 rtlpriv->glb_var = &rtl_global_var;
2220 rtl_efuse_ops_init(hw);
2221
2222
2223 err = pci_request_regions(pdev, KBUILD_MODNAME);
2224 if (err) {
2225 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2226 goto fail1;
2227 }
2228
2229 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2230 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2231 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2232
2233
2234 rtlpriv->io.pci_mem_start =
2235 (unsigned long)pci_iomap(pdev,
2236 rtlpriv->cfg->bar_id, pmem_len);
2237 if (rtlpriv->io.pci_mem_start == 0) {
2238 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2239 err = -ENOMEM;
2240 goto fail2;
2241 }
2242
2243 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2244 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2245 pmem_start, pmem_len, pmem_flags,
2246 rtlpriv->io.pci_mem_start);
2247
2248
2249 pci_write_config_byte(pdev, 0x81, 0);
2250
2251 pci_write_config_byte(pdev, 0x44, 0);
2252 pci_write_config_byte(pdev, 0x04, 0x06);
2253 pci_write_config_byte(pdev, 0x04, 0x07);
2254
2255
2256 if (!_rtl_pci_find_adapter(pdev, hw)) {
2257 err = -ENODEV;
2258 goto fail2;
2259 }
2260
2261
2262 _rtl_pci_io_handler_init(&pdev->dev, hw);
2263
2264
2265 rtlpriv->cfg->ops->read_eeprom_info(hw);
2266
2267 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2268 pr_err("Can't init_sw_vars\n");
2269 err = -ENODEV;
2270 goto fail3;
2271 }
2272 rtlpriv->cfg->ops->init_sw_leds(hw);
2273
2274
2275 rtl_pci_init_aspm(hw);
2276
2277
2278 err = rtl_init_core(hw);
2279 if (err) {
2280 pr_err("Can't allocate sw for mac80211\n");
2281 goto fail3;
2282 }
2283
2284
2285 err = rtl_pci_init(hw, pdev);
2286 if (err) {
2287 pr_err("Failed to init PCI\n");
2288 goto fail3;
2289 }
2290
2291 err = ieee80211_register_hw(hw);
2292 if (err) {
2293 pr_err("Can't register mac80211 hw.\n");
2294 err = -ENODEV;
2295 goto fail3;
2296 }
2297 rtlpriv->mac80211.mac80211_registered = 1;
2298
2299
2300 rtl_debug_add_one(hw);
2301
2302
2303 rtl_init_rfkill(hw);
2304
2305 rtlpci = rtl_pcidev(pcipriv);
2306 err = rtl_pci_intr_mode_decide(hw);
2307 if (err) {
2308 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2309 "%s: failed to register IRQ handler\n",
2310 wiphy_name(hw->wiphy));
2311 goto fail3;
2312 }
2313 rtlpci->irq_alloc = 1;
2314
2315 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2316 return 0;
2317
2318fail3:
2319 pci_set_drvdata(pdev, NULL);
2320 rtl_deinit_core(hw);
2321
2322fail2:
2323 if (rtlpriv->io.pci_mem_start != 0)
2324 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2325
2326 pci_release_regions(pdev);
2327 complete(&rtlpriv->firmware_loading_complete);
2328
2329fail1:
2330 if (hw)
2331 ieee80211_free_hw(hw);
2332 pci_disable_device(pdev);
2333
2334 return err;
2335}
2336EXPORT_SYMBOL(rtl_pci_probe);
2337
2338void rtl_pci_disconnect(struct pci_dev *pdev)
2339{
2340 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2341 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2342 struct rtl_priv *rtlpriv = rtl_priv(hw);
2343 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2344 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2345
2346
2347 wait_for_completion(&rtlpriv->firmware_loading_complete);
2348 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2349
2350
2351 rtl_debug_remove_one(hw);
2352
2353
2354 if (rtlmac->mac80211_registered == 1) {
2355 ieee80211_unregister_hw(hw);
2356 rtlmac->mac80211_registered = 0;
2357 } else {
2358 rtl_deinit_deferred_work(hw, false);
2359 rtlpriv->intf_ops->adapter_stop(hw);
2360 }
2361 rtlpriv->cfg->ops->disable_interrupt(hw);
2362
2363
2364 rtl_deinit_rfkill(hw);
2365
2366 rtl_pci_deinit(hw);
2367 rtl_deinit_core(hw);
2368 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2369
2370 if (rtlpci->irq_alloc) {
2371 free_irq(rtlpci->pdev->irq, hw);
2372 rtlpci->irq_alloc = 0;
2373 }
2374
2375 if (rtlpci->using_msi)
2376 pci_disable_msi(rtlpci->pdev);
2377
2378 list_del(&rtlpriv->list);
2379 if (rtlpriv->io.pci_mem_start != 0) {
2380 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2381 pci_release_regions(pdev);
2382 }
2383
2384 pci_disable_device(pdev);
2385
2386 rtl_pci_disable_aspm(hw);
2387
2388 pci_set_drvdata(pdev, NULL);
2389
2390 ieee80211_free_hw(hw);
2391}
2392EXPORT_SYMBOL(rtl_pci_disconnect);
2393
2394#ifdef CONFIG_PM_SLEEP
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410int rtl_pci_suspend(struct device *dev)
2411{
2412 struct pci_dev *pdev = to_pci_dev(dev);
2413 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2414 struct rtl_priv *rtlpriv = rtl_priv(hw);
2415
2416 rtlpriv->cfg->ops->hw_suspend(hw);
2417 rtl_deinit_rfkill(hw);
2418
2419 return 0;
2420}
2421EXPORT_SYMBOL(rtl_pci_suspend);
2422
2423int rtl_pci_resume(struct device *dev)
2424{
2425 struct pci_dev *pdev = to_pci_dev(dev);
2426 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2427 struct rtl_priv *rtlpriv = rtl_priv(hw);
2428
2429 rtlpriv->cfg->ops->hw_resume(hw);
2430 rtl_init_rfkill(hw);
2431 return 0;
2432}
2433EXPORT_SYMBOL(rtl_pci_resume);
2434#endif
2435
2436const struct rtl_intf_ops rtl_pci_ops = {
2437 .read_efuse_byte = read_efuse_byte,
2438 .adapter_start = rtl_pci_start,
2439 .adapter_stop = rtl_pci_stop,
2440 .check_buddy_priv = rtl_pci_check_buddy_priv,
2441 .adapter_tx = rtl_pci_tx,
2442 .flush = rtl_pci_flush,
2443 .reset_trx_ring = rtl_pci_reset_trx_ring,
2444 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2445
2446 .disable_aspm = rtl_pci_disable_aspm,
2447 .enable_aspm = rtl_pci_enable_aspm,
2448};
2449
