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2
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4
5#ifndef __RTK_MAIN_H_
6#define __RTK_MAIN_H_
7
8#include <net/mac80211.h>
9#include <linux/vmalloc.h>
10#include <linux/firmware.h>
11#include <linux/average.h>
12#include <linux/bitops.h>
13#include <linux/bitfield.h>
14
15#include "util.h"
16
17#define RTW_MAX_MAC_ID_NUM 32
18#define RTW_MAX_SEC_CAM_NUM 32
19
20#define RTW_WATCH_DOG_DELAY_TIME round_jiffies_relative(HZ * 2)
21
22#define RFREG_MASK 0xfffff
23#define INV_RF_DATA 0xffffffff
24#define TX_PAGE_SIZE_SHIFT 7
25
26#define RTW_CHANNEL_WIDTH_MAX 3
27#define RTW_RF_PATH_MAX 4
28#define HW_FEATURE_LEN 13
29
30extern unsigned int rtw_debug_mask;
31extern const struct ieee80211_ops rtw_ops;
32extern struct rtw_chip_info rtw8822b_hw_spec;
33extern struct rtw_chip_info rtw8822c_hw_spec;
34
35#define RTW_MAX_CHANNEL_NUM_2G 14
36#define RTW_MAX_CHANNEL_NUM_5G 49
37
38struct rtw_dev;
39
40enum rtw_hci_type {
41 RTW_HCI_TYPE_PCIE,
42 RTW_HCI_TYPE_USB,
43 RTW_HCI_TYPE_SDIO,
44
45 RTW_HCI_TYPE_UNDEFINE,
46};
47
48struct rtw_hci {
49 struct rtw_hci_ops *ops;
50 enum rtw_hci_type type;
51
52 u32 rpwm_addr;
53
54 u8 bulkout_num;
55};
56
57enum rtw_supported_band {
58 RTW_BAND_2G = 1 << 0,
59 RTW_BAND_5G = 1 << 1,
60 RTW_BAND_60G = 1 << 2,
61
62 RTW_BAND_MAX,
63};
64
65enum rtw_bandwidth {
66 RTW_CHANNEL_WIDTH_20 = 0,
67 RTW_CHANNEL_WIDTH_40 = 1,
68 RTW_CHANNEL_WIDTH_80 = 2,
69 RTW_CHANNEL_WIDTH_160 = 3,
70 RTW_CHANNEL_WIDTH_80_80 = 4,
71 RTW_CHANNEL_WIDTH_5 = 5,
72 RTW_CHANNEL_WIDTH_10 = 6,
73};
74
75enum rtw_net_type {
76 RTW_NET_NO_LINK = 0,
77 RTW_NET_AD_HOC = 1,
78 RTW_NET_MGD_LINKED = 2,
79 RTW_NET_AP_MODE = 3,
80};
81
82enum rtw_rf_type {
83 RF_1T1R = 0,
84 RF_1T2R = 1,
85 RF_2T2R = 2,
86 RF_2T3R = 3,
87 RF_2T4R = 4,
88 RF_3T3R = 5,
89 RF_3T4R = 6,
90 RF_4T4R = 7,
91 RF_TYPE_MAX,
92};
93
94enum rtw_rf_path {
95 RF_PATH_A = 0,
96 RF_PATH_B = 1,
97 RF_PATH_C = 2,
98 RF_PATH_D = 3,
99};
100
101enum rtw_bb_path {
102 BB_PATH_A = BIT(0),
103 BB_PATH_B = BIT(1),
104 BB_PATH_C = BIT(2),
105 BB_PATH_D = BIT(3),
106
107 BB_PATH_AB = (BB_PATH_A | BB_PATH_B),
108 BB_PATH_AC = (BB_PATH_A | BB_PATH_C),
109 BB_PATH_AD = (BB_PATH_A | BB_PATH_D),
110 BB_PATH_BC = (BB_PATH_B | BB_PATH_C),
111 BB_PATH_BD = (BB_PATH_B | BB_PATH_D),
112 BB_PATH_CD = (BB_PATH_C | BB_PATH_D),
113
114 BB_PATH_ABC = (BB_PATH_A | BB_PATH_B | BB_PATH_C),
115 BB_PATH_ABD = (BB_PATH_A | BB_PATH_B | BB_PATH_D),
116 BB_PATH_ACD = (BB_PATH_A | BB_PATH_C | BB_PATH_D),
117 BB_PATH_BCD = (BB_PATH_B | BB_PATH_C | BB_PATH_D),
118
119 BB_PATH_ABCD = (BB_PATH_A | BB_PATH_B | BB_PATH_C | BB_PATH_D),
120};
121
122enum rtw_rate_section {
123 RTW_RATE_SECTION_CCK = 0,
124 RTW_RATE_SECTION_OFDM,
125 RTW_RATE_SECTION_HT_1S,
126 RTW_RATE_SECTION_HT_2S,
127 RTW_RATE_SECTION_VHT_1S,
128 RTW_RATE_SECTION_VHT_2S,
129
130
131 RTW_RATE_SECTION_MAX,
132};
133
134enum rtw_wireless_set {
135 WIRELESS_CCK = 0x00000001,
136 WIRELESS_OFDM = 0x00000002,
137 WIRELESS_HT = 0x00000004,
138 WIRELESS_VHT = 0x00000008,
139};
140
141#define HT_STBC_EN BIT(0)
142#define VHT_STBC_EN BIT(1)
143#define HT_LDPC_EN BIT(0)
144#define VHT_LDPC_EN BIT(1)
145
146enum rtw_chip_type {
147 RTW_CHIP_TYPE_8822B,
148 RTW_CHIP_TYPE_8822C,
149};
150
151enum rtw_tx_queue_type {
152
153 RTW_TX_QUEUE_BK = 0x0,
154 RTW_TX_QUEUE_BE = 0x1,
155 RTW_TX_QUEUE_VI = 0x2,
156 RTW_TX_QUEUE_VO = 0x3,
157
158 RTW_TX_QUEUE_BCN = 0x4,
159 RTW_TX_QUEUE_MGMT = 0x5,
160 RTW_TX_QUEUE_HI0 = 0x6,
161 RTW_TX_QUEUE_H2C = 0x7,
162
163 RTK_MAX_TX_QUEUE_NUM
164};
165
166enum rtw_rx_queue_type {
167 RTW_RX_QUEUE_MPDU = 0x0,
168 RTW_RX_QUEUE_C2H = 0x1,
169
170 RTK_MAX_RX_QUEUE_NUM
171};
172
173enum rtw_rate_index {
174 RTW_RATEID_BGN_40M_2SS = 0,
175 RTW_RATEID_BGN_40M_1SS = 1,
176 RTW_RATEID_BGN_20M_2SS = 2,
177 RTW_RATEID_BGN_20M_1SS = 3,
178 RTW_RATEID_GN_N2SS = 4,
179 RTW_RATEID_GN_N1SS = 5,
180 RTW_RATEID_BG = 6,
181 RTW_RATEID_G = 7,
182 RTW_RATEID_B_20M = 8,
183 RTW_RATEID_ARFR0_AC_2SS = 9,
184 RTW_RATEID_ARFR1_AC_1SS = 10,
185 RTW_RATEID_ARFR2_AC_2G_1SS = 11,
186 RTW_RATEID_ARFR3_AC_2G_2SS = 12,
187 RTW_RATEID_ARFR4_AC_3SS = 13,
188 RTW_RATEID_ARFR5_N_3SS = 14,
189 RTW_RATEID_ARFR7_N_4SS = 15,
190 RTW_RATEID_ARFR6_AC_4SS = 16
191};
192
193enum rtw_trx_desc_rate {
194 DESC_RATE1M = 0x00,
195 DESC_RATE2M = 0x01,
196 DESC_RATE5_5M = 0x02,
197 DESC_RATE11M = 0x03,
198
199 DESC_RATE6M = 0x04,
200 DESC_RATE9M = 0x05,
201 DESC_RATE12M = 0x06,
202 DESC_RATE18M = 0x07,
203 DESC_RATE24M = 0x08,
204 DESC_RATE36M = 0x09,
205 DESC_RATE48M = 0x0a,
206 DESC_RATE54M = 0x0b,
207
208 DESC_RATEMCS0 = 0x0c,
209 DESC_RATEMCS1 = 0x0d,
210 DESC_RATEMCS2 = 0x0e,
211 DESC_RATEMCS3 = 0x0f,
212 DESC_RATEMCS4 = 0x10,
213 DESC_RATEMCS5 = 0x11,
214 DESC_RATEMCS6 = 0x12,
215 DESC_RATEMCS7 = 0x13,
216 DESC_RATEMCS8 = 0x14,
217 DESC_RATEMCS9 = 0x15,
218 DESC_RATEMCS10 = 0x16,
219 DESC_RATEMCS11 = 0x17,
220 DESC_RATEMCS12 = 0x18,
221 DESC_RATEMCS13 = 0x19,
222 DESC_RATEMCS14 = 0x1a,
223 DESC_RATEMCS15 = 0x1b,
224 DESC_RATEMCS16 = 0x1c,
225 DESC_RATEMCS17 = 0x1d,
226 DESC_RATEMCS18 = 0x1e,
227 DESC_RATEMCS19 = 0x1f,
228 DESC_RATEMCS20 = 0x20,
229 DESC_RATEMCS21 = 0x21,
230 DESC_RATEMCS22 = 0x22,
231 DESC_RATEMCS23 = 0x23,
232 DESC_RATEMCS24 = 0x24,
233 DESC_RATEMCS25 = 0x25,
234 DESC_RATEMCS26 = 0x26,
235 DESC_RATEMCS27 = 0x27,
236 DESC_RATEMCS28 = 0x28,
237 DESC_RATEMCS29 = 0x29,
238 DESC_RATEMCS30 = 0x2a,
239 DESC_RATEMCS31 = 0x2b,
240
241 DESC_RATEVHT1SS_MCS0 = 0x2c,
242 DESC_RATEVHT1SS_MCS1 = 0x2d,
243 DESC_RATEVHT1SS_MCS2 = 0x2e,
244 DESC_RATEVHT1SS_MCS3 = 0x2f,
245 DESC_RATEVHT1SS_MCS4 = 0x30,
246 DESC_RATEVHT1SS_MCS5 = 0x31,
247 DESC_RATEVHT1SS_MCS6 = 0x32,
248 DESC_RATEVHT1SS_MCS7 = 0x33,
249 DESC_RATEVHT1SS_MCS8 = 0x34,
250 DESC_RATEVHT1SS_MCS9 = 0x35,
251
252 DESC_RATEVHT2SS_MCS0 = 0x36,
253 DESC_RATEVHT2SS_MCS1 = 0x37,
254 DESC_RATEVHT2SS_MCS2 = 0x38,
255 DESC_RATEVHT2SS_MCS3 = 0x39,
256 DESC_RATEVHT2SS_MCS4 = 0x3a,
257 DESC_RATEVHT2SS_MCS5 = 0x3b,
258 DESC_RATEVHT2SS_MCS6 = 0x3c,
259 DESC_RATEVHT2SS_MCS7 = 0x3d,
260 DESC_RATEVHT2SS_MCS8 = 0x3e,
261 DESC_RATEVHT2SS_MCS9 = 0x3f,
262
263 DESC_RATEVHT3SS_MCS0 = 0x40,
264 DESC_RATEVHT3SS_MCS1 = 0x41,
265 DESC_RATEVHT3SS_MCS2 = 0x42,
266 DESC_RATEVHT3SS_MCS3 = 0x43,
267 DESC_RATEVHT3SS_MCS4 = 0x44,
268 DESC_RATEVHT3SS_MCS5 = 0x45,
269 DESC_RATEVHT3SS_MCS6 = 0x46,
270 DESC_RATEVHT3SS_MCS7 = 0x47,
271 DESC_RATEVHT3SS_MCS8 = 0x48,
272 DESC_RATEVHT3SS_MCS9 = 0x49,
273
274 DESC_RATEVHT4SS_MCS0 = 0x4a,
275 DESC_RATEVHT4SS_MCS1 = 0x4b,
276 DESC_RATEVHT4SS_MCS2 = 0x4c,
277 DESC_RATEVHT4SS_MCS3 = 0x4d,
278 DESC_RATEVHT4SS_MCS4 = 0x4e,
279 DESC_RATEVHT4SS_MCS5 = 0x4f,
280 DESC_RATEVHT4SS_MCS6 = 0x50,
281 DESC_RATEVHT4SS_MCS7 = 0x51,
282 DESC_RATEVHT4SS_MCS8 = 0x52,
283 DESC_RATEVHT4SS_MCS9 = 0x53,
284
285 DESC_RATE_MAX,
286};
287
288enum rtw_regulatory_domains {
289 RTW_REGD_FCC = 0,
290 RTW_REGD_MKK = 1,
291 RTW_REGD_ETSI = 2,
292 RTW_REGD_WW = 3,
293
294 RTW_REGD_MAX
295};
296
297enum rtw_flags {
298 RTW_FLAG_RUNNING,
299 RTW_FLAG_FW_RUNNING,
300 RTW_FLAG_SCANNING,
301 RTW_FLAG_INACTIVE_PS,
302 RTW_FLAG_LEISURE_PS,
303 RTW_FLAG_DIG_DISABLE,
304
305 NUM_OF_RTW_FLAGS,
306};
307
308
309
310
311struct rtw_2g_1s_pwr_idx_diff {
312#ifdef __LITTLE_ENDIAN
313 s8 ofdm:4;
314 s8 bw20:4;
315#else
316 s8 bw20:4;
317 s8 ofdm:4;
318#endif
319} __packed;
320
321struct rtw_2g_ns_pwr_idx_diff {
322#ifdef __LITTLE_ENDIAN
323 s8 bw20:4;
324 s8 bw40:4;
325 s8 cck:4;
326 s8 ofdm:4;
327#else
328 s8 ofdm:4;
329 s8 cck:4;
330 s8 bw40:4;
331 s8 bw20:4;
332#endif
333} __packed;
334
335struct rtw_2g_txpwr_idx {
336 u8 cck_base[6];
337 u8 bw40_base[5];
338 struct rtw_2g_1s_pwr_idx_diff ht_1s_diff;
339 struct rtw_2g_ns_pwr_idx_diff ht_2s_diff;
340 struct rtw_2g_ns_pwr_idx_diff ht_3s_diff;
341 struct rtw_2g_ns_pwr_idx_diff ht_4s_diff;
342};
343
344struct rtw_5g_ht_1s_pwr_idx_diff {
345#ifdef __LITTLE_ENDIAN
346 s8 ofdm:4;
347 s8 bw20:4;
348#else
349 s8 bw20:4;
350 s8 ofdm:4;
351#endif
352} __packed;
353
354struct rtw_5g_ht_ns_pwr_idx_diff {
355#ifdef __LITTLE_ENDIAN
356 s8 bw20:4;
357 s8 bw40:4;
358#else
359 s8 bw40:4;
360 s8 bw20:4;
361#endif
362} __packed;
363
364struct rtw_5g_ofdm_ns_pwr_idx_diff {
365#ifdef __LITTLE_ENDIAN
366 s8 ofdm_3s:4;
367 s8 ofdm_2s:4;
368 s8 ofdm_4s:4;
369 s8 res:4;
370#else
371 s8 res:4;
372 s8 ofdm_4s:4;
373 s8 ofdm_2s:4;
374 s8 ofdm_3s:4;
375#endif
376} __packed;
377
378struct rtw_5g_vht_ns_pwr_idx_diff {
379#ifdef __LITTLE_ENDIAN
380 s8 bw160:4;
381 s8 bw80:4;
382#else
383 s8 bw80:4;
384 s8 bw160:4;
385#endif
386} __packed;
387
388struct rtw_5g_txpwr_idx {
389 u8 bw40_base[14];
390 struct rtw_5g_ht_1s_pwr_idx_diff ht_1s_diff;
391 struct rtw_5g_ht_ns_pwr_idx_diff ht_2s_diff;
392 struct rtw_5g_ht_ns_pwr_idx_diff ht_3s_diff;
393 struct rtw_5g_ht_ns_pwr_idx_diff ht_4s_diff;
394 struct rtw_5g_ofdm_ns_pwr_idx_diff ofdm_diff;
395 struct rtw_5g_vht_ns_pwr_idx_diff vht_1s_diff;
396 struct rtw_5g_vht_ns_pwr_idx_diff vht_2s_diff;
397 struct rtw_5g_vht_ns_pwr_idx_diff vht_3s_diff;
398 struct rtw_5g_vht_ns_pwr_idx_diff vht_4s_diff;
399};
400
401struct rtw_txpwr_idx {
402 struct rtw_2g_txpwr_idx pwr_idx_2g;
403 struct rtw_5g_txpwr_idx pwr_idx_5g;
404};
405
406struct rtw_timer_list {
407 struct timer_list timer;
408 void (*function)(void *data);
409 void *args;
410};
411
412struct rtw_channel_params {
413 u8 center_chan;
414 u8 bandwidth;
415 u8 primary_chan_idx;
416};
417
418struct rtw_hw_reg {
419 u32 addr;
420 u32 mask;
421};
422
423struct rtw_backup_info {
424 u8 len;
425 u32 reg;
426 u32 val;
427};
428
429enum rtw_vif_port_set {
430 PORT_SET_MAC_ADDR = BIT(0),
431 PORT_SET_BSSID = BIT(1),
432 PORT_SET_NET_TYPE = BIT(2),
433 PORT_SET_AID = BIT(3),
434};
435
436struct rtw_vif_port {
437 struct rtw_hw_reg mac_addr;
438 struct rtw_hw_reg bssid;
439 struct rtw_hw_reg net_type;
440 struct rtw_hw_reg aid;
441};
442
443struct rtw_tx_pkt_info {
444 u32 tx_pkt_size;
445 u8 offset;
446 u8 pkt_offset;
447 u8 mac_id;
448 u8 rate_id;
449 u8 rate;
450 u8 qsel;
451 u8 bw;
452 u8 sec_type;
453 u8 sn;
454 bool ampdu_en;
455 u8 ampdu_factor;
456 u8 ampdu_density;
457 u16 seq;
458 bool stbc;
459 bool ldpc;
460 bool dis_rate_fallback;
461 bool bmc;
462 bool use_rate;
463 bool ls;
464 bool fs;
465 bool short_gi;
466 bool report;
467};
468
469struct rtw_rx_pkt_stat {
470 bool phy_status;
471 bool icv_err;
472 bool crc_err;
473 bool decrypted;
474 bool is_c2h;
475
476 s32 signal_power;
477 u16 pkt_len;
478 u8 bw;
479 u8 drv_info_sz;
480 u8 shift;
481 u8 rate;
482 u8 mac_id;
483 u8 cam_id;
484 u8 ppdu_cnt;
485 u32 tsf_low;
486 s8 rx_power[RTW_RF_PATH_MAX];
487 u8 rssi;
488 u8 rxsc;
489 struct rtw_sta_info *si;
490 struct ieee80211_vif *vif;
491};
492
493struct rtw_traffic_stats {
494
495 u64 tx_unicast;
496 u64 rx_unicast;
497
498
499 u64 tx_cnt;
500 u64 rx_cnt;
501
502
503 u32 tx_throughput;
504 u32 rx_throughput;
505};
506
507enum rtw_lps_mode {
508 RTW_MODE_ACTIVE = 0,
509 RTW_MODE_LPS = 1,
510 RTW_MODE_WMM_PS = 2,
511};
512
513enum rtw_pwr_state {
514 RTW_RF_OFF = 0x0,
515 RTW_RF_ON = 0x4,
516 RTW_ALL_ON = 0xc,
517};
518
519struct rtw_lps_conf {
520
521 struct rtw_vif *rtwvif;
522 enum rtw_lps_mode mode;
523 enum rtw_pwr_state state;
524 u8 awake_interval;
525 u8 rlbm;
526 u8 smart_ps;
527 u8 port_id;
528};
529
530enum rtw_hw_key_type {
531 RTW_CAM_NONE = 0,
532 RTW_CAM_WEP40 = 1,
533 RTW_CAM_TKIP = 2,
534 RTW_CAM_AES = 4,
535 RTW_CAM_WEP104 = 5,
536};
537
538struct rtw_cam_entry {
539 bool valid;
540 bool group;
541 u8 addr[ETH_ALEN];
542 u8 hw_key_type;
543 struct ieee80211_key_conf *key;
544};
545
546struct rtw_sec_desc {
547
548 bool default_key_search;
549
550 u32 total_cam_num;
551 struct rtw_cam_entry cam_table[RTW_MAX_SEC_CAM_NUM];
552 DECLARE_BITMAP(cam_map, RTW_MAX_SEC_CAM_NUM);
553};
554
555struct rtw_tx_report {
556
557 spinlock_t q_lock;
558 struct sk_buff_head queue;
559 atomic_t sn;
560 struct timer_list purge_timer;
561};
562
563#define RTW_BC_MC_MACID 1
564DECLARE_EWMA(rssi, 10, 16);
565
566struct rtw_sta_info {
567 struct ieee80211_sta *sta;
568 struct ieee80211_vif *vif;
569
570 struct ewma_rssi avg_rssi;
571 u8 rssi_level;
572
573 u8 mac_id;
574 u8 rate_id;
575 enum rtw_bandwidth bw_mode;
576 enum rtw_rf_type rf_type;
577 enum rtw_wireless_set wireless_set;
578 u8 stbc_en:2;
579 u8 ldpc_en:2;
580 bool sgi_enable;
581 bool vht_enable;
582 bool updated;
583 u8 init_ra_lv;
584 u64 ra_mask;
585};
586
587struct rtw_vif {
588 struct ieee80211_vif *vif;
589 enum rtw_net_type net_type;
590 u16 aid;
591 u8 mac_addr[ETH_ALEN];
592 u8 bssid[ETH_ALEN];
593 u8 port;
594 const struct rtw_vif_port *conf;
595
596 struct rtw_traffic_stats stats;
597 bool in_lps;
598};
599
600struct rtw_regulatory {
601 char alpha2[2];
602 u8 chplan;
603 u8 txpwr_regd;
604};
605
606struct rtw_chip_ops {
607 int (*mac_init)(struct rtw_dev *rtwdev);
608 int (*read_efuse)(struct rtw_dev *rtwdev, u8 *map);
609 void (*phy_set_param)(struct rtw_dev *rtwdev);
610 void (*set_channel)(struct rtw_dev *rtwdev, u8 channel,
611 u8 bandwidth, u8 primary_chan_idx);
612 void (*query_rx_desc)(struct rtw_dev *rtwdev, u8 *rx_desc,
613 struct rtw_rx_pkt_stat *pkt_stat,
614 struct ieee80211_rx_status *rx_status);
615 u32 (*read_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
616 u32 addr, u32 mask);
617 bool (*write_rf)(struct rtw_dev *rtwdev, enum rtw_rf_path rf_path,
618 u32 addr, u32 mask, u32 data);
619 void (*set_tx_power_index)(struct rtw_dev *rtwdev);
620 int (*rsvd_page_dump)(struct rtw_dev *rtwdev, u8 *buf, u32 offset,
621 u32 size);
622 void (*set_antenna)(struct rtw_dev *rtwdev, u8 antenna_tx,
623 u8 antenna_rx);
624 void (*cfg_ldo25)(struct rtw_dev *rtwdev, bool enable);
625 void (*false_alarm_statistics)(struct rtw_dev *rtwdev);
626 void (*do_iqk)(struct rtw_dev *rtwdev);
627};
628
629#define RTW_PWR_POLLING_CNT 20000
630
631#define RTW_PWR_CMD_READ 0x00
632#define RTW_PWR_CMD_WRITE 0x01
633#define RTW_PWR_CMD_POLLING 0x02
634#define RTW_PWR_CMD_DELAY 0x03
635#define RTW_PWR_CMD_END 0x04
636
637
638#define RTW_PWR_ADDR_MAC 0x00
639#define RTW_PWR_ADDR_USB 0x01
640#define RTW_PWR_ADDR_PCIE 0x02
641#define RTW_PWR_ADDR_SDIO 0x03
642
643#define RTW_PWR_INTF_SDIO_MSK BIT(0)
644#define RTW_PWR_INTF_USB_MSK BIT(1)
645#define RTW_PWR_INTF_PCI_MSK BIT(2)
646#define RTW_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
647
648#define RTW_PWR_CUT_A_MSK BIT(1)
649#define RTW_PWR_CUT_B_MSK BIT(2)
650#define RTW_PWR_CUT_C_MSK BIT(3)
651#define RTW_PWR_CUT_D_MSK BIT(4)
652#define RTW_PWR_CUT_E_MSK BIT(5)
653#define RTW_PWR_CUT_F_MSK BIT(6)
654#define RTW_PWR_CUT_G_MSK BIT(7)
655#define RTW_PWR_CUT_ALL_MSK 0xFF
656
657enum rtw_pwr_seq_cmd_delay_unit {
658 RTW_PWR_DELAY_US,
659 RTW_PWR_DELAY_MS,
660};
661
662struct rtw_pwr_seq_cmd {
663 u16 offset;
664 u8 cut_mask;
665 u8 intf_mask;
666 u8 base:4;
667 u8 cmd:4;
668 u8 mask;
669 u8 value;
670};
671
672enum rtw_chip_ver {
673 RTW_CHIP_VER_CUT_A = 0x00,
674 RTW_CHIP_VER_CUT_B = 0x01,
675 RTW_CHIP_VER_CUT_C = 0x02,
676 RTW_CHIP_VER_CUT_D = 0x03,
677 RTW_CHIP_VER_CUT_E = 0x04,
678 RTW_CHIP_VER_CUT_F = 0x05,
679 RTW_CHIP_VER_CUT_G = 0x06,
680};
681
682#define RTW_INTF_PHY_PLATFORM_ALL 0
683
684enum rtw_intf_phy_cut {
685 RTW_INTF_PHY_CUT_A = BIT(0),
686 RTW_INTF_PHY_CUT_B = BIT(1),
687 RTW_INTF_PHY_CUT_C = BIT(2),
688 RTW_INTF_PHY_CUT_D = BIT(3),
689 RTW_INTF_PHY_CUT_E = BIT(4),
690 RTW_INTF_PHY_CUT_F = BIT(5),
691 RTW_INTF_PHY_CUT_G = BIT(6),
692 RTW_INTF_PHY_CUT_ALL = 0xFFFF,
693};
694
695enum rtw_ip_sel {
696 RTW_IP_SEL_PHY = 0,
697 RTW_IP_SEL_MAC = 1,
698 RTW_IP_SEL_DBI = 2,
699
700 RTW_IP_SEL_UNDEF = 0xFFFF
701};
702
703enum rtw_pq_map_id {
704 RTW_PQ_MAP_VO = 0x0,
705 RTW_PQ_MAP_VI = 0x1,
706 RTW_PQ_MAP_BE = 0x2,
707 RTW_PQ_MAP_BK = 0x3,
708 RTW_PQ_MAP_MG = 0x4,
709 RTW_PQ_MAP_HI = 0x5,
710 RTW_PQ_MAP_NUM = 0x6,
711
712 RTW_PQ_MAP_UNDEF,
713};
714
715enum rtw_dma_mapping {
716 RTW_DMA_MAPPING_EXTRA = 0,
717 RTW_DMA_MAPPING_LOW = 1,
718 RTW_DMA_MAPPING_NORMAL = 2,
719 RTW_DMA_MAPPING_HIGH = 3,
720
721 RTW_DMA_MAPPING_UNDEF,
722};
723
724struct rtw_rqpn {
725 enum rtw_dma_mapping dma_map_vo;
726 enum rtw_dma_mapping dma_map_vi;
727 enum rtw_dma_mapping dma_map_be;
728 enum rtw_dma_mapping dma_map_bk;
729 enum rtw_dma_mapping dma_map_mg;
730 enum rtw_dma_mapping dma_map_hi;
731};
732
733struct rtw_page_table {
734 u16 hq_num;
735 u16 nq_num;
736 u16 lq_num;
737 u16 exq_num;
738 u16 gapq_num;
739};
740
741struct rtw_intf_phy_para {
742 u16 offset;
743 u16 value;
744 u16 ip_sel;
745 u16 cut_mask;
746 u16 platform;
747};
748
749struct rtw_intf_phy_para_table {
750 struct rtw_intf_phy_para *usb2_para;
751 struct rtw_intf_phy_para *usb3_para;
752 struct rtw_intf_phy_para *gen1_para;
753 struct rtw_intf_phy_para *gen2_para;
754 u8 n_usb2_para;
755 u8 n_usb3_para;
756 u8 n_gen1_para;
757 u8 n_gen2_para;
758};
759
760struct rtw_table {
761 const void *data;
762 const u32 size;
763 void (*parse)(struct rtw_dev *rtwdev, const struct rtw_table *tbl);
764 void (*do_cfg)(struct rtw_dev *rtwdev, const struct rtw_table *tbl,
765 u32 addr, u32 data);
766 enum rtw_rf_path rf_path;
767};
768
769static inline void rtw_load_table(struct rtw_dev *rtwdev,
770 const struct rtw_table *tbl)
771{
772 (*tbl->parse)(rtwdev, tbl);
773}
774
775enum rtw_rfe_fem {
776 RTW_RFE_IFEM,
777 RTW_RFE_EFEM,
778 RTW_RFE_IFEM2G_EFEM5G,
779 RTW_RFE_NUM,
780};
781
782struct rtw_rfe_def {
783 const struct rtw_table *phy_pg_tbl;
784 const struct rtw_table *txpwr_lmt_tbl;
785};
786
787#define RTW_DEF_RFE(chip, bb_pg, pwrlmt) { \
788 .phy_pg_tbl = &rtw ## chip ## _bb_pg_type ## bb_pg ## _tbl, \
789 .txpwr_lmt_tbl = &rtw ## chip ## _txpwr_lmt_type ## pwrlmt ## _tbl, \
790 }
791
792
793struct rtw_chip_info {
794 struct rtw_chip_ops *ops;
795 u8 id;
796
797 const char *fw_name;
798 u8 tx_pkt_desc_sz;
799 u8 tx_buf_desc_sz;
800 u8 rx_pkt_desc_sz;
801 u8 rx_buf_desc_sz;
802 u32 phy_efuse_size;
803 u32 log_efuse_size;
804 u32 ptct_efuse_size;
805 u32 txff_size;
806 u32 rxff_size;
807 u8 band;
808 u8 page_size;
809 u8 csi_buf_pg_num;
810 u8 dig_max;
811 u8 dig_min;
812 u8 txgi_factor;
813 bool is_pwr_by_rate_dec;
814 u8 max_power_index;
815
816 bool ht_supported;
817 bool vht_supported;
818
819
820 u8 sys_func_en;
821 struct rtw_pwr_seq_cmd **pwr_on_seq;
822 struct rtw_pwr_seq_cmd **pwr_off_seq;
823 struct rtw_rqpn *rqpn_table;
824 struct rtw_page_table *page_table;
825 struct rtw_intf_phy_para_table *intf_table;
826
827 struct rtw_hw_reg *dig;
828 u32 rf_base_addr[2];
829 u32 rf_sipi_addr[2];
830
831 const struct rtw_table *mac_tbl;
832 const struct rtw_table *agc_tbl;
833 const struct rtw_table *bb_tbl;
834 const struct rtw_table *rf_tbl[RTW_RF_PATH_MAX];
835 const struct rtw_table *rfk_init_tbl;
836
837 const struct rtw_rfe_def *rfe_defs;
838 u32 rfe_defs_size;
839};
840
841struct rtw_dm_info {
842 u32 cck_fa_cnt;
843 u32 ofdm_fa_cnt;
844 u32 total_fa_cnt;
845 u8 min_rssi;
846 u8 pre_min_rssi;
847 u16 fa_history[4];
848 u8 igi_history[4];
849 u8 igi_bitmap;
850 bool damping;
851 u8 damping_cnt;
852 u8 damping_rssi;
853
854 u8 cck_gi_u_bnd;
855 u8 cck_gi_l_bnd;
856};
857
858struct rtw_efuse {
859 u32 size;
860 u32 physical_size;
861 u32 logical_size;
862 u32 protect_size;
863
864 u8 addr[ETH_ALEN];
865 u8 channel_plan;
866 u8 country_code[2];
867 u8 rfe_option;
868 u8 thermal_meter;
869 u8 crystal_cap;
870 u8 ant_div_cfg;
871 u8 ant_div_type;
872 u8 regd;
873
874 u8 lna_type_2g;
875 u8 lna_type_5g;
876 u8 glna_type;
877 u8 alna_type;
878 bool ext_lna_2g;
879 bool ext_lna_5g;
880 u8 pa_type_2g;
881 u8 pa_type_5g;
882 u8 gpa_type;
883 u8 apa_type;
884 bool ext_pa_2g;
885 bool ext_pa_5g;
886
887 bool btcoex;
888
889 bool share_ant;
890 u8 bt_setting;
891
892 struct {
893 u8 hci;
894 u8 bw;
895 u8 ptcl;
896 u8 nss;
897 u8 ant_num;
898 } hw_cap;
899
900 struct rtw_txpwr_idx txpwr_idx_table[4];
901};
902
903struct rtw_phy_cond {
904#ifdef __LITTLE_ENDIAN
905 u32 rfe:8;
906 u32 intf:4;
907 u32 pkg:4;
908 u32 plat:4;
909 u32 intf_rsvd:4;
910 u32 cut:4;
911 u32 branch:2;
912 u32 neg:1;
913 u32 pos:1;
914#else
915 u32 pos:1;
916 u32 neg:1;
917 u32 branch:2;
918 u32 cut:4;
919 u32 intf_rsvd:4;
920 u32 plat:4;
921 u32 pkg:4;
922 u32 intf:4;
923 u32 rfe:8;
924#endif
925
926 #define INTF_PCIE BIT(0)
927 #define INTF_USB BIT(1)
928 #define INTF_SDIO BIT(2)
929
930 #define BRANCH_IF 0
931 #define BRANCH_ELIF 1
932 #define BRANCH_ELSE 2
933 #define BRANCH_ENDIF 3
934};
935
936struct rtw_fifo_conf {
937
938 u16 rsvd_boundary;
939 u16 rsvd_pg_num;
940 u16 rsvd_drv_pg_num;
941 u16 txff_pg_num;
942 u16 acq_pg_num;
943 u16 rsvd_drv_addr;
944 u16 rsvd_h2c_info_addr;
945 u16 rsvd_h2c_sta_info_addr;
946 u16 rsvd_h2cq_addr;
947 u16 rsvd_cpu_instr_addr;
948 u16 rsvd_fw_txbuf_addr;
949 u16 rsvd_csibuf_addr;
950 enum rtw_dma_mapping pq_map[RTW_PQ_MAP_NUM];
951};
952
953struct rtw_fw_state {
954 const struct firmware *firmware;
955 struct completion completion;
956 u16 version;
957 u8 sub_version;
958 u8 sub_index;
959 u16 h2c_version;
960};
961
962struct rtw_hal {
963 u32 rcr;
964
965 u32 chip_version;
966 u8 fab_version;
967 u8 cut_version;
968 u8 mp_chip;
969 u8 oem_id;
970 struct rtw_phy_cond phy_cond;
971
972 u8 ps_mode;
973 u8 current_channel;
974 u8 current_band_width;
975 u8 current_band_type;
976 u8 sec_ch_offset;
977 u8 rf_type;
978 u8 rf_path_num;
979 u8 antenna_tx;
980 u8 antenna_rx;
981
982
983 struct mutex tx_power_mutex;
984 s8 tx_pwr_by_rate_offset_2g[RTW_RF_PATH_MAX]
985 [DESC_RATE_MAX];
986 s8 tx_pwr_by_rate_offset_5g[RTW_RF_PATH_MAX]
987 [DESC_RATE_MAX];
988 s8 tx_pwr_by_rate_base_2g[RTW_RF_PATH_MAX]
989 [RTW_RATE_SECTION_MAX];
990 s8 tx_pwr_by_rate_base_5g[RTW_RF_PATH_MAX]
991 [RTW_RATE_SECTION_MAX];
992 s8 tx_pwr_limit_2g[RTW_REGD_MAX]
993 [RTW_CHANNEL_WIDTH_MAX]
994 [RTW_RATE_SECTION_MAX]
995 [RTW_MAX_CHANNEL_NUM_2G];
996 s8 tx_pwr_limit_5g[RTW_REGD_MAX]
997 [RTW_CHANNEL_WIDTH_MAX]
998 [RTW_RATE_SECTION_MAX]
999 [RTW_MAX_CHANNEL_NUM_5G];
1000 s8 tx_pwr_tbl[RTW_RF_PATH_MAX]
1001 [DESC_RATE_MAX];
1002};
1003
1004struct rtw_dev {
1005 struct ieee80211_hw *hw;
1006 struct device *dev;
1007
1008 struct rtw_hci hci;
1009
1010 struct rtw_chip_info *chip;
1011 struct rtw_hal hal;
1012 struct rtw_fifo_conf fifo;
1013 struct rtw_fw_state fw;
1014 struct rtw_efuse efuse;
1015 struct rtw_sec_desc sec;
1016 struct rtw_traffic_stats stats;
1017 struct rtw_regulatory regd;
1018
1019 struct rtw_dm_info dm_info;
1020
1021
1022 struct mutex mutex;
1023
1024
1025 spinlock_t dm_lock;
1026
1027
1028 spinlock_t rf_lock;
1029
1030
1031 struct delayed_work watch_dog_work;
1032 u32 watch_dog_cnt;
1033
1034 struct list_head rsvd_page_list;
1035
1036
1037 struct sk_buff_head c2h_queue;
1038 struct work_struct c2h_work;
1039
1040 struct rtw_tx_report tx_report;
1041
1042 struct {
1043
1044 u8 last_box_num;
1045
1046 spinlock_t lock;
1047 u32 seq;
1048 } h2c;
1049
1050
1051 struct rtw_lps_conf lps_conf;
1052 struct delayed_work lps_work;
1053
1054 struct dentry *debugfs;
1055
1056 u8 sta_cnt;
1057
1058 DECLARE_BITMAP(mac_id_map, RTW_MAX_MAC_ID_NUM);
1059 DECLARE_BITMAP(flags, NUM_OF_RTW_FLAGS);
1060
1061 u8 mp_mode;
1062
1063
1064 u8 priv[0] __aligned(sizeof(void *));
1065};
1066
1067#include "hci.h"
1068
1069static inline bool rtw_flag_check(struct rtw_dev *rtwdev, enum rtw_flags flag)
1070{
1071 return test_bit(flag, rtwdev->flags);
1072}
1073
1074static inline void rtw_flag_clear(struct rtw_dev *rtwdev, enum rtw_flags flag)
1075{
1076 clear_bit(flag, rtwdev->flags);
1077}
1078
1079static inline void rtw_flag_set(struct rtw_dev *rtwdev, enum rtw_flags flag)
1080{
1081 set_bit(flag, rtwdev->flags);
1082}
1083
1084void rtw_get_channel_params(struct cfg80211_chan_def *chandef,
1085 struct rtw_channel_params *ch_param);
1086bool check_hw_ready(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 target);
1087bool ltecoex_read_reg(struct rtw_dev *rtwdev, u16 offset, u32 *val);
1088bool ltecoex_reg_write(struct rtw_dev *rtwdev, u16 offset, u32 value);
1089void rtw_restore_reg(struct rtw_dev *rtwdev,
1090 struct rtw_backup_info *bckp, u32 num);
1091void rtw_set_channel(struct rtw_dev *rtwdev);
1092void rtw_vif_port_config(struct rtw_dev *rtwdev, struct rtw_vif *rtwvif,
1093 u32 config);
1094void rtw_tx_report_purge_timer(struct timer_list *t);
1095void rtw_update_sta_info(struct rtw_dev *rtwdev, struct rtw_sta_info *si);
1096int rtw_core_start(struct rtw_dev *rtwdev);
1097void rtw_core_stop(struct rtw_dev *rtwdev);
1098int rtw_chip_info_setup(struct rtw_dev *rtwdev);
1099int rtw_core_init(struct rtw_dev *rtwdev);
1100void rtw_core_deinit(struct rtw_dev *rtwdev);
1101int rtw_register_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1102void rtw_unregister_hw(struct rtw_dev *rtwdev, struct ieee80211_hw *hw);
1103
1104#endif
1105
