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9#include <linux/device.h>
10#include <linux/gpio.h>
11#include <linux/init.h>
12#include <linux/module.h>
13#include <linux/pinctrl/consumer.h>
14#include <linux/slab.h>
15#include <linux/spinlock.h>
16
17#include "core.h"
18
19struct sh_pfc_gpio_data_reg {
20 const struct pinmux_data_reg *info;
21 u32 shadow;
22};
23
24struct sh_pfc_gpio_pin {
25 u8 dbit;
26 u8 dreg;
27};
28
29struct sh_pfc_chip {
30 struct sh_pfc *pfc;
31 struct gpio_chip gpio_chip;
32
33 struct sh_pfc_window *mem;
34 struct sh_pfc_gpio_data_reg *regs;
35 struct sh_pfc_gpio_pin *pins;
36};
37
38static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
39{
40 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
41 return chip->pfc;
42}
43
44static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
45 struct sh_pfc_gpio_data_reg **reg,
46 unsigned int *bit)
47{
48 int idx = sh_pfc_get_pin_index(chip->pfc, offset);
49 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
50
51 *reg = &chip->regs[gpio_pin->dreg];
52 *bit = gpio_pin->dbit;
53}
54
55static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
56 const struct pinmux_data_reg *dreg)
57{
58 phys_addr_t address = dreg->reg;
59 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
60
61 return sh_pfc_read_raw_reg(mem, dreg->reg_width);
62}
63
64static void gpio_write_data_reg(struct sh_pfc_chip *chip,
65 const struct pinmux_data_reg *dreg, u32 value)
66{
67 phys_addr_t address = dreg->reg;
68 void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
69
70 sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
71}
72
73static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
74{
75 struct sh_pfc *pfc = chip->pfc;
76 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
77 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
78 const struct pinmux_data_reg *dreg;
79 unsigned int bit;
80 unsigned int i;
81
82 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
83 for (bit = 0; bit < dreg->reg_width; bit++) {
84 if (dreg->enum_ids[bit] == pin->enum_id) {
85 gpio_pin->dreg = i;
86 gpio_pin->dbit = bit;
87 return;
88 }
89 }
90 }
91
92 BUG();
93}
94
95static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
96{
97 struct sh_pfc *pfc = chip->pfc;
98 const struct pinmux_data_reg *dreg;
99 unsigned int i;
100
101
102
103
104 for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
105 ;
106
107 chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
108 GFP_KERNEL);
109 if (chip->regs == NULL)
110 return -ENOMEM;
111
112 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
113 chip->regs[i].info = dreg;
114 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
115 }
116
117 for (i = 0; i < pfc->info->nr_pins; i++) {
118 if (pfc->info->pins[i].enum_id == 0)
119 continue;
120
121 gpio_setup_data_reg(chip, i);
122 }
123
124 return 0;
125}
126
127
128
129
130
131static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
132{
133 struct sh_pfc *pfc = gpio_to_pfc(gc);
134 int idx = sh_pfc_get_pin_index(pfc, offset);
135
136 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
137 return -EINVAL;
138
139 return pinctrl_gpio_request(offset);
140}
141
142static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
143{
144 return pinctrl_gpio_free(offset);
145}
146
147static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
148 int value)
149{
150 struct sh_pfc_gpio_data_reg *reg;
151 unsigned int bit;
152 unsigned int pos;
153
154 gpio_get_data_reg(chip, offset, ®, &bit);
155
156 pos = reg->info->reg_width - (bit + 1);
157
158 if (value)
159 reg->shadow |= BIT(pos);
160 else
161 reg->shadow &= ~BIT(pos);
162
163 gpio_write_data_reg(chip, reg->info, reg->shadow);
164}
165
166static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
167{
168 return pinctrl_gpio_direction_input(offset);
169}
170
171static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
172 int value)
173{
174 gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
175
176 return pinctrl_gpio_direction_output(offset);
177}
178
179static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
180{
181 struct sh_pfc_chip *chip = gpiochip_get_data(gc);
182 struct sh_pfc_gpio_data_reg *reg;
183 unsigned int bit;
184 unsigned int pos;
185
186 gpio_get_data_reg(chip, offset, ®, &bit);
187
188 pos = reg->info->reg_width - (bit + 1);
189
190 return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
191}
192
193static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
194{
195 gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
196}
197
198static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
199{
200 struct sh_pfc *pfc = gpio_to_pfc(gc);
201 unsigned int i, k;
202
203 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
204 const short *gpios = pfc->info->gpio_irq[i].gpios;
205
206 for (k = 0; gpios[k] >= 0; k++) {
207 if (gpios[k] == offset)
208 goto found;
209 }
210 }
211
212 return 0;
213
214found:
215 return pfc->irqs[i];
216}
217
218static int gpio_pin_setup(struct sh_pfc_chip *chip)
219{
220 struct sh_pfc *pfc = chip->pfc;
221 struct gpio_chip *gc = &chip->gpio_chip;
222 int ret;
223
224 chip->pins = devm_kcalloc(pfc->dev,
225 pfc->info->nr_pins, sizeof(*chip->pins),
226 GFP_KERNEL);
227 if (chip->pins == NULL)
228 return -ENOMEM;
229
230 ret = gpio_setup_data_regs(chip);
231 if (ret < 0)
232 return ret;
233
234 gc->request = gpio_pin_request;
235 gc->free = gpio_pin_free;
236 gc->direction_input = gpio_pin_direction_input;
237 gc->get = gpio_pin_get;
238 gc->direction_output = gpio_pin_direction_output;
239 gc->set = gpio_pin_set;
240 gc->to_irq = gpio_pin_to_irq;
241
242 gc->label = pfc->info->name;
243 gc->parent = pfc->dev;
244 gc->owner = THIS_MODULE;
245 gc->base = 0;
246 gc->ngpio = pfc->nr_gpio_pins;
247
248 return 0;
249}
250
251
252
253
254
255#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
256static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
257{
258 static bool __print_once;
259 struct sh_pfc *pfc = gpio_to_pfc(gc);
260 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
261 unsigned long flags;
262 int ret;
263
264 if (!__print_once) {
265 dev_notice(pfc->dev,
266 "Use of GPIO API for function requests is deprecated."
267 " Convert to pinctrl\n");
268 __print_once = true;
269 }
270
271 if (mark == 0)
272 return -EINVAL;
273
274 spin_lock_irqsave(&pfc->lock, flags);
275 ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
276 spin_unlock_irqrestore(&pfc->lock, flags);
277
278 return ret;
279}
280
281static int gpio_function_setup(struct sh_pfc_chip *chip)
282{
283 struct sh_pfc *pfc = chip->pfc;
284 struct gpio_chip *gc = &chip->gpio_chip;
285
286 gc->request = gpio_function_request;
287
288 gc->label = pfc->info->name;
289 gc->owner = THIS_MODULE;
290 gc->base = pfc->nr_gpio_pins;
291 gc->ngpio = pfc->info->nr_func_gpios;
292
293 return 0;
294}
295#endif
296
297
298
299
300
301static struct sh_pfc_chip *
302sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
303 struct sh_pfc_window *mem)
304{
305 struct sh_pfc_chip *chip;
306 int ret;
307
308 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
309 if (unlikely(!chip))
310 return ERR_PTR(-ENOMEM);
311
312 chip->mem = mem;
313 chip->pfc = pfc;
314
315 ret = setup(chip);
316 if (ret < 0)
317 return ERR_PTR(ret);
318
319 ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
320 if (unlikely(ret < 0))
321 return ERR_PTR(ret);
322
323 dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
324 chip->gpio_chip.label, chip->gpio_chip.base,
325 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
326
327 return chip;
328}
329
330int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
331{
332 struct sh_pfc_chip *chip;
333 phys_addr_t address;
334 unsigned int i;
335
336 if (pfc->info->data_regs == NULL)
337 return 0;
338
339
340
341
342
343
344 address = pfc->info->data_regs[0].reg;
345 for (i = 0; i < pfc->num_windows; ++i) {
346 struct sh_pfc_window *window = &pfc->windows[i];
347
348 if (address >= window->phys &&
349 address < window->phys + window->size)
350 break;
351 }
352
353 if (i == pfc->num_windows)
354 return 0;
355
356
357 if (pfc->num_irqs != pfc->info->gpio_irq_size) {
358 dev_err(pfc->dev, "invalid number of IRQ resources\n");
359 return -EINVAL;
360 }
361
362
363 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
364 if (IS_ERR(chip))
365 return PTR_ERR(chip);
366
367 pfc->gpio = chip;
368
369 if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
370 return 0;
371
372#ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
373
374
375
376
377
378
379 for (i = 0; i < pfc->nr_ranges; ++i) {
380 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
381 int ret;
382
383 if (range->start >= pfc->nr_gpio_pins)
384 break;
385
386 ret = gpiochip_add_pin_range(&chip->gpio_chip,
387 dev_name(pfc->dev), range->start, range->start,
388 range->end - range->start + 1);
389 if (ret < 0)
390 return ret;
391 }
392
393
394 if (pfc->info->nr_func_gpios == 0)
395 return 0;
396
397 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
398 if (IS_ERR(chip))
399 return PTR_ERR(chip);
400#endif
401
402 return 0;
403}
404