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36#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37
38#include <linux/module.h>
39#include <linux/slab.h>
40#include <linux/log2.h>
41
42#include "../comedi_pci.h"
43
44#include "mite.h"
45
46
47
48
49#define MITE_UNKNOWN_DMA_BURST_REG 0x28
50#define UNKNOWN_DMA_BURST_ENABLE_BITS 0x600
51
52#define MITE_PCI_CONFIG_OFFSET 0x300
53#define MITE_CSIGR 0x460
54#define CSIGR_TO_IOWINS(x) (((x) >> 29) & 0x7)
55#define CSIGR_TO_WINS(x) (((x) >> 24) & 0x1f)
56#define CSIGR_TO_WPDEP(x) (((x) >> 20) & 0x7)
57#define CSIGR_TO_DMAC(x) (((x) >> 16) & 0xf)
58#define CSIGR_TO_IMODE(x) (((x) >> 12) & 0x3)
59#define CSIGR_TO_MMODE(x) (((x) >> 8) & 0x3)
60#define CSIGR_TO_TYPE(x) (((x) >> 4) & 0xf)
61#define CSIGR_TO_VER(x) (((x) >> 0) & 0xf)
62
63#define MITE_CHAN(x) (0x500 + 0x100 * (x))
64#define MITE_CHOR(x) (0x00 + MITE_CHAN(x))
65#define CHOR_DMARESET BIT(31)
66#define CHOR_SET_SEND_TC BIT(11)
67#define CHOR_CLR_SEND_TC BIT(10)
68#define CHOR_SET_LPAUSE BIT(9)
69#define CHOR_CLR_LPAUSE BIT(8)
70#define CHOR_CLRDONE BIT(7)
71#define CHOR_CLRRB BIT(6)
72#define CHOR_CLRLC BIT(5)
73#define CHOR_FRESET BIT(4)
74#define CHOR_ABORT BIT(3)
75#define CHOR_STOP BIT(2)
76#define CHOR_CONT BIT(1)
77#define CHOR_START BIT(0)
78#define MITE_CHCR(x) (0x04 + MITE_CHAN(x))
79#define CHCR_SET_DMA_IE BIT(31)
80#define CHCR_CLR_DMA_IE BIT(30)
81#define CHCR_SET_LINKP_IE BIT(29)
82#define CHCR_CLR_LINKP_IE BIT(28)
83#define CHCR_SET_SAR_IE BIT(27)
84#define CHCR_CLR_SAR_IE BIT(26)
85#define CHCR_SET_DONE_IE BIT(25)
86#define CHCR_CLR_DONE_IE BIT(24)
87#define CHCR_SET_MRDY_IE BIT(23)
88#define CHCR_CLR_MRDY_IE BIT(22)
89#define CHCR_SET_DRDY_IE BIT(21)
90#define CHCR_CLR_DRDY_IE BIT(20)
91#define CHCR_SET_LC_IE BIT(19)
92#define CHCR_CLR_LC_IE BIT(18)
93#define CHCR_SET_CONT_RB_IE BIT(17)
94#define CHCR_CLR_CONT_RB_IE BIT(16)
95#define CHCR_FIFO(x) (((x) & 0x1) << 15)
96#define CHCR_FIFODIS CHCR_FIFO(1)
97#define CHCR_FIFO_ON CHCR_FIFO(0)
98#define CHCR_BURST(x) (((x) & 0x1) << 14)
99#define CHCR_BURSTEN CHCR_BURST(1)
100#define CHCR_NO_BURSTEN CHCR_BURST(0)
101#define CHCR_BYTE_SWAP_DEVICE BIT(6)
102#define CHCR_BYTE_SWAP_MEMORY BIT(4)
103#define CHCR_DIR(x) (((x) & 0x1) << 3)
104#define CHCR_DEV_TO_MEM CHCR_DIR(1)
105#define CHCR_MEM_TO_DEV CHCR_DIR(0)
106#define CHCR_MODE(x) (((x) & 0x7) << 0)
107#define CHCR_NORMAL CHCR_MODE(0)
108#define CHCR_CONTINUE CHCR_MODE(1)
109#define CHCR_RINGBUFF CHCR_MODE(2)
110#define CHCR_LINKSHORT CHCR_MODE(4)
111#define CHCR_LINKLONG CHCR_MODE(5)
112#define MITE_TCR(x) (0x08 + MITE_CHAN(x))
113#define MITE_MCR(x) (0x0c + MITE_CHAN(x))
114#define MITE_MAR(x) (0x10 + MITE_CHAN(x))
115#define MITE_DCR(x) (0x14 + MITE_CHAN(x))
116#define DCR_NORMAL BIT(29)
117#define MITE_DAR(x) (0x18 + MITE_CHAN(x))
118#define MITE_LKCR(x) (0x1c + MITE_CHAN(x))
119#define MITE_LKAR(x) (0x20 + MITE_CHAN(x))
120#define MITE_LLKAR(x) (0x24 + MITE_CHAN(x))
121#define MITE_BAR(x) (0x28 + MITE_CHAN(x))
122#define MITE_BCR(x) (0x2c + MITE_CHAN(x))
123#define MITE_SAR(x) (0x30 + MITE_CHAN(x))
124#define MITE_WSCR(x) (0x34 + MITE_CHAN(x))
125#define MITE_WSER(x) (0x38 + MITE_CHAN(x))
126#define MITE_CHSR(x) (0x3c + MITE_CHAN(x))
127#define CHSR_INT BIT(31)
128#define CHSR_LPAUSES BIT(29)
129#define CHSR_SARS BIT(27)
130#define CHSR_DONE BIT(25)
131#define CHSR_MRDY BIT(23)
132#define CHSR_DRDY BIT(21)
133#define CHSR_LINKC BIT(19)
134#define CHSR_CONTS_RB BIT(17)
135#define CHSR_ERROR BIT(15)
136#define CHSR_SABORT BIT(14)
137#define CHSR_HABORT BIT(13)
138#define CHSR_STOPS BIT(12)
139#define CHSR_OPERR(x) (((x) & 0x3) << 10)
140#define CHSR_OPERR_MASK CHSR_OPERR(3)
141#define CHSR_OPERR_NOERROR CHSR_OPERR(0)
142#define CHSR_OPERR_FIFOERROR CHSR_OPERR(1)
143#define CHSR_OPERR_LINKERROR CHSR_OPERR(1)
144#define CHSR_XFERR BIT(9)
145#define CHSR_END BIT(8)
146#define CHSR_DRQ1 BIT(7)
147#define CHSR_DRQ0 BIT(6)
148#define CHSR_LERR(x) (((x) & 0x3) << 4)
149#define CHSR_LERR_MASK CHSR_LERR(3)
150#define CHSR_LBERR CHSR_LERR(1)
151#define CHSR_LRERR CHSR_LERR(2)
152#define CHSR_LOERR CHSR_LERR(3)
153#define CHSR_MERR(x) (((x) & 0x3) << 2)
154#define CHSR_MERR_MASK CHSR_MERR(3)
155#define CHSR_MBERR CHSR_MERR(1)
156#define CHSR_MRERR CHSR_MERR(2)
157#define CHSR_MOERR CHSR_MERR(3)
158#define CHSR_DERR(x) (((x) & 0x3) << 0)
159#define CHSR_DERR_MASK CHSR_DERR(3)
160#define CHSR_DBERR CHSR_DERR(1)
161#define CHSR_DRERR CHSR_DERR(2)
162#define CHSR_DOERR CHSR_DERR(3)
163#define MITE_FCR(x) (0x40 + MITE_CHAN(x))
164
165
166#define CR_RL(x) (((x) & 0x7) << 21)
167#define CR_REQS(x) (((x) & 0x7) << 16)
168#define CR_REQS_MASK CR_REQS(7)
169#define CR_ASEQ(x) (((x) & 0x3) << 10)
170#define CR_ASEQDONT CR_ASEQ(0)
171#define CR_ASEQUP CR_ASEQ(1)
172#define CR_ASEQDOWN CR_ASEQ(2)
173#define CR_ASEQ_MASK CR_ASEQ(3)
174#define CR_PSIZE(x) (((x) & 0x3) << 8)
175#define CR_PSIZE8 CR_PSIZE(1)
176#define CR_PSIZE16 CR_PSIZE(2)
177#define CR_PSIZE32 CR_PSIZE(3)
178#define CR_PORT(x) (((x) & 0x3) << 6)
179#define CR_PORTCPU CR_PORT(0)
180#define CR_PORTIO CR_PORT(1)
181#define CR_PORTVXI CR_PORT(2)
182#define CR_PORTMXI CR_PORT(3)
183#define CR_AMDEVICE BIT(0)
184
185static unsigned int MITE_IODWBSR_1_WSIZE_bits(unsigned int size)
186{
187 return (ilog2(size) - 1) & 0x1f;
188}
189
190static unsigned int mite_retry_limit(unsigned int retry_limit)
191{
192 unsigned int value = 0;
193
194 if (retry_limit)
195 value = 1 + ilog2(retry_limit);
196 if (value > 0x7)
197 value = 0x7;
198 return CR_RL(value);
199}
200
201static unsigned int mite_drq_reqs(unsigned int drq_line)
202{
203
204 return CR_REQS((drq_line & 0x3) | 0x4);
205}
206
207static unsigned int mite_fifo_size(struct mite *mite, unsigned int channel)
208{
209 unsigned int fcr_bits = readl(mite->mmio + MITE_FCR(channel));
210 unsigned int empty_count = (fcr_bits >> 16) & 0xff;
211 unsigned int full_count = fcr_bits & 0xff;
212
213 return empty_count + full_count;
214}
215
216static u32 mite_device_bytes_transferred(struct mite_channel *mite_chan)
217{
218 struct mite *mite = mite_chan->mite;
219
220 return readl(mite->mmio + MITE_DAR(mite_chan->channel));
221}
222
223
224
225
226
227u32 mite_bytes_in_transit(struct mite_channel *mite_chan)
228{
229 struct mite *mite = mite_chan->mite;
230
231 return readl(mite->mmio + MITE_FCR(mite_chan->channel)) & 0xff;
232}
233EXPORT_SYMBOL_GPL(mite_bytes_in_transit);
234
235
236static u32 mite_bytes_written_to_memory_lb(struct mite_channel *mite_chan)
237{
238 u32 device_byte_count;
239
240 device_byte_count = mite_device_bytes_transferred(mite_chan);
241 return device_byte_count - mite_bytes_in_transit(mite_chan);
242}
243
244
245static u32 mite_bytes_written_to_memory_ub(struct mite_channel *mite_chan)
246{
247 u32 in_transit_count;
248
249 in_transit_count = mite_bytes_in_transit(mite_chan);
250 return mite_device_bytes_transferred(mite_chan) - in_transit_count;
251}
252
253
254static u32 mite_bytes_read_from_memory_lb(struct mite_channel *mite_chan)
255{
256 u32 device_byte_count;
257
258 device_byte_count = mite_device_bytes_transferred(mite_chan);
259 return device_byte_count + mite_bytes_in_transit(mite_chan);
260}
261
262
263static u32 mite_bytes_read_from_memory_ub(struct mite_channel *mite_chan)
264{
265 u32 in_transit_count;
266
267 in_transit_count = mite_bytes_in_transit(mite_chan);
268 return mite_device_bytes_transferred(mite_chan) + in_transit_count;
269}
270
271static void mite_sync_input_dma(struct mite_channel *mite_chan,
272 struct comedi_subdevice *s)
273{
274 struct comedi_async *async = s->async;
275 int count;
276 unsigned int nbytes, old_alloc_count;
277
278 old_alloc_count = async->buf_write_alloc_count;
279
280 comedi_buf_write_alloc(s, async->prealloc_bufsz);
281
282 nbytes = mite_bytes_written_to_memory_lb(mite_chan);
283 if ((int)(mite_bytes_written_to_memory_ub(mite_chan) -
284 old_alloc_count) > 0) {
285 dev_warn(s->device->class_dev,
286 "mite: DMA overwrite of free area\n");
287 async->events |= COMEDI_CB_OVERFLOW;
288 return;
289 }
290
291 count = nbytes - async->buf_write_count;
292
293
294
295
296 if (count > 0) {
297 comedi_buf_write_free(s, count);
298 comedi_inc_scan_progress(s, count);
299 async->events |= COMEDI_CB_BLOCK;
300 }
301}
302
303static void mite_sync_output_dma(struct mite_channel *mite_chan,
304 struct comedi_subdevice *s)
305{
306 struct comedi_async *async = s->async;
307 struct comedi_cmd *cmd = &async->cmd;
308 u32 stop_count = cmd->stop_arg * comedi_bytes_per_scan(s);
309 unsigned int old_alloc_count = async->buf_read_alloc_count;
310 u32 nbytes_ub, nbytes_lb;
311 int count;
312 bool finite_regen = (cmd->stop_src == TRIG_NONE && stop_count != 0);
313
314
315 comedi_buf_read_alloc(s, async->prealloc_bufsz);
316 nbytes_lb = mite_bytes_read_from_memory_lb(mite_chan);
317 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_lb - stop_count) > 0)
318 nbytes_lb = stop_count;
319 nbytes_ub = mite_bytes_read_from_memory_ub(mite_chan);
320 if (cmd->stop_src == TRIG_COUNT && (int)(nbytes_ub - stop_count) > 0)
321 nbytes_ub = stop_count;
322
323 if ((!finite_regen || stop_count > old_alloc_count) &&
324 ((int)(nbytes_ub - old_alloc_count) > 0)) {
325 dev_warn(s->device->class_dev, "mite: DMA underrun\n");
326 async->events |= COMEDI_CB_OVERFLOW;
327 return;
328 }
329
330 if (finite_regen) {
331
332
333
334
335
336
337 return;
338 }
339
340 count = nbytes_lb - async->buf_read_count;
341 if (count > 0) {
342 comedi_buf_read_free(s, count);
343 async->events |= COMEDI_CB_BLOCK;
344 }
345}
346
347
348
349
350
351
352void mite_sync_dma(struct mite_channel *mite_chan, struct comedi_subdevice *s)
353{
354 if (mite_chan->dir == COMEDI_INPUT)
355 mite_sync_input_dma(mite_chan, s);
356 else
357 mite_sync_output_dma(mite_chan, s);
358}
359EXPORT_SYMBOL_GPL(mite_sync_dma);
360
361static unsigned int mite_get_status(struct mite_channel *mite_chan)
362{
363 struct mite *mite = mite_chan->mite;
364 unsigned int status;
365 unsigned long flags;
366
367 spin_lock_irqsave(&mite->lock, flags);
368 status = readl(mite->mmio + MITE_CHSR(mite_chan->channel));
369 if (status & CHSR_DONE) {
370 mite_chan->done = 1;
371 writel(CHOR_CLRDONE,
372 mite->mmio + MITE_CHOR(mite_chan->channel));
373 }
374 spin_unlock_irqrestore(&mite->lock, flags);
375 return status;
376}
377
378
379
380
381
382
383
384
385
386void mite_ack_linkc(struct mite_channel *mite_chan,
387 struct comedi_subdevice *s,
388 bool sync)
389{
390 struct mite *mite = mite_chan->mite;
391 unsigned int status;
392
393 status = mite_get_status(mite_chan);
394 if (status & CHSR_LINKC) {
395 writel(CHOR_CLRLC, mite->mmio + MITE_CHOR(mite_chan->channel));
396 sync = true;
397 }
398 if (sync)
399 mite_sync_dma(mite_chan, s);
400
401 if (status & CHSR_XFERR) {
402 dev_err(s->device->class_dev,
403 "mite: transfer error %08x\n", status);
404 s->async->events |= COMEDI_CB_ERROR;
405 }
406}
407EXPORT_SYMBOL_GPL(mite_ack_linkc);
408
409
410
411
412
413
414
415int mite_done(struct mite_channel *mite_chan)
416{
417 struct mite *mite = mite_chan->mite;
418 unsigned long flags;
419 int done;
420
421 mite_get_status(mite_chan);
422 spin_lock_irqsave(&mite->lock, flags);
423 done = mite_chan->done;
424 spin_unlock_irqrestore(&mite->lock, flags);
425 return done;
426}
427EXPORT_SYMBOL_GPL(mite_done);
428
429static void mite_dma_reset(struct mite_channel *mite_chan)
430{
431 writel(CHOR_DMARESET | CHOR_FRESET,
432 mite_chan->mite->mmio + MITE_CHOR(mite_chan->channel));
433}
434
435
436
437
438
439void mite_dma_arm(struct mite_channel *mite_chan)
440{
441 struct mite *mite = mite_chan->mite;
442 unsigned long flags;
443
444
445
446
447
448 smp_mb();
449 spin_lock_irqsave(&mite->lock, flags);
450 mite_chan->done = 0;
451
452 writel(CHOR_START, mite->mmio + MITE_CHOR(mite_chan->channel));
453 spin_unlock_irqrestore(&mite->lock, flags);
454}
455EXPORT_SYMBOL_GPL(mite_dma_arm);
456
457
458
459
460
461void mite_dma_disarm(struct mite_channel *mite_chan)
462{
463 struct mite *mite = mite_chan->mite;
464
465
466 writel(CHOR_ABORT, mite->mmio + MITE_CHOR(mite_chan->channel));
467}
468EXPORT_SYMBOL_GPL(mite_dma_disarm);
469
470
471
472
473
474
475
476void mite_prep_dma(struct mite_channel *mite_chan,
477 unsigned int num_device_bits, unsigned int num_memory_bits)
478{
479 struct mite *mite = mite_chan->mite;
480 unsigned int chcr, mcr, dcr, lkcr;
481
482 mite_dma_reset(mite_chan);
483
484
485 chcr = CHCR_SET_DMA_IE | CHCR_LINKSHORT | CHCR_SET_DONE_IE |
486 CHCR_BURSTEN;
487
488
489
490
491
492
493
494
495 chcr |= CHCR_SET_LC_IE;
496 if (num_memory_bits == 32 && num_device_bits == 16) {
497
498
499
500
501
502
503
504 chcr |= CHCR_BYTE_SWAP_DEVICE | CHCR_BYTE_SWAP_MEMORY;
505 }
506 if (mite_chan->dir == COMEDI_INPUT)
507 chcr |= CHCR_DEV_TO_MEM;
508
509 writel(chcr, mite->mmio + MITE_CHCR(mite_chan->channel));
510
511
512 mcr = mite_retry_limit(64) | CR_ASEQUP;
513 switch (num_memory_bits) {
514 case 8:
515 mcr |= CR_PSIZE8;
516 break;
517 case 16:
518 mcr |= CR_PSIZE16;
519 break;
520 case 32:
521 mcr |= CR_PSIZE32;
522 break;
523 default:
524 pr_warn("bug! invalid mem bit width for dma transfer\n");
525 break;
526 }
527 writel(mcr, mite->mmio + MITE_MCR(mite_chan->channel));
528
529
530 dcr = mite_retry_limit(64) | CR_ASEQUP;
531 dcr |= CR_PORTIO | CR_AMDEVICE | mite_drq_reqs(mite_chan->channel);
532 switch (num_device_bits) {
533 case 8:
534 dcr |= CR_PSIZE8;
535 break;
536 case 16:
537 dcr |= CR_PSIZE16;
538 break;
539 case 32:
540 dcr |= CR_PSIZE32;
541 break;
542 default:
543 pr_warn("bug! invalid dev bit width for dma transfer\n");
544 break;
545 }
546 writel(dcr, mite->mmio + MITE_DCR(mite_chan->channel));
547
548
549 writel(0, mite->mmio + MITE_DAR(mite_chan->channel));
550
551
552 lkcr = mite_retry_limit(64) | CR_ASEQUP | CR_PSIZE32;
553 writel(lkcr, mite->mmio + MITE_LKCR(mite_chan->channel));
554
555
556 writel(mite_chan->ring->dma_addr,
557 mite->mmio + MITE_LKAR(mite_chan->channel));
558}
559EXPORT_SYMBOL_GPL(mite_prep_dma);
560
561static struct mite_channel *__mite_request_channel(struct mite *mite,
562 struct mite_ring *ring,
563 unsigned int min_channel,
564 unsigned int max_channel)
565{
566 struct mite_channel *mite_chan = NULL;
567 unsigned long flags;
568 int i;
569
570
571
572
573
574 spin_lock_irqsave(&mite->lock, flags);
575 for (i = min_channel; i <= max_channel; ++i) {
576 mite_chan = &mite->channels[i];
577 if (!mite_chan->ring) {
578 mite_chan->ring = ring;
579 break;
580 }
581 mite_chan = NULL;
582 }
583 spin_unlock_irqrestore(&mite->lock, flags);
584 return mite_chan;
585}
586
587
588
589
590
591
592
593
594struct mite_channel *mite_request_channel_in_range(struct mite *mite,
595 struct mite_ring *ring,
596 unsigned int min_channel,
597 unsigned int max_channel)
598{
599 return __mite_request_channel(mite, ring, min_channel, max_channel);
600}
601EXPORT_SYMBOL_GPL(mite_request_channel_in_range);
602
603
604
605
606
607
608struct mite_channel *mite_request_channel(struct mite *mite,
609 struct mite_ring *ring)
610{
611 return __mite_request_channel(mite, ring, 0, mite->num_channels - 1);
612}
613EXPORT_SYMBOL_GPL(mite_request_channel);
614
615
616
617
618
619void mite_release_channel(struct mite_channel *mite_chan)
620{
621 struct mite *mite = mite_chan->mite;
622 unsigned long flags;
623
624
625 spin_lock_irqsave(&mite->lock, flags);
626 if (mite_chan->ring) {
627 mite_dma_disarm(mite_chan);
628 mite_dma_reset(mite_chan);
629
630
631
632
633 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE |
634 CHCR_CLR_SAR_IE | CHCR_CLR_DONE_IE |
635 CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
636 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
637 mite->mmio + MITE_CHCR(mite_chan->channel));
638 mite_chan->ring = NULL;
639 }
640 spin_unlock_irqrestore(&mite->lock, flags);
641}
642EXPORT_SYMBOL_GPL(mite_release_channel);
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657int mite_init_ring_descriptors(struct mite_ring *ring,
658 struct comedi_subdevice *s,
659 unsigned int nbytes)
660{
661 struct comedi_async *async = s->async;
662 struct mite_dma_desc *desc = NULL;
663 unsigned int n_full_links = nbytes >> PAGE_SHIFT;
664 unsigned int remainder = nbytes % PAGE_SIZE;
665 int i;
666
667 dev_dbg(s->device->class_dev,
668 "mite: init ring buffer to %u bytes\n", nbytes);
669
670 if ((n_full_links + (remainder > 0 ? 1 : 0)) > ring->n_links) {
671 dev_err(s->device->class_dev,
672 "mite: ring buffer too small for requested init\n");
673 return -ENOMEM;
674 }
675
676
677 for (i = 0; i < n_full_links; ++i) {
678 desc = &ring->descs[i];
679 desc->count = cpu_to_le32(PAGE_SIZE);
680 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr);
681 desc->next = cpu_to_le32(ring->dma_addr +
682 (i + 1) * sizeof(*desc));
683 }
684
685
686 if (remainder > 0) {
687 desc = &ring->descs[i];
688
689 desc->count = cpu_to_le32(remainder);
690 desc->addr = cpu_to_le32(async->buf_map->page_list[i].dma_addr);
691 }
692
693
694 desc->next = cpu_to_le32(ring->dma_addr);
695
696
697
698
699
700 smp_wmb();
701 return 0;
702}
703EXPORT_SYMBOL_GPL(mite_init_ring_descriptors);
704
705static void mite_free_dma_descs(struct mite_ring *ring)
706{
707 struct mite_dma_desc *descs = ring->descs;
708
709 if (descs) {
710 dma_free_coherent(ring->hw_dev,
711 ring->n_links * sizeof(*descs),
712 descs, ring->dma_addr);
713 ring->descs = NULL;
714 ring->dma_addr = 0;
715 ring->n_links = 0;
716 }
717}
718
719
720
721
722
723
724int mite_buf_change(struct mite_ring *ring, struct comedi_subdevice *s)
725{
726 struct comedi_async *async = s->async;
727 struct mite_dma_desc *descs;
728 unsigned int n_links;
729
730 mite_free_dma_descs(ring);
731
732 if (async->prealloc_bufsz == 0)
733 return 0;
734
735 n_links = async->prealloc_bufsz >> PAGE_SHIFT;
736
737 descs = dma_alloc_coherent(ring->hw_dev,
738 n_links * sizeof(*descs),
739 &ring->dma_addr, GFP_KERNEL);
740 if (!descs) {
741 dev_err(s->device->class_dev,
742 "mite: ring buffer allocation failed\n");
743 return -ENOMEM;
744 }
745 ring->descs = descs;
746 ring->n_links = n_links;
747
748 return mite_init_ring_descriptors(ring, s, n_links << PAGE_SHIFT);
749}
750EXPORT_SYMBOL_GPL(mite_buf_change);
751
752
753
754
755
756struct mite_ring *mite_alloc_ring(struct mite *mite)
757{
758 struct mite_ring *ring;
759
760 ring = kmalloc(sizeof(*ring), GFP_KERNEL);
761 if (!ring)
762 return NULL;
763 ring->hw_dev = get_device(&mite->pcidev->dev);
764 if (!ring->hw_dev) {
765 kfree(ring);
766 return NULL;
767 }
768 ring->n_links = 0;
769 ring->descs = NULL;
770 ring->dma_addr = 0;
771 return ring;
772}
773EXPORT_SYMBOL_GPL(mite_alloc_ring);
774
775
776
777
778
779void mite_free_ring(struct mite_ring *ring)
780{
781 if (ring) {
782 mite_free_dma_descs(ring);
783 put_device(ring->hw_dev);
784 kfree(ring);
785 }
786}
787EXPORT_SYMBOL_GPL(mite_free_ring);
788
789static int mite_setup(struct comedi_device *dev, struct mite *mite,
790 bool use_win1)
791{
792 resource_size_t daq_phys_addr;
793 unsigned long length;
794 int i;
795 u32 csigr_bits;
796 unsigned int unknown_dma_burst_bits;
797 unsigned int wpdep;
798
799 pci_set_master(mite->pcidev);
800
801 mite->mmio = pci_ioremap_bar(mite->pcidev, 0);
802 if (!mite->mmio)
803 return -ENOMEM;
804
805 dev->mmio = pci_ioremap_bar(mite->pcidev, 1);
806 if (!dev->mmio)
807 return -ENOMEM;
808 daq_phys_addr = pci_resource_start(mite->pcidev, 1);
809 length = pci_resource_len(mite->pcidev, 1);
810
811 if (use_win1) {
812 writel(0, mite->mmio + MITE_IODWBSR);
813 dev_dbg(dev->class_dev,
814 "mite: using I/O Window Base Size register 1\n");
815 writel(daq_phys_addr | WENAB |
816 MITE_IODWBSR_1_WSIZE_bits(length),
817 mite->mmio + MITE_IODWBSR_1);
818 writel(0, mite->mmio + MITE_IODWCR_1);
819 } else {
820 writel(daq_phys_addr | WENAB, mite->mmio + MITE_IODWBSR);
821 }
822
823
824
825
826
827
828
829
830
831
832
833 unknown_dma_burst_bits = readl(mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
834 unknown_dma_burst_bits |= UNKNOWN_DMA_BURST_ENABLE_BITS;
835 writel(unknown_dma_burst_bits, mite->mmio + MITE_UNKNOWN_DMA_BURST_REG);
836
837 csigr_bits = readl(mite->mmio + MITE_CSIGR);
838 mite->num_channels = CSIGR_TO_DMAC(csigr_bits);
839 if (mite->num_channels > MAX_MITE_DMA_CHANNELS) {
840 dev_warn(dev->class_dev,
841 "mite: bug? chip claims to have %i dma channels. Setting to %i.\n",
842 mite->num_channels, MAX_MITE_DMA_CHANNELS);
843 mite->num_channels = MAX_MITE_DMA_CHANNELS;
844 }
845
846
847 wpdep = CSIGR_TO_WPDEP(csigr_bits);
848 if (wpdep)
849 wpdep = BIT(wpdep);
850
851 dev_dbg(dev->class_dev,
852 "mite: version = %i, type = %i, mite mode = %i, interface mode = %i\n",
853 CSIGR_TO_VER(csigr_bits), CSIGR_TO_TYPE(csigr_bits),
854 CSIGR_TO_MMODE(csigr_bits), CSIGR_TO_IMODE(csigr_bits));
855 dev_dbg(dev->class_dev,
856 "mite: num channels = %i, write post fifo depth = %i, wins = %i, iowins = %i\n",
857 CSIGR_TO_DMAC(csigr_bits), wpdep,
858 CSIGR_TO_WINS(csigr_bits), CSIGR_TO_IOWINS(csigr_bits));
859
860 for (i = 0; i < mite->num_channels; i++) {
861 writel(CHOR_DMARESET, mite->mmio + MITE_CHOR(i));
862
863 writel(CHCR_CLR_DMA_IE | CHCR_CLR_LINKP_IE | CHCR_CLR_SAR_IE |
864 CHCR_CLR_DONE_IE | CHCR_CLR_MRDY_IE | CHCR_CLR_DRDY_IE |
865 CHCR_CLR_LC_IE | CHCR_CLR_CONT_RB_IE,
866 mite->mmio + MITE_CHCR(i));
867 }
868 mite->fifo_size = mite_fifo_size(mite, 0);
869 dev_dbg(dev->class_dev, "mite: fifo size is %i.\n", mite->fifo_size);
870 return 0;
871}
872
873
874
875
876
877
878
879
880
881
882
883struct mite *mite_attach(struct comedi_device *dev, bool use_win1)
884{
885 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
886 struct mite *mite;
887 unsigned int i;
888 int ret;
889
890 mite = kzalloc(sizeof(*mite), GFP_KERNEL);
891 if (!mite)
892 return NULL;
893
894 spin_lock_init(&mite->lock);
895 mite->pcidev = pcidev;
896 for (i = 0; i < MAX_MITE_DMA_CHANNELS; ++i) {
897 mite->channels[i].mite = mite;
898 mite->channels[i].channel = i;
899 mite->channels[i].done = 1;
900 }
901
902 ret = mite_setup(dev, mite, use_win1);
903 if (ret) {
904 if (mite->mmio)
905 iounmap(mite->mmio);
906 kfree(mite);
907 return NULL;
908 }
909
910 return mite;
911}
912EXPORT_SYMBOL_GPL(mite_attach);
913
914
915
916
917
918
919
920void mite_detach(struct mite *mite)
921{
922 if (!mite)
923 return;
924
925 if (mite->mmio)
926 iounmap(mite->mmio);
927
928 kfree(mite);
929}
930EXPORT_SYMBOL_GPL(mite_detach);
931
932static int __init mite_module_init(void)
933{
934 return 0;
935}
936module_init(mite_module_init);
937
938static void __exit mite_module_exit(void)
939{
940}
941module_exit(mite_module_exit);
942
943MODULE_AUTHOR("Comedi http://www.comedi.org");
944MODULE_DESCRIPTION("Comedi helper for NI Mite PCI interface chip");
945MODULE_LICENSE("GPL");
946