1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8#ifndef __HALHWOUTSRC_H__ 9#define __HALHWOUTSRC_H__ 10 11/* Definition */ 12/* CCK Rates, TxHT = 0 */ 13#define DESC92C_RATE1M 0x00 14#define DESC92C_RATE2M 0x01 15#define DESC92C_RATE5_5M 0x02 16#define DESC92C_RATE11M 0x03 17 18/* OFDM Rates, TxHT = 0 */ 19#define DESC92C_RATE6M 0x04 20#define DESC92C_RATE9M 0x05 21#define DESC92C_RATE12M 0x06 22#define DESC92C_RATE18M 0x07 23#define DESC92C_RATE24M 0x08 24#define DESC92C_RATE36M 0x09 25#define DESC92C_RATE48M 0x0a 26#define DESC92C_RATE54M 0x0b 27 28/* MCS Rates, TxHT = 1 */ 29#define DESC92C_RATEMCS0 0x0c 30#define DESC92C_RATEMCS1 0x0d 31#define DESC92C_RATEMCS2 0x0e 32#define DESC92C_RATEMCS3 0x0f 33#define DESC92C_RATEMCS4 0x10 34#define DESC92C_RATEMCS5 0x11 35#define DESC92C_RATEMCS6 0x12 36#define DESC92C_RATEMCS7 0x13 37#define DESC92C_RATEMCS8 0x14 38#define DESC92C_RATEMCS9 0x15 39#define DESC92C_RATEMCS10 0x16 40#define DESC92C_RATEMCS11 0x17 41#define DESC92C_RATEMCS12 0x18 42#define DESC92C_RATEMCS13 0x19 43#define DESC92C_RATEMCS14 0x1a 44#define DESC92C_RATEMCS15 0x1b 45#define DESC92C_RATEMCS15_SG 0x1c 46#define DESC92C_RATEMCS32 0x20 47 48/* structure and define */ 49 50struct phy_rx_agc_info { 51 #ifdef __LITTLE_ENDIAN 52 u8 gain:7, trsw:1; 53 #else 54 u8 trsw:1, gain:7; 55 #endif 56}; 57 58struct phy_status_rpt { 59 struct phy_rx_agc_info path_agc[RF_PATH_MAX]; 60 u8 ch_corr[2]; 61 u8 cck_sig_qual_ofdm_pwdb_all; 62 u8 cck_agc_rpt_ofdm_cfosho_a; 63 u8 cck_rpt_b_ofdm_cfosho_b; 64 u8 rsvd_1;/* ch_corr_msb; */ 65 u8 noise_power_db_msb; 66 u8 path_cfotail[2]; 67 u8 pcts_mask[2]; 68 s8 stream_rxevm[2]; 69 u8 path_rxsnr[3]; 70 u8 noise_power_db_lsb; 71 u8 rsvd_2[3]; 72 u8 stream_csi[2]; 73 u8 stream_target_csi[2]; 74 s8 sig_evm; 75 u8 rsvd_3; 76 77#ifdef __LITTLE_ENDIAN 78 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 79 u8 sgi_en:1; 80 u8 rxsc:2; 81 u8 idle_long:1; 82 u8 r_ant_train_en:1; 83 u8 ant_sel_b:1; 84 u8 ant_sel:1; 85#else /* _BIG_ENDIAN_ */ 86 u8 ant_sel:1; 87 u8 ant_sel_b:1; 88 u8 r_ant_train_en:1; 89 u8 idle_long:1; 90 u8 rxsc:2; 91 u8 sgi_en:1; 92 u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */ 93#endif 94}; 95 96void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm, 97 struct odm_phy_status_info *pPhyInfo, 98 u8 *pPhyStatus, 99 struct odm_per_pkt_info *pPktinfo); 100 101#endif 102