1/* SPDX-License-Identifier: GPL-2.0 */ 2/****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7#ifndef __HALPWRSEQCMD_H__ 8#define __HALPWRSEQCMD_H__ 9 10#include <drv_types.h> 11 12/* The value of cmd: 4 bits */ 13#define PWR_CMD_READ 0x00 14#define PWR_CMD_WRITE 0x01 15#define PWR_CMD_POLLING 0x02 16#define PWR_CMD_DELAY 0x03 17#define PWR_CMD_END 0x04 18 19/* The value of cut_msk: 8 bits */ 20#define PWR_CUT_TESTCHIP_MSK BIT(0) 21#define PWR_CUT_A_MSK BIT(1) 22#define PWR_CUT_B_MSK BIT(2) 23#define PWR_CUT_C_MSK BIT(3) 24#define PWR_CUT_D_MSK BIT(4) 25#define PWR_CUT_E_MSK BIT(5) 26#define PWR_CUT_F_MSK BIT(6) 27#define PWR_CUT_G_MSK BIT(7) 28#define PWR_CUT_ALL_MSK 0xFF 29 30 31enum pwrseq_cmd_delat_unit { 32 PWRSEQ_DELAY_US, 33 PWRSEQ_DELAY_MS, 34}; 35 36struct wl_pwr_cfg { 37 u16 offset; 38 u8 cut_msk; 39 u8 cmd:4; 40 u8 msk; 41 u8 value; 42}; 43 44#define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset 45#define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk 46#define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd 47#define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk 48#define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value 49 50u8 rtl88eu_pwrseqcmdparsing(struct adapter *padapter, u8 cut_vers, 51 struct wl_pwr_cfg pwrcfgCmd[]); 52 53#endif 54