LXR linux/drivers/staging/rtl8188eu/include/rtl8188e

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/******************************************************************************
   3 *
   4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5 *
   6 ******************************************************************************/
   7#ifndef __RTL8188E_HAL_H__
   8#define __RTL8188E_HAL_H__
   9
  10
  11/* include HAL Related header after HAL Related compiling flags */
  12#include "rtl8188e_spec.h"
  13#include "hal8188e_phy_reg.h"
  14#include "hal8188e_phy_cfg.h"
  15#include "rtl8188e_dm.h"
  16#include "rtl8188e_recv.h"
  17#include "rtl8188e_xmit.h"
  18#include "rtl8188e_cmd.h"
  19#include "pwrseq.h"
  20#include "rtw_efuse.h"
  21#include "rtw_sreset.h"
  22#include "odm_precomp.h"
  23
  24/*  Fw Array */
  25#define Rtl8188E_FwImageArray           Rtl8188EFwImgArray
  26#define Rtl8188E_FWImgArrayLength       Rtl8188EFWImgArrayLength
  27
  28#define RTL8188E_FW_UMC_IMG                     "rtl8188E\\rtl8188efw.bin"
  29#define RTL8188E_PHY_REG                        "rtl8188E\\PHY_REG_1T.txt"
  30#define RTL8188E_PHY_RADIO_A                    "rtl8188E\\radio_a_1T.txt"
  31#define RTL8188E_PHY_RADIO_B                    "rtl8188E\\radio_b_1T.txt"
  32#define RTL8188E_AGC_TAB                        "rtl8188E\\AGC_TAB_1T.txt"
  33#define RTL8188E_PHY_MACREG                     "rtl8188E\\MAC_REG.txt"
  34#define RTL8188E_PHY_REG_PG                     "rtl8188E\\PHY_REG_PG.txt"
  35#define RTL8188E_PHY_REG_MP                     "rtl8188E\\PHY_REG_MP.txt"
  36
  37/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
  38#define Rtl8188E_NIC_PWR_ON_FLOW                rtl8188E_power_on_flow
  39#define Rtl8188E_NIC_RF_OFF_FLOW                rtl8188E_radio_off_flow
  40#define Rtl8188E_NIC_DISABLE_FLOW               rtl8188E_card_disable_flow
  41#define Rtl8188E_NIC_ENABLE_FLOW                rtl8188E_card_enable_flow
  42#define Rtl8188E_NIC_SUSPEND_FLOW               rtl8188E_suspend_flow
  43#define Rtl8188E_NIC_RESUME_FLOW                rtl8188E_resume_flow
  44#define Rtl8188E_NIC_PDN_FLOW                   rtl8188E_hwpdn_flow
  45#define Rtl8188E_NIC_LPS_ENTER_FLOW             rtl8188E_enter_lps_flow
  46#define Rtl8188E_NIC_LPS_LEAVE_FLOW             rtl8188E_leave_lps_flow
  47
  48#define DRVINFO_SZ      4 /*  unit is 8bytes */
  49#define PageNum_128(_Len)       (u32)(((_Len)>>7) + ((_Len) & 0x7F ? 1 : 0))
  50
  51/*  download firmware related data structure */
  52#define FW_8188E_SIZE                   0x4000 /* 16384,16k */
  53#define FW_8188E_START_ADDRESS          0x1000
  54#define FW_8188E_END_ADDRESS            0x1FFF /* 0x5FFF */
  55
  56#define MAX_PAGE_SIZE                   4096    /*  @ page : 4k bytes */
  57
  58#define IS_FW_HEADER_EXIST(_pFwHdr)                             \
  59        ((le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x92C0 ||  \
  60        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88C0 ||   \
  61        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x2300 ||   \
  62        (le16_to_cpu(_pFwHdr->signature)&0xFFF0) == 0x88E0)
  63
  64#define DRIVER_EARLY_INT_TIME           0x05
  65#define BCN_DMA_ATIME_INT_TIME          0x02
  66
  67enum usb_rx_agg_mode {
  68        USB_RX_AGG_DISABLE,
  69        USB_RX_AGG_DMA,
  70        USB_RX_AGG_USB,
  71        USB_RX_AGG_MIX
  72};
  73
  74#define MAX_RX_DMA_BUFFER_SIZE_88E                              \
  75      0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
  76              * WOLPattern(16*24))
  77              */
  78
  79#define MAX_TX_REPORT_BUFFER_SIZE               0x0400 /*  1k */
  80
  81
  82/*  BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
  83#define MAX_TX_QUEUE                    9
  84
  85#define TX_SELE_HQ                      BIT(0)          /*  High Queue */
  86#define TX_SELE_LQ                      BIT(1)          /*  Low Queue */
  87#define TX_SELE_NQ                      BIT(2)          /*  Normal Queue */
  88
  89/*  Note: We will divide number of page equally for each queue other
  90 *  than public queue!
  91 */
  92/*  22k = 22528 bytes = 176 pages (@page =  128 bytes) */
  93/*  must reserved about 7 pages for LPS =>  176-7 = 169 (0xA9) */
  94/*  2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
  95 *  null-data
  96 */
  97
  98#define TX_TOTAL_PAGE_NUMBER_88E                0xA9/*   169 (21632=> 21k) */
  99
 100#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
 101
 102/* Note: For Normal Chip Setting ,modify later */
 103#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER                 \
 104        TX_TOTAL_PAGE_NUMBER_88E  /* 0xA9 , 0xb0=>176=>22k */
 105#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E                 \
 106        (WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
 107
 108/* Chip specific */
 109#define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 110#define CHIP_BONDING_92C_1T2R   0x1
 111#define CHIP_BONDING_88C_USB_MCARD      0x2
 112#define CHIP_BONDING_88C_USB_HP 0x1
 113#include "HalVerDef.h"
 114#include "hal_com.h"
 115
 116/* Channel Plan */
 117enum ChannelPlan {
 118        CHPL_FCC        = 0,
 119        CHPL_IC         = 1,
 120        CHPL_ETSI       = 2,
 121        CHPL_SPA        = 3,
 122        CHPL_FRANCE     = 4,
 123        CHPL_MKK        = 5,
 124        CHPL_MKK1       = 6,
 125        CHPL_ISRAEL     = 7,
 126        CHPL_TELEC      = 8,
 127        CHPL_GLOBAL     = 9,
 128        CHPL_WORLD      = 10,
 129};
 130
 131struct txpowerinfo24g {
 132        u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 133        u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
 134        /* If only one tx, only BW20 and OFDM are used. */
 135        s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 136        s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 137        s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 138        s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 139};
 140
 141#define EFUSE_REAL_CONTENT_LEN          512
 142#define EFUSE_MAX_SECTION               16
 143#define EFUSE_IC_ID_OFFSET              506 /* For some inferior IC purpose*/
 144#define AVAILABLE_EFUSE_ADDR(addr)      (addr < EFUSE_REAL_CONTENT_LEN)
 145/*  To prevent out of boundary programming case, */
 146/*  leave 1byte and program full section */
 147/*  9bytes + 1byt + 5bytes and pre 1byte. */
 148/*  For worst case: */
 149/*  | 1byte|----8bytes----|1byte|--5bytes--| */
 150/*  |         |            Reserved(14bytes)          | */
 151
 152/*  PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
 153#define EFUSE_OOB_PROTECT_BYTES                 15
 154
 155#define         HWSET_MAX_SIZE_88E              512
 156
 157#define         EFUSE_REAL_CONTENT_LEN_88E      256
 158#define         EFUSE_MAP_LEN_88E               512
 159#define EFUSE_MAP_LEN                   EFUSE_MAP_LEN_88E
 160#define         EFUSE_MAX_SECTION_88E           64
 161#define         EFUSE_MAX_WORD_UNIT_88E         4
 162#define         EFUSE_IC_ID_OFFSET_88E          506
 163#define         AVAILABLE_EFUSE_ADDR_88E(addr)                  \
 164        (addr < EFUSE_REAL_CONTENT_LEN_88E)
 165/*  To prevent out of boundary programming case, leave 1byte and program
 166 *  full section
 167 */
 168/*  9bytes + 1byt + 5bytes and pre 1byte. */
 169/*  For worst case: */
 170/*  | 2byte|----8bytes----|1byte|--7bytes--| 92D */
 171/*  PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
 172#define         EFUSE_OOB_PROTECT_BYTES_88E     18
 173#define         EFUSE_PROTECT_BYTES_BANK_88E    16
 174
 175/* EFUSE for BT definition */
 176#define EFUSE_BT_REAL_CONTENT_LEN       1536    /*  512*3 */
 177#define EFUSE_BT_MAP_LEN                1024    /*  1k bytes */
 178#define EFUSE_BT_MAX_SECTION            128     /*  1024/8 */
 179
 180#define EFUSE_PROTECT_BYTES_BANK        16
 181
 182struct hal_data_8188e {
 183        struct HAL_VERSION      VersionID;
 184        u16     CustomerID;
 185        u16     FirmwareVersion;
 186        u16     FirmwareVersionRev;
 187        u16     FirmwareSubVersion;
 188        u16     FirmwareSignature;
 189        u8      PGMaxGroup;
 190        /* current WIFI_PHY values */
 191        u32     ReceiveConfig;
 192        enum wireless_mode CurrentWirelessMode;
 193        enum ht_channel_width CurrentChannelBW;
 194        u8      CurrentChannel;
 195        u8      nCur40MhzPrimeSC;/*  Control channel sub-carrier */
 196
 197        u16     BasicRateSet;
 198
 199        u8      BoardType;
 200
 201        /*  EEPROM setting. */
 202        u16     EEPROMVID;
 203        u16     EEPROMPID;
 204        u16     EEPROMSVID;
 205        u16     EEPROMSDID;
 206        u8      EEPROMCustomerID;
 207        u8      EEPROMSubCustomerID;
 208        u8      EEPROMVersion;
 209        u8      EEPROMRegulatory;
 210
 211        u8      bTXPowerDataReadFromEEPORM;
 212        u8      EEPROMThermalMeter;
 213        u8      bAPKThermalMeterIgnore;
 214
 215        bool    EepromOrEfuse;
 216        /* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
 217        u8      EfuseMap[2][HWSET_MAX_SIZE_512];
 218        u8      EfuseUsedPercentage;
 219        struct efuse_hal        EfuseHal;
 220
 221        u8      Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 222        u8      Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
 223        /* If only one tx, only BW20 and OFDM are used. */
 224        s8      CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 225        s8      OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 226        s8      BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 227        s8      BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
 228
 229        u8      TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 230        /*  For HT 40MHZ pwr */
 231        u8      TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 232        /*  For HT 40MHZ pwr */
 233        u8      TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 234        /*  HT 20<->40 Pwr diff */
 235        u8      TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 236        /*  For HT<->legacy pwr diff */
 237        u8      TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 238        /*  For power group */
 239        u8      PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 240        u8      PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
 241
 242        u8      LegacyHTTxPowerDiff;/*  Legacy to HT rate power diff */
 243        /*  The current Tx Power Level */
 244        u8      CurrentCckTxPwrIdx;
 245        u8      CurrentOfdm24GTxPwrIdx;
 246        u8      CurrentBW2024GTxPwrIdx;
 247        u8      CurrentBW4024GTxPwrIdx;
 248
 249
 250        /*  Read/write are allow for following hardware information variables */
 251        u8      framesync;
 252        u32     framesyncC34;
 253        u8      framesyncMonitor;
 254        u8      DefaultInitialGain[4];
 255        u8      pwrGroupCnt;
 256        u32     MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
 257        u32     CCKTxPowerLevelOriginalOffset;
 258
 259        u8      CrystalCap;
 260
 261        u32     AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
 262
 263        struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
 264
 265        u32     RfRegChnlVal[2];
 266
 267        /* RDG enable */
 268        bool     bRDGEnable;
 269
 270        /* for host message to fw */
 271        u8      LastHMEBoxNum;
 272
 273        u8      RegTxPause;
 274        /*  Beacon function related global variable. */
 275        u32     RegBcnCtrlVal;
 276        u8      RegFwHwTxQCtrl;
 277        u8      RegReg542;
 278        u8      RegCR_1;
 279
 280        struct dm_priv  dmpriv;
 281        struct odm_dm_struct odmpriv;
 282        struct sreset_priv srestpriv;
 283
 284        u8      CurAntenna;
 285        u8      AntDivCfg;
 286        u8      TRxAntDivType;
 287
 288
 289        u8      bDumpRxPkt;/* for debug */
 290        u8      bDumpTxPkt;/* for debug */
 291        u8      FwRsvdPageStartOffset; /* Reserve page start offset except
 292                                        *  beacon in TxQ.
 293                                        */
 294
 295        /*  2010/08/09 MH Add CU power down mode. */
 296        bool            pwrdown;
 297
 298        /*  Add for dual MAC  0--Mac0 1--Mac1 */
 299        u32     interfaceIndex;
 300
 301        u8      OutEpQueueSel;
 302        u8      OutEpNumber;
 303
 304        u16     EfuseUsedBytes;
 305
 306        /*  Auto FSM to Turn On, include clock, isolation, power control
 307         *  for MAC only
 308         */
 309        u8      bMacPwrCtrlOn;
 310
 311        u32     UsbBulkOutSize;
 312
 313        /*  Interrupt relatd register information. */
 314        u32     IntArray[3];/* HISR0,HISR1,HSISR */
 315        u32     IntrMask[3];
 316        u8      C2hArray[16];
 317        u8      UsbTxAggMode;
 318        u8      UsbTxAggDescNum;
 319        u16     HwRxPageSize;           /*  Hardware setting */
 320        u32     MaxUsbRxAggBlock;
 321
 322        enum usb_rx_agg_mode UsbRxAggMode;
 323        u8      UsbRxAggBlockCount;     /*  USB Block count. Block size is
 324                                         * 512-byte in high speed and 64-byte
 325                                         * in full speed
 326                                         */
 327        u8      UsbRxAggBlockTimeout;
 328        u8      UsbRxAggPageCount;      /*  8192C DMA page count */
 329        u8      UsbRxAggPageTimeout;
 330};
 331
 332void Hal_GetChnlGroup88E(u8 chnl, u8 *group);
 333
 334/*  rtl8188e_hal_init.c */
 335void _8051Reset88E(struct adapter *padapter);
 336void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
 337
 338
 339s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
 340
 341/*  EFuse */
 342void Hal_InitPGData88E(struct adapter *padapter);
 343void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
 344void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
 345                            bool AutoLoadFail);
 346
 347void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
 348                                bool AutoLoadFail);
 349void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
 350                                 bool AutoLoadFail);
 351void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
 352                                 bool AutoLoadFail);
 353void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
 354                                 bool AutoLoadFail);
 355void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
 356                              bool AutoloadFail);
 357void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
 358                              bool AutoLoadFail);
 359void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
 360                                bool AutoLoadFail);
 361void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
 362                                bool AutoLoadFail);
 363
 364/*  register */
 365
 366void rtl8188e_start_thread(struct adapter *padapter);
 367void rtl8188e_stop_thread(struct adapter *padapter);
 368
 369s32 iol_execute(struct adapter *padapter, u8 control);
 370void iol_mode_enable(struct adapter *padapter, u8 enable);
 371s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
 372void rtw_cancel_all_timer(struct adapter *padapter);
 373
 374#endif /* __RTL8188E_HAL_H__ */
 375