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11#include <linux/clk.h>
12#include <linux/version.h>
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/slab.h>
16#include <linux/spinlock.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <linux/interrupt.h>
20#include <linux/ioport.h>
21#include <linux/io.h>
22#include <linux/list.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/of.h>
26#include <linux/acpi.h>
27#include <linux/pinctrl/consumer.h>
28#include <linux/reset.h>
29
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/of.h>
33#include <linux/usb/otg.h>
34
35#include "core.h"
36#include "gadget.h"
37#include "io.h"
38
39#include "debug.h"
40
41#define DWC3_DEFAULT_AUTOSUSPEND_DELAY 5000
42
43
44
45
46
47static int dwc3_get_dr_mode(struct dwc3 *dwc)
48{
49 enum usb_dr_mode mode;
50 struct device *dev = dwc->dev;
51 unsigned int hw_mode;
52
53 if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
54 dwc->dr_mode = USB_DR_MODE_OTG;
55
56 mode = dwc->dr_mode;
57 hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
58
59 switch (hw_mode) {
60 case DWC3_GHWPARAMS0_MODE_GADGET:
61 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
62 dev_err(dev,
63 "Controller does not support host mode.\n");
64 return -EINVAL;
65 }
66 mode = USB_DR_MODE_PERIPHERAL;
67 break;
68 case DWC3_GHWPARAMS0_MODE_HOST:
69 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
70 dev_err(dev,
71 "Controller does not support device mode.\n");
72 return -EINVAL;
73 }
74 mode = USB_DR_MODE_HOST;
75 break;
76 default:
77 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
78 mode = USB_DR_MODE_HOST;
79 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
80 mode = USB_DR_MODE_PERIPHERAL;
81
82
83
84
85
86
87 if (mode == USB_DR_MODE_OTG &&
88 dwc->revision >= DWC3_REVISION_330A)
89 mode = USB_DR_MODE_PERIPHERAL;
90 }
91
92 if (mode != dwc->dr_mode) {
93 dev_warn(dev,
94 "Configuration mismatch. dr_mode forced to %s\n",
95 mode == USB_DR_MODE_HOST ? "host" : "gadget");
96
97 dwc->dr_mode = mode;
98 }
99
100 return 0;
101}
102
103void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
104{
105 u32 reg;
106
107 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
108 reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
109 reg |= DWC3_GCTL_PRTCAPDIR(mode);
110 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
111
112 dwc->current_dr_role = mode;
113}
114
115static void __dwc3_set_mode(struct work_struct *work)
116{
117 struct dwc3 *dwc = work_to_dwc(work);
118 unsigned long flags;
119 int ret;
120
121 if (dwc->dr_mode != USB_DR_MODE_OTG)
122 return;
123
124 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
125 dwc3_otg_update(dwc, 0);
126
127 if (!dwc->desired_dr_role)
128 return;
129
130 if (dwc->desired_dr_role == dwc->current_dr_role)
131 return;
132
133 if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
134 return;
135
136 switch (dwc->current_dr_role) {
137 case DWC3_GCTL_PRTCAP_HOST:
138 dwc3_host_exit(dwc);
139 break;
140 case DWC3_GCTL_PRTCAP_DEVICE:
141 dwc3_gadget_exit(dwc);
142 dwc3_event_buffers_cleanup(dwc);
143 break;
144 case DWC3_GCTL_PRTCAP_OTG:
145 dwc3_otg_exit(dwc);
146 spin_lock_irqsave(&dwc->lock, flags);
147 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
148 spin_unlock_irqrestore(&dwc->lock, flags);
149 dwc3_otg_update(dwc, 1);
150 break;
151 default:
152 break;
153 }
154
155 spin_lock_irqsave(&dwc->lock, flags);
156
157 dwc3_set_prtcap(dwc, dwc->desired_dr_role);
158
159 spin_unlock_irqrestore(&dwc->lock, flags);
160
161 switch (dwc->desired_dr_role) {
162 case DWC3_GCTL_PRTCAP_HOST:
163 ret = dwc3_host_init(dwc);
164 if (ret) {
165 dev_err(dwc->dev, "failed to initialize host\n");
166 } else {
167 if (dwc->usb2_phy)
168 otg_set_vbus(dwc->usb2_phy->otg, true);
169 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
170 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
171 phy_calibrate(dwc->usb2_generic_phy);
172 }
173 break;
174 case DWC3_GCTL_PRTCAP_DEVICE:
175 dwc3_event_buffers_setup(dwc);
176
177 if (dwc->usb2_phy)
178 otg_set_vbus(dwc->usb2_phy->otg, false);
179 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
180 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
181
182 ret = dwc3_gadget_init(dwc);
183 if (ret)
184 dev_err(dwc->dev, "failed to initialize peripheral\n");
185 break;
186 case DWC3_GCTL_PRTCAP_OTG:
187 dwc3_otg_init(dwc);
188 dwc3_otg_update(dwc, 0);
189 break;
190 default:
191 break;
192 }
193
194}
195
196void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
197{
198 unsigned long flags;
199
200 spin_lock_irqsave(&dwc->lock, flags);
201 dwc->desired_dr_role = mode;
202 spin_unlock_irqrestore(&dwc->lock, flags);
203
204 queue_work(system_freezable_wq, &dwc->drd_work);
205}
206
207u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
208{
209 struct dwc3 *dwc = dep->dwc;
210 u32 reg;
211
212 dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
213 DWC3_GDBGFIFOSPACE_NUM(dep->number) |
214 DWC3_GDBGFIFOSPACE_TYPE(type));
215
216 reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
217
218 return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
219}
220
221
222
223
224
225static int dwc3_core_soft_reset(struct dwc3 *dwc)
226{
227 u32 reg;
228 int retries = 1000;
229 int ret;
230
231 usb_phy_init(dwc->usb2_phy);
232 usb_phy_init(dwc->usb3_phy);
233 ret = phy_init(dwc->usb2_generic_phy);
234 if (ret < 0)
235 return ret;
236
237 ret = phy_init(dwc->usb3_generic_phy);
238 if (ret < 0) {
239 phy_exit(dwc->usb2_generic_phy);
240 return ret;
241 }
242
243
244
245
246
247
248 if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
249 return 0;
250
251 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
252 reg |= DWC3_DCTL_CSFTRST;
253 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
254
255 do {
256 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
257 if (!(reg & DWC3_DCTL_CSFTRST))
258 goto done;
259
260 udelay(1);
261 } while (--retries);
262
263 phy_exit(dwc->usb3_generic_phy);
264 phy_exit(dwc->usb2_generic_phy);
265
266 return -ETIMEDOUT;
267
268done:
269
270
271
272
273
274 if (dwc3_is_usb31(dwc))
275 msleep(50);
276
277 return 0;
278}
279
280static const struct clk_bulk_data dwc3_core_clks[] = {
281 { .id = "ref" },
282 { .id = "bus_early" },
283 { .id = "suspend" },
284};
285
286
287
288
289
290static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
291{
292 u32 reg;
293 u32 dft;
294
295 if (dwc->revision < DWC3_REVISION_250A)
296 return;
297
298 if (dwc->fladj == 0)
299 return;
300
301 reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
302 dft = reg & DWC3_GFLADJ_30MHZ_MASK;
303 if (!dev_WARN_ONCE(dwc->dev, dft == dwc->fladj,
304 "request value same as default, ignoring\n")) {
305 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
306 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
307 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
308 }
309}
310
311
312
313
314
315
316static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
317 struct dwc3_event_buffer *evt)
318{
319 dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
320}
321
322
323
324
325
326
327
328
329
330static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
331 unsigned length)
332{
333 struct dwc3_event_buffer *evt;
334
335 evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
336 if (!evt)
337 return ERR_PTR(-ENOMEM);
338
339 evt->dwc = dwc;
340 evt->length = length;
341 evt->cache = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
342 if (!evt->cache)
343 return ERR_PTR(-ENOMEM);
344
345 evt->buf = dma_alloc_coherent(dwc->sysdev, length,
346 &evt->dma, GFP_KERNEL);
347 if (!evt->buf)
348 return ERR_PTR(-ENOMEM);
349
350 return evt;
351}
352
353
354
355
356
357static void dwc3_free_event_buffers(struct dwc3 *dwc)
358{
359 struct dwc3_event_buffer *evt;
360
361 evt = dwc->ev_buf;
362 if (evt)
363 dwc3_free_one_event_buffer(dwc, evt);
364}
365
366
367
368
369
370
371
372
373
374static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
375{
376 struct dwc3_event_buffer *evt;
377
378 evt = dwc3_alloc_one_event_buffer(dwc, length);
379 if (IS_ERR(evt)) {
380 dev_err(dwc->dev, "can't allocate event buffer\n");
381 return PTR_ERR(evt);
382 }
383 dwc->ev_buf = evt;
384
385 return 0;
386}
387
388
389
390
391
392
393
394int dwc3_event_buffers_setup(struct dwc3 *dwc)
395{
396 struct dwc3_event_buffer *evt;
397
398 evt = dwc->ev_buf;
399 evt->lpos = 0;
400 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
401 lower_32_bits(evt->dma));
402 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
403 upper_32_bits(evt->dma));
404 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
405 DWC3_GEVNTSIZ_SIZE(evt->length));
406 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
407
408 return 0;
409}
410
411void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
412{
413 struct dwc3_event_buffer *evt;
414
415 evt = dwc->ev_buf;
416
417 evt->lpos = 0;
418
419 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
420 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
421 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
422 | DWC3_GEVNTSIZ_SIZE(0));
423 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
424}
425
426static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
427{
428 if (!dwc->has_hibernation)
429 return 0;
430
431 if (!dwc->nr_scratch)
432 return 0;
433
434 dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
435 DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
436 if (!dwc->scratchbuf)
437 return -ENOMEM;
438
439 return 0;
440}
441
442static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
443{
444 dma_addr_t scratch_addr;
445 u32 param;
446 int ret;
447
448 if (!dwc->has_hibernation)
449 return 0;
450
451 if (!dwc->nr_scratch)
452 return 0;
453
454
455 if (!WARN_ON(dwc->scratchbuf))
456 return 0;
457
458 scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
459 dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
460 DMA_BIDIRECTIONAL);
461 if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
462 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
463 ret = -EFAULT;
464 goto err0;
465 }
466
467 dwc->scratch_addr = scratch_addr;
468
469 param = lower_32_bits(scratch_addr);
470
471 ret = dwc3_send_gadget_generic_command(dwc,
472 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
473 if (ret < 0)
474 goto err1;
475
476 param = upper_32_bits(scratch_addr);
477
478 ret = dwc3_send_gadget_generic_command(dwc,
479 DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
480 if (ret < 0)
481 goto err1;
482
483 return 0;
484
485err1:
486 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
487 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
488
489err0:
490 return ret;
491}
492
493static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
494{
495 if (!dwc->has_hibernation)
496 return;
497
498 if (!dwc->nr_scratch)
499 return;
500
501
502 if (!WARN_ON(dwc->scratchbuf))
503 return;
504
505 dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
506 DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
507 kfree(dwc->scratchbuf);
508}
509
510static void dwc3_core_num_eps(struct dwc3 *dwc)
511{
512 struct dwc3_hwparams *parms = &dwc->hwparams;
513
514 dwc->num_eps = DWC3_NUM_EPS(parms);
515}
516
517static void dwc3_cache_hwparams(struct dwc3 *dwc)
518{
519 struct dwc3_hwparams *parms = &dwc->hwparams;
520
521 parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
522 parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
523 parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
524 parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
525 parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
526 parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
527 parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
528 parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
529 parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
530}
531
532static int dwc3_core_ulpi_init(struct dwc3 *dwc)
533{
534 int intf;
535 int ret = 0;
536
537 intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
538
539 if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
540 (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
541 dwc->hsphy_interface &&
542 !strncmp(dwc->hsphy_interface, "ulpi", 4)))
543 ret = dwc3_ulpi_init(dwc);
544
545 return ret;
546}
547
548
549
550
551
552
553
554
555
556static int dwc3_phy_setup(struct dwc3 *dwc)
557{
558 u32 reg;
559
560 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
561
562
563
564
565
566 reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
567
568
569
570
571
572
573
574 if (dwc->revision > DWC3_REVISION_194A)
575 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
576
577 if (dwc->u2ss_inp3_quirk)
578 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
579
580 if (dwc->dis_rxdet_inp3_quirk)
581 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
582
583 if (dwc->req_p1p2p3_quirk)
584 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
585
586 if (dwc->del_p1p2p3_quirk)
587 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
588
589 if (dwc->del_phy_power_chg_quirk)
590 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
591
592 if (dwc->lfps_filter_quirk)
593 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
594
595 if (dwc->rx_detect_poll_quirk)
596 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
597
598 if (dwc->tx_de_emphasis_quirk)
599 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
600
601 if (dwc->dis_u3_susphy_quirk)
602 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
603
604 if (dwc->dis_del_phy_power_chg_quirk)
605 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
606
607 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
608
609 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
610
611
612 switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
613 case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
614 if (dwc->hsphy_interface &&
615 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
616 reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
617 break;
618 } else if (dwc->hsphy_interface &&
619 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
620 reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
621 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
622 } else {
623
624 if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
625 break;
626 }
627
628 case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
629
630 default:
631 break;
632 }
633
634 switch (dwc->hsphy_mode) {
635 case USBPHY_INTERFACE_MODE_UTMI:
636 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
637 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
638 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
639 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
640 break;
641 case USBPHY_INTERFACE_MODE_UTMIW:
642 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
643 DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
644 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
645 DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
646 break;
647 default:
648 break;
649 }
650
651
652
653
654
655
656
657 if (dwc->revision > DWC3_REVISION_194A)
658 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
659
660 if (dwc->dis_u2_susphy_quirk)
661 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
662
663 if (dwc->dis_enblslpm_quirk)
664 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
665 else
666 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
667
668 if (dwc->dis_u2_freeclk_exists_quirk)
669 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
670
671 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
672
673 return 0;
674}
675
676static void dwc3_core_exit(struct dwc3 *dwc)
677{
678 dwc3_event_buffers_cleanup(dwc);
679
680 usb_phy_shutdown(dwc->usb2_phy);
681 usb_phy_shutdown(dwc->usb3_phy);
682 phy_exit(dwc->usb2_generic_phy);
683 phy_exit(dwc->usb3_generic_phy);
684
685 usb_phy_set_suspend(dwc->usb2_phy, 1);
686 usb_phy_set_suspend(dwc->usb3_phy, 1);
687 phy_power_off(dwc->usb2_generic_phy);
688 phy_power_off(dwc->usb3_generic_phy);
689 clk_bulk_disable(dwc->num_clks, dwc->clks);
690 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
691 reset_control_assert(dwc->reset);
692}
693
694static bool dwc3_core_is_valid(struct dwc3 *dwc)
695{
696 u32 reg;
697
698 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
699
700
701 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
702
703 dwc->revision = reg;
704 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
705
706 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
707 dwc->revision |= DWC3_REVISION_IS_DWC31;
708 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
709 } else {
710 return false;
711 }
712
713 return true;
714}
715
716static void dwc3_core_setup_global_control(struct dwc3 *dwc)
717{
718 u32 hwparams4 = dwc->hwparams.hwparams4;
719 u32 reg;
720
721 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
722 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
723
724 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
725 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
726
727
728
729
730
731
732
733
734
735
736
737
738 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
739 dwc->dr_mode == USB_DR_MODE_OTG) &&
740 (dwc->revision >= DWC3_REVISION_210A &&
741 dwc->revision <= DWC3_REVISION_250A))
742 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
743 else
744 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
745 break;
746 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
747
748 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
749
750
751
752
753
754 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
755 break;
756 default:
757
758 break;
759 }
760
761
762 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
763 dev_info(dwc->dev, "Running with FPGA optimizations\n");
764 dwc->is_fpga = true;
765 }
766
767 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
768 "disable_scramble cannot be used on non-FPGA builds\n");
769
770 if (dwc->disable_scramble_quirk && dwc->is_fpga)
771 reg |= DWC3_GCTL_DISSCRAMBLE;
772 else
773 reg &= ~DWC3_GCTL_DISSCRAMBLE;
774
775 if (dwc->u2exit_lfps_quirk)
776 reg |= DWC3_GCTL_U2EXIT_LFPS;
777
778
779
780
781
782
783
784 if (dwc->revision < DWC3_REVISION_190A)
785 reg |= DWC3_GCTL_U2RSTECN;
786
787 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
788}
789
790static int dwc3_core_get_phy(struct dwc3 *dwc);
791static int dwc3_core_ulpi_init(struct dwc3 *dwc);
792
793
794static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
795{
796 struct device *dev = dwc->dev;
797
798 bool incrx_mode;
799
800 u32 incrx_size;
801 u32 *vals;
802 u32 cfg;
803 int ntype;
804 int ret;
805 int i;
806
807 cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
808
809
810
811
812
813
814
815
816 ntype = device_property_read_u32_array(dev,
817 "snps,incr-burst-type-adjustment", NULL, 0);
818 if (ntype <= 0)
819 return;
820
821 vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
822 if (!vals) {
823 dev_err(dev, "Error to get memory\n");
824 return;
825 }
826
827
828 ret = device_property_read_u32_array(dev,
829 "snps,incr-burst-type-adjustment", vals, ntype);
830 if (ret) {
831 kfree(vals);
832 dev_err(dev, "Error to get property\n");
833 return;
834 }
835
836 incrx_size = *vals;
837
838 if (ntype > 1) {
839
840 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
841 for (i = 1; i < ntype; i++) {
842 if (vals[i] > incrx_size)
843 incrx_size = vals[i];
844 }
845 } else {
846
847 incrx_mode = INCRX_BURST_MODE;
848 }
849
850 kfree(vals);
851
852
853 cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
854 if (incrx_mode)
855 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
856 switch (incrx_size) {
857 case 256:
858 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
859 break;
860 case 128:
861 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
862 break;
863 case 64:
864 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
865 break;
866 case 32:
867 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
868 break;
869 case 16:
870 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
871 break;
872 case 8:
873 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
874 break;
875 case 4:
876 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
877 break;
878 case 1:
879 break;
880 default:
881 dev_err(dev, "Invalid property\n");
882 break;
883 }
884
885 dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
886}
887
888
889
890
891
892
893
894static int dwc3_core_init(struct dwc3 *dwc)
895{
896 u32 reg;
897 int ret;
898
899
900
901
902
903 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
904
905
906 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
907 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
908 if (dwc->maximum_speed == USB_SPEED_SUPER)
909 dwc->maximum_speed = USB_SPEED_HIGH;
910 }
911
912 ret = dwc3_phy_setup(dwc);
913 if (ret)
914 goto err0;
915
916 if (!dwc->ulpi_ready) {
917 ret = dwc3_core_ulpi_init(dwc);
918 if (ret)
919 goto err0;
920 dwc->ulpi_ready = true;
921 }
922
923 if (!dwc->phys_ready) {
924 ret = dwc3_core_get_phy(dwc);
925 if (ret)
926 goto err0a;
927 dwc->phys_ready = true;
928 }
929
930 ret = dwc3_core_soft_reset(dwc);
931 if (ret)
932 goto err0a;
933
934 dwc3_core_setup_global_control(dwc);
935 dwc3_core_num_eps(dwc);
936
937 ret = dwc3_setup_scratch_buffers(dwc);
938 if (ret)
939 goto err1;
940
941
942 dwc3_frame_length_adjustment(dwc);
943
944 dwc3_set_incr_burst_type(dwc);
945
946 usb_phy_set_suspend(dwc->usb2_phy, 0);
947 usb_phy_set_suspend(dwc->usb3_phy, 0);
948 ret = phy_power_on(dwc->usb2_generic_phy);
949 if (ret < 0)
950 goto err2;
951
952 ret = phy_power_on(dwc->usb3_generic_phy);
953 if (ret < 0)
954 goto err3;
955
956 ret = dwc3_event_buffers_setup(dwc);
957 if (ret) {
958 dev_err(dwc->dev, "failed to setup event buffers\n");
959 goto err4;
960 }
961
962
963
964
965
966
967 if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
968 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
969 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
970 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
971 }
972
973 if (dwc->revision >= DWC3_REVISION_250A) {
974 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
975
976
977
978
979
980 if (dwc->revision >= DWC3_REVISION_290A)
981 reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
982
983 if (dwc->dis_tx_ipgap_linecheck_quirk)
984 reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
985
986 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
987 }
988
989 if (dwc->dr_mode == USB_DR_MODE_HOST ||
990 dwc->dr_mode == USB_DR_MODE_OTG) {
991 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
992
993
994
995
996
997
998
999
1000 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1001
1002 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1003 }
1004
1005
1006
1007
1008
1009 if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1010 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1011 u8 rx_maxburst = dwc->rx_max_burst_prd;
1012 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1013 u8 tx_maxburst = dwc->tx_max_burst_prd;
1014
1015 if (rx_thr_num && rx_maxburst) {
1016 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1017 reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1018
1019 reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1020 reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1021
1022 reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1023 reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1024
1025 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1026 }
1027
1028 if (tx_thr_num && tx_maxburst) {
1029 reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1030 reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1031
1032 reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1033 reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1034
1035 reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1036 reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1037
1038 dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1039 }
1040 }
1041
1042 return 0;
1043
1044err4:
1045 phy_power_off(dwc->usb3_generic_phy);
1046
1047err3:
1048 phy_power_off(dwc->usb2_generic_phy);
1049
1050err2:
1051 usb_phy_set_suspend(dwc->usb2_phy, 1);
1052 usb_phy_set_suspend(dwc->usb3_phy, 1);
1053
1054err1:
1055 usb_phy_shutdown(dwc->usb2_phy);
1056 usb_phy_shutdown(dwc->usb3_phy);
1057 phy_exit(dwc->usb2_generic_phy);
1058 phy_exit(dwc->usb3_generic_phy);
1059
1060err0a:
1061 dwc3_ulpi_exit(dwc);
1062
1063err0:
1064 return ret;
1065}
1066
1067static int dwc3_core_get_phy(struct dwc3 *dwc)
1068{
1069 struct device *dev = dwc->dev;
1070 struct device_node *node = dev->of_node;
1071 int ret;
1072
1073 if (node) {
1074 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1075 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1076 } else {
1077 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1078 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1079 }
1080
1081 if (IS_ERR(dwc->usb2_phy)) {
1082 ret = PTR_ERR(dwc->usb2_phy);
1083 if (ret == -ENXIO || ret == -ENODEV) {
1084 dwc->usb2_phy = NULL;
1085 } else if (ret == -EPROBE_DEFER) {
1086 return ret;
1087 } else {
1088 dev_err(dev, "no usb2 phy configured\n");
1089 return ret;
1090 }
1091 }
1092
1093 if (IS_ERR(dwc->usb3_phy)) {
1094 ret = PTR_ERR(dwc->usb3_phy);
1095 if (ret == -ENXIO || ret == -ENODEV) {
1096 dwc->usb3_phy = NULL;
1097 } else if (ret == -EPROBE_DEFER) {
1098 return ret;
1099 } else {
1100 dev_err(dev, "no usb3 phy configured\n");
1101 return ret;
1102 }
1103 }
1104
1105 dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1106 if (IS_ERR(dwc->usb2_generic_phy)) {
1107 ret = PTR_ERR(dwc->usb2_generic_phy);
1108 if (ret == -ENOSYS || ret == -ENODEV) {
1109 dwc->usb2_generic_phy = NULL;
1110 } else if (ret == -EPROBE_DEFER) {
1111 return ret;
1112 } else {
1113 dev_err(dev, "no usb2 phy configured\n");
1114 return ret;
1115 }
1116 }
1117
1118 dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1119 if (IS_ERR(dwc->usb3_generic_phy)) {
1120 ret = PTR_ERR(dwc->usb3_generic_phy);
1121 if (ret == -ENOSYS || ret == -ENODEV) {
1122 dwc->usb3_generic_phy = NULL;
1123 } else if (ret == -EPROBE_DEFER) {
1124 return ret;
1125 } else {
1126 dev_err(dev, "no usb3 phy configured\n");
1127 return ret;
1128 }
1129 }
1130
1131 return 0;
1132}
1133
1134static int dwc3_core_init_mode(struct dwc3 *dwc)
1135{
1136 struct device *dev = dwc->dev;
1137 int ret;
1138
1139 switch (dwc->dr_mode) {
1140 case USB_DR_MODE_PERIPHERAL:
1141 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1142
1143 if (dwc->usb2_phy)
1144 otg_set_vbus(dwc->usb2_phy->otg, false);
1145 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1146 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1147
1148 ret = dwc3_gadget_init(dwc);
1149 if (ret) {
1150 if (ret != -EPROBE_DEFER)
1151 dev_err(dev, "failed to initialize gadget\n");
1152 return ret;
1153 }
1154 break;
1155 case USB_DR_MODE_HOST:
1156 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1157
1158 if (dwc->usb2_phy)
1159 otg_set_vbus(dwc->usb2_phy->otg, true);
1160 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1161 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1162
1163 ret = dwc3_host_init(dwc);
1164 if (ret) {
1165 if (ret != -EPROBE_DEFER)
1166 dev_err(dev, "failed to initialize host\n");
1167 return ret;
1168 }
1169 phy_calibrate(dwc->usb2_generic_phy);
1170 break;
1171 case USB_DR_MODE_OTG:
1172 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1173 ret = dwc3_drd_init(dwc);
1174 if (ret) {
1175 if (ret != -EPROBE_DEFER)
1176 dev_err(dev, "failed to initialize dual-role\n");
1177 return ret;
1178 }
1179 break;
1180 default:
1181 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1182 return -EINVAL;
1183 }
1184
1185 return 0;
1186}
1187
1188static void dwc3_core_exit_mode(struct dwc3 *dwc)
1189{
1190 switch (dwc->dr_mode) {
1191 case USB_DR_MODE_PERIPHERAL:
1192 dwc3_gadget_exit(dwc);
1193 break;
1194 case USB_DR_MODE_HOST:
1195 dwc3_host_exit(dwc);
1196 break;
1197 case USB_DR_MODE_OTG:
1198 dwc3_drd_exit(dwc);
1199 break;
1200 default:
1201
1202 break;
1203 }
1204}
1205
1206static void dwc3_get_properties(struct dwc3 *dwc)
1207{
1208 struct device *dev = dwc->dev;
1209 u8 lpm_nyet_threshold;
1210 u8 tx_de_emphasis;
1211 u8 hird_threshold;
1212 u8 rx_thr_num_pkt_prd;
1213 u8 rx_max_burst_prd;
1214 u8 tx_thr_num_pkt_prd;
1215 u8 tx_max_burst_prd;
1216
1217
1218 lpm_nyet_threshold = 0xf;
1219
1220
1221 tx_de_emphasis = 1;
1222
1223
1224
1225
1226
1227 hird_threshold = 12;
1228
1229 dwc->maximum_speed = usb_get_maximum_speed(dev);
1230 dwc->dr_mode = usb_get_dr_mode(dev);
1231 dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1232
1233 dwc->sysdev_is_parent = device_property_read_bool(dev,
1234 "linux,sysdev_is_parent");
1235 if (dwc->sysdev_is_parent)
1236 dwc->sysdev = dwc->dev->parent;
1237 else
1238 dwc->sysdev = dwc->dev;
1239
1240 dwc->has_lpm_erratum = device_property_read_bool(dev,
1241 "snps,has-lpm-erratum");
1242 device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1243 &lpm_nyet_threshold);
1244 dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1245 "snps,is-utmi-l1-suspend");
1246 device_property_read_u8(dev, "snps,hird-threshold",
1247 &hird_threshold);
1248 dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1249 "snps,dis-start-transfer-quirk");
1250 dwc->usb3_lpm_capable = device_property_read_bool(dev,
1251 "snps,usb3_lpm_capable");
1252 dwc->usb2_lpm_disable = device_property_read_bool(dev,
1253 "snps,usb2-lpm-disable");
1254 device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1255 &rx_thr_num_pkt_prd);
1256 device_property_read_u8(dev, "snps,rx-max-burst-prd",
1257 &rx_max_burst_prd);
1258 device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1259 &tx_thr_num_pkt_prd);
1260 device_property_read_u8(dev, "snps,tx-max-burst-prd",
1261 &tx_max_burst_prd);
1262
1263 dwc->disable_scramble_quirk = device_property_read_bool(dev,
1264 "snps,disable_scramble_quirk");
1265 dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1266 "snps,u2exit_lfps_quirk");
1267 dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1268 "snps,u2ss_inp3_quirk");
1269 dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1270 "snps,req_p1p2p3_quirk");
1271 dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1272 "snps,del_p1p2p3_quirk");
1273 dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1274 "snps,del_phy_power_chg_quirk");
1275 dwc->lfps_filter_quirk = device_property_read_bool(dev,
1276 "snps,lfps_filter_quirk");
1277 dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1278 "snps,rx_detect_poll_quirk");
1279 dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1280 "snps,dis_u3_susphy_quirk");
1281 dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1282 "snps,dis_u2_susphy_quirk");
1283 dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1284 "snps,dis_enblslpm_quirk");
1285 dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1286 "snps,dis_rxdet_inp3_quirk");
1287 dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1288 "snps,dis-u2-freeclk-exists-quirk");
1289 dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1290 "snps,dis-del-phy-power-chg-quirk");
1291 dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1292 "snps,dis-tx-ipgap-linecheck-quirk");
1293
1294 dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1295 "snps,tx_de_emphasis_quirk");
1296 device_property_read_u8(dev, "snps,tx_de_emphasis",
1297 &tx_de_emphasis);
1298 device_property_read_string(dev, "snps,hsphy_interface",
1299 &dwc->hsphy_interface);
1300 device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1301 &dwc->fladj);
1302
1303 dwc->dis_metastability_quirk = device_property_read_bool(dev,
1304 "snps,dis_metastability_quirk");
1305
1306 dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1307 dwc->tx_de_emphasis = tx_de_emphasis;
1308
1309 dwc->hird_threshold = hird_threshold
1310 | (dwc->is_utmi_l1_suspend << 4);
1311
1312 dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1313 dwc->rx_max_burst_prd = rx_max_burst_prd;
1314
1315 dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1316 dwc->tx_max_burst_prd = tx_max_burst_prd;
1317
1318 dwc->imod_interval = 0;
1319}
1320
1321
1322bool dwc3_has_imod(struct dwc3 *dwc)
1323{
1324 return ((dwc3_is_usb3(dwc) &&
1325 dwc->revision >= DWC3_REVISION_300A) ||
1326 (dwc3_is_usb31(dwc) &&
1327 dwc->revision >= DWC3_USB31_REVISION_120A));
1328}
1329
1330static void dwc3_check_params(struct dwc3 *dwc)
1331{
1332 struct device *dev = dwc->dev;
1333
1334
1335 if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1336 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1337 dwc->imod_interval = 0;
1338 }
1339
1340
1341
1342
1343
1344
1345
1346
1347 if (!dwc->imod_interval &&
1348 (dwc->revision == DWC3_REVISION_300A))
1349 dwc->imod_interval = 1;
1350
1351
1352 switch (dwc->maximum_speed) {
1353 case USB_SPEED_LOW:
1354 case USB_SPEED_FULL:
1355 case USB_SPEED_HIGH:
1356 case USB_SPEED_SUPER:
1357 case USB_SPEED_SUPER_PLUS:
1358 break;
1359 default:
1360 dev_err(dev, "invalid maximum_speed parameter %d\n",
1361 dwc->maximum_speed);
1362
1363 case USB_SPEED_UNKNOWN:
1364
1365 dwc->maximum_speed = USB_SPEED_SUPER;
1366
1367
1368
1369
1370 if (dwc3_is_usb31(dwc) &&
1371 (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1372 DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1373 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1374
1375 break;
1376 }
1377}
1378
1379static int dwc3_probe(struct platform_device *pdev)
1380{
1381 struct device *dev = &pdev->dev;
1382 struct resource *res, dwc_res;
1383 struct dwc3 *dwc;
1384
1385 int ret;
1386
1387 void __iomem *regs;
1388
1389 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1390 if (!dwc)
1391 return -ENOMEM;
1392
1393 dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1394 GFP_KERNEL);
1395 if (!dwc->clks)
1396 return -ENOMEM;
1397
1398 dwc->dev = dev;
1399
1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1401 if (!res) {
1402 dev_err(dev, "missing memory resource\n");
1403 return -ENODEV;
1404 }
1405
1406 dwc->xhci_resources[0].start = res->start;
1407 dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1408 DWC3_XHCI_REGS_END;
1409 dwc->xhci_resources[0].flags = res->flags;
1410 dwc->xhci_resources[0].name = res->name;
1411
1412
1413
1414
1415
1416 dwc_res = *res;
1417 dwc_res.start += DWC3_GLOBALS_REGS_START;
1418
1419 regs = devm_ioremap_resource(dev, &dwc_res);
1420 if (IS_ERR(regs))
1421 return PTR_ERR(regs);
1422
1423 dwc->regs = regs;
1424 dwc->regs_size = resource_size(&dwc_res);
1425
1426 if (!dwc3_core_is_valid(dwc)) {
1427 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1428 return -ENODEV;
1429 }
1430
1431 dwc3_get_properties(dwc);
1432
1433 dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1434 if (IS_ERR(dwc->reset))
1435 return PTR_ERR(dwc->reset);
1436
1437 if (dev->of_node) {
1438 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1439
1440 ret = clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1441 if (ret == -EPROBE_DEFER)
1442 return ret;
1443
1444
1445
1446
1447 if (ret)
1448 dwc->num_clks = 0;
1449 }
1450
1451 ret = reset_control_deassert(dwc->reset);
1452 if (ret)
1453 goto put_clks;
1454
1455 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1456 if (ret)
1457 goto assert_reset;
1458
1459 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1460 if (ret)
1461 goto unprepare_clks;
1462
1463 platform_set_drvdata(pdev, dwc);
1464 dwc3_cache_hwparams(dwc);
1465
1466 spin_lock_init(&dwc->lock);
1467
1468 pm_runtime_set_active(dev);
1469 pm_runtime_use_autosuspend(dev);
1470 pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1471 pm_runtime_enable(dev);
1472 ret = pm_runtime_get_sync(dev);
1473 if (ret < 0)
1474 goto err1;
1475
1476 pm_runtime_forbid(dev);
1477
1478 ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1479 if (ret) {
1480 dev_err(dwc->dev, "failed to allocate event buffers\n");
1481 ret = -ENOMEM;
1482 goto err2;
1483 }
1484
1485 ret = dwc3_get_dr_mode(dwc);
1486 if (ret)
1487 goto err3;
1488
1489 ret = dwc3_alloc_scratch_buffers(dwc);
1490 if (ret)
1491 goto err3;
1492
1493 ret = dwc3_core_init(dwc);
1494 if (ret) {
1495 if (ret != -EPROBE_DEFER)
1496 dev_err(dev, "failed to initialize core: %d\n", ret);
1497 goto err4;
1498 }
1499
1500 dwc3_check_params(dwc);
1501
1502 ret = dwc3_core_init_mode(dwc);
1503 if (ret)
1504 goto err5;
1505
1506 dwc3_debugfs_init(dwc);
1507 pm_runtime_put(dev);
1508
1509 return 0;
1510
1511err5:
1512 dwc3_event_buffers_cleanup(dwc);
1513 dwc3_ulpi_exit(dwc);
1514
1515err4:
1516 dwc3_free_scratch_buffers(dwc);
1517
1518err3:
1519 dwc3_free_event_buffers(dwc);
1520
1521err2:
1522 pm_runtime_allow(&pdev->dev);
1523
1524err1:
1525 pm_runtime_put_sync(&pdev->dev);
1526 pm_runtime_disable(&pdev->dev);
1527
1528 clk_bulk_disable(dwc->num_clks, dwc->clks);
1529unprepare_clks:
1530 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1531assert_reset:
1532 reset_control_assert(dwc->reset);
1533put_clks:
1534 clk_bulk_put(dwc->num_clks, dwc->clks);
1535
1536 return ret;
1537}
1538
1539static int dwc3_remove(struct platform_device *pdev)
1540{
1541 struct dwc3 *dwc = platform_get_drvdata(pdev);
1542
1543 pm_runtime_get_sync(&pdev->dev);
1544
1545 dwc3_debugfs_exit(dwc);
1546 dwc3_core_exit_mode(dwc);
1547
1548 dwc3_core_exit(dwc);
1549 dwc3_ulpi_exit(dwc);
1550
1551 pm_runtime_put_sync(&pdev->dev);
1552 pm_runtime_allow(&pdev->dev);
1553 pm_runtime_disable(&pdev->dev);
1554
1555 dwc3_free_event_buffers(dwc);
1556 dwc3_free_scratch_buffers(dwc);
1557 clk_bulk_put(dwc->num_clks, dwc->clks);
1558
1559 return 0;
1560}
1561
1562#ifdef CONFIG_PM
1563static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1564{
1565 int ret;
1566
1567 ret = reset_control_deassert(dwc->reset);
1568 if (ret)
1569 return ret;
1570
1571 ret = clk_bulk_prepare(dwc->num_clks, dwc->clks);
1572 if (ret)
1573 goto assert_reset;
1574
1575 ret = clk_bulk_enable(dwc->num_clks, dwc->clks);
1576 if (ret)
1577 goto unprepare_clks;
1578
1579 ret = dwc3_core_init(dwc);
1580 if (ret)
1581 goto disable_clks;
1582
1583 return 0;
1584
1585disable_clks:
1586 clk_bulk_disable(dwc->num_clks, dwc->clks);
1587unprepare_clks:
1588 clk_bulk_unprepare(dwc->num_clks, dwc->clks);
1589assert_reset:
1590 reset_control_assert(dwc->reset);
1591
1592 return ret;
1593}
1594
1595static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1596{
1597 unsigned long flags;
1598 u32 reg;
1599
1600 switch (dwc->current_dr_role) {
1601 case DWC3_GCTL_PRTCAP_DEVICE:
1602 spin_lock_irqsave(&dwc->lock, flags);
1603 dwc3_gadget_suspend(dwc);
1604 spin_unlock_irqrestore(&dwc->lock, flags);
1605 synchronize_irq(dwc->irq_gadget);
1606 dwc3_core_exit(dwc);
1607 break;
1608 case DWC3_GCTL_PRTCAP_HOST:
1609 if (!PMSG_IS_AUTO(msg)) {
1610 dwc3_core_exit(dwc);
1611 break;
1612 }
1613
1614
1615 if (dwc->dis_u2_susphy_quirk ||
1616 dwc->dis_enblslpm_quirk) {
1617 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1618 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM |
1619 DWC3_GUSB2PHYCFG_SUSPHY;
1620 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1621
1622
1623 usleep_range(5000, 6000);
1624 }
1625
1626 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1627 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1628 break;
1629 case DWC3_GCTL_PRTCAP_OTG:
1630
1631 if (PMSG_IS_AUTO(msg))
1632 break;
1633
1634 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1635 spin_lock_irqsave(&dwc->lock, flags);
1636 dwc3_gadget_suspend(dwc);
1637 spin_unlock_irqrestore(&dwc->lock, flags);
1638 synchronize_irq(dwc->irq_gadget);
1639 }
1640
1641 dwc3_otg_exit(dwc);
1642 dwc3_core_exit(dwc);
1643 break;
1644 default:
1645
1646 break;
1647 }
1648
1649 return 0;
1650}
1651
1652static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1653{
1654 unsigned long flags;
1655 int ret;
1656 u32 reg;
1657
1658 switch (dwc->current_dr_role) {
1659 case DWC3_GCTL_PRTCAP_DEVICE:
1660 ret = dwc3_core_init_for_resume(dwc);
1661 if (ret)
1662 return ret;
1663
1664 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1665 spin_lock_irqsave(&dwc->lock, flags);
1666 dwc3_gadget_resume(dwc);
1667 spin_unlock_irqrestore(&dwc->lock, flags);
1668 break;
1669 case DWC3_GCTL_PRTCAP_HOST:
1670 if (!PMSG_IS_AUTO(msg)) {
1671 ret = dwc3_core_init_for_resume(dwc);
1672 if (ret)
1673 return ret;
1674 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1675 break;
1676 }
1677
1678 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1679 if (dwc->dis_u2_susphy_quirk)
1680 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1681
1682 if (dwc->dis_enblslpm_quirk)
1683 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1684
1685 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1686
1687 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1688 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1689 break;
1690 case DWC3_GCTL_PRTCAP_OTG:
1691
1692 if (PMSG_IS_AUTO(msg))
1693 break;
1694
1695 ret = dwc3_core_init(dwc);
1696 if (ret)
1697 return ret;
1698
1699 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1700
1701 dwc3_otg_init(dwc);
1702 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1703 dwc3_otg_host_init(dwc);
1704 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1705 spin_lock_irqsave(&dwc->lock, flags);
1706 dwc3_gadget_resume(dwc);
1707 spin_unlock_irqrestore(&dwc->lock, flags);
1708 }
1709
1710 break;
1711 default:
1712
1713 break;
1714 }
1715
1716 return 0;
1717}
1718
1719static int dwc3_runtime_checks(struct dwc3 *dwc)
1720{
1721 switch (dwc->current_dr_role) {
1722 case DWC3_GCTL_PRTCAP_DEVICE:
1723 if (dwc->connected)
1724 return -EBUSY;
1725 break;
1726 case DWC3_GCTL_PRTCAP_HOST:
1727 default:
1728
1729 break;
1730 }
1731
1732 return 0;
1733}
1734
1735static int dwc3_runtime_suspend(struct device *dev)
1736{
1737 struct dwc3 *dwc = dev_get_drvdata(dev);
1738 int ret;
1739
1740 if (dwc3_runtime_checks(dwc))
1741 return -EBUSY;
1742
1743 ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1744 if (ret)
1745 return ret;
1746
1747 device_init_wakeup(dev, true);
1748
1749 return 0;
1750}
1751
1752static int dwc3_runtime_resume(struct device *dev)
1753{
1754 struct dwc3 *dwc = dev_get_drvdata(dev);
1755 int ret;
1756
1757 device_init_wakeup(dev, false);
1758
1759 ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1760 if (ret)
1761 return ret;
1762
1763 switch (dwc->current_dr_role) {
1764 case DWC3_GCTL_PRTCAP_DEVICE:
1765 dwc3_gadget_process_pending_events(dwc);
1766 break;
1767 case DWC3_GCTL_PRTCAP_HOST:
1768 default:
1769
1770 break;
1771 }
1772
1773 pm_runtime_mark_last_busy(dev);
1774
1775 return 0;
1776}
1777
1778static int dwc3_runtime_idle(struct device *dev)
1779{
1780 struct dwc3 *dwc = dev_get_drvdata(dev);
1781
1782 switch (dwc->current_dr_role) {
1783 case DWC3_GCTL_PRTCAP_DEVICE:
1784 if (dwc3_runtime_checks(dwc))
1785 return -EBUSY;
1786 break;
1787 case DWC3_GCTL_PRTCAP_HOST:
1788 default:
1789
1790 break;
1791 }
1792
1793 pm_runtime_mark_last_busy(dev);
1794 pm_runtime_autosuspend(dev);
1795
1796 return 0;
1797}
1798#endif
1799
1800#ifdef CONFIG_PM_SLEEP
1801static int dwc3_suspend(struct device *dev)
1802{
1803 struct dwc3 *dwc = dev_get_drvdata(dev);
1804 int ret;
1805
1806 ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1807 if (ret)
1808 return ret;
1809
1810 pinctrl_pm_select_sleep_state(dev);
1811
1812 return 0;
1813}
1814
1815static int dwc3_resume(struct device *dev)
1816{
1817 struct dwc3 *dwc = dev_get_drvdata(dev);
1818 int ret;
1819
1820 pinctrl_pm_select_default_state(dev);
1821
1822 ret = dwc3_resume_common(dwc, PMSG_RESUME);
1823 if (ret)
1824 return ret;
1825
1826 pm_runtime_disable(dev);
1827 pm_runtime_set_active(dev);
1828 pm_runtime_enable(dev);
1829
1830 return 0;
1831}
1832#endif
1833
1834static const struct dev_pm_ops dwc3_dev_pm_ops = {
1835 SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1836 SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1837 dwc3_runtime_idle)
1838};
1839
1840#ifdef CONFIG_OF
1841static const struct of_device_id of_dwc3_match[] = {
1842 {
1843 .compatible = "snps,dwc3"
1844 },
1845 {
1846 .compatible = "synopsys,dwc3"
1847 },
1848 { },
1849};
1850MODULE_DEVICE_TABLE(of, of_dwc3_match);
1851#endif
1852
1853#ifdef CONFIG_ACPI
1854
1855#define ACPI_ID_INTEL_BSW "808622B7"
1856
1857static const struct acpi_device_id dwc3_acpi_match[] = {
1858 { ACPI_ID_INTEL_BSW, 0 },
1859 { },
1860};
1861MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1862#endif
1863
1864static struct platform_driver dwc3_driver = {
1865 .probe = dwc3_probe,
1866 .remove = dwc3_remove,
1867 .driver = {
1868 .name = "dwc3",
1869 .of_match_table = of_match_ptr(of_dwc3_match),
1870 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1871 .pm = &dwc3_dev_pm_ops,
1872 },
1873};
1874
1875module_platform_driver(dwc3_driver);
1876
1877MODULE_ALIAS("platform:dwc3");
1878MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1879MODULE_LICENSE("GPL v2");
1880MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
1881
