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12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25
26#define XHCI_SBRN_OFFSET (0x60)
27
28
29#define MAX_HC_SLOTS 256
30
31#define MAX_HC_PORTS 127
32
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49
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2;
59
60};
61
62
63
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68
69
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77
78
79
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83
84
85
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88
89
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94
95
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99
100
101
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103
104#define HCC_PPC(p) ((p) & (1 << 3))
105
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109
110#define HCC_LTC(p) ((p) & (1 << 6))
111
112#define HCC_NSS(p) ((p) & (1 << 7))
113
114#define HCC_SPC(p) ((p) & (1 << 9))
115
116#define HCC_CFC(p) ((p) & (1 << 11))
117
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124
125#define DBOFF_MASK (~0x3)
126
127
128#define RTSOFF_MASK (~0x1f)
129
130
131
132#define HCC2_U3C(p) ((p) & (1 << 0))
133
134#define HCC2_CMC(p) ((p) & (1 << 1))
135
136#define HCC2_FSC(p) ((p) & (1 << 2))
137
138#define HCC2_CTC(p) ((p) & (1 << 3))
139
140#define HCC2_LEC(p) ((p) & (1 << 4))
141
142#define HCC2_CIC(p) ((p) & (1 << 5))
143
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
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176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188
189 __le32 reserved4[241];
190
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199
200
201#define CMD_RUN XHCI_CMD_RUN
202
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204
205
206#define CMD_RESET (1 << 1)
207
208#define CMD_EIE XHCI_CMD_EIE
209
210#define CMD_HSEIE XHCI_CMD_HSEIE
211
212
213#define CMD_LRESET (1 << 7)
214
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217
218#define CMD_EWE XHCI_CMD_EWE
219
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222
223
224#define CMD_PM_INDEX (1 << 11)
225
226#define CMD_ETE (1 << 14)
227
228
229
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233
234
235#define STS_HALT XHCI_STS_HALT
236
237#define STS_FATAL (1 << 2)
238
239#define STS_EINT (1 << 3)
240
241#define STS_PORT (1 << 4)
242
243
244#define STS_SAVE (1 << 8)
245
246#define STS_RESTORE (1 << 9)
247
248#define STS_SRE (1 << 10)
249
250#define STS_CNR XHCI_STS_CNR
251
252#define STS_HCE (1 << 12)
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259
260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
262
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264
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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269
270#define CMD_RING_PAUSE (1 << 1)
271
272#define CMD_RING_ABORT (1 << 2)
273
274#define CMD_RING_RUNNING (1 << 3)
275
276
277#define CMD_RING_RSVD_BITS (0x3f)
278
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280
281#define MAX_DEVS(p) ((p) & 0xff)
282
283#define CONFIG_U3E (1 << 8)
284
285#define CONFIG_CIE (1 << 9)
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289
290#define PORT_CONNECT (1 << 0)
291
292#define PORT_PE (1 << 1)
293
294
295#define PORT_OC (1 << 3)
296
297#define PORT_RESET (1 << 4)
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301
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317
318#define PORT_POWER (1 << 9)
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327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353
354#define PORT_LINK_STROBE (1 << 16)
355
356#define PORT_CSC (1 << 17)
357
358#define PORT_PEC (1 << 18)
359
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363
364#define PORT_WRC (1 << 19)
365
366#define PORT_OCC (1 << 20)
367
368#define PORT_RC (1 << 21)
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382#define PORT_PLC (1 << 22)
383
384#define PORT_CEC (1 << 23)
385#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
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393#define PORT_CAS (1 << 24)
394
395#define PORT_WKCONN_E (1 << 25)
396
397#define PORT_WKDISC_E (1 << 26)
398
399#define PORT_WKOC_E (1 << 27)
400
401
402#define PORT_DEV_REMOVE (1 << 30)
403
404#define PORT_WR (1 << 31)
405
406
407#define DUPLICATE_ENTRY ((u8)(-1))
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412
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418
419
420
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429#define PORT_TEST_MODE_SHIFT 28
430
431
432#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
434
435
436#define PORT_HIRDM(p)((p) & 3)
437#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438#define PORT_BESLD(p)(((p) & 0xf) << 10)
439
440
441#define XHCI_L1_TIMEOUT 512
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452
453#define XHCI_DEFAULT_BESL 4
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461#define XHCI_PORT_POLLING_LFPS_TIME 36
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480struct xhci_intr_reg {
481 __le32 irq_pending;
482 __le32 irq_control;
483 __le32 erst_size;
484 __le32 rsvd;
485 __le64 erst_base;
486 __le64 erst_dequeue;
487};
488
489
490#define ER_IRQ_PENDING(p) ((p) & 0x1)
491
492
493#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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501
502#define ER_IRQ_INTERVAL_MASK (0xffff)
503
504#define ER_IRQ_COUNTER_MASK (0xffff << 16)
505
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508#define ERST_SIZE_MASK (0xffff << 16)
509
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514#define ERST_DESI_MASK (0x7)
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518#define ERST_EHB (1 << 3)
519#define ERST_PTR_MASK (0xf)
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530struct xhci_run_regs {
531 __le32 microframe_index;
532 __le32 rsvd[7];
533 struct xhci_intr_reg ir_set[128];
534};
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545struct xhci_doorbell_array {
546 __le32 doorbell[256];
547};
548
549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550#define DB_VALUE_HOST 0x00000000
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560struct xhci_protocol_caps {
561 u32 revision;
562 u32 name_string;
563 u32 port_info;
564};
565
566#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
571
572#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
578
579#define PLT_MASK (0x03 << 6)
580#define PLT_SYM (0x00 << 6)
581#define PLT_ASYM_RX (0x02 << 6)
582#define PLT_ASYM_TX (0x03 << 6)
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594struct xhci_container_ctx {
595 unsigned type;
596#define XHCI_CTX_TYPE_DEVICE 0x1
597#define XHCI_CTX_TYPE_INPUT 0x2
598
599 int size;
600
601 u8 *bytes;
602 dma_addr_t dma;
603};
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616struct xhci_slot_ctx {
617 __le32 dev_info;
618 __le32 dev_info2;
619 __le32 tt_info;
620 __le32 dev_state;
621
622 __le32 reserved[4];
623};
624
625
626
627#define ROUTE_STRING_MASK (0xfffff)
628
629#define DEV_SPEED (0xf << 20)
630#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631
632
633#define DEV_MTT (0x1 << 25)
634
635#define DEV_HUB (0x1 << 26)
636
637#define LAST_CTX_MASK (0x1f << 27)
638#define LAST_CTX(p) ((p) << 27)
639#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640#define SLOT_FLAG (1 << 0)
641#define EP0_FLAG (1 << 1)
642
643
644
645#define MAX_EXIT (0xffff)
646
647#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649
650#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
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657
658
659#define TT_SLOT (0xff)
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664#define TT_PORT (0xff << 8)
665#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
667
668
669
670#define DEV_ADDR_MASK (0xff)
671
672
673#define SLOT_STATE (0x1f << 27)
674#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
675
676#define SLOT_STATE_DISABLED 0
677#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678#define SLOT_STATE_DEFAULT 1
679#define SLOT_STATE_ADDRESSED 2
680#define SLOT_STATE_CONFIGURED 3
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700struct xhci_ep_ctx {
701 __le32 ep_info;
702 __le32 ep_info2;
703 __le64 deq;
704 __le32 tx_info;
705
706 __le32 reserved[3];
707};
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718
719#define EP_STATE_MASK (0xf)
720#define EP_STATE_DISABLED 0
721#define EP_STATE_RUNNING 1
722#define EP_STATE_HALTED 2
723#define EP_STATE_STOPPED 3
724#define EP_STATE_ERROR 4
725#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
726
727
728#define EP_MULT(p) (((p) & 0x3) << 8)
729#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730
731
732
733#define EP_INTERVAL(p) (((p) & 0xff) << 16)
734#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736#define EP_MAXPSTREAMS_MASK (0x1f << 10)
737#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739
740#define EP_HAS_LSA (1 << 15)
741
742#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
743
744
745
746
747
748
749#define FORCE_EVENT (0x1)
750#define ERROR_COUNT(p) (((p) & 0x3) << 1)
751#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752#define EP_TYPE(p) ((p) << 3)
753#define ISOC_OUT_EP 1
754#define BULK_OUT_EP 2
755#define INT_OUT_EP 3
756#define CTRL_EP 4
757#define ISOC_IN_EP 5
758#define BULK_IN_EP 6
759#define INT_IN_EP 7
760
761
762#define MAX_BURST(p) (((p)&0xff) << 8)
763#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764#define MAX_PACKET(p) (((p)&0xffff) << 16)
765#define MAX_PACKET_MASK (0xffff << 16)
766#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
767
768
769#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
773
774
775#define EP_CTX_CYCLE_MASK (1 << 0)
776#define SCTX_DEQ_MASK (~0xfL)
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785
786struct xhci_input_control_ctx {
787 __le32 drop_flags;
788 __le32 add_flags;
789 __le32 rsvd2[6];
790};
791
792#define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794#define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
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799
800
801struct xhci_command {
802
803 struct xhci_container_ctx *in_ctx;
804 u32 status;
805 int slot_id;
806
807
808
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
812};
813
814
815#define DROP_EP(x) (0x1 << x)
816
817#define ADD_EP(x) (0x1 << x)
818
819struct xhci_stream_ctx {
820
821 __le64 stream_ring;
822
823 __le32 reserved[2];
824};
825
826
827#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828
829#define SCT_SEC_TR 0
830
831#define SCT_PRI_TR 1
832
833#define SCT_SSA_8 2
834#define SCT_SSA_16 3
835#define SCT_SSA_32 4
836#define SCT_SSA_64 5
837#define SCT_SSA_128 6
838#define SCT_SSA_256 7
839
840
841struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843
844 unsigned int num_streams;
845
846
847
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
854};
855
856#define SMALL_STREAM_ARRAY_SIZE 256
857#define MEDIUM_STREAM_ARRAY_SIZE 1024
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864
865struct xhci_bw_info {
866
867 unsigned int ep_interval;
868
869 unsigned int mult;
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
873 unsigned int type;
874};
875
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879
880
881#define FS_BLOCK 1
882#define HS_BLOCK 4
883#define SS_BLOCK 16
884#define DMI_BLOCK 32
885
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890
891#define DMI_OVERHEAD 8
892#define DMI_OVERHEAD_BURST 4
893#define SS_OVERHEAD 8
894#define SS_OVERHEAD_BURST 32
895#define HS_OVERHEAD 26
896#define FS_OVERHEAD 20
897#define LS_OVERHEAD 128
898
899
900
901
902
903#define TT_HS_OVERHEAD (31 + 94)
904#define TT_DMI_OVERHEAD (25 + 12)
905
906
907#define FS_BW_LIMIT 1285
908#define TT_BW_LIMIT 1320
909#define HS_BW_LIMIT 1607
910#define SS_BW_LIMIT_IN 3906
911#define DMI_BW_LIMIT_IN 3906
912#define SS_BW_LIMIT_OUT 3906
913#define DMI_BW_LIMIT_OUT 3906
914
915
916#define FS_BW_RESERVED 10
917#define HS_BW_RESERVED 20
918#define SS_BW_RESERVED 10
919
920struct xhci_virt_ep {
921 struct xhci_ring *ring;
922
923 struct xhci_stream_info *stream_info;
924
925
926
927 struct xhci_ring *new_ring;
928 unsigned int ep_state;
929#define SET_DEQ_PENDING (1 << 0)
930#define EP_HALTED (1 << 1)
931#define EP_STOP_CMD_PENDING (1 << 2)
932
933#define EP_GETTING_STREAMS (1 << 3)
934#define EP_HAS_STREAMS (1 << 4)
935
936#define EP_GETTING_NO_STREAMS (1 << 5)
937#define EP_HARD_CLEAR_TOGGLE (1 << 6)
938#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
939
940 struct list_head cancelled_td_list;
941
942 struct timer_list stop_cmd_timer;
943 struct xhci_hcd *xhci;
944
945
946
947
948 struct xhci_segment *queued_deq_seg;
949 union xhci_trb *queued_deq_ptr;
950
951
952
953
954
955
956
957 bool skip;
958
959 struct xhci_bw_info bw_info;
960 struct list_head bw_endpoint_list;
961
962 int next_frame_id;
963
964 bool use_extended_tbc;
965};
966
967enum xhci_overhead_type {
968 LS_OVERHEAD_TYPE = 0,
969 FS_OVERHEAD_TYPE,
970 HS_OVERHEAD_TYPE,
971};
972
973struct xhci_interval_bw {
974 unsigned int num_packets;
975
976
977
978 struct list_head endpoints;
979
980 unsigned int overhead[3];
981};
982
983#define XHCI_MAX_INTERVAL 16
984
985struct xhci_interval_bw_table {
986 unsigned int interval0_esit_payload;
987 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
988
989 unsigned int bw_used;
990 unsigned int ss_bw_in;
991 unsigned int ss_bw_out;
992};
993
994
995struct xhci_virt_device {
996 struct usb_device *udev;
997
998
999
1000
1001
1002
1003
1004
1005 struct xhci_container_ctx *out_ctx;
1006
1007 struct xhci_container_ctx *in_ctx;
1008 struct xhci_virt_ep eps[31];
1009 u8 fake_port;
1010 u8 real_port;
1011 struct xhci_interval_bw_table *bw_table;
1012 struct xhci_tt_bw_info *tt_info;
1013
1014
1015
1016
1017
1018
1019 unsigned long flags;
1020#define VDEV_PORT_ERROR BIT(0)
1021
1022
1023 u16 current_mel;
1024
1025 void *debugfs_private;
1026};
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036struct xhci_root_port_bw_info {
1037 struct list_head tts;
1038 unsigned int num_active_tts;
1039 struct xhci_interval_bw_table bw_table;
1040};
1041
1042struct xhci_tt_bw_info {
1043 struct list_head tt_list;
1044 int slot_id;
1045 int ttport;
1046 struct xhci_interval_bw_table bw_table;
1047 int active_eps;
1048};
1049
1050
1051
1052
1053
1054
1055struct xhci_device_context_array {
1056
1057 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1058
1059 dma_addr_t dma;
1060};
1061
1062
1063
1064
1065
1066
1067
1068struct xhci_transfer_event {
1069
1070 __le64 buffer;
1071 __le32 transfer_len;
1072
1073 __le32 flags;
1074};
1075
1076
1077
1078#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1079
1080
1081#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1082
1083
1084#define COMP_CODE_MASK (0xff << 24)
1085#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1086#define COMP_INVALID 0
1087#define COMP_SUCCESS 1
1088#define COMP_DATA_BUFFER_ERROR 2
1089#define COMP_BABBLE_DETECTED_ERROR 3
1090#define COMP_USB_TRANSACTION_ERROR 4
1091#define COMP_TRB_ERROR 5
1092#define COMP_STALL_ERROR 6
1093#define COMP_RESOURCE_ERROR 7
1094#define COMP_BANDWIDTH_ERROR 8
1095#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1096#define COMP_INVALID_STREAM_TYPE_ERROR 10
1097#define COMP_SLOT_NOT_ENABLED_ERROR 11
1098#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1099#define COMP_SHORT_PACKET 13
1100#define COMP_RING_UNDERRUN 14
1101#define COMP_RING_OVERRUN 15
1102#define COMP_VF_EVENT_RING_FULL_ERROR 16
1103#define COMP_PARAMETER_ERROR 17
1104#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1105#define COMP_CONTEXT_STATE_ERROR 19
1106#define COMP_NO_PING_RESPONSE_ERROR 20
1107#define COMP_EVENT_RING_FULL_ERROR 21
1108#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1109#define COMP_MISSED_SERVICE_ERROR 23
1110#define COMP_COMMAND_RING_STOPPED 24
1111#define COMP_COMMAND_ABORTED 25
1112#define COMP_STOPPED 26
1113#define COMP_STOPPED_LENGTH_INVALID 27
1114#define COMP_STOPPED_SHORT_PACKET 28
1115#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1116#define COMP_ISOCH_BUFFER_OVERRUN 31
1117#define COMP_EVENT_LOST_ERROR 32
1118#define COMP_UNDEFINED_ERROR 33
1119#define COMP_INVALID_STREAM_ID_ERROR 34
1120#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1121#define COMP_SPLIT_TRANSACTION_ERROR 36
1122
1123static inline const char *xhci_trb_comp_code_string(u8 status)
1124{
1125 switch (status) {
1126 case COMP_INVALID:
1127 return "Invalid";
1128 case COMP_SUCCESS:
1129 return "Success";
1130 case COMP_DATA_BUFFER_ERROR:
1131 return "Data Buffer Error";
1132 case COMP_BABBLE_DETECTED_ERROR:
1133 return "Babble Detected";
1134 case COMP_USB_TRANSACTION_ERROR:
1135 return "USB Transaction Error";
1136 case COMP_TRB_ERROR:
1137 return "TRB Error";
1138 case COMP_STALL_ERROR:
1139 return "Stall Error";
1140 case COMP_RESOURCE_ERROR:
1141 return "Resource Error";
1142 case COMP_BANDWIDTH_ERROR:
1143 return "Bandwidth Error";
1144 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1145 return "No Slots Available Error";
1146 case COMP_INVALID_STREAM_TYPE_ERROR:
1147 return "Invalid Stream Type Error";
1148 case COMP_SLOT_NOT_ENABLED_ERROR:
1149 return "Slot Not Enabled Error";
1150 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1151 return "Endpoint Not Enabled Error";
1152 case COMP_SHORT_PACKET:
1153 return "Short Packet";
1154 case COMP_RING_UNDERRUN:
1155 return "Ring Underrun";
1156 case COMP_RING_OVERRUN:
1157 return "Ring Overrun";
1158 case COMP_VF_EVENT_RING_FULL_ERROR:
1159 return "VF Event Ring Full Error";
1160 case COMP_PARAMETER_ERROR:
1161 return "Parameter Error";
1162 case COMP_BANDWIDTH_OVERRUN_ERROR:
1163 return "Bandwidth Overrun Error";
1164 case COMP_CONTEXT_STATE_ERROR:
1165 return "Context State Error";
1166 case COMP_NO_PING_RESPONSE_ERROR:
1167 return "No Ping Response Error";
1168 case COMP_EVENT_RING_FULL_ERROR:
1169 return "Event Ring Full Error";
1170 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1171 return "Incompatible Device Error";
1172 case COMP_MISSED_SERVICE_ERROR:
1173 return "Missed Service Error";
1174 case COMP_COMMAND_RING_STOPPED:
1175 return "Command Ring Stopped";
1176 case COMP_COMMAND_ABORTED:
1177 return "Command Aborted";
1178 case COMP_STOPPED:
1179 return "Stopped";
1180 case COMP_STOPPED_LENGTH_INVALID:
1181 return "Stopped - Length Invalid";
1182 case COMP_STOPPED_SHORT_PACKET:
1183 return "Stopped - Short Packet";
1184 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1185 return "Max Exit Latency Too Large Error";
1186 case COMP_ISOCH_BUFFER_OVERRUN:
1187 return "Isoch Buffer Overrun";
1188 case COMP_EVENT_LOST_ERROR:
1189 return "Event Lost Error";
1190 case COMP_UNDEFINED_ERROR:
1191 return "Undefined Error";
1192 case COMP_INVALID_STREAM_ID_ERROR:
1193 return "Invalid Stream ID Error";
1194 case COMP_SECONDARY_BANDWIDTH_ERROR:
1195 return "Secondary Bandwidth Error";
1196 case COMP_SPLIT_TRANSACTION_ERROR:
1197 return "Split Transaction Error";
1198 default:
1199 return "Unknown!!";
1200 }
1201}
1202
1203struct xhci_link_trb {
1204
1205 __le64 segment_ptr;
1206 __le32 intr_target;
1207 __le32 control;
1208};
1209
1210
1211#define LINK_TOGGLE (0x1<<1)
1212
1213
1214struct xhci_event_cmd {
1215
1216 __le64 cmd_trb;
1217 __le32 status;
1218 __le32 flags;
1219};
1220
1221
1222
1223
1224#define TRB_BSR (1<<9)
1225
1226
1227#define TRB_DC (1<<9)
1228
1229
1230#define TRB_TSP (1<<9)
1231
1232enum xhci_ep_reset_type {
1233 EP_HARD_RESET,
1234 EP_SOFT_RESET,
1235};
1236
1237
1238#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1239#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1240
1241
1242#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1243
1244
1245#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1246
1247
1248#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1249#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1250
1251enum xhci_setup_dev {
1252 SETUP_CONTEXT_ONLY,
1253 SETUP_CONTEXT_ADDRESS,
1254};
1255
1256
1257
1258#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1259#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1260
1261
1262#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1263#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1264
1265#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1266#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1267#define LAST_EP_INDEX 30
1268
1269
1270#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1271#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1272#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1273
1274
1275#define TRB_TC (1<<1)
1276
1277
1278
1279#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1280
1281#define EVENT_DATA (1 << 2)
1282
1283
1284
1285#define TRB_LEN(p) ((p) & 0x1ffff)
1286
1287#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1288#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1289
1290#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1291
1292#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1293#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1294
1295#define TRB_TBC(p) (((p) & 0x3) << 7)
1296#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1297
1298
1299#define TRB_CYCLE (1<<0)
1300
1301
1302
1303
1304#define TRB_ENT (1<<1)
1305
1306#define TRB_ISP (1<<2)
1307
1308#define TRB_NO_SNOOP (1<<3)
1309
1310#define TRB_CHAIN (1<<4)
1311
1312#define TRB_IOC (1<<5)
1313
1314#define TRB_IDT (1<<6)
1315
1316#define TRB_IDT_MAX_SIZE 8
1317
1318
1319#define TRB_BEI (1<<9)
1320
1321
1322#define TRB_DIR_IN (1<<16)
1323#define TRB_TX_TYPE(p) ((p) << 16)
1324#define TRB_DATA_OUT 2
1325#define TRB_DATA_IN 3
1326
1327
1328#define TRB_SIA (1<<31)
1329#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1330
1331struct xhci_generic_trb {
1332 __le32 field[4];
1333};
1334
1335union xhci_trb {
1336 struct xhci_link_trb link;
1337 struct xhci_transfer_event trans_event;
1338 struct xhci_event_cmd event_cmd;
1339 struct xhci_generic_trb generic;
1340};
1341
1342
1343#define TRB_TYPE_BITMASK (0xfc00)
1344#define TRB_TYPE(p) ((p) << 10)
1345#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1346
1347
1348#define TRB_NORMAL 1
1349
1350#define TRB_SETUP 2
1351
1352#define TRB_DATA 3
1353
1354#define TRB_STATUS 4
1355
1356#define TRB_ISOC 5
1357
1358#define TRB_LINK 6
1359#define TRB_EVENT_DATA 7
1360
1361#define TRB_TR_NOOP 8
1362
1363
1364#define TRB_ENABLE_SLOT 9
1365
1366#define TRB_DISABLE_SLOT 10
1367
1368#define TRB_ADDR_DEV 11
1369
1370#define TRB_CONFIG_EP 12
1371
1372#define TRB_EVAL_CONTEXT 13
1373
1374#define TRB_RESET_EP 14
1375
1376#define TRB_STOP_RING 15
1377
1378#define TRB_SET_DEQ 16
1379
1380#define TRB_RESET_DEV 17
1381
1382#define TRB_FORCE_EVENT 18
1383
1384#define TRB_NEG_BANDWIDTH 19
1385
1386#define TRB_SET_LT 20
1387
1388#define TRB_GET_BW 21
1389
1390#define TRB_FORCE_HEADER 22
1391
1392#define TRB_CMD_NOOP 23
1393
1394
1395
1396#define TRB_TRANSFER 32
1397
1398#define TRB_COMPLETION 33
1399
1400#define TRB_PORT_STATUS 34
1401
1402#define TRB_BANDWIDTH_EVENT 35
1403
1404#define TRB_DOORBELL 36
1405
1406#define TRB_HC_EVENT 37
1407
1408#define TRB_DEV_NOTE 38
1409
1410#define TRB_MFINDEX_WRAP 39
1411
1412
1413
1414#define TRB_NEC_CMD_COMP 48
1415
1416#define TRB_NEC_GET_FW 49
1417
1418static inline const char *xhci_trb_type_string(u8 type)
1419{
1420 switch (type) {
1421 case TRB_NORMAL:
1422 return "Normal";
1423 case TRB_SETUP:
1424 return "Setup Stage";
1425 case TRB_DATA:
1426 return "Data Stage";
1427 case TRB_STATUS:
1428 return "Status Stage";
1429 case TRB_ISOC:
1430 return "Isoch";
1431 case TRB_LINK:
1432 return "Link";
1433 case TRB_EVENT_DATA:
1434 return "Event Data";
1435 case TRB_TR_NOOP:
1436 return "No-Op";
1437 case TRB_ENABLE_SLOT:
1438 return "Enable Slot Command";
1439 case TRB_DISABLE_SLOT:
1440 return "Disable Slot Command";
1441 case TRB_ADDR_DEV:
1442 return "Address Device Command";
1443 case TRB_CONFIG_EP:
1444 return "Configure Endpoint Command";
1445 case TRB_EVAL_CONTEXT:
1446 return "Evaluate Context Command";
1447 case TRB_RESET_EP:
1448 return "Reset Endpoint Command";
1449 case TRB_STOP_RING:
1450 return "Stop Ring Command";
1451 case TRB_SET_DEQ:
1452 return "Set TR Dequeue Pointer Command";
1453 case TRB_RESET_DEV:
1454 return "Reset Device Command";
1455 case TRB_FORCE_EVENT:
1456 return "Force Event Command";
1457 case TRB_NEG_BANDWIDTH:
1458 return "Negotiate Bandwidth Command";
1459 case TRB_SET_LT:
1460 return "Set Latency Tolerance Value Command";
1461 case TRB_GET_BW:
1462 return "Get Port Bandwidth Command";
1463 case TRB_FORCE_HEADER:
1464 return "Force Header Command";
1465 case TRB_CMD_NOOP:
1466 return "No-Op Command";
1467 case TRB_TRANSFER:
1468 return "Transfer Event";
1469 case TRB_COMPLETION:
1470 return "Command Completion Event";
1471 case TRB_PORT_STATUS:
1472 return "Port Status Change Event";
1473 case TRB_BANDWIDTH_EVENT:
1474 return "Bandwidth Request Event";
1475 case TRB_DOORBELL:
1476 return "Doorbell Event";
1477 case TRB_HC_EVENT:
1478 return "Host Controller Event";
1479 case TRB_DEV_NOTE:
1480 return "Device Notification Event";
1481 case TRB_MFINDEX_WRAP:
1482 return "MFINDEX Wrap Event";
1483 case TRB_NEC_CMD_COMP:
1484 return "NEC Command Completion Event";
1485 case TRB_NEC_GET_FW:
1486 return "NET Get Firmware Revision Command";
1487 default:
1488 return "UNKNOWN";
1489 }
1490}
1491
1492#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1493
1494#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1495 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1496#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1497 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1498
1499#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1500#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1501
1502
1503
1504
1505
1506
1507#define TRBS_PER_SEGMENT 256
1508
1509#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1510#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1511#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1512
1513#define TRB_MAX_BUFF_SHIFT 16
1514#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1515
1516#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1517 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1518#define MAX_SOFT_RETRY 3
1519
1520struct xhci_segment {
1521 union xhci_trb *trbs;
1522
1523 struct xhci_segment *next;
1524 dma_addr_t dma;
1525
1526 dma_addr_t bounce_dma;
1527 void *bounce_buf;
1528 unsigned int bounce_offs;
1529 unsigned int bounce_len;
1530};
1531
1532struct xhci_td {
1533 struct list_head td_list;
1534 struct list_head cancelled_td_list;
1535 struct urb *urb;
1536 struct xhci_segment *start_seg;
1537 union xhci_trb *first_trb;
1538 union xhci_trb *last_trb;
1539 struct xhci_segment *bounce_seg;
1540
1541 bool urb_length_set;
1542};
1543
1544
1545#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1546
1547
1548struct xhci_cd {
1549 struct xhci_command *command;
1550 union xhci_trb *cmd_trb;
1551};
1552
1553struct xhci_dequeue_state {
1554 struct xhci_segment *new_deq_seg;
1555 union xhci_trb *new_deq_ptr;
1556 int new_cycle_state;
1557 unsigned int stream_id;
1558};
1559
1560enum xhci_ring_type {
1561 TYPE_CTRL = 0,
1562 TYPE_ISOC,
1563 TYPE_BULK,
1564 TYPE_INTR,
1565 TYPE_STREAM,
1566 TYPE_COMMAND,
1567 TYPE_EVENT,
1568};
1569
1570static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1571{
1572 switch (type) {
1573 case TYPE_CTRL:
1574 return "CTRL";
1575 case TYPE_ISOC:
1576 return "ISOC";
1577 case TYPE_BULK:
1578 return "BULK";
1579 case TYPE_INTR:
1580 return "INTR";
1581 case TYPE_STREAM:
1582 return "STREAM";
1583 case TYPE_COMMAND:
1584 return "CMD";
1585 case TYPE_EVENT:
1586 return "EVENT";
1587 }
1588
1589 return "UNKNOWN";
1590}
1591
1592struct xhci_ring {
1593 struct xhci_segment *first_seg;
1594 struct xhci_segment *last_seg;
1595 union xhci_trb *enqueue;
1596 struct xhci_segment *enq_seg;
1597 union xhci_trb *dequeue;
1598 struct xhci_segment *deq_seg;
1599 struct list_head td_list;
1600
1601
1602
1603
1604
1605 u32 cycle_state;
1606 unsigned int err_count;
1607 unsigned int stream_id;
1608 unsigned int num_segs;
1609 unsigned int num_trbs_free;
1610 unsigned int num_trbs_free_temp;
1611 unsigned int bounce_buf_len;
1612 enum xhci_ring_type type;
1613 bool last_td_was_short;
1614 struct radix_tree_root *trb_address_map;
1615};
1616
1617struct xhci_erst_entry {
1618
1619 __le64 seg_addr;
1620 __le32 seg_size;
1621
1622 __le32 rsvd;
1623};
1624
1625struct xhci_erst {
1626 struct xhci_erst_entry *entries;
1627 unsigned int num_entries;
1628
1629 dma_addr_t erst_dma_addr;
1630
1631 unsigned int erst_size;
1632};
1633
1634struct xhci_scratchpad {
1635 u64 *sp_array;
1636 dma_addr_t sp_dma;
1637 void **sp_buffers;
1638};
1639
1640struct urb_priv {
1641 int num_tds;
1642 int num_tds_done;
1643 struct xhci_td td[0];
1644};
1645
1646
1647
1648
1649
1650
1651#define ERST_NUM_SEGS 1
1652
1653#define ERST_SIZE 64
1654
1655#define ERST_ENTRIES 1
1656
1657#define POLL_TIMEOUT 60
1658
1659#define XHCI_STOP_EP_CMD_TIMEOUT 5
1660
1661
1662struct s3_save {
1663 u32 command;
1664 u32 dev_nt;
1665 u64 dcbaa_ptr;
1666 u32 config_reg;
1667 u32 irq_pending;
1668 u32 irq_control;
1669 u32 erst_size;
1670 u64 erst_base;
1671 u64 erst_dequeue;
1672};
1673
1674
1675struct dev_info {
1676 u32 dev_id;
1677 struct list_head list;
1678};
1679
1680struct xhci_bus_state {
1681 unsigned long bus_suspended;
1682 unsigned long next_statechange;
1683
1684
1685
1686 u32 port_c_suspend;
1687 u32 suspended_ports;
1688 u32 port_remote_wakeup;
1689 unsigned long resume_done[USB_MAXCHILDREN];
1690
1691 unsigned long resuming_ports;
1692
1693 unsigned long rexit_ports;
1694 struct completion rexit_done[USB_MAXCHILDREN];
1695};
1696
1697
1698
1699
1700
1701
1702#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1703
1704struct xhci_port {
1705 __le32 __iomem *addr;
1706 int hw_portnum;
1707 int hcd_portnum;
1708 struct xhci_hub *rhub;
1709};
1710
1711struct xhci_hub {
1712 struct xhci_port **ports;
1713 unsigned int num_ports;
1714 struct usb_hcd *hcd;
1715
1716 struct xhci_bus_state bus_state;
1717
1718 u8 maj_rev;
1719 u8 min_rev;
1720 u32 *psi;
1721 u8 psi_count;
1722 u8 psi_uid_count;
1723};
1724
1725
1726struct xhci_hcd {
1727 struct usb_hcd *main_hcd;
1728 struct usb_hcd *shared_hcd;
1729
1730 struct xhci_cap_regs __iomem *cap_regs;
1731 struct xhci_op_regs __iomem *op_regs;
1732 struct xhci_run_regs __iomem *run_regs;
1733 struct xhci_doorbell_array __iomem *dba;
1734
1735 struct xhci_intr_reg __iomem *ir_set;
1736
1737
1738 __u32 hcs_params1;
1739 __u32 hcs_params2;
1740 __u32 hcs_params3;
1741 __u32 hcc_params;
1742 __u32 hcc_params2;
1743
1744 spinlock_t lock;
1745
1746
1747 u8 sbrn;
1748 u16 hci_version;
1749 u8 max_slots;
1750 u8 max_interrupters;
1751 u8 max_ports;
1752 u8 isoc_threshold;
1753
1754 u32 imod_interval;
1755 int event_ring_max;
1756
1757 int page_size;
1758
1759 int page_shift;
1760
1761 int msix_count;
1762
1763 struct clk *clk;
1764 struct clk *reg_clk;
1765
1766 struct xhci_device_context_array *dcbaa;
1767 struct xhci_ring *cmd_ring;
1768 unsigned int cmd_ring_state;
1769#define CMD_RING_STATE_RUNNING (1 << 0)
1770#define CMD_RING_STATE_ABORTED (1 << 1)
1771#define CMD_RING_STATE_STOPPED (1 << 2)
1772 struct list_head cmd_list;
1773 unsigned int cmd_ring_reserved_trbs;
1774 struct delayed_work cmd_timer;
1775 struct completion cmd_ring_stop_completion;
1776 struct xhci_command *current_cmd;
1777 struct xhci_ring *event_ring;
1778 struct xhci_erst erst;
1779
1780 struct xhci_scratchpad *scratchpad;
1781
1782 struct list_head lpm_failed_devs;
1783
1784
1785
1786 struct mutex mutex;
1787
1788 struct xhci_command *lpm_command;
1789
1790 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1791
1792 struct xhci_root_port_bw_info *rh_bw;
1793
1794
1795 struct dma_pool *device_pool;
1796 struct dma_pool *segment_pool;
1797 struct dma_pool *small_streams_pool;
1798 struct dma_pool *medium_streams_pool;
1799
1800
1801 unsigned int xhc_state;
1802
1803 u32 command;
1804 struct s3_save s3;
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817#define XHCI_STATE_DYING (1 << 0)
1818#define XHCI_STATE_HALTED (1 << 1)
1819#define XHCI_STATE_REMOVING (1 << 2)
1820 unsigned long long quirks;
1821#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1822#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1823#define XHCI_NEC_HOST BIT_ULL(2)
1824#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1825#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1836#define XHCI_BROKEN_MSI BIT_ULL(6)
1837#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1838#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1839#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1840#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1841#define XHCI_LPM_SUPPORT BIT_ULL(11)
1842#define XHCI_INTEL_HOST BIT_ULL(12)
1843#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1844#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1845#define XHCI_AVOID_BEI BIT_ULL(15)
1846#define XHCI_PLAT BIT_ULL(16)
1847#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1848#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1849
1850#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1851#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1852#define XHCI_MTK_HOST BIT_ULL(21)
1853#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1854#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1855#define XHCI_MISSING_CAS BIT_ULL(24)
1856
1857#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1858#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1859#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1860#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1861#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1862#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1863#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1864#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1865#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1866#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1867#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1868
1869 unsigned int num_active_eps;
1870 unsigned int limit_active_eps;
1871 struct xhci_port *hw_ports;
1872 struct xhci_hub usb2_rhub;
1873 struct xhci_hub usb3_rhub;
1874
1875 unsigned hw_lpm_support:1;
1876
1877 unsigned broken_suspend:1;
1878
1879 u32 *ext_caps;
1880 unsigned int num_ext_caps;
1881
1882 struct timer_list comp_mode_recovery_timer;
1883 u32 port_status_u0;
1884 u16 test_mode;
1885
1886#define COMP_MODE_RCVRY_MSECS 2000
1887
1888 struct dentry *debugfs_root;
1889 struct dentry *debugfs_slots;
1890 struct list_head regset_list;
1891
1892 void *dbc;
1893
1894 unsigned long priv[0] __aligned(sizeof(s64));
1895};
1896
1897
1898struct xhci_driver_overrides {
1899 size_t extra_priv_size;
1900 int (*reset)(struct usb_hcd *hcd);
1901 int (*start)(struct usb_hcd *hcd);
1902};
1903
1904#define XHCI_CFC_DELAY 10
1905
1906
1907static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1908{
1909 struct usb_hcd *primary_hcd;
1910
1911 if (usb_hcd_is_primary_hcd(hcd))
1912 primary_hcd = hcd;
1913 else
1914 primary_hcd = hcd->primary_hcd;
1915
1916 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1917}
1918
1919static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1920{
1921 return xhci->main_hcd;
1922}
1923
1924#define xhci_dbg(xhci, fmt, args...) \
1925 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1926#define xhci_err(xhci, fmt, args...) \
1927 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1928#define xhci_warn(xhci, fmt, args...) \
1929 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1930#define xhci_warn_ratelimited(xhci, fmt, args...) \
1931 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1932#define xhci_info(xhci, fmt, args...) \
1933 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1934
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1945 __le64 __iomem *regs)
1946{
1947 return lo_hi_readq(regs);
1948}
1949static inline void xhci_write_64(struct xhci_hcd *xhci,
1950 const u64 val, __le64 __iomem *regs)
1951{
1952 lo_hi_writeq(val, regs);
1953}
1954
1955static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1956{
1957 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1958}
1959
1960
1961char *xhci_get_slot_state(struct xhci_hcd *xhci,
1962 struct xhci_container_ctx *ctx);
1963void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
1964 const char *fmt, ...);
1965
1966
1967void xhci_mem_cleanup(struct xhci_hcd *xhci);
1968int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
1969void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
1970int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
1971int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
1972void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1973 struct usb_device *udev);
1974unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
1975unsigned int xhci_get_endpoint_address(unsigned int ep_index);
1976unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
1977void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
1978void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
1979 struct xhci_virt_device *virt_dev,
1980 int old_active_eps);
1981void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
1982void xhci_update_bw_info(struct xhci_hcd *xhci,
1983 struct xhci_container_ctx *in_ctx,
1984 struct xhci_input_control_ctx *ctrl_ctx,
1985 struct xhci_virt_device *virt_dev);
1986void xhci_endpoint_copy(struct xhci_hcd *xhci,
1987 struct xhci_container_ctx *in_ctx,
1988 struct xhci_container_ctx *out_ctx,
1989 unsigned int ep_index);
1990void xhci_slot_copy(struct xhci_hcd *xhci,
1991 struct xhci_container_ctx *in_ctx,
1992 struct xhci_container_ctx *out_ctx);
1993int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
1994 struct usb_device *udev, struct usb_host_endpoint *ep,
1995 gfp_t mem_flags);
1996struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
1997 unsigned int num_segs, unsigned int cycle_state,
1998 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
1999void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2000int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2001 unsigned int num_trbs, gfp_t flags);
2002int xhci_alloc_erst(struct xhci_hcd *xhci,
2003 struct xhci_ring *evt_ring,
2004 struct xhci_erst *erst,
2005 gfp_t flags);
2006void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2007void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2008 struct xhci_virt_device *virt_dev,
2009 unsigned int ep_index);
2010struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2011 unsigned int num_stream_ctxs,
2012 unsigned int num_streams,
2013 unsigned int max_packet, gfp_t flags);
2014void xhci_free_stream_info(struct xhci_hcd *xhci,
2015 struct xhci_stream_info *stream_info);
2016void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2017 struct xhci_ep_ctx *ep_ctx,
2018 struct xhci_stream_info *stream_info);
2019void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2020 struct xhci_virt_ep *ep);
2021void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2022 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2023struct xhci_ring *xhci_dma_to_transfer_ring(
2024 struct xhci_virt_ep *ep,
2025 u64 address);
2026struct xhci_ring *xhci_stream_id_to_ring(
2027 struct xhci_virt_device *dev,
2028 unsigned int ep_index,
2029 unsigned int stream_id);
2030struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2031 bool allocate_completion, gfp_t mem_flags);
2032struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2033 bool allocate_completion, gfp_t mem_flags);
2034void xhci_urb_free_priv(struct urb_priv *urb_priv);
2035void xhci_free_command(struct xhci_hcd *xhci,
2036 struct xhci_command *command);
2037struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2038 int type, gfp_t flags);
2039void xhci_free_container_ctx(struct xhci_hcd *xhci,
2040 struct xhci_container_ctx *ctx);
2041
2042
2043typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2044int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2045void xhci_quiesce(struct xhci_hcd *xhci);
2046int xhci_halt(struct xhci_hcd *xhci);
2047int xhci_start(struct xhci_hcd *xhci);
2048int xhci_reset(struct xhci_hcd *xhci);
2049int xhci_run(struct usb_hcd *hcd);
2050int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2051void xhci_init_driver(struct hc_driver *drv,
2052 const struct xhci_driver_overrides *over);
2053int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2054int xhci_ext_cap_init(struct xhci_hcd *xhci);
2055
2056int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2057int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2058
2059irqreturn_t xhci_irq(struct usb_hcd *hcd);
2060irqreturn_t xhci_msi_irq(int irq, void *hcd);
2061int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2062int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2063 struct xhci_virt_device *virt_dev,
2064 struct usb_device *hdev,
2065 struct usb_tt *tt, gfp_t mem_flags);
2066
2067
2068dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2069struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2070 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2071 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2072int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2073void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2074int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2075 u32 trb_type, u32 slot_id);
2076int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2077 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2078int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2079 u32 field1, u32 field2, u32 field3, u32 field4);
2080int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2081 int slot_id, unsigned int ep_index, int suspend);
2082int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2083 int slot_id, unsigned int ep_index);
2084int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2085 int slot_id, unsigned int ep_index);
2086int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2087 int slot_id, unsigned int ep_index);
2088int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2089 struct urb *urb, int slot_id, unsigned int ep_index);
2090int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2091 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2092 bool command_must_succeed);
2093int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2094 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2095int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2096 int slot_id, unsigned int ep_index,
2097 enum xhci_ep_reset_type reset_type);
2098int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2099 u32 slot_id);
2100void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
2101 unsigned int slot_id, unsigned int ep_index,
2102 unsigned int stream_id, struct xhci_td *cur_td,
2103 struct xhci_dequeue_state *state);
2104void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
2105 unsigned int slot_id, unsigned int ep_index,
2106 struct xhci_dequeue_state *deq_state);
2107void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int ep_index,
2108 unsigned int stream_id, struct xhci_td *td);
2109void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2110void xhci_handle_command_timeout(struct work_struct *work);
2111
2112void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2113 unsigned int ep_index, unsigned int stream_id);
2114void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2115void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2116unsigned int count_trbs(u64 addr, u64 len);
2117
2118
2119void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2120 u32 link_state);
2121void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2122 u32 port_bit);
2123int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2124 char *buf, u16 wLength);
2125int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2126int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2127struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2128
2129void xhci_hc_died(struct xhci_hcd *xhci);
2130
2131#ifdef CONFIG_PM
2132int xhci_bus_suspend(struct usb_hcd *hcd);
2133int xhci_bus_resume(struct usb_hcd *hcd);
2134unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2135#else
2136#define xhci_bus_suspend NULL
2137#define xhci_bus_resume NULL
2138#define xhci_get_resuming_ports NULL
2139#endif
2140
2141u32 xhci_port_state_to_neutral(u32 state);
2142int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2143 u16 port);
2144void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2145
2146
2147struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2148struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2149struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2150
2151struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2152 unsigned int slot_id, unsigned int ep_index,
2153 unsigned int stream_id);
2154
2155static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2156 struct urb *urb)
2157{
2158 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2159 xhci_get_endpoint_index(&urb->ep->desc),
2160 urb->stream_id);
2161}
2162
2163
2164
2165
2166
2167
2168static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2169{
2170 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2171 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2172 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2173 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP))
2174 return true;
2175
2176 return false;
2177}
2178
2179static inline char *xhci_slot_state_string(u32 state)
2180{
2181 switch (state) {
2182 case SLOT_STATE_ENABLED:
2183 return "enabled/disabled";
2184 case SLOT_STATE_DEFAULT:
2185 return "default";
2186 case SLOT_STATE_ADDRESSED:
2187 return "addressed";
2188 case SLOT_STATE_CONFIGURED:
2189 return "configured";
2190 default:
2191 return "reserved";
2192 }
2193}
2194
2195static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2196 u32 field3)
2197{
2198 static char str[256];
2199 int type = TRB_FIELD_TO_TYPE(field3);
2200
2201 switch (type) {
2202 case TRB_LINK:
2203 sprintf(str,
2204 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2205 field1, field0, GET_INTR_TARGET(field2),
2206 xhci_trb_type_string(type),
2207 field3 & TRB_IOC ? 'I' : 'i',
2208 field3 & TRB_CHAIN ? 'C' : 'c',
2209 field3 & TRB_TC ? 'T' : 't',
2210 field3 & TRB_CYCLE ? 'C' : 'c');
2211 break;
2212 case TRB_TRANSFER:
2213 case TRB_COMPLETION:
2214 case TRB_PORT_STATUS:
2215 case TRB_BANDWIDTH_EVENT:
2216 case TRB_DOORBELL:
2217 case TRB_HC_EVENT:
2218 case TRB_DEV_NOTE:
2219 case TRB_MFINDEX_WRAP:
2220 sprintf(str,
2221 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2222 field1, field0,
2223 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2224 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2225
2226 TRB_TO_EP_INDEX(field3) + 1,
2227 xhci_trb_type_string(type),
2228 field3 & EVENT_DATA ? 'E' : 'e',
2229 field3 & TRB_CYCLE ? 'C' : 'c');
2230
2231 break;
2232 case TRB_SETUP:
2233 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2234 field0 & 0xff,
2235 (field0 & 0xff00) >> 8,
2236 (field0 & 0xff000000) >> 24,
2237 (field0 & 0xff0000) >> 16,
2238 (field1 & 0xff00) >> 8,
2239 field1 & 0xff,
2240 (field1 & 0xff000000) >> 16 |
2241 (field1 & 0xff0000) >> 16,
2242 TRB_LEN(field2), GET_TD_SIZE(field2),
2243 GET_INTR_TARGET(field2),
2244 xhci_trb_type_string(type),
2245 field3 & TRB_IDT ? 'I' : 'i',
2246 field3 & TRB_IOC ? 'I' : 'i',
2247 field3 & TRB_CYCLE ? 'C' : 'c');
2248 break;
2249 case TRB_DATA:
2250 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2251 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2252 GET_INTR_TARGET(field2),
2253 xhci_trb_type_string(type),
2254 field3 & TRB_IDT ? 'I' : 'i',
2255 field3 & TRB_IOC ? 'I' : 'i',
2256 field3 & TRB_CHAIN ? 'C' : 'c',
2257 field3 & TRB_NO_SNOOP ? 'S' : 's',
2258 field3 & TRB_ISP ? 'I' : 'i',
2259 field3 & TRB_ENT ? 'E' : 'e',
2260 field3 & TRB_CYCLE ? 'C' : 'c');
2261 break;
2262 case TRB_STATUS:
2263 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2264 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2265 GET_INTR_TARGET(field2),
2266 xhci_trb_type_string(type),
2267 field3 & TRB_IOC ? 'I' : 'i',
2268 field3 & TRB_CHAIN ? 'C' : 'c',
2269 field3 & TRB_ENT ? 'E' : 'e',
2270 field3 & TRB_CYCLE ? 'C' : 'c');
2271 break;
2272 case TRB_NORMAL:
2273 case TRB_ISOC:
2274 case TRB_EVENT_DATA:
2275 case TRB_TR_NOOP:
2276 sprintf(str,
2277 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2278 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2279 GET_INTR_TARGET(field2),
2280 xhci_trb_type_string(type),
2281 field3 & TRB_BEI ? 'B' : 'b',
2282 field3 & TRB_IDT ? 'I' : 'i',
2283 field3 & TRB_IOC ? 'I' : 'i',
2284 field3 & TRB_CHAIN ? 'C' : 'c',
2285 field3 & TRB_NO_SNOOP ? 'S' : 's',
2286 field3 & TRB_ISP ? 'I' : 'i',
2287 field3 & TRB_ENT ? 'E' : 'e',
2288 field3 & TRB_CYCLE ? 'C' : 'c');
2289 break;
2290
2291 case TRB_CMD_NOOP:
2292 case TRB_ENABLE_SLOT:
2293 sprintf(str,
2294 "%s: flags %c",
2295 xhci_trb_type_string(type),
2296 field3 & TRB_CYCLE ? 'C' : 'c');
2297 break;
2298 case TRB_DISABLE_SLOT:
2299 case TRB_NEG_BANDWIDTH:
2300 sprintf(str,
2301 "%s: slot %d flags %c",
2302 xhci_trb_type_string(type),
2303 TRB_TO_SLOT_ID(field3),
2304 field3 & TRB_CYCLE ? 'C' : 'c');
2305 break;
2306 case TRB_ADDR_DEV:
2307 sprintf(str,
2308 "%s: ctx %08x%08x slot %d flags %c:%c",
2309 xhci_trb_type_string(type),
2310 field1, field0,
2311 TRB_TO_SLOT_ID(field3),
2312 field3 & TRB_BSR ? 'B' : 'b',
2313 field3 & TRB_CYCLE ? 'C' : 'c');
2314 break;
2315 case TRB_CONFIG_EP:
2316 sprintf(str,
2317 "%s: ctx %08x%08x slot %d flags %c:%c",
2318 xhci_trb_type_string(type),
2319 field1, field0,
2320 TRB_TO_SLOT_ID(field3),
2321 field3 & TRB_DC ? 'D' : 'd',
2322 field3 & TRB_CYCLE ? 'C' : 'c');
2323 break;
2324 case TRB_EVAL_CONTEXT:
2325 sprintf(str,
2326 "%s: ctx %08x%08x slot %d flags %c",
2327 xhci_trb_type_string(type),
2328 field1, field0,
2329 TRB_TO_SLOT_ID(field3),
2330 field3 & TRB_CYCLE ? 'C' : 'c');
2331 break;
2332 case TRB_RESET_EP:
2333 sprintf(str,
2334 "%s: ctx %08x%08x slot %d ep %d flags %c",
2335 xhci_trb_type_string(type),
2336 field1, field0,
2337 TRB_TO_SLOT_ID(field3),
2338
2339 TRB_TO_EP_INDEX(field3) + 1,
2340 field3 & TRB_CYCLE ? 'C' : 'c');
2341 break;
2342 case TRB_STOP_RING:
2343 sprintf(str,
2344 "%s: slot %d sp %d ep %d flags %c",
2345 xhci_trb_type_string(type),
2346 TRB_TO_SLOT_ID(field3),
2347 TRB_TO_SUSPEND_PORT(field3),
2348
2349 TRB_TO_EP_INDEX(field3) + 1,
2350 field3 & TRB_CYCLE ? 'C' : 'c');
2351 break;
2352 case TRB_SET_DEQ:
2353 sprintf(str,
2354 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2355 xhci_trb_type_string(type),
2356 field1, field0,
2357 TRB_TO_STREAM_ID(field2),
2358 TRB_TO_SLOT_ID(field3),
2359
2360 TRB_TO_EP_INDEX(field3) + 1,
2361 field3 & TRB_CYCLE ? 'C' : 'c');
2362 break;
2363 case TRB_RESET_DEV:
2364 sprintf(str,
2365 "%s: slot %d flags %c",
2366 xhci_trb_type_string(type),
2367 TRB_TO_SLOT_ID(field3),
2368 field3 & TRB_CYCLE ? 'C' : 'c');
2369 break;
2370 case TRB_FORCE_EVENT:
2371 sprintf(str,
2372 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2373 xhci_trb_type_string(type),
2374 field1, field0,
2375 TRB_TO_VF_INTR_TARGET(field2),
2376 TRB_TO_VF_ID(field3),
2377 field3 & TRB_CYCLE ? 'C' : 'c');
2378 break;
2379 case TRB_SET_LT:
2380 sprintf(str,
2381 "%s: belt %d flags %c",
2382 xhci_trb_type_string(type),
2383 TRB_TO_BELT(field3),
2384 field3 & TRB_CYCLE ? 'C' : 'c');
2385 break;
2386 case TRB_GET_BW:
2387 sprintf(str,
2388 "%s: ctx %08x%08x slot %d speed %d flags %c",
2389 xhci_trb_type_string(type),
2390 field1, field0,
2391 TRB_TO_SLOT_ID(field3),
2392 TRB_TO_DEV_SPEED(field3),
2393 field3 & TRB_CYCLE ? 'C' : 'c');
2394 break;
2395 case TRB_FORCE_HEADER:
2396 sprintf(str,
2397 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2398 xhci_trb_type_string(type),
2399 field2, field1, field0 & 0xffffffe0,
2400 TRB_TO_PACKET_TYPE(field0),
2401 TRB_TO_ROOTHUB_PORT(field3),
2402 field3 & TRB_CYCLE ? 'C' : 'c');
2403 break;
2404 default:
2405 sprintf(str,
2406 "type '%s' -> raw %08x %08x %08x %08x",
2407 xhci_trb_type_string(type),
2408 field0, field1, field2, field3);
2409 }
2410
2411 return str;
2412}
2413
2414static inline const char *xhci_decode_ctrl_ctx(unsigned long drop,
2415 unsigned long add)
2416{
2417 static char str[1024];
2418 unsigned int bit;
2419 int ret = 0;
2420
2421 if (drop) {
2422 ret = sprintf(str, "Drop:");
2423 for_each_set_bit(bit, &drop, 32)
2424 ret += sprintf(str + ret, " %d%s",
2425 bit / 2,
2426 bit % 2 ? "in":"out");
2427 ret += sprintf(str + ret, ", ");
2428 }
2429
2430 if (add) {
2431 ret += sprintf(str + ret, "Add:%s%s",
2432 (add & SLOT_FLAG) ? " slot":"",
2433 (add & EP0_FLAG) ? " ep0":"");
2434 add &= ~(SLOT_FLAG | EP0_FLAG);
2435 for_each_set_bit(bit, &add, 32)
2436 ret += sprintf(str + ret, " %d%s",
2437 bit / 2,
2438 bit % 2 ? "in":"out");
2439 }
2440 return str;
2441}
2442
2443static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2444 u32 tt_info, u32 state)
2445{
2446 static char str[1024];
2447 u32 speed;
2448 u32 hub;
2449 u32 mtt;
2450 int ret = 0;
2451
2452 speed = info & DEV_SPEED;
2453 hub = info & DEV_HUB;
2454 mtt = info & DEV_MTT;
2455
2456 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2457 info & ROUTE_STRING_MASK,
2458 ({ char *s;
2459 switch (speed) {
2460 case SLOT_SPEED_FS:
2461 s = "full-speed";
2462 break;
2463 case SLOT_SPEED_LS:
2464 s = "low-speed";
2465 break;
2466 case SLOT_SPEED_HS:
2467 s = "high-speed";
2468 break;
2469 case SLOT_SPEED_SS:
2470 s = "super-speed";
2471 break;
2472 case SLOT_SPEED_SSP:
2473 s = "super-speed plus";
2474 break;
2475 default:
2476 s = "UNKNOWN speed";
2477 } s; }),
2478 mtt ? " multi-TT" : "",
2479 hub ? " Hub" : "",
2480 (info & LAST_CTX_MASK) >> 27,
2481 info2 & MAX_EXIT,
2482 DEVINFO_TO_ROOT_HUB_PORT(info2),
2483 DEVINFO_TO_MAX_PORTS(info2));
2484
2485 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2486 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2487 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2488 state & DEV_ADDR_MASK,
2489 xhci_slot_state_string(GET_SLOT_STATE(state)));
2490
2491 return str;
2492}
2493
2494
2495static inline const char *xhci_portsc_link_state_string(u32 portsc)
2496{
2497 switch (portsc & PORT_PLS_MASK) {
2498 case XDEV_U0:
2499 return "U0";
2500 case XDEV_U1:
2501 return "U1";
2502 case XDEV_U2:
2503 return "U2";
2504 case XDEV_U3:
2505 return "U3";
2506 case XDEV_DISABLED:
2507 return "Disabled";
2508 case XDEV_RXDETECT:
2509 return "RxDetect";
2510 case XDEV_INACTIVE:
2511 return "Inactive";
2512 case XDEV_POLLING:
2513 return "Polling";
2514 case XDEV_RECOVERY:
2515 return "Recovery";
2516 case XDEV_HOT_RESET:
2517 return "Hot Reset";
2518 case XDEV_COMP_MODE:
2519 return "Compliance mode";
2520 case XDEV_TEST_MODE:
2521 return "Test mode";
2522 case XDEV_RESUME:
2523 return "Resume";
2524 default:
2525 break;
2526 }
2527 return "Unknown";
2528}
2529
2530static inline const char *xhci_decode_portsc(u32 portsc)
2531{
2532 static char str[256];
2533 int ret;
2534
2535 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2536 portsc & PORT_POWER ? "Powered" : "Powered-off",
2537 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2538 portsc & PORT_PE ? "Enabled" : "Disabled",
2539 xhci_portsc_link_state_string(portsc),
2540 DEV_PORT_SPEED(portsc));
2541
2542 if (portsc & PORT_OC)
2543 ret += sprintf(str + ret, "OverCurrent ");
2544 if (portsc & PORT_RESET)
2545 ret += sprintf(str + ret, "In-Reset ");
2546
2547 ret += sprintf(str + ret, "Change: ");
2548 if (portsc & PORT_CSC)
2549 ret += sprintf(str + ret, "CSC ");
2550 if (portsc & PORT_PEC)
2551 ret += sprintf(str + ret, "PEC ");
2552 if (portsc & PORT_WRC)
2553 ret += sprintf(str + ret, "WRC ");
2554 if (portsc & PORT_OCC)
2555 ret += sprintf(str + ret, "OCC ");
2556 if (portsc & PORT_RC)
2557 ret += sprintf(str + ret, "PRC ");
2558 if (portsc & PORT_PLC)
2559 ret += sprintf(str + ret, "PLC ");
2560 if (portsc & PORT_CEC)
2561 ret += sprintf(str + ret, "CEC ");
2562 if (portsc & PORT_CAS)
2563 ret += sprintf(str + ret, "CAS ");
2564
2565 ret += sprintf(str + ret, "Wake: ");
2566 if (portsc & PORT_WKCONN_E)
2567 ret += sprintf(str + ret, "WCE ");
2568 if (portsc & PORT_WKDISC_E)
2569 ret += sprintf(str + ret, "WDE ");
2570 if (portsc & PORT_WKOC_E)
2571 ret += sprintf(str + ret, "WOE ");
2572
2573 return str;
2574}
2575
2576static inline const char *xhci_ep_state_string(u8 state)
2577{
2578 switch (state) {
2579 case EP_STATE_DISABLED:
2580 return "disabled";
2581 case EP_STATE_RUNNING:
2582 return "running";
2583 case EP_STATE_HALTED:
2584 return "halted";
2585 case EP_STATE_STOPPED:
2586 return "stopped";
2587 case EP_STATE_ERROR:
2588 return "error";
2589 default:
2590 return "INVALID";
2591 }
2592}
2593
2594static inline const char *xhci_ep_type_string(u8 type)
2595{
2596 switch (type) {
2597 case ISOC_OUT_EP:
2598 return "Isoc OUT";
2599 case BULK_OUT_EP:
2600 return "Bulk OUT";
2601 case INT_OUT_EP:
2602 return "Int OUT";
2603 case CTRL_EP:
2604 return "Ctrl";
2605 case ISOC_IN_EP:
2606 return "Isoc IN";
2607 case BULK_IN_EP:
2608 return "Bulk IN";
2609 case INT_IN_EP:
2610 return "Int IN";
2611 default:
2612 return "INVALID";
2613 }
2614}
2615
2616static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2617 u32 tx_info)
2618{
2619 static char str[1024];
2620 int ret;
2621
2622 u32 esit;
2623 u16 maxp;
2624 u16 avg;
2625
2626 u8 max_pstr;
2627 u8 ep_state;
2628 u8 interval;
2629 u8 ep_type;
2630 u8 burst;
2631 u8 cerr;
2632 u8 mult;
2633
2634 bool lsa;
2635 bool hid;
2636
2637 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2638 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2639
2640 ep_state = info & EP_STATE_MASK;
2641 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2642 interval = CTX_TO_EP_INTERVAL(info);
2643 mult = CTX_TO_EP_MULT(info) + 1;
2644 lsa = !!(info & EP_HAS_LSA);
2645
2646 cerr = (info2 & (3 << 1)) >> 1;
2647 ep_type = CTX_TO_EP_TYPE(info2);
2648 hid = !!(info2 & (1 << 7));
2649 burst = CTX_TO_MAX_BURST(info2);
2650 maxp = MAX_PACKET_DECODED(info2);
2651
2652 avg = EP_AVG_TRB_LENGTH(tx_info);
2653
2654 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2655 xhci_ep_state_string(ep_state), mult,
2656 max_pstr, lsa ? "LSA " : "");
2657
2658 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2659 (1 << interval) * 125, esit, cerr);
2660
2661 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2662 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2663 burst, maxp, deq);
2664
2665 ret += sprintf(str + ret, "avg trb len %d", avg);
2666
2667 return str;
2668}
2669
2670#endif
2671