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67#include <linux/module.h>
68#include <linux/kernel.h>
69#include <linux/sched.h>
70#include <linux/slab.h>
71#include <linux/list.h>
72#include <linux/kobject.h>
73#include <linux/prefetch.h>
74#include <linux/platform_device.h>
75#include <linux/io.h>
76#include <linux/dma-mapping.h>
77#include <linux/usb.h>
78#include <linux/usb/of.h>
79
80#include "musb_core.h"
81#include "musb_trace.h"
82
83#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
84
85
86#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
87#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
88
89#define MUSB_VERSION "6.0"
90
91#define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
92
93#define MUSB_DRIVER_NAME "musb-hdrc"
94const char musb_driver_name[] = MUSB_DRIVER_NAME;
95
96MODULE_DESCRIPTION(DRIVER_INFO);
97MODULE_AUTHOR(DRIVER_AUTHOR);
98MODULE_LICENSE("GPL");
99MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
100
101
102
103
104static inline struct musb *dev_to_musb(struct device *dev)
105{
106 return dev_get_drvdata(dev);
107}
108
109enum musb_mode musb_get_mode(struct device *dev)
110{
111 enum usb_dr_mode mode;
112
113 mode = usb_get_dr_mode(dev);
114 switch (mode) {
115 case USB_DR_MODE_HOST:
116 return MUSB_HOST;
117 case USB_DR_MODE_PERIPHERAL:
118 return MUSB_PERIPHERAL;
119 case USB_DR_MODE_OTG:
120 case USB_DR_MODE_UNKNOWN:
121 default:
122 return MUSB_OTG;
123 }
124}
125EXPORT_SYMBOL_GPL(musb_get_mode);
126
127
128
129static int musb_ulpi_read(struct usb_phy *phy, u32 reg)
130{
131 void __iomem *addr = phy->io_priv;
132 int i = 0;
133 u8 r;
134 u8 power;
135 int ret;
136
137 pm_runtime_get_sync(phy->io_dev);
138
139
140 power = musb_readb(addr, MUSB_POWER);
141 power &= ~MUSB_POWER_SUSPENDM;
142 musb_writeb(addr, MUSB_POWER, power);
143
144
145
146
147
148 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
149 musb_writeb(addr, MUSB_ULPI_REG_CONTROL,
150 MUSB_ULPI_REG_REQ | MUSB_ULPI_RDN_WR);
151
152 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
153 & MUSB_ULPI_REG_CMPLT)) {
154 i++;
155 if (i == 10000) {
156 ret = -ETIMEDOUT;
157 goto out;
158 }
159
160 }
161 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
162 r &= ~MUSB_ULPI_REG_CMPLT;
163 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
164
165 ret = musb_readb(addr, MUSB_ULPI_REG_DATA);
166
167out:
168 pm_runtime_put(phy->io_dev);
169
170 return ret;
171}
172
173static int musb_ulpi_write(struct usb_phy *phy, u32 val, u32 reg)
174{
175 void __iomem *addr = phy->io_priv;
176 int i = 0;
177 u8 r = 0;
178 u8 power;
179 int ret = 0;
180
181 pm_runtime_get_sync(phy->io_dev);
182
183
184 power = musb_readb(addr, MUSB_POWER);
185 power &= ~MUSB_POWER_SUSPENDM;
186 musb_writeb(addr, MUSB_POWER, power);
187
188 musb_writeb(addr, MUSB_ULPI_REG_ADDR, (u8)reg);
189 musb_writeb(addr, MUSB_ULPI_REG_DATA, (u8)val);
190 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, MUSB_ULPI_REG_REQ);
191
192 while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
193 & MUSB_ULPI_REG_CMPLT)) {
194 i++;
195 if (i == 10000) {
196 ret = -ETIMEDOUT;
197 goto out;
198 }
199 }
200
201 r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
202 r &= ~MUSB_ULPI_REG_CMPLT;
203 musb_writeb(addr, MUSB_ULPI_REG_CONTROL, r);
204
205out:
206 pm_runtime_put(phy->io_dev);
207
208 return ret;
209}
210
211static struct usb_phy_io_ops musb_ulpi_access = {
212 .read = musb_ulpi_read,
213 .write = musb_ulpi_write,
214};
215
216
217
218static u32 musb_default_fifo_offset(u8 epnum)
219{
220 return 0x20 + (epnum * 4);
221}
222
223
224static void musb_flat_ep_select(void __iomem *mbase, u8 epnum)
225{
226}
227
228static u32 musb_flat_ep_offset(u8 epnum, u16 offset)
229{
230 return 0x100 + (0x10 * epnum) + offset;
231}
232
233
234static void musb_indexed_ep_select(void __iomem *mbase, u8 epnum)
235{
236 musb_writeb(mbase, MUSB_INDEX, epnum);
237}
238
239static u32 musb_indexed_ep_offset(u8 epnum, u16 offset)
240{
241 return 0x10 + offset;
242}
243
244static u32 musb_default_busctl_offset(u8 epnum, u16 offset)
245{
246 return 0x80 + (0x08 * epnum) + offset;
247}
248
249static u8 musb_default_readb(const void __iomem *addr, unsigned offset)
250{
251 u8 data = __raw_readb(addr + offset);
252
253 trace_musb_readb(__builtin_return_address(0), addr, offset, data);
254 return data;
255}
256
257static void musb_default_writeb(void __iomem *addr, unsigned offset, u8 data)
258{
259 trace_musb_writeb(__builtin_return_address(0), addr, offset, data);
260 __raw_writeb(data, addr + offset);
261}
262
263static u16 musb_default_readw(const void __iomem *addr, unsigned offset)
264{
265 u16 data = __raw_readw(addr + offset);
266
267 trace_musb_readw(__builtin_return_address(0), addr, offset, data);
268 return data;
269}
270
271static void musb_default_writew(void __iomem *addr, unsigned offset, u16 data)
272{
273 trace_musb_writew(__builtin_return_address(0), addr, offset, data);
274 __raw_writew(data, addr + offset);
275}
276
277
278
279
280static void musb_default_write_fifo(struct musb_hw_ep *hw_ep, u16 len,
281 const u8 *src)
282{
283 struct musb *musb = hw_ep->musb;
284 void __iomem *fifo = hw_ep->fifo;
285
286 if (unlikely(len == 0))
287 return;
288
289 prefetch((u8 *)src);
290
291 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
292 'T', hw_ep->epnum, fifo, len, src);
293
294
295 if (likely((0x01 & (unsigned long) src) == 0)) {
296 u16 index = 0;
297
298
299 if ((0x02 & (unsigned long) src) == 0) {
300 if (len >= 4) {
301 iowrite32_rep(fifo, src + index, len >> 2);
302 index += len & ~0x03;
303 }
304 if (len & 0x02) {
305 __raw_writew(*(u16 *)&src[index], fifo);
306 index += 2;
307 }
308 } else {
309 if (len >= 2) {
310 iowrite16_rep(fifo, src + index, len >> 1);
311 index += len & ~0x01;
312 }
313 }
314 if (len & 0x01)
315 __raw_writeb(src[index], fifo);
316 } else {
317
318 iowrite8_rep(fifo, src, len);
319 }
320}
321
322
323
324
325static void musb_default_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
326{
327 struct musb *musb = hw_ep->musb;
328 void __iomem *fifo = hw_ep->fifo;
329
330 if (unlikely(len == 0))
331 return;
332
333 dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
334 'R', hw_ep->epnum, fifo, len, dst);
335
336
337 if (likely((0x01 & (unsigned long) dst) == 0)) {
338 u16 index = 0;
339
340
341 if ((0x02 & (unsigned long) dst) == 0) {
342 if (len >= 4) {
343 ioread32_rep(fifo, dst, len >> 2);
344 index = len & ~0x03;
345 }
346 if (len & 0x02) {
347 *(u16 *)&dst[index] = __raw_readw(fifo);
348 index += 2;
349 }
350 } else {
351 if (len >= 2) {
352 ioread16_rep(fifo, dst, len >> 1);
353 index = len & ~0x01;
354 }
355 }
356 if (len & 0x01)
357 dst[index] = __raw_readb(fifo);
358 } else {
359
360 ioread8_rep(fifo, dst, len);
361 }
362}
363
364
365
366
367u8 (*musb_readb)(const void __iomem *addr, unsigned offset);
368EXPORT_SYMBOL_GPL(musb_readb);
369
370void (*musb_writeb)(void __iomem *addr, unsigned offset, u8 data);
371EXPORT_SYMBOL_GPL(musb_writeb);
372
373u16 (*musb_readw)(const void __iomem *addr, unsigned offset);
374EXPORT_SYMBOL_GPL(musb_readw);
375
376void (*musb_writew)(void __iomem *addr, unsigned offset, u16 data);
377EXPORT_SYMBOL_GPL(musb_writew);
378
379u32 musb_readl(const void __iomem *addr, unsigned offset)
380{
381 u32 data = __raw_readl(addr + offset);
382
383 trace_musb_readl(__builtin_return_address(0), addr, offset, data);
384 return data;
385}
386EXPORT_SYMBOL_GPL(musb_readl);
387
388void musb_writel(void __iomem *addr, unsigned offset, u32 data)
389{
390 trace_musb_writel(__builtin_return_address(0), addr, offset, data);
391 __raw_writel(data, addr + offset);
392}
393EXPORT_SYMBOL_GPL(musb_writel);
394
395#ifndef CONFIG_MUSB_PIO_ONLY
396struct dma_controller *
397(*musb_dma_controller_create)(struct musb *musb, void __iomem *base);
398EXPORT_SYMBOL(musb_dma_controller_create);
399
400void (*musb_dma_controller_destroy)(struct dma_controller *c);
401EXPORT_SYMBOL(musb_dma_controller_destroy);
402#endif
403
404
405
406
407void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
408{
409 return hw_ep->musb->io.read_fifo(hw_ep, len, dst);
410}
411
412void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
413{
414 return hw_ep->musb->io.write_fifo(hw_ep, len, src);
415}
416
417
418
419
420static const u8 musb_test_packet[53] = {
421
422
423
424 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
425
426 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
427
428 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
429
430 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
431
432 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
433
434 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
435
436
437};
438
439void musb_load_testpacket(struct musb *musb)
440{
441 void __iomem *regs = musb->endpoints[0].regs;
442
443 musb_ep_select(musb->mregs, 0);
444 musb_write_fifo(musb->control_ep,
445 sizeof(musb_test_packet), musb_test_packet);
446 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
447}
448
449
450
451
452
453
454static void musb_otg_timer_func(struct timer_list *t)
455{
456 struct musb *musb = from_timer(musb, t, otg_timer);
457 unsigned long flags;
458
459 spin_lock_irqsave(&musb->lock, flags);
460 switch (musb->xceiv->otg->state) {
461 case OTG_STATE_B_WAIT_ACON:
462 musb_dbg(musb,
463 "HNP: b_wait_acon timeout; back to b_peripheral");
464 musb_g_disconnect(musb);
465 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
466 musb->is_active = 0;
467 break;
468 case OTG_STATE_A_SUSPEND:
469 case OTG_STATE_A_WAIT_BCON:
470 musb_dbg(musb, "HNP: %s timeout",
471 usb_otg_state_string(musb->xceiv->otg->state));
472 musb_platform_set_vbus(musb, 0);
473 musb->xceiv->otg->state = OTG_STATE_A_WAIT_VFALL;
474 break;
475 default:
476 musb_dbg(musb, "HNP: Unhandled mode %s",
477 usb_otg_state_string(musb->xceiv->otg->state));
478 }
479 spin_unlock_irqrestore(&musb->lock, flags);
480}
481
482
483
484
485void musb_hnp_stop(struct musb *musb)
486{
487 struct usb_hcd *hcd = musb->hcd;
488 void __iomem *mbase = musb->mregs;
489 u8 reg;
490
491 musb_dbg(musb, "HNP: stop from %s",
492 usb_otg_state_string(musb->xceiv->otg->state));
493
494 switch (musb->xceiv->otg->state) {
495 case OTG_STATE_A_PERIPHERAL:
496 musb_g_disconnect(musb);
497 musb_dbg(musb, "HNP: back to %s",
498 usb_otg_state_string(musb->xceiv->otg->state));
499 break;
500 case OTG_STATE_B_HOST:
501 musb_dbg(musb, "HNP: Disabling HR");
502 if (hcd)
503 hcd->self.is_b_host = 0;
504 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
505 MUSB_DEV_MODE(musb);
506 reg = musb_readb(mbase, MUSB_POWER);
507 reg |= MUSB_POWER_SUSPENDM;
508 musb_writeb(mbase, MUSB_POWER, reg);
509
510 break;
511 default:
512 musb_dbg(musb, "HNP: Stopping in unknown state %s",
513 usb_otg_state_string(musb->xceiv->otg->state));
514 }
515
516
517
518
519
520
521 musb->port1_status &= ~(USB_PORT_STAT_C_CONNECTION << 16);
522}
523
524static void musb_recover_from_babble(struct musb *musb);
525
526static void musb_handle_intr_resume(struct musb *musb, u8 devctl)
527{
528 musb_dbg(musb, "RESUME (%s)",
529 usb_otg_state_string(musb->xceiv->otg->state));
530
531 if (devctl & MUSB_DEVCTL_HM) {
532 switch (musb->xceiv->otg->state) {
533 case OTG_STATE_A_SUSPEND:
534
535 musb->port1_status |=
536 (USB_PORT_STAT_C_SUSPEND << 16)
537 | MUSB_PORT_STAT_RESUME;
538 musb->rh_timer = jiffies
539 + msecs_to_jiffies(USB_RESUME_TIMEOUT);
540 musb->xceiv->otg->state = OTG_STATE_A_HOST;
541 musb->is_active = 1;
542 musb_host_resume_root_hub(musb);
543 schedule_delayed_work(&musb->finish_resume_work,
544 msecs_to_jiffies(USB_RESUME_TIMEOUT));
545 break;
546 case OTG_STATE_B_WAIT_ACON:
547 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
548 musb->is_active = 1;
549 MUSB_DEV_MODE(musb);
550 break;
551 default:
552 WARNING("bogus %s RESUME (%s)\n",
553 "host",
554 usb_otg_state_string(musb->xceiv->otg->state));
555 }
556 } else {
557 switch (musb->xceiv->otg->state) {
558 case OTG_STATE_A_SUSPEND:
559
560 musb->xceiv->otg->state = OTG_STATE_A_HOST;
561 musb_host_resume_root_hub(musb);
562 break;
563 case OTG_STATE_B_WAIT_ACON:
564 case OTG_STATE_B_PERIPHERAL:
565
566
567
568 if ((devctl & MUSB_DEVCTL_VBUS)
569 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
570 ) {
571 musb->int_usb |= MUSB_INTR_DISCONNECT;
572 musb->int_usb &= ~MUSB_INTR_SUSPEND;
573 break;
574 }
575 musb_g_resume(musb);
576 break;
577 case OTG_STATE_B_IDLE:
578 musb->int_usb &= ~MUSB_INTR_SUSPEND;
579 break;
580 default:
581 WARNING("bogus %s RESUME (%s)\n",
582 "peripheral",
583 usb_otg_state_string(musb->xceiv->otg->state));
584 }
585 }
586}
587
588
589static irqreturn_t musb_handle_intr_sessreq(struct musb *musb, u8 devctl)
590{
591 void __iomem *mbase = musb->mregs;
592
593 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
594 && (devctl & MUSB_DEVCTL_BDEVICE)) {
595 musb_dbg(musb, "SessReq while on B state");
596 return IRQ_HANDLED;
597 }
598
599 musb_dbg(musb, "SESSION_REQUEST (%s)",
600 usb_otg_state_string(musb->xceiv->otg->state));
601
602
603
604
605
606
607
608
609 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
610 musb->ep0_stage = MUSB_EP0_START;
611 musb->xceiv->otg->state = OTG_STATE_A_IDLE;
612 MUSB_HST_MODE(musb);
613 musb_platform_set_vbus(musb, 1);
614
615 return IRQ_NONE;
616}
617
618static void musb_handle_intr_vbuserr(struct musb *musb, u8 devctl)
619{
620 int ignore = 0;
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638 switch (musb->xceiv->otg->state) {
639 case OTG_STATE_A_HOST:
640
641
642
643
644
645
646 case OTG_STATE_A_WAIT_BCON:
647 case OTG_STATE_A_WAIT_VRISE:
648 if (musb->vbuserr_retry) {
649 void __iomem *mbase = musb->mregs;
650
651 musb->vbuserr_retry--;
652 ignore = 1;
653 devctl |= MUSB_DEVCTL_SESSION;
654 musb_writeb(mbase, MUSB_DEVCTL, devctl);
655 } else {
656 musb->port1_status |=
657 USB_PORT_STAT_OVERCURRENT
658 | (USB_PORT_STAT_C_OVERCURRENT << 16);
659 }
660 break;
661 default:
662 break;
663 }
664
665 dev_printk(ignore ? KERN_DEBUG : KERN_ERR, musb->controller,
666 "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
667 usb_otg_state_string(musb->xceiv->otg->state),
668 devctl,
669 ({ char *s;
670 switch (devctl & MUSB_DEVCTL_VBUS) {
671 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
672 s = "<SessEnd"; break;
673 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
674 s = "<AValid"; break;
675 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
676 s = "<VBusValid"; break;
677
678 default:
679 s = "VALID"; break;
680 } s; }),
681 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
682 musb->port1_status);
683
684
685 if (!ignore)
686 musb_platform_set_vbus(musb, 0);
687}
688
689static void musb_handle_intr_suspend(struct musb *musb, u8 devctl)
690{
691 musb_dbg(musb, "SUSPEND (%s) devctl %02x",
692 usb_otg_state_string(musb->xceiv->otg->state), devctl);
693
694 switch (musb->xceiv->otg->state) {
695 case OTG_STATE_A_PERIPHERAL:
696
697
698
699
700
701
702
703 musb_hnp_stop(musb);
704 musb_host_resume_root_hub(musb);
705 musb_root_disconnect(musb);
706 musb_platform_try_idle(musb, jiffies
707 + msecs_to_jiffies(musb->a_wait_bcon
708 ? : OTG_TIME_A_WAIT_BCON));
709
710 break;
711 case OTG_STATE_B_IDLE:
712 if (!musb->is_active)
713 break;
714
715 case OTG_STATE_B_PERIPHERAL:
716 musb_g_suspend(musb);
717 musb->is_active = musb->g.b_hnp_enable;
718 if (musb->is_active) {
719 musb->xceiv->otg->state = OTG_STATE_B_WAIT_ACON;
720 musb_dbg(musb, "HNP: Setting timer for b_ase0_brst");
721 mod_timer(&musb->otg_timer, jiffies
722 + msecs_to_jiffies(
723 OTG_TIME_B_ASE0_BRST));
724 }
725 break;
726 case OTG_STATE_A_WAIT_BCON:
727 if (musb->a_wait_bcon != 0)
728 musb_platform_try_idle(musb, jiffies
729 + msecs_to_jiffies(musb->a_wait_bcon));
730 break;
731 case OTG_STATE_A_HOST:
732 musb->xceiv->otg->state = OTG_STATE_A_SUSPEND;
733 musb->is_active = musb->hcd->self.b_hnp_enable;
734 break;
735 case OTG_STATE_B_HOST:
736
737 musb_dbg(musb, "REVISIT: SUSPEND as B_HOST");
738 break;
739 default:
740
741 musb->is_active = 0;
742 break;
743 }
744}
745
746static void musb_handle_intr_connect(struct musb *musb, u8 devctl, u8 int_usb)
747{
748 struct usb_hcd *hcd = musb->hcd;
749
750 musb->is_active = 1;
751 musb->ep0_stage = MUSB_EP0_START;
752
753 musb->intrtxe = musb->epmask;
754 musb_writew(musb->mregs, MUSB_INTRTXE, musb->intrtxe);
755 musb->intrrxe = musb->epmask & 0xfffe;
756 musb_writew(musb->mregs, MUSB_INTRRXE, musb->intrrxe);
757 musb_writeb(musb->mregs, MUSB_INTRUSBE, 0xf7);
758 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
759 |USB_PORT_STAT_HIGH_SPEED
760 |USB_PORT_STAT_ENABLE
761 );
762 musb->port1_status |= USB_PORT_STAT_CONNECTION
763 |(USB_PORT_STAT_C_CONNECTION << 16);
764
765
766 if (devctl & MUSB_DEVCTL_LSDEV)
767 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
768
769
770 switch (musb->xceiv->otg->state) {
771 case OTG_STATE_B_PERIPHERAL:
772 if (int_usb & MUSB_INTR_SUSPEND) {
773 musb_dbg(musb, "HNP: SUSPEND+CONNECT, now b_host");
774 int_usb &= ~MUSB_INTR_SUSPEND;
775 goto b_host;
776 } else
777 musb_dbg(musb, "CONNECT as b_peripheral???");
778 break;
779 case OTG_STATE_B_WAIT_ACON:
780 musb_dbg(musb, "HNP: CONNECT, now b_host");
781b_host:
782 musb->xceiv->otg->state = OTG_STATE_B_HOST;
783 if (musb->hcd)
784 musb->hcd->self.is_b_host = 1;
785 del_timer(&musb->otg_timer);
786 break;
787 default:
788 if ((devctl & MUSB_DEVCTL_VBUS)
789 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
790 musb->xceiv->otg->state = OTG_STATE_A_HOST;
791 if (hcd)
792 hcd->self.is_b_host = 0;
793 }
794 break;
795 }
796
797 musb_host_poke_root_hub(musb);
798
799 musb_dbg(musb, "CONNECT (%s) devctl %02x",
800 usb_otg_state_string(musb->xceiv->otg->state), devctl);
801}
802
803static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
804{
805 musb_dbg(musb, "DISCONNECT (%s) as %s, devctl %02x",
806 usb_otg_state_string(musb->xceiv->otg->state),
807 MUSB_MODE(musb), devctl);
808
809 switch (musb->xceiv->otg->state) {
810 case OTG_STATE_A_HOST:
811 case OTG_STATE_A_SUSPEND:
812 musb_host_resume_root_hub(musb);
813 musb_root_disconnect(musb);
814 if (musb->a_wait_bcon != 0)
815 musb_platform_try_idle(musb, jiffies
816 + msecs_to_jiffies(musb->a_wait_bcon));
817 break;
818 case OTG_STATE_B_HOST:
819
820
821
822
823
824 musb_root_disconnect(musb);
825 if (musb->hcd)
826 musb->hcd->self.is_b_host = 0;
827 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
828 MUSB_DEV_MODE(musb);
829 musb_g_disconnect(musb);
830 break;
831 case OTG_STATE_A_PERIPHERAL:
832 musb_hnp_stop(musb);
833 musb_root_disconnect(musb);
834
835 case OTG_STATE_B_WAIT_ACON:
836
837 case OTG_STATE_B_PERIPHERAL:
838 case OTG_STATE_B_IDLE:
839 musb_g_disconnect(musb);
840 break;
841 default:
842 WARNING("unhandled DISCONNECT transition (%s)\n",
843 usb_otg_state_string(musb->xceiv->otg->state));
844 break;
845 }
846}
847
848
849
850
851
852static void musb_handle_intr_reset(struct musb *musb)
853{
854 if (is_host_active(musb)) {
855
856
857
858
859
860
861
862
863 dev_err(musb->controller, "Babble\n");
864 musb_recover_from_babble(musb);
865 } else {
866 musb_dbg(musb, "BUS RESET as %s",
867 usb_otg_state_string(musb->xceiv->otg->state));
868 switch (musb->xceiv->otg->state) {
869 case OTG_STATE_A_SUSPEND:
870 musb_g_reset(musb);
871
872 case OTG_STATE_A_WAIT_BCON:
873
874 musb_dbg(musb, "HNP: in %s, %d msec timeout",
875 usb_otg_state_string(musb->xceiv->otg->state),
876 TA_WAIT_BCON(musb));
877 mod_timer(&musb->otg_timer, jiffies
878 + msecs_to_jiffies(TA_WAIT_BCON(musb)));
879 break;
880 case OTG_STATE_A_PERIPHERAL:
881 del_timer(&musb->otg_timer);
882 musb_g_reset(musb);
883 break;
884 case OTG_STATE_B_WAIT_ACON:
885 musb_dbg(musb, "HNP: RESET (%s), to b_peripheral",
886 usb_otg_state_string(musb->xceiv->otg->state));
887 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
888 musb_g_reset(musb);
889 break;
890 case OTG_STATE_B_IDLE:
891 musb->xceiv->otg->state = OTG_STATE_B_PERIPHERAL;
892
893 case OTG_STATE_B_PERIPHERAL:
894 musb_g_reset(musb);
895 break;
896 default:
897 musb_dbg(musb, "Unhandled BUS RESET as %s",
898 usb_otg_state_string(musb->xceiv->otg->state));
899 }
900 }
901}
902
903
904
905
906
907
908
909
910
911
912
913
914
915static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
916 u8 devctl)
917{
918 irqreturn_t handled = IRQ_NONE;
919
920 musb_dbg(musb, "<== DevCtl=%02x, int_usb=0x%x", devctl, int_usb);
921
922
923
924
925
926 if (int_usb & MUSB_INTR_RESUME) {
927 musb_handle_intr_resume(musb, devctl);
928 handled = IRQ_HANDLED;
929 }
930
931
932 if (int_usb & MUSB_INTR_SESSREQ) {
933 if (musb_handle_intr_sessreq(musb, devctl))
934 return IRQ_HANDLED;
935 handled = IRQ_HANDLED;
936 }
937
938 if (int_usb & MUSB_INTR_VBUSERROR) {
939 musb_handle_intr_vbuserr(musb, devctl);
940 handled = IRQ_HANDLED;
941 }
942
943 if (int_usb & MUSB_INTR_SUSPEND) {
944 musb_handle_intr_suspend(musb, devctl);
945 handled = IRQ_HANDLED;
946 }
947
948 if (int_usb & MUSB_INTR_CONNECT) {
949 musb_handle_intr_connect(musb, devctl, int_usb);
950 handled = IRQ_HANDLED;
951 }
952
953 if (int_usb & MUSB_INTR_DISCONNECT) {
954 musb_handle_intr_disconnect(musb, devctl);
955 handled = IRQ_HANDLED;
956 }
957
958 if (int_usb & MUSB_INTR_RESET) {
959 musb_handle_intr_reset(musb);
960 handled = IRQ_HANDLED;
961 }
962
963#if 0
964
965
966
967
968
969
970
971
972
973
974
975 if (int_usb & MUSB_INTR_SOF) {
976 void __iomem *mbase = musb->mregs;
977 struct musb_hw_ep *ep;
978 u8 epnum;
979 u16 frame;
980
981 dev_dbg(musb->controller, "START_OF_FRAME\n");
982 handled = IRQ_HANDLED;
983
984
985 frame = musb_readw(mbase, MUSB_FRAME);
986 ep = musb->endpoints;
987 for (epnum = 1; (epnum < musb->nr_endpoints)
988 && (musb->epmask >= (1 << epnum));
989 epnum++, ep++) {
990
991
992
993
994 if (ep->dwWaitFrame >= frame) {
995 ep->dwWaitFrame = 0;
996 pr_debug("SOF --> periodic TX%s on %d\n",
997 ep->tx_channel ? " DMA" : "",
998 epnum);
999 if (!ep->tx_channel)
1000 musb_h_tx_start(musb, epnum);
1001 else
1002 cppi_hostdma_start(musb, epnum);
1003 }
1004 }
1005 }
1006#endif
1007
1008 schedule_delayed_work(&musb->irq_work, 0);
1009
1010 return handled;
1011}
1012
1013
1014
1015static void musb_disable_interrupts(struct musb *musb)
1016{
1017 void __iomem *mbase = musb->mregs;
1018 u16 temp;
1019
1020
1021 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1022 musb->intrtxe = 0;
1023 musb_writew(mbase, MUSB_INTRTXE, 0);
1024 musb->intrrxe = 0;
1025 musb_writew(mbase, MUSB_INTRRXE, 0);
1026
1027
1028 temp = musb_readb(mbase, MUSB_INTRUSB);
1029 temp = musb_readw(mbase, MUSB_INTRTX);
1030 temp = musb_readw(mbase, MUSB_INTRRX);
1031}
1032
1033static void musb_enable_interrupts(struct musb *musb)
1034{
1035 void __iomem *regs = musb->mregs;
1036
1037
1038 musb->intrtxe = musb->epmask;
1039 musb_writew(regs, MUSB_INTRTXE, musb->intrtxe);
1040 musb->intrrxe = musb->epmask & 0xfffe;
1041 musb_writew(regs, MUSB_INTRRXE, musb->intrrxe);
1042 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1043
1044}
1045
1046
1047
1048
1049void musb_start(struct musb *musb)
1050{
1051 void __iomem *regs = musb->mregs;
1052 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1053 u8 power;
1054
1055 musb_dbg(musb, "<== devctl %02x", devctl);
1056
1057 musb_enable_interrupts(musb);
1058 musb_writeb(regs, MUSB_TESTMODE, 0);
1059
1060 power = MUSB_POWER_ISOUPDATE;
1061
1062
1063
1064
1065 if (musb->config->maximum_speed == USB_SPEED_HIGH ||
1066 musb->config->maximum_speed == USB_SPEED_UNKNOWN)
1067 power |= MUSB_POWER_HSENAB;
1068 musb_writeb(regs, MUSB_POWER, power);
1069
1070 musb->is_active = 0;
1071 devctl = musb_readb(regs, MUSB_DEVCTL);
1072 devctl &= ~MUSB_DEVCTL_SESSION;
1073
1074
1075
1076
1077
1078
1079 if (musb->port_mode != MUSB_HOST &&
1080 musb->xceiv->otg->state != OTG_STATE_A_WAIT_BCON &&
1081 (devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS) {
1082 musb->is_active = 1;
1083 } else {
1084 devctl |= MUSB_DEVCTL_SESSION;
1085 }
1086
1087 musb_platform_enable(musb);
1088 musb_writeb(regs, MUSB_DEVCTL, devctl);
1089}
1090
1091
1092
1093
1094
1095
1096
1097
1098void musb_stop(struct musb *musb)
1099{
1100
1101 musb_platform_disable(musb);
1102 musb_disable_interrupts(musb);
1103 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
1104
1105
1106
1107
1108
1109
1110
1111
1112 musb_platform_try_idle(musb, 0);
1113}
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127static ushort fifo_mode;
1128
1129
1130module_param(fifo_mode, ushort, 0);
1131MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1132
1133
1134
1135
1136
1137
1138
1139static struct musb_fifo_cfg mode_0_cfg[] = {
1140{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1141{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1142{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1143{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1144{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1145};
1146
1147
1148static struct musb_fifo_cfg mode_1_cfg[] = {
1149{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1150{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1151{ .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1152{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1153{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1154};
1155
1156
1157static struct musb_fifo_cfg mode_2_cfg[] = {
1158{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1159{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1160{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1161{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1162{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 960, },
1163{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 1024, },
1164};
1165
1166
1167static struct musb_fifo_cfg mode_3_cfg[] = {
1168{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1169{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1170{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1171{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1172{ .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1173{ .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1174};
1175
1176
1177static struct musb_fifo_cfg mode_4_cfg[] = {
1178{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1179{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1180{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1181{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1182{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1183{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1184{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1185{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1186{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1187{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1188{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1189{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1190{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1191{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1192{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1193{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1194{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1195{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1196{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 256, },
1197{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1198{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1199{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 64, },
1200{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1201{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 64, },
1202{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 4096, },
1203{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1204{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1205};
1206
1207
1208static struct musb_fifo_cfg mode_5_cfg[] = {
1209{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1210{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1211{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1212{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1213{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1214{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1215{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1216{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1217{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1218{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1219{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 32, },
1220{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 32, },
1221{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 32, },
1222{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 32, },
1223{ .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 32, },
1224{ .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 32, },
1225{ .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 32, },
1226{ .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 32, },
1227{ .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 32, },
1228{ .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 32, },
1229{ .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 32, },
1230{ .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 32, },
1231{ .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 32, },
1232{ .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 32, },
1233{ .hw_ep_num = 13, .style = FIFO_RXTX, .maxpacket = 512, },
1234{ .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1235{ .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1236};
1237
1238
1239
1240
1241
1242
1243
1244static int
1245fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1246 const struct musb_fifo_cfg *cfg, u16 offset)
1247{
1248 void __iomem *mbase = musb->mregs;
1249 int size = 0;
1250 u16 maxpacket = cfg->maxpacket;
1251 u16 c_off = offset >> 3;
1252 u8 c_size;
1253
1254
1255
1256 size = ffs(max(maxpacket, (u16) 8)) - 1;
1257 maxpacket = 1 << size;
1258
1259 c_size = size - 3;
1260 if (cfg->mode == BUF_DOUBLE) {
1261 if ((offset + (maxpacket << 1)) >
1262 (1 << (musb->config->ram_bits + 2)))
1263 return -EMSGSIZE;
1264 c_size |= MUSB_FIFOSZ_DPB;
1265 } else {
1266 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1267 return -EMSGSIZE;
1268 }
1269
1270
1271 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1272
1273
1274
1275
1276 if (hw_ep->epnum == 1)
1277 musb->bulk_ep = hw_ep;
1278
1279 switch (cfg->style) {
1280 case FIFO_TX:
1281 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1282 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1283 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1284 hw_ep->max_packet_sz_tx = maxpacket;
1285 break;
1286 case FIFO_RX:
1287 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1288 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1289 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1290 hw_ep->max_packet_sz_rx = maxpacket;
1291 break;
1292 case FIFO_RXTX:
1293 musb_writeb(mbase, MUSB_TXFIFOSZ, c_size);
1294 musb_writew(mbase, MUSB_TXFIFOADD, c_off);
1295 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1296 hw_ep->max_packet_sz_rx = maxpacket;
1297
1298 musb_writeb(mbase, MUSB_RXFIFOSZ, c_size);
1299 musb_writew(mbase, MUSB_RXFIFOADD, c_off);
1300 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1301 hw_ep->max_packet_sz_tx = maxpacket;
1302
1303 hw_ep->is_shared_fifo = true;
1304 break;
1305 }
1306
1307
1308
1309
1310 musb->epmask |= (1 << hw_ep->epnum);
1311
1312 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1313}
1314
1315static struct musb_fifo_cfg ep0_cfg = {
1316 .style = FIFO_RXTX, .maxpacket = 64,
1317};
1318
1319static int ep_config_from_table(struct musb *musb)
1320{
1321 const struct musb_fifo_cfg *cfg;
1322 unsigned i, n;
1323 int offset;
1324 struct musb_hw_ep *hw_ep = musb->endpoints;
1325
1326 if (musb->config->fifo_cfg) {
1327 cfg = musb->config->fifo_cfg;
1328 n = musb->config->fifo_cfg_size;
1329 goto done;
1330 }
1331
1332 switch (fifo_mode) {
1333 default:
1334 fifo_mode = 0;
1335
1336 case 0:
1337 cfg = mode_0_cfg;
1338 n = ARRAY_SIZE(mode_0_cfg);
1339 break;
1340 case 1:
1341 cfg = mode_1_cfg;
1342 n = ARRAY_SIZE(mode_1_cfg);
1343 break;
1344 case 2:
1345 cfg = mode_2_cfg;
1346 n = ARRAY_SIZE(mode_2_cfg);
1347 break;
1348 case 3:
1349 cfg = mode_3_cfg;
1350 n = ARRAY_SIZE(mode_3_cfg);
1351 break;
1352 case 4:
1353 cfg = mode_4_cfg;
1354 n = ARRAY_SIZE(mode_4_cfg);
1355 break;
1356 case 5:
1357 cfg = mode_5_cfg;
1358 n = ARRAY_SIZE(mode_5_cfg);
1359 break;
1360 }
1361
1362 pr_debug("%s: setup fifo_mode %d\n", musb_driver_name, fifo_mode);
1363
1364
1365done:
1366 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1367
1368
1369
1370
1371
1372
1373 for (i = 0; i < n; i++) {
1374 u8 epn = cfg->hw_ep_num;
1375
1376 if (epn >= musb->config->num_eps) {
1377 pr_debug("%s: invalid ep %d\n",
1378 musb_driver_name, epn);
1379 return -EINVAL;
1380 }
1381 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1382 if (offset < 0) {
1383 pr_debug("%s: mem overrun, ep %d\n",
1384 musb_driver_name, epn);
1385 return offset;
1386 }
1387 epn++;
1388 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1389 }
1390
1391 pr_debug("%s: %d/%d max ep, %d/%d memory\n",
1392 musb_driver_name,
1393 n + 1, musb->config->num_eps * 2 - 1,
1394 offset, (1 << (musb->config->ram_bits + 2)));
1395
1396 if (!musb->bulk_ep) {
1397 pr_debug("%s: missing bulk\n", musb_driver_name);
1398 return -EINVAL;
1399 }
1400
1401 return 0;
1402}
1403
1404
1405
1406
1407
1408
1409static int ep_config_from_hw(struct musb *musb)
1410{
1411 u8 epnum = 0;
1412 struct musb_hw_ep *hw_ep;
1413 void __iomem *mbase = musb->mregs;
1414 int ret = 0;
1415
1416 musb_dbg(musb, "<== static silicon ep config");
1417
1418
1419
1420 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1421 musb_ep_select(mbase, epnum);
1422 hw_ep = musb->endpoints + epnum;
1423
1424 ret = musb_read_fifosize(musb, hw_ep, epnum);
1425 if (ret < 0)
1426 break;
1427
1428
1429
1430
1431 if (hw_ep->max_packet_sz_tx < 512
1432 || hw_ep->max_packet_sz_rx < 512)
1433 continue;
1434
1435
1436
1437
1438 if (musb->bulk_ep)
1439 continue;
1440 musb->bulk_ep = hw_ep;
1441 }
1442
1443 if (!musb->bulk_ep) {
1444 pr_debug("%s: missing bulk\n", musb_driver_name);
1445 return -EINVAL;
1446 }
1447
1448 return 0;
1449}
1450
1451enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1452
1453
1454
1455
1456static int musb_core_init(u16 musb_type, struct musb *musb)
1457{
1458 u8 reg;
1459 char *type;
1460 char aInfo[90];
1461 void __iomem *mbase = musb->mregs;
1462 int status = 0;
1463 int i;
1464
1465
1466 reg = musb_read_configdata(mbase);
1467
1468 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1469 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1470 strcat(aInfo, ", dyn FIFOs");
1471 musb->dyn_fifo = true;
1472 }
1473 if (reg & MUSB_CONFIGDATA_MPRXE) {
1474 strcat(aInfo, ", bulk combine");
1475 musb->bulk_combine = true;
1476 }
1477 if (reg & MUSB_CONFIGDATA_MPTXE) {
1478 strcat(aInfo, ", bulk split");
1479 musb->bulk_split = true;
1480 }
1481 if (reg & MUSB_CONFIGDATA_HBRXE) {
1482 strcat(aInfo, ", HB-ISO Rx");
1483 musb->hb_iso_rx = true;
1484 }
1485 if (reg & MUSB_CONFIGDATA_HBTXE) {
1486 strcat(aInfo, ", HB-ISO Tx");
1487 musb->hb_iso_tx = true;
1488 }
1489 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1490 strcat(aInfo, ", SoftConn");
1491
1492 pr_debug("%s: ConfigData=0x%02x (%s)\n", musb_driver_name, reg, aInfo);
1493
1494 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1495 musb->is_multipoint = 1;
1496 type = "M";
1497 } else {
1498 musb->is_multipoint = 0;
1499 type = "";
1500 if (IS_ENABLED(CONFIG_USB) &&
1501 !IS_ENABLED(CONFIG_USB_OTG_BLACKLIST_HUB)) {
1502 pr_err("%s: kernel must blacklist external hubs\n",
1503 musb_driver_name);
1504 }
1505 }
1506
1507
1508 musb->hwvers = musb_readw(mbase, MUSB_HWVERS);
1509 pr_debug("%s: %sHDRC RTL version %d.%d%s\n",
1510 musb_driver_name, type, MUSB_HWVERS_MAJOR(musb->hwvers),
1511 MUSB_HWVERS_MINOR(musb->hwvers),
1512 (musb->hwvers & MUSB_HWVERS_RC) ? "RC" : "");
1513
1514
1515 musb_configure_ep0(musb);
1516
1517
1518 musb->nr_endpoints = 1;
1519 musb->epmask = 1;
1520
1521 if (musb->dyn_fifo)
1522 status = ep_config_from_table(musb);
1523 else
1524 status = ep_config_from_hw(musb);
1525
1526 if (status < 0)
1527 return status;
1528
1529
1530 for (i = 0; i < musb->nr_endpoints; i++) {
1531 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1532
1533 hw_ep->fifo = musb->io.fifo_offset(i) + mbase;
1534#if IS_ENABLED(CONFIG_USB_MUSB_TUSB6010)
1535 if (musb->ops->quirks & MUSB_IN_TUSB) {
1536 hw_ep->fifo_async = musb->async + 0x400 +
1537 musb->io.fifo_offset(i);
1538 hw_ep->fifo_sync = musb->sync + 0x400 +
1539 musb->io.fifo_offset(i);
1540 hw_ep->fifo_sync_va =
1541 musb->sync_va + 0x400 + musb->io.fifo_offset(i);
1542
1543 if (i == 0)
1544 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1545 else
1546 hw_ep->conf = mbase + 0x400 +
1547 (((i - 1) & 0xf) << 2);
1548 }
1549#endif
1550
1551 hw_ep->regs = musb->io.ep_offset(i, 0) + mbase;
1552 hw_ep->rx_reinit = 1;
1553 hw_ep->tx_reinit = 1;
1554
1555 if (hw_ep->max_packet_sz_tx) {
1556 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1557 musb_driver_name, i,
1558 hw_ep->is_shared_fifo ? "shared" : "tx",
1559 hw_ep->tx_double_buffered
1560 ? "doublebuffer, " : "",
1561 hw_ep->max_packet_sz_tx);
1562 }
1563 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1564 musb_dbg(musb, "%s: hw_ep %d%s, %smax %d",
1565 musb_driver_name, i,
1566 "rx",
1567 hw_ep->rx_double_buffered
1568 ? "doublebuffer, " : "",
1569 hw_ep->max_packet_sz_rx);
1570 }
1571 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1572 musb_dbg(musb, "hw_ep %d not configured", i);
1573 }
1574
1575 return 0;
1576}
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587irqreturn_t musb_interrupt(struct musb *musb)
1588{
1589 irqreturn_t retval = IRQ_NONE;
1590 unsigned long status;
1591 unsigned long epnum;
1592 u8 devctl;
1593
1594 if (!musb->int_usb && !musb->int_tx && !musb->int_rx)
1595 return IRQ_NONE;
1596
1597 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1598
1599 trace_musb_isr(musb);
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621 if (musb->int_usb)
1622 retval |= musb_stage0_irq(musb, musb->int_usb, devctl);
1623
1624 if (musb->int_tx & 1) {
1625 if (is_host_active(musb))
1626 retval |= musb_h_ep0_irq(musb);
1627 else
1628 retval |= musb_g_ep0_irq(musb);
1629
1630
1631 musb->int_tx &= ~BIT(0);
1632 }
1633
1634 status = musb->int_tx;
1635
1636 for_each_set_bit(epnum, &status, 16) {
1637 retval = IRQ_HANDLED;
1638 if (is_host_active(musb))
1639 musb_host_tx(musb, epnum);
1640 else
1641 musb_g_tx(musb, epnum);
1642 }
1643
1644 status = musb->int_rx;
1645
1646 for_each_set_bit(epnum, &status, 16) {
1647 retval = IRQ_HANDLED;
1648 if (is_host_active(musb))
1649 musb_host_rx(musb, epnum);
1650 else
1651 musb_g_rx(musb, epnum);
1652 }
1653
1654 return retval;
1655}
1656EXPORT_SYMBOL_GPL(musb_interrupt);
1657
1658#ifndef CONFIG_MUSB_PIO_ONLY
1659static bool use_dma = 1;
1660
1661
1662module_param(use_dma, bool, 0644);
1663MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
1664
1665void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1666{
1667
1668
1669 if (!epnum) {
1670 if (!is_cppi_enabled(musb)) {
1671
1672 if (is_host_active(musb))
1673 musb_h_ep0_irq(musb);
1674 else
1675 musb_g_ep0_irq(musb);
1676 }
1677 } else {
1678
1679 if (transmit) {
1680 if (is_host_active(musb))
1681 musb_host_tx(musb, epnum);
1682 else
1683 musb_g_tx(musb, epnum);
1684 } else {
1685
1686 if (is_host_active(musb))
1687 musb_host_rx(musb, epnum);
1688 else
1689 musb_g_rx(musb, epnum);
1690 }
1691 }
1692}
1693EXPORT_SYMBOL_GPL(musb_dma_completion);
1694
1695#else
1696#define use_dma 0
1697#endif
1698
1699static int (*musb_phy_callback)(enum musb_vbus_id_status status);
1700
1701
1702
1703
1704
1705
1706
1707
1708int musb_mailbox(enum musb_vbus_id_status status)
1709{
1710 if (musb_phy_callback)
1711 return musb_phy_callback(status);
1712
1713 return -ENODEV;
1714};
1715EXPORT_SYMBOL_GPL(musb_mailbox);
1716
1717
1718
1719static ssize_t
1720mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1721{
1722 struct musb *musb = dev_to_musb(dev);
1723 unsigned long flags;
1724 int ret = -EINVAL;
1725
1726 spin_lock_irqsave(&musb->lock, flags);
1727 ret = sprintf(buf, "%s\n", usb_otg_state_string(musb->xceiv->otg->state));
1728 spin_unlock_irqrestore(&musb->lock, flags);
1729
1730 return ret;
1731}
1732
1733static ssize_t
1734mode_store(struct device *dev, struct device_attribute *attr,
1735 const char *buf, size_t n)
1736{
1737 struct musb *musb = dev_to_musb(dev);
1738 unsigned long flags;
1739 int status;
1740
1741 spin_lock_irqsave(&musb->lock, flags);
1742 if (sysfs_streq(buf, "host"))
1743 status = musb_platform_set_mode(musb, MUSB_HOST);
1744 else if (sysfs_streq(buf, "peripheral"))
1745 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
1746 else if (sysfs_streq(buf, "otg"))
1747 status = musb_platform_set_mode(musb, MUSB_OTG);
1748 else
1749 status = -EINVAL;
1750 spin_unlock_irqrestore(&musb->lock, flags);
1751
1752 return (status == 0) ? n : status;
1753}
1754static DEVICE_ATTR_RW(mode);
1755
1756static ssize_t
1757vbus_store(struct device *dev, struct device_attribute *attr,
1758 const char *buf, size_t n)
1759{
1760 struct musb *musb = dev_to_musb(dev);
1761 unsigned long flags;
1762 unsigned long val;
1763
1764 if (sscanf(buf, "%lu", &val) < 1) {
1765 dev_err(dev, "Invalid VBUS timeout ms value\n");
1766 return -EINVAL;
1767 }
1768
1769 spin_lock_irqsave(&musb->lock, flags);
1770
1771 musb->a_wait_bcon = val ? max_t(int, val, OTG_TIME_A_WAIT_BCON) : 0 ;
1772 if (musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON)
1773 musb->is_active = 0;
1774 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
1775 spin_unlock_irqrestore(&musb->lock, flags);
1776
1777 return n;
1778}
1779
1780static ssize_t
1781vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
1782{
1783 struct musb *musb = dev_to_musb(dev);
1784 unsigned long flags;
1785 unsigned long val;
1786 int vbus;
1787 u8 devctl;
1788
1789 pm_runtime_get_sync(dev);
1790 spin_lock_irqsave(&musb->lock, flags);
1791 val = musb->a_wait_bcon;
1792 vbus = musb_platform_get_vbus_status(musb);
1793 if (vbus < 0) {
1794
1795 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1796 if ((devctl & MUSB_DEVCTL_VBUS)
1797 == (3 << MUSB_DEVCTL_VBUS_SHIFT))
1798 vbus = 1;
1799 else
1800 vbus = 0;
1801 }
1802 spin_unlock_irqrestore(&musb->lock, flags);
1803 pm_runtime_put_sync(dev);
1804
1805 return sprintf(buf, "Vbus %s, timeout %lu msec\n",
1806 vbus ? "on" : "off", val);
1807}
1808static DEVICE_ATTR_RW(vbus);
1809
1810
1811
1812
1813static ssize_t srp_store(struct device *dev, struct device_attribute *attr,
1814 const char *buf, size_t n)
1815{
1816 struct musb *musb = dev_to_musb(dev);
1817 unsigned short srp;
1818
1819 if (sscanf(buf, "%hu", &srp) != 1
1820 || (srp != 1)) {
1821 dev_err(dev, "SRP: Value must be 1\n");
1822 return -EINVAL;
1823 }
1824
1825 if (srp == 1)
1826 musb_g_wakeup(musb);
1827
1828 return n;
1829}
1830static DEVICE_ATTR_WO(srp);
1831
1832static struct attribute *musb_attributes[] = {
1833 &dev_attr_mode.attr,
1834 &dev_attr_vbus.attr,
1835 &dev_attr_srp.attr,
1836 NULL
1837};
1838
1839static const struct attribute_group musb_attr_group = {
1840 .attrs = musb_attributes,
1841};
1842
1843#define MUSB_QUIRK_B_INVALID_VBUS_91 (MUSB_DEVCTL_BDEVICE | \
1844 (2 << MUSB_DEVCTL_VBUS_SHIFT) | \
1845 MUSB_DEVCTL_SESSION)
1846#define MUSB_QUIRK_A_DISCONNECT_19 ((3 << MUSB_DEVCTL_VBUS_SHIFT) | \
1847 MUSB_DEVCTL_SESSION)
1848
1849
1850
1851
1852
1853
1854
1855
1856
1857static void musb_pm_runtime_check_session(struct musb *musb)
1858{
1859 u8 devctl, s;
1860 int error;
1861
1862 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1863
1864
1865 s = MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV |
1866 MUSB_DEVCTL_HR;
1867 switch (devctl & ~s) {
1868 case MUSB_QUIRK_B_INVALID_VBUS_91:
1869 if (musb->quirk_retries && !musb->flush_irq_work) {
1870 musb_dbg(musb,
1871 "Poll devctl on invalid vbus, assume no session");
1872 schedule_delayed_work(&musb->irq_work,
1873 msecs_to_jiffies(1000));
1874 musb->quirk_retries--;
1875 return;
1876 }
1877
1878 case MUSB_QUIRK_A_DISCONNECT_19:
1879 if (musb->quirk_retries && !musb->flush_irq_work) {
1880 musb_dbg(musb,
1881 "Poll devctl on possible host mode disconnect");
1882 schedule_delayed_work(&musb->irq_work,
1883 msecs_to_jiffies(1000));
1884 musb->quirk_retries--;
1885 return;
1886 }
1887 if (!musb->session)
1888 break;
1889 musb_dbg(musb, "Allow PM on possible host mode disconnect");
1890 pm_runtime_mark_last_busy(musb->controller);
1891 pm_runtime_put_autosuspend(musb->controller);
1892 musb->session = false;
1893 return;
1894 default:
1895 break;
1896 }
1897
1898
1899 s = devctl & MUSB_DEVCTL_SESSION;
1900 if (s == musb->session)
1901 return;
1902
1903
1904 if (s) {
1905 musb_dbg(musb, "Block PM on active session: %02x", devctl);
1906 error = pm_runtime_get_sync(musb->controller);
1907 if (error < 0)
1908 dev_err(musb->controller, "Could not enable: %i\n",
1909 error);
1910 musb->quirk_retries = 3;
1911 } else {
1912 musb_dbg(musb, "Allow PM with no session: %02x", devctl);
1913 pm_runtime_mark_last_busy(musb->controller);
1914 pm_runtime_put_autosuspend(musb->controller);
1915 }
1916
1917 musb->session = s;
1918}
1919
1920
1921static void musb_irq_work(struct work_struct *data)
1922{
1923 struct musb *musb = container_of(data, struct musb, irq_work.work);
1924 int error;
1925
1926 error = pm_runtime_get_sync(musb->controller);
1927 if (error < 0) {
1928 dev_err(musb->controller, "Could not enable: %i\n", error);
1929
1930 return;
1931 }
1932
1933 musb_pm_runtime_check_session(musb);
1934
1935 if (musb->xceiv->otg->state != musb->xceiv_old_state) {
1936 musb->xceiv_old_state = musb->xceiv->otg->state;
1937 sysfs_notify(&musb->controller->kobj, NULL, "mode");
1938 }
1939
1940 pm_runtime_mark_last_busy(musb->controller);
1941 pm_runtime_put_autosuspend(musb->controller);
1942}
1943
1944static void musb_recover_from_babble(struct musb *musb)
1945{
1946 int ret;
1947 u8 devctl;
1948
1949 musb_disable_interrupts(musb);
1950
1951
1952
1953
1954
1955 udelay(10);
1956
1957 ret = musb_platform_recover(musb);
1958 if (ret) {
1959 musb_enable_interrupts(musb);
1960 return;
1961 }
1962
1963
1964 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1965 devctl &= ~MUSB_DEVCTL_SESSION;
1966 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
1967
1968
1969 musb_root_disconnect(musb);
1970
1971
1972
1973
1974
1975 if (musb->dyn_fifo)
1976 ret = ep_config_from_table(musb);
1977 else
1978 ret = ep_config_from_hw(musb);
1979
1980
1981 if (ret == 0)
1982 musb_start(musb);
1983}
1984
1985
1986
1987
1988
1989static struct musb *allocate_instance(struct device *dev,
1990 const struct musb_hdrc_config *config, void __iomem *mbase)
1991{
1992 struct musb *musb;
1993 struct musb_hw_ep *ep;
1994 int epnum;
1995 int ret;
1996
1997 musb = devm_kzalloc(dev, sizeof(*musb), GFP_KERNEL);
1998 if (!musb)
1999 return NULL;
2000
2001 INIT_LIST_HEAD(&musb->control);
2002 INIT_LIST_HEAD(&musb->in_bulk);
2003 INIT_LIST_HEAD(&musb->out_bulk);
2004 INIT_LIST_HEAD(&musb->pending_list);
2005
2006 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2007 musb->a_wait_bcon = OTG_TIME_A_WAIT_BCON;
2008 musb->mregs = mbase;
2009 musb->ctrl_base = mbase;
2010 musb->nIrq = -ENODEV;
2011 musb->config = config;
2012 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2013 for (epnum = 0, ep = musb->endpoints;
2014 epnum < musb->config->num_eps;
2015 epnum++, ep++) {
2016 ep->musb = musb;
2017 ep->epnum = epnum;
2018 }
2019
2020 musb->controller = dev;
2021
2022 ret = musb_host_alloc(musb);
2023 if (ret < 0)
2024 goto err_free;
2025
2026 dev_set_drvdata(dev, musb);
2027
2028 return musb;
2029
2030err_free:
2031 return NULL;
2032}
2033
2034static void musb_free(struct musb *musb)
2035{
2036
2037
2038
2039
2040
2041#ifdef CONFIG_SYSFS
2042 sysfs_remove_group(&musb->controller->kobj, &musb_attr_group);
2043#endif
2044
2045 if (musb->nIrq >= 0) {
2046 if (musb->irq_wake)
2047 disable_irq_wake(musb->nIrq);
2048 free_irq(musb->nIrq, musb);
2049 }
2050
2051 musb_host_free(musb);
2052}
2053
2054struct musb_pending_work {
2055 int (*callback)(struct musb *musb, void *data);
2056 void *data;
2057 struct list_head node;
2058};
2059
2060#ifdef CONFIG_PM
2061
2062
2063
2064
2065static int musb_run_resume_work(struct musb *musb)
2066{
2067 struct musb_pending_work *w, *_w;
2068 unsigned long flags;
2069 int error = 0;
2070
2071 spin_lock_irqsave(&musb->list_lock, flags);
2072 list_for_each_entry_safe(w, _w, &musb->pending_list, node) {
2073 if (w->callback) {
2074 error = w->callback(musb, w->data);
2075 if (error < 0) {
2076 dev_err(musb->controller,
2077 "resume callback %p failed: %i\n",
2078 w->callback, error);
2079 }
2080 }
2081 list_del(&w->node);
2082 devm_kfree(musb->controller, w);
2083 }
2084 spin_unlock_irqrestore(&musb->list_lock, flags);
2085
2086 return error;
2087}
2088#endif
2089
2090
2091
2092
2093
2094
2095
2096
2097
2098int musb_queue_resume_work(struct musb *musb,
2099 int (*callback)(struct musb *musb, void *data),
2100 void *data)
2101{
2102 struct musb_pending_work *w;
2103 unsigned long flags;
2104 int error;
2105
2106 if (WARN_ON(!callback))
2107 return -EINVAL;
2108
2109 if (pm_runtime_active(musb->controller))
2110 return callback(musb, data);
2111
2112 w = devm_kzalloc(musb->controller, sizeof(*w), GFP_ATOMIC);
2113 if (!w)
2114 return -ENOMEM;
2115
2116 w->callback = callback;
2117 w->data = data;
2118 spin_lock_irqsave(&musb->list_lock, flags);
2119 if (musb->is_runtime_suspended) {
2120 list_add_tail(&w->node, &musb->pending_list);
2121 error = 0;
2122 } else {
2123 dev_err(musb->controller, "could not add resume work %p\n",
2124 callback);
2125 devm_kfree(musb->controller, w);
2126 error = -EINPROGRESS;
2127 }
2128 spin_unlock_irqrestore(&musb->list_lock, flags);
2129
2130 return error;
2131}
2132EXPORT_SYMBOL_GPL(musb_queue_resume_work);
2133
2134static void musb_deassert_reset(struct work_struct *work)
2135{
2136 struct musb *musb;
2137 unsigned long flags;
2138
2139 musb = container_of(work, struct musb, deassert_reset_work.work);
2140
2141 spin_lock_irqsave(&musb->lock, flags);
2142
2143 if (musb->port1_status & USB_PORT_STAT_RESET)
2144 musb_port_reset(musb, false);
2145
2146 spin_unlock_irqrestore(&musb->lock, flags);
2147}
2148
2149
2150
2151
2152
2153
2154
2155
2156
2157static int
2158musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2159{
2160 int status;
2161 struct musb *musb;
2162 struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
2163
2164
2165
2166
2167 if (!plat) {
2168 dev_err(dev, "no platform_data?\n");
2169 status = -ENODEV;
2170 goto fail0;
2171 }
2172
2173
2174 musb = allocate_instance(dev, plat->config, ctrl);
2175 if (!musb) {
2176 status = -ENOMEM;
2177 goto fail0;
2178 }
2179
2180 spin_lock_init(&musb->lock);
2181 spin_lock_init(&musb->list_lock);
2182 musb->board_set_power = plat->set_power;
2183 musb->min_power = plat->min_power;
2184 musb->ops = plat->platform_ops;
2185 musb->port_mode = plat->mode;
2186
2187
2188
2189
2190
2191
2192 musb_readb = musb_default_readb;
2193 musb_writeb = musb_default_writeb;
2194 musb_readw = musb_default_readw;
2195 musb_writew = musb_default_writew;
2196
2197
2198
2199
2200
2201
2202
2203
2204
2205
2206
2207
2208
2209 status = musb_platform_init(musb);
2210 if (status < 0)
2211 goto fail1;
2212
2213 if (!musb->isr) {
2214 status = -ENODEV;
2215 goto fail2;
2216 }
2217
2218
2219
2220 if (musb->ops->quirks & MUSB_INDEXED_EP) {
2221 musb->io.ep_offset = musb_indexed_ep_offset;
2222 musb->io.ep_select = musb_indexed_ep_select;
2223 } else {
2224 musb->io.ep_offset = musb_flat_ep_offset;
2225 musb->io.ep_select = musb_flat_ep_select;
2226 }
2227
2228 if (musb->ops->quirks & MUSB_G_NO_SKB_RESERVE)
2229 musb->g.quirk_avoids_skb_reserve = 1;
2230
2231
2232 if (musb->ops->ep_offset)
2233 musb->io.ep_offset = musb->ops->ep_offset;
2234 if (musb->ops->ep_select)
2235 musb->io.ep_select = musb->ops->ep_select;
2236
2237 if (musb->ops->fifo_mode)
2238 fifo_mode = musb->ops->fifo_mode;
2239 else
2240 fifo_mode = 4;
2241
2242 if (musb->ops->fifo_offset)
2243 musb->io.fifo_offset = musb->ops->fifo_offset;
2244 else
2245 musb->io.fifo_offset = musb_default_fifo_offset;
2246
2247 if (musb->ops->busctl_offset)
2248 musb->io.busctl_offset = musb->ops->busctl_offset;
2249 else
2250 musb->io.busctl_offset = musb_default_busctl_offset;
2251
2252 if (musb->ops->readb)
2253 musb_readb = musb->ops->readb;
2254 if (musb->ops->writeb)
2255 musb_writeb = musb->ops->writeb;
2256 if (musb->ops->readw)
2257 musb_readw = musb->ops->readw;
2258 if (musb->ops->writew)
2259 musb_writew = musb->ops->writew;
2260
2261#ifndef CONFIG_MUSB_PIO_ONLY
2262 if (!musb->ops->dma_init || !musb->ops->dma_exit) {
2263 dev_err(dev, "DMA controller not set\n");
2264 status = -ENODEV;
2265 goto fail2;
2266 }
2267 musb_dma_controller_create = musb->ops->dma_init;
2268 musb_dma_controller_destroy = musb->ops->dma_exit;
2269#endif
2270
2271 if (musb->ops->read_fifo)
2272 musb->io.read_fifo = musb->ops->read_fifo;
2273 else
2274 musb->io.read_fifo = musb_default_read_fifo;
2275
2276 if (musb->ops->write_fifo)
2277 musb->io.write_fifo = musb->ops->write_fifo;
2278 else
2279 musb->io.write_fifo = musb_default_write_fifo;
2280
2281 if (!musb->xceiv->io_ops) {
2282 musb->xceiv->io_dev = musb->controller;
2283 musb->xceiv->io_priv = musb->mregs;
2284 musb->xceiv->io_ops = &musb_ulpi_access;
2285 }
2286
2287 if (musb->ops->phy_callback)
2288 musb_phy_callback = musb->ops->phy_callback;
2289
2290
2291
2292
2293
2294
2295
2296
2297 pm_runtime_use_autosuspend(musb->controller);
2298 pm_runtime_set_autosuspend_delay(musb->controller, 500);
2299 pm_runtime_enable(musb->controller);
2300 pm_runtime_get_sync(musb->controller);
2301
2302 status = usb_phy_init(musb->xceiv);
2303 if (status < 0)
2304 goto err_usb_phy_init;
2305
2306 if (use_dma && dev->dma_mask) {
2307 musb->dma_controller =
2308 musb_dma_controller_create(musb, musb->mregs);
2309 if (IS_ERR(musb->dma_controller)) {
2310 status = PTR_ERR(musb->dma_controller);
2311 goto fail2_5;
2312 }
2313 }
2314
2315
2316 musb_platform_disable(musb);
2317 musb_disable_interrupts(musb);
2318 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2319
2320
2321 INIT_DELAYED_WORK(&musb->irq_work, musb_irq_work);
2322 INIT_DELAYED_WORK(&musb->deassert_reset_work, musb_deassert_reset);
2323 INIT_DELAYED_WORK(&musb->finish_resume_work, musb_host_finish_resume);
2324
2325
2326 status = musb_core_init(plat->config->multipoint
2327 ? MUSB_CONTROLLER_MHDRC
2328 : MUSB_CONTROLLER_HDRC, musb);
2329 if (status < 0)
2330 goto fail3;
2331
2332 timer_setup(&musb->otg_timer, musb_otg_timer_func, 0);
2333
2334
2335 if (request_irq(nIrq, musb->isr, IRQF_SHARED, dev_name(dev), musb)) {
2336 dev_err(dev, "request_irq %d failed!\n", nIrq);
2337 status = -ENODEV;
2338 goto fail3;
2339 }
2340 musb->nIrq = nIrq;
2341
2342 if (enable_irq_wake(nIrq) == 0) {
2343 musb->irq_wake = 1;
2344 device_init_wakeup(dev, 1);
2345 } else {
2346 musb->irq_wake = 0;
2347 }
2348
2349
2350 if (plat->extvbus) {
2351 u8 busctl = musb_readb(musb->mregs, MUSB_ULPI_BUSCONTROL);
2352 busctl |= MUSB_ULPI_USE_EXTVBUS;
2353 musb_writeb(musb->mregs, MUSB_ULPI_BUSCONTROL, busctl);
2354 }
2355
2356 MUSB_DEV_MODE(musb);
2357 musb->xceiv->otg->state = OTG_STATE_B_IDLE;
2358
2359 switch (musb->port_mode) {
2360 case MUSB_HOST:
2361 status = musb_host_setup(musb, plat->power);
2362 if (status < 0)
2363 goto fail3;
2364 status = musb_platform_set_mode(musb, MUSB_HOST);
2365 break;
2366 case MUSB_PERIPHERAL:
2367 status = musb_gadget_setup(musb);
2368 if (status < 0)
2369 goto fail3;
2370 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2371 break;
2372 case MUSB_OTG:
2373 status = musb_host_setup(musb, plat->power);
2374 if (status < 0)
2375 goto fail3;
2376 status = musb_gadget_setup(musb);
2377 if (status) {
2378 musb_host_cleanup(musb);
2379 goto fail3;
2380 }
2381 status = musb_platform_set_mode(musb, MUSB_OTG);
2382 break;
2383 default:
2384 dev_err(dev, "unsupported port mode %d\n", musb->port_mode);
2385 break;
2386 }
2387
2388 if (status < 0)
2389 goto fail3;
2390
2391 musb_init_debugfs(musb);
2392
2393 status = sysfs_create_group(&musb->controller->kobj, &musb_attr_group);
2394 if (status)
2395 goto fail5;
2396
2397 musb->is_initialized = 1;
2398 pm_runtime_mark_last_busy(musb->controller);
2399 pm_runtime_put_autosuspend(musb->controller);
2400
2401 return 0;
2402
2403fail5:
2404 musb_exit_debugfs(musb);
2405
2406 musb_gadget_cleanup(musb);
2407 musb_host_cleanup(musb);
2408
2409fail3:
2410 cancel_delayed_work_sync(&musb->irq_work);
2411 cancel_delayed_work_sync(&musb->finish_resume_work);
2412 cancel_delayed_work_sync(&musb->deassert_reset_work);
2413 if (musb->dma_controller)
2414 musb_dma_controller_destroy(musb->dma_controller);
2415
2416fail2_5:
2417 usb_phy_shutdown(musb->xceiv);
2418
2419err_usb_phy_init:
2420 pm_runtime_dont_use_autosuspend(musb->controller);
2421 pm_runtime_put_sync(musb->controller);
2422 pm_runtime_disable(musb->controller);
2423
2424fail2:
2425 if (musb->irq_wake)
2426 device_init_wakeup(dev, 0);
2427 musb_platform_exit(musb);
2428
2429fail1:
2430 if (status != -EPROBE_DEFER)
2431 dev_err(musb->controller,
2432 "%s failed with status %d\n", __func__, status);
2433
2434 musb_free(musb);
2435
2436fail0:
2437
2438 return status;
2439
2440}
2441
2442
2443
2444
2445
2446
2447static int musb_probe(struct platform_device *pdev)
2448{
2449 struct device *dev = &pdev->dev;
2450 int irq = platform_get_irq_byname(pdev, "mc");
2451 struct resource *iomem;
2452 void __iomem *base;
2453
2454 if (irq <= 0)
2455 return -ENODEV;
2456
2457 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2458 base = devm_ioremap_resource(dev, iomem);
2459 if (IS_ERR(base))
2460 return PTR_ERR(base);
2461
2462 return musb_init_controller(dev, irq, base);
2463}
2464
2465static int musb_remove(struct platform_device *pdev)
2466{
2467 struct device *dev = &pdev->dev;
2468 struct musb *musb = dev_to_musb(dev);
2469 unsigned long flags;
2470
2471
2472
2473
2474
2475
2476 musb_exit_debugfs(musb);
2477
2478 cancel_delayed_work_sync(&musb->irq_work);
2479 cancel_delayed_work_sync(&musb->finish_resume_work);
2480 cancel_delayed_work_sync(&musb->deassert_reset_work);
2481 pm_runtime_get_sync(musb->controller);
2482 musb_host_cleanup(musb);
2483 musb_gadget_cleanup(musb);
2484
2485 musb_platform_disable(musb);
2486 spin_lock_irqsave(&musb->lock, flags);
2487 musb_disable_interrupts(musb);
2488 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2489 spin_unlock_irqrestore(&musb->lock, flags);
2490 musb_platform_exit(musb);
2491
2492 pm_runtime_dont_use_autosuspend(musb->controller);
2493 pm_runtime_put_sync(musb->controller);
2494 pm_runtime_disable(musb->controller);
2495 musb_phy_callback = NULL;
2496 if (musb->dma_controller)
2497 musb_dma_controller_destroy(musb->dma_controller);
2498 usb_phy_shutdown(musb->xceiv);
2499 musb_free(musb);
2500 device_init_wakeup(dev, 0);
2501 return 0;
2502}
2503
2504#ifdef CONFIG_PM
2505
2506static void musb_save_context(struct musb *musb)
2507{
2508 int i;
2509 void __iomem *musb_base = musb->mregs;
2510 void __iomem *epio;
2511
2512 musb->context.frame = musb_readw(musb_base, MUSB_FRAME);
2513 musb->context.testmode = musb_readb(musb_base, MUSB_TESTMODE);
2514 musb->context.busctl = musb_readb(musb_base, MUSB_ULPI_BUSCONTROL);
2515 musb->context.power = musb_readb(musb_base, MUSB_POWER);
2516 musb->context.intrusbe = musb_readb(musb_base, MUSB_INTRUSBE);
2517 musb->context.index = musb_readb(musb_base, MUSB_INDEX);
2518 musb->context.devctl = musb_readb(musb_base, MUSB_DEVCTL);
2519
2520 for (i = 0; i < musb->config->num_eps; ++i) {
2521 struct musb_hw_ep *hw_ep;
2522
2523 hw_ep = &musb->endpoints[i];
2524 if (!hw_ep)
2525 continue;
2526
2527 epio = hw_ep->regs;
2528 if (!epio)
2529 continue;
2530
2531 musb_writeb(musb_base, MUSB_INDEX, i);
2532 musb->context.index_regs[i].txmaxp =
2533 musb_readw(epio, MUSB_TXMAXP);
2534 musb->context.index_regs[i].txcsr =
2535 musb_readw(epio, MUSB_TXCSR);
2536 musb->context.index_regs[i].rxmaxp =
2537 musb_readw(epio, MUSB_RXMAXP);
2538 musb->context.index_regs[i].rxcsr =
2539 musb_readw(epio, MUSB_RXCSR);
2540
2541 if (musb->dyn_fifo) {
2542 musb->context.index_regs[i].txfifoadd =
2543 musb_readw(musb_base, MUSB_TXFIFOADD);
2544 musb->context.index_regs[i].rxfifoadd =
2545 musb_readw(musb_base, MUSB_RXFIFOADD);
2546 musb->context.index_regs[i].txfifosz =
2547 musb_readb(musb_base, MUSB_TXFIFOSZ);
2548 musb->context.index_regs[i].rxfifosz =
2549 musb_readb(musb_base, MUSB_RXFIFOSZ);
2550 }
2551
2552 musb->context.index_regs[i].txtype =
2553 musb_readb(epio, MUSB_TXTYPE);
2554 musb->context.index_regs[i].txinterval =
2555 musb_readb(epio, MUSB_TXINTERVAL);
2556 musb->context.index_regs[i].rxtype =
2557 musb_readb(epio, MUSB_RXTYPE);
2558 musb->context.index_regs[i].rxinterval =
2559 musb_readb(epio, MUSB_RXINTERVAL);
2560
2561 musb->context.index_regs[i].txfunaddr =
2562 musb_read_txfunaddr(musb, i);
2563 musb->context.index_regs[i].txhubaddr =
2564 musb_read_txhubaddr(musb, i);
2565 musb->context.index_regs[i].txhubport =
2566 musb_read_txhubport(musb, i);
2567
2568 musb->context.index_regs[i].rxfunaddr =
2569 musb_read_rxfunaddr(musb, i);
2570 musb->context.index_regs[i].rxhubaddr =
2571 musb_read_rxhubaddr(musb, i);
2572 musb->context.index_regs[i].rxhubport =
2573 musb_read_rxhubport(musb, i);
2574 }
2575}
2576
2577static void musb_restore_context(struct musb *musb)
2578{
2579 int i;
2580 void __iomem *musb_base = musb->mregs;
2581 void __iomem *epio;
2582 u8 power;
2583
2584 musb_writew(musb_base, MUSB_FRAME, musb->context.frame);
2585 musb_writeb(musb_base, MUSB_TESTMODE, musb->context.testmode);
2586 musb_writeb(musb_base, MUSB_ULPI_BUSCONTROL, musb->context.busctl);
2587
2588
2589 power = musb_readb(musb_base, MUSB_POWER);
2590 power &= MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME;
2591 musb->context.power &= ~(MUSB_POWER_SUSPENDM | MUSB_POWER_RESUME);
2592 power |= musb->context.power;
2593 musb_writeb(musb_base, MUSB_POWER, power);
2594
2595 musb_writew(musb_base, MUSB_INTRTXE, musb->intrtxe);
2596 musb_writew(musb_base, MUSB_INTRRXE, musb->intrrxe);
2597 musb_writeb(musb_base, MUSB_INTRUSBE, musb->context.intrusbe);
2598 if (musb->context.devctl & MUSB_DEVCTL_SESSION)
2599 musb_writeb(musb_base, MUSB_DEVCTL, musb->context.devctl);
2600
2601 for (i = 0; i < musb->config->num_eps; ++i) {
2602 struct musb_hw_ep *hw_ep;
2603
2604 hw_ep = &musb->endpoints[i];
2605 if (!hw_ep)
2606 continue;
2607
2608 epio = hw_ep->regs;
2609 if (!epio)
2610 continue;
2611
2612 musb_writeb(musb_base, MUSB_INDEX, i);
2613 musb_writew(epio, MUSB_TXMAXP,
2614 musb->context.index_regs[i].txmaxp);
2615 musb_writew(epio, MUSB_TXCSR,
2616 musb->context.index_regs[i].txcsr);
2617 musb_writew(epio, MUSB_RXMAXP,
2618 musb->context.index_regs[i].rxmaxp);
2619 musb_writew(epio, MUSB_RXCSR,
2620 musb->context.index_regs[i].rxcsr);
2621
2622 if (musb->dyn_fifo) {
2623 musb_writeb(musb_base, MUSB_TXFIFOSZ,
2624 musb->context.index_regs[i].txfifosz);
2625 musb_writeb(musb_base, MUSB_RXFIFOSZ,
2626 musb->context.index_regs[i].rxfifosz);
2627 musb_writew(musb_base, MUSB_TXFIFOADD,
2628 musb->context.index_regs[i].txfifoadd);
2629 musb_writew(musb_base, MUSB_RXFIFOADD,
2630 musb->context.index_regs[i].rxfifoadd);
2631 }
2632
2633 musb_writeb(epio, MUSB_TXTYPE,
2634 musb->context.index_regs[i].txtype);
2635 musb_writeb(epio, MUSB_TXINTERVAL,
2636 musb->context.index_regs[i].txinterval);
2637 musb_writeb(epio, MUSB_RXTYPE,
2638 musb->context.index_regs[i].rxtype);
2639 musb_writeb(epio, MUSB_RXINTERVAL,
2640
2641 musb->context.index_regs[i].rxinterval);
2642 musb_write_txfunaddr(musb, i,
2643 musb->context.index_regs[i].txfunaddr);
2644 musb_write_txhubaddr(musb, i,
2645 musb->context.index_regs[i].txhubaddr);
2646 musb_write_txhubport(musb, i,
2647 musb->context.index_regs[i].txhubport);
2648
2649 musb_write_rxfunaddr(musb, i,
2650 musb->context.index_regs[i].rxfunaddr);
2651 musb_write_rxhubaddr(musb, i,
2652 musb->context.index_regs[i].rxhubaddr);
2653 musb_write_rxhubport(musb, i,
2654 musb->context.index_regs[i].rxhubport);
2655 }
2656 musb_writeb(musb_base, MUSB_INDEX, musb->context.index);
2657}
2658
2659static int musb_suspend(struct device *dev)
2660{
2661 struct musb *musb = dev_to_musb(dev);
2662 unsigned long flags;
2663 int ret;
2664
2665 ret = pm_runtime_get_sync(dev);
2666 if (ret < 0) {
2667 pm_runtime_put_noidle(dev);
2668 return ret;
2669 }
2670
2671 musb_platform_disable(musb);
2672 musb_disable_interrupts(musb);
2673
2674 musb->flush_irq_work = true;
2675 while (flush_delayed_work(&musb->irq_work))
2676 ;
2677 musb->flush_irq_work = false;
2678
2679 if (!(musb->ops->quirks & MUSB_PRESERVE_SESSION))
2680 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2681
2682 WARN_ON(!list_empty(&musb->pending_list));
2683
2684 spin_lock_irqsave(&musb->lock, flags);
2685
2686 if (is_peripheral_active(musb)) {
2687
2688
2689
2690 } else if (is_host_active(musb)) {
2691
2692
2693
2694 }
2695
2696 musb_save_context(musb);
2697
2698 spin_unlock_irqrestore(&musb->lock, flags);
2699 return 0;
2700}
2701
2702static int musb_resume(struct device *dev)
2703{
2704 struct musb *musb = dev_to_musb(dev);
2705 unsigned long flags;
2706 int error;
2707 u8 devctl;
2708 u8 mask;
2709
2710
2711
2712
2713
2714
2715
2716
2717
2718
2719
2720 musb_restore_context(musb);
2721
2722 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2723 mask = MUSB_DEVCTL_BDEVICE | MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV;
2724 if ((devctl & mask) != (musb->context.devctl & mask))
2725 musb->port1_status = 0;
2726
2727 musb_enable_interrupts(musb);
2728 musb_platform_enable(musb);
2729
2730 spin_lock_irqsave(&musb->lock, flags);
2731 error = musb_run_resume_work(musb);
2732 if (error)
2733 dev_err(musb->controller, "resume work failed with %i\n",
2734 error);
2735 spin_unlock_irqrestore(&musb->lock, flags);
2736
2737 pm_runtime_mark_last_busy(dev);
2738 pm_runtime_put_autosuspend(dev);
2739
2740 return 0;
2741}
2742
2743static int musb_runtime_suspend(struct device *dev)
2744{
2745 struct musb *musb = dev_to_musb(dev);
2746
2747 musb_save_context(musb);
2748 musb->is_runtime_suspended = 1;
2749
2750 return 0;
2751}
2752
2753static int musb_runtime_resume(struct device *dev)
2754{
2755 struct musb *musb = dev_to_musb(dev);
2756 unsigned long flags;
2757 int error;
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768 if (!musb->is_initialized)
2769 return 0;
2770
2771 musb_restore_context(musb);
2772
2773 spin_lock_irqsave(&musb->lock, flags);
2774 error = musb_run_resume_work(musb);
2775 if (error)
2776 dev_err(musb->controller, "resume work failed with %i\n",
2777 error);
2778 musb->is_runtime_suspended = 0;
2779 spin_unlock_irqrestore(&musb->lock, flags);
2780
2781 return 0;
2782}
2783
2784static const struct dev_pm_ops musb_dev_pm_ops = {
2785 .suspend = musb_suspend,
2786 .resume = musb_resume,
2787 .runtime_suspend = musb_runtime_suspend,
2788 .runtime_resume = musb_runtime_resume,
2789};
2790
2791#define MUSB_DEV_PM_OPS (&musb_dev_pm_ops)
2792#else
2793#define MUSB_DEV_PM_OPS NULL
2794#endif
2795
2796static struct platform_driver musb_driver = {
2797 .driver = {
2798 .name = (char *)musb_driver_name,
2799 .bus = &platform_bus_type,
2800 .pm = MUSB_DEV_PM_OPS,
2801 },
2802 .probe = musb_probe,
2803 .remove = musb_remove,
2804};
2805
2806module_platform_driver(musb_driver);
2807