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10#ifndef __ACTBL2_H__
11#define __ACTBL2_H__
12
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25
26
27#define ACPI_SIG_IORT "IORT"
28#define ACPI_SIG_IVRS "IVRS"
29#define ACPI_SIG_LPIT "LPIT"
30#define ACPI_SIG_MADT "APIC"
31#define ACPI_SIG_MCFG "MCFG"
32#define ACPI_SIG_MCHI "MCHI"
33#define ACPI_SIG_MPST "MPST"
34#define ACPI_SIG_MSCT "MSCT"
35#define ACPI_SIG_MSDM "MSDM"
36#define ACPI_SIG_MTMR "MTMR"
37#define ACPI_SIG_NFIT "NFIT"
38#define ACPI_SIG_PCCT "PCCT"
39#define ACPI_SIG_PDTT "PDTT"
40#define ACPI_SIG_PMTT "PMTT"
41#define ACPI_SIG_PPTT "PPTT"
42#define ACPI_SIG_RASF "RASF"
43#define ACPI_SIG_SBST "SBST"
44#define ACPI_SIG_SDEI "SDEI"
45#define ACPI_SIG_SDEV "SDEV"
46
47
48
49
50
51#pragma pack(1)
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73
74struct acpi_table_iort {
75 struct acpi_table_header header;
76 u32 node_count;
77 u32 node_offset;
78 u32 reserved;
79};
80
81
82
83
84struct acpi_iort_node {
85 u8 type;
86 u16 length;
87 u8 revision;
88 u32 reserved;
89 u32 mapping_count;
90 u32 mapping_offset;
91 char node_data[1];
92};
93
94
95
96enum acpi_iort_node_type {
97 ACPI_IORT_NODE_ITS_GROUP = 0x00,
98 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
99 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
100 ACPI_IORT_NODE_SMMU = 0x03,
101 ACPI_IORT_NODE_SMMU_V3 = 0x04,
102 ACPI_IORT_NODE_PMCG = 0x05
103};
104
105struct acpi_iort_id_mapping {
106 u32 input_base;
107 u32 id_count;
108 u32 output_base;
109 u32 output_reference;
110 u32 flags;
111};
112
113
114
115#define ACPI_IORT_ID_SINGLE_MAPPING (1)
116
117struct acpi_iort_memory_access {
118 u32 cache_coherency;
119 u8 hints;
120 u16 reserved;
121 u8 memory_flags;
122};
123
124
125
126#define ACPI_IORT_NODE_COHERENT 0x00000001
127#define ACPI_IORT_NODE_NOT_COHERENT 0x00000000
128
129
130
131#define ACPI_IORT_HT_TRANSIENT (1)
132#define ACPI_IORT_HT_WRITE (1<<1)
133#define ACPI_IORT_HT_READ (1<<2)
134#define ACPI_IORT_HT_OVERRIDE (1<<3)
135
136
137
138#define ACPI_IORT_MF_COHERENCY (1)
139#define ACPI_IORT_MF_ATTRIBUTES (1<<1)
140
141
142
143
144struct acpi_iort_its_group {
145 u32 its_count;
146 u32 identifiers[1];
147};
148
149struct acpi_iort_named_component {
150 u32 node_flags;
151 u64 memory_properties;
152 u8 memory_address_limit;
153 char device_name[1];
154};
155
156
157
158#define ACPI_IORT_NC_STALL_SUPPORTED (1)
159#define ACPI_IORT_NC_PASID_BITS (31<<1)
160
161struct acpi_iort_root_complex {
162 u64 memory_properties;
163 u32 ats_attribute;
164 u32 pci_segment_number;
165 u8 memory_address_limit;
166 u8 reserved[3];
167};
168
169
170
171#define ACPI_IORT_ATS_SUPPORTED 0x00000001
172#define ACPI_IORT_ATS_UNSUPPORTED 0x00000000
173
174struct acpi_iort_smmu {
175 u64 base_address;
176 u64 span;
177 u32 model;
178 u32 flags;
179 u32 global_interrupt_offset;
180 u32 context_interrupt_count;
181 u32 context_interrupt_offset;
182 u32 pmu_interrupt_count;
183 u32 pmu_interrupt_offset;
184 u64 interrupts[1];
185};
186
187
188
189#define ACPI_IORT_SMMU_V1 0x00000000
190#define ACPI_IORT_SMMU_V2 0x00000001
191#define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002
192#define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003
193#define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004
194#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005
195
196
197
198#define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
199#define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
200
201
202
203struct acpi_iort_smmu_gsi {
204 u32 nsg_irpt;
205 u32 nsg_irpt_flags;
206 u32 nsg_cfg_irpt;
207 u32 nsg_cfg_irpt_flags;
208};
209
210struct acpi_iort_smmu_v3 {
211 u64 base_address;
212 u32 flags;
213 u32 reserved;
214 u64 vatos_address;
215 u32 model;
216 u32 event_gsiv;
217 u32 pri_gsiv;
218 u32 gerr_gsiv;
219 u32 sync_gsiv;
220 u32 pxm;
221 u32 id_mapping_index;
222};
223
224
225
226#define ACPI_IORT_SMMU_V3_GENERIC 0x00000000
227#define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001
228#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002
229
230
231
232#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
233#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1)
234#define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
235
236struct acpi_iort_pmcg {
237 u64 page0_base_address;
238 u32 overflow_gsiv;
239 u32 node_reference;
240 u64 page1_base_address;
241};
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252
253struct acpi_table_ivrs {
254 struct acpi_table_header header;
255 u32 info;
256 u64 reserved;
257};
258
259
260
261#define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00
262#define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000
263#define ACPI_IVRS_ATS_RESERVED 0x00400000
264
265
266
267struct acpi_ivrs_header {
268 u8 type;
269 u8 flags;
270 u16 length;
271 u16 device_id;
272};
273
274
275
276enum acpi_ivrs_type {
277 ACPI_IVRS_TYPE_HARDWARE = 0x10,
278 ACPI_IVRS_TYPE_MEMORY1 = 0x20,
279 ACPI_IVRS_TYPE_MEMORY2 = 0x21,
280 ACPI_IVRS_TYPE_MEMORY3 = 0x22
281};
282
283
284
285#define ACPI_IVHD_TT_ENABLE (1)
286#define ACPI_IVHD_PASS_PW (1<<1)
287#define ACPI_IVHD_RES_PASS_PW (1<<2)
288#define ACPI_IVHD_ISOC (1<<3)
289#define ACPI_IVHD_IOTLB (1<<4)
290
291
292
293#define ACPI_IVMD_UNITY (1)
294#define ACPI_IVMD_READ (1<<1)
295#define ACPI_IVMD_WRITE (1<<2)
296#define ACPI_IVMD_EXCLUSION_RANGE (1<<3)
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303
304struct acpi_ivrs_hardware {
305 struct acpi_ivrs_header header;
306 u16 capability_offset;
307 u64 base_address;
308 u16 pci_segment_group;
309 u16 info;
310 u32 reserved;
311};
312
313
314
315#define ACPI_IVHD_MSI_NUMBER_MASK 0x001F
316#define ACPI_IVHD_UNIT_ID_MASK 0x1F00
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323
324struct acpi_ivrs_de_header {
325 u8 type;
326 u16 id;
327 u8 data_setting;
328};
329
330
331
332#define ACPI_IVHD_ENTRY_LENGTH 0xC0
333
334
335
336enum acpi_ivrs_device_entry_type {
337
338
339 ACPI_IVRS_TYPE_PAD4 = 0,
340 ACPI_IVRS_TYPE_ALL = 1,
341 ACPI_IVRS_TYPE_SELECT = 2,
342 ACPI_IVRS_TYPE_START = 3,
343 ACPI_IVRS_TYPE_END = 4,
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345
346
347 ACPI_IVRS_TYPE_PAD8 = 64,
348 ACPI_IVRS_TYPE_NOT_USED = 65,
349 ACPI_IVRS_TYPE_ALIAS_SELECT = 66,
350 ACPI_IVRS_TYPE_ALIAS_START = 67,
351 ACPI_IVRS_TYPE_EXT_SELECT = 70,
352 ACPI_IVRS_TYPE_EXT_START = 71,
353 ACPI_IVRS_TYPE_SPECIAL = 72
354};
355
356
357
358#define ACPI_IVHD_INIT_PASS (1)
359#define ACPI_IVHD_EINT_PASS (1<<1)
360#define ACPI_IVHD_NMI_PASS (1<<2)
361#define ACPI_IVHD_SYSTEM_MGMT (3<<4)
362#define ACPI_IVHD_LINT0_PASS (1<<6)
363#define ACPI_IVHD_LINT1_PASS (1<<7)
364
365
366
367struct acpi_ivrs_device4 {
368 struct acpi_ivrs_de_header header;
369};
370
371
372
373struct acpi_ivrs_device8a {
374 struct acpi_ivrs_de_header header;
375 u8 reserved1;
376 u16 used_id;
377 u8 reserved2;
378};
379
380
381
382struct acpi_ivrs_device8b {
383 struct acpi_ivrs_de_header header;
384 u32 extended_data;
385};
386
387
388
389#define ACPI_IVHD_ATS_DISABLED (1<<31)
390
391
392
393struct acpi_ivrs_device8c {
394 struct acpi_ivrs_de_header header;
395 u8 handle;
396 u16 used_id;
397 u8 variety;
398};
399
400
401
402#define ACPI_IVHD_IOAPIC 1
403#define ACPI_IVHD_HPET 2
404
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406
407struct acpi_ivrs_memory {
408 struct acpi_ivrs_header header;
409 u16 aux_data;
410 u64 reserved;
411 u64 start_address;
412 u64 memory_length;
413};
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422
423struct acpi_table_lpit {
424 struct acpi_table_header header;
425};
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427
428
429struct acpi_lpit_header {
430 u32 type;
431 u32 length;
432 u16 unique_id;
433 u16 reserved;
434 u32 flags;
435};
436
437
438
439enum acpi_lpit_type {
440 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
441 ACPI_LPIT_TYPE_RESERVED = 0x01
442};
443
444
445
446#define ACPI_LPIT_STATE_DISABLED (1)
447#define ACPI_LPIT_NO_COUNTER (1<<1)
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454
455struct acpi_lpit_native {
456 struct acpi_lpit_header header;
457 struct acpi_generic_address entry_trigger;
458 u32 residency;
459 u32 latency;
460 struct acpi_generic_address residency_counter;
461 u64 counter_frequency;
462};
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470
471struct acpi_table_madt {
472 struct acpi_table_header header;
473 u32 address;
474 u32 flags;
475};
476
477
478
479#define ACPI_MADT_PCAT_COMPAT (1)
480
481
482
483#define ACPI_MADT_DUAL_PIC 1
484#define ACPI_MADT_MULTIPLE_APIC 0
485
486
487
488enum acpi_madt_type {
489 ACPI_MADT_TYPE_LOCAL_APIC = 0,
490 ACPI_MADT_TYPE_IO_APIC = 1,
491 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,
492 ACPI_MADT_TYPE_NMI_SOURCE = 3,
493 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,
494 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,
495 ACPI_MADT_TYPE_IO_SAPIC = 6,
496 ACPI_MADT_TYPE_LOCAL_SAPIC = 7,
497 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,
498 ACPI_MADT_TYPE_LOCAL_X2APIC = 9,
499 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
500 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,
501 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,
502 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,
503 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
504 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
505 ACPI_MADT_TYPE_RESERVED = 16
506};
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514struct acpi_madt_local_apic {
515 struct acpi_subtable_header header;
516 u8 processor_id;
517 u8 id;
518 u32 lapic_flags;
519};
520
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522
523struct acpi_madt_io_apic {
524 struct acpi_subtable_header header;
525 u8 id;
526 u8 reserved;
527 u32 address;
528 u32 global_irq_base;
529};
530
531
532
533struct acpi_madt_interrupt_override {
534 struct acpi_subtable_header header;
535 u8 bus;
536 u8 source_irq;
537 u32 global_irq;
538 u16 inti_flags;
539};
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543struct acpi_madt_nmi_source {
544 struct acpi_subtable_header header;
545 u16 inti_flags;
546 u32 global_irq;
547};
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550
551struct acpi_madt_local_apic_nmi {
552 struct acpi_subtable_header header;
553 u8 processor_id;
554 u16 inti_flags;
555 u8 lint;
556};
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560struct acpi_madt_local_apic_override {
561 struct acpi_subtable_header header;
562 u16 reserved;
563 u64 address;
564};
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568struct acpi_madt_io_sapic {
569 struct acpi_subtable_header header;
570 u8 id;
571 u8 reserved;
572 u32 global_irq_base;
573 u64 address;
574};
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576
577
578struct acpi_madt_local_sapic {
579 struct acpi_subtable_header header;
580 u8 processor_id;
581 u8 id;
582 u8 eid;
583 u8 reserved[3];
584 u32 lapic_flags;
585 u32 uid;
586 char uid_string[1];
587};
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590
591struct acpi_madt_interrupt_source {
592 struct acpi_subtable_header header;
593 u16 inti_flags;
594 u8 type;
595 u8 id;
596 u8 eid;
597 u8 io_sapic_vector;
598 u32 global_irq;
599 u32 flags;
600};
601
602
603
604#define ACPI_MADT_CPEI_OVERRIDE (1)
605
606
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608struct acpi_madt_local_x2apic {
609 struct acpi_subtable_header header;
610 u16 reserved;
611 u32 local_apic_id;
612 u32 lapic_flags;
613 u32 uid;
614};
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617
618struct acpi_madt_local_x2apic_nmi {
619 struct acpi_subtable_header header;
620 u16 inti_flags;
621 u32 uid;
622 u8 lint;
623 u8 reserved[3];
624};
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627
628struct acpi_madt_generic_interrupt {
629 struct acpi_subtable_header header;
630 u16 reserved;
631 u32 cpu_interface_number;
632 u32 uid;
633 u32 flags;
634 u32 parking_version;
635 u32 performance_interrupt;
636 u64 parked_address;
637 u64 base_address;
638 u64 gicv_base_address;
639 u64 gich_base_address;
640 u32 vgic_interrupt;
641 u64 gicr_base_address;
642 u64 arm_mpidr;
643 u8 efficiency_class;
644 u8 reserved2[1];
645 u16 spe_interrupt;
646};
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649
650
651#define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1)
652#define ACPI_MADT_VGIC_IRQ_MODE (1<<2)
653
654
655
656struct acpi_madt_generic_distributor {
657 struct acpi_subtable_header header;
658 u16 reserved;
659 u32 gic_id;
660 u64 base_address;
661 u32 global_irq_base;
662 u8 version;
663 u8 reserved2[3];
664};
665
666
667
668enum acpi_madt_gic_version {
669 ACPI_MADT_GIC_VERSION_NONE = 0,
670 ACPI_MADT_GIC_VERSION_V1 = 1,
671 ACPI_MADT_GIC_VERSION_V2 = 2,
672 ACPI_MADT_GIC_VERSION_V3 = 3,
673 ACPI_MADT_GIC_VERSION_V4 = 4,
674 ACPI_MADT_GIC_VERSION_RESERVED = 5
675};
676
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678
679struct acpi_madt_generic_msi_frame {
680 struct acpi_subtable_header header;
681 u16 reserved;
682 u32 msi_frame_id;
683 u64 base_address;
684 u32 flags;
685 u16 spi_count;
686 u16 spi_base;
687};
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690
691#define ACPI_MADT_OVERRIDE_SPI_VALUES (1)
692
693
694
695struct acpi_madt_generic_redistributor {
696 struct acpi_subtable_header header;
697 u16 reserved;
698 u64 base_address;
699 u32 length;
700};
701
702
703
704struct acpi_madt_generic_translator {
705 struct acpi_subtable_header header;
706 u16 reserved;
707 u32 translation_id;
708 u64 base_address;
709 u32 reserved2;
710};
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717
718#define ACPI_MADT_ENABLED (1)
719
720
721
722#define ACPI_MADT_POLARITY_MASK (3)
723#define ACPI_MADT_TRIGGER_MASK (3<<2)
724
725
726
727#define ACPI_MADT_POLARITY_CONFORMS 0
728#define ACPI_MADT_POLARITY_ACTIVE_HIGH 1
729#define ACPI_MADT_POLARITY_RESERVED 2
730#define ACPI_MADT_POLARITY_ACTIVE_LOW 3
731
732#define ACPI_MADT_TRIGGER_CONFORMS (0)
733#define ACPI_MADT_TRIGGER_EDGE (1<<2)
734#define ACPI_MADT_TRIGGER_RESERVED (2<<2)
735#define ACPI_MADT_TRIGGER_LEVEL (3<<2)
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745
746struct acpi_table_mcfg {
747 struct acpi_table_header header;
748 u8 reserved[8];
749};
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752
753struct acpi_mcfg_allocation {
754 u64 address;
755 u16 pci_segment;
756 u8 start_bus_number;
757 u8 end_bus_number;
758 u32 reserved;
759};
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769
770
771struct acpi_table_mchi {
772 struct acpi_table_header header;
773 u8 interface_type;
774 u8 protocol;
775 u64 protocol_data;
776 u8 interrupt_type;
777 u8 gpe;
778 u8 pci_device_flag;
779 u32 global_interrupt;
780 struct acpi_generic_address control_register;
781 u8 pci_segment;
782 u8 pci_bus;
783 u8 pci_device;
784 u8 pci_function;
785};
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793
794#define ACPI_MPST_CHANNEL_INFO \
795 u8 channel_id; \
796 u8 reserved1[3]; \
797 u16 power_node_count; \
798 u16 reserved2;
799
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801
802struct acpi_table_mpst {
803 struct acpi_table_header header;
804 ACPI_MPST_CHANNEL_INFO
805};
806
807
808
809struct acpi_mpst_channel {
810 ACPI_MPST_CHANNEL_INFO
811};
812
813
814
815struct acpi_mpst_power_node {
816 u8 flags;
817 u8 reserved1;
818 u16 node_id;
819 u32 length;
820 u64 range_address;
821 u64 range_length;
822 u32 num_power_states;
823 u32 num_physical_components;
824};
825
826
827
828#define ACPI_MPST_ENABLED 1
829#define ACPI_MPST_POWER_MANAGED 2
830#define ACPI_MPST_HOT_PLUG_CAPABLE 4
831
832
833
834struct acpi_mpst_power_state {
835 u8 power_state;
836 u8 info_index;
837};
838
839
840
841struct acpi_mpst_component {
842 u16 component_id;
843};
844
845
846
847struct acpi_mpst_data_hdr {
848 u16 characteristics_count;
849 u16 reserved;
850};
851
852struct acpi_mpst_power_data {
853 u8 structure_id;
854 u8 flags;
855 u16 reserved1;
856 u32 average_power;
857 u32 power_saving;
858 u64 exit_latency;
859 u64 reserved2;
860};
861
862
863
864#define ACPI_MPST_PRESERVE 1
865#define ACPI_MPST_AUTOENTRY 2
866#define ACPI_MPST_AUTOEXIT 4
867
868
869
870struct acpi_mpst_shared {
871 u32 signature;
872 u16 pcc_command;
873 u16 pcc_status;
874 u32 command_register;
875 u32 status_register;
876 u32 power_state_id;
877 u32 power_node_id;
878 u64 energy_consumed;
879 u64 average_power;
880};
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888
889struct acpi_table_msct {
890 struct acpi_table_header header;
891 u32 proximity_offset;
892 u32 max_proximity_domains;
893 u32 max_clock_domains;
894 u64 max_address;
895};
896
897
898
899struct acpi_msct_proximity {
900 u8 revision;
901 u8 length;
902 u32 range_start;
903 u32 range_end;
904 u32 processor_capacity;
905 u64 memory_capacity;
906};
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918
919struct acpi_table_msdm {
920 struct acpi_table_header header;
921};
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933
934struct acpi_table_mtmr {
935 struct acpi_table_header header;
936};
937
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939
940struct acpi_mtmr_entry {
941 struct acpi_generic_address physical_address;
942 u32 frequency;
943 u32 irq;
944};
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951
952
953struct acpi_table_nfit {
954 struct acpi_table_header header;
955 u32 reserved;
956};
957
958
959
960struct acpi_nfit_header {
961 u16 type;
962 u16 length;
963};
964
965
966
967enum acpi_nfit_type {
968 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0,
969 ACPI_NFIT_TYPE_MEMORY_MAP = 1,
970 ACPI_NFIT_TYPE_INTERLEAVE = 2,
971 ACPI_NFIT_TYPE_SMBIOS = 3,
972 ACPI_NFIT_TYPE_CONTROL_REGION = 4,
973 ACPI_NFIT_TYPE_DATA_REGION = 5,
974 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6,
975 ACPI_NFIT_TYPE_CAPABILITIES = 7,
976 ACPI_NFIT_TYPE_RESERVED = 8
977};
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983
984
985struct acpi_nfit_system_address {
986 struct acpi_nfit_header header;
987 u16 range_index;
988 u16 flags;
989 u32 reserved;
990 u32 proximity_domain;
991 u8 range_guid[16];
992 u64 address;
993 u64 length;
994 u64 memory_mapping;
995};
996
997
998
999#define ACPI_NFIT_ADD_ONLINE_ONLY (1)
1000#define ACPI_NFIT_PROXIMITY_VALID (1<<1)
1001
1002
1003
1004
1005
1006struct acpi_nfit_memory_map {
1007 struct acpi_nfit_header header;
1008 u32 device_handle;
1009 u16 physical_id;
1010 u16 region_id;
1011 u16 range_index;
1012 u16 region_index;
1013 u64 region_size;
1014 u64 region_offset;
1015 u64 address;
1016 u16 interleave_index;
1017 u16 interleave_ways;
1018 u16 flags;
1019 u16 reserved;
1020};
1021
1022
1023
1024#define ACPI_NFIT_MEM_SAVE_FAILED (1)
1025#define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1)
1026#define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2)
1027#define ACPI_NFIT_MEM_NOT_ARMED (1<<3)
1028#define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4)
1029#define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5)
1030#define ACPI_NFIT_MEM_MAP_FAILED (1<<6)
1031
1032
1033
1034struct acpi_nfit_interleave {
1035 struct acpi_nfit_header header;
1036 u16 interleave_index;
1037 u16 reserved;
1038 u32 line_count;
1039 u32 line_size;
1040 u32 line_offset[1];
1041};
1042
1043
1044
1045struct acpi_nfit_smbios {
1046 struct acpi_nfit_header header;
1047 u32 reserved;
1048 u8 data[1];
1049};
1050
1051
1052
1053struct acpi_nfit_control_region {
1054 struct acpi_nfit_header header;
1055 u16 region_index;
1056 u16 vendor_id;
1057 u16 device_id;
1058 u16 revision_id;
1059 u16 subsystem_vendor_id;
1060 u16 subsystem_device_id;
1061 u16 subsystem_revision_id;
1062 u8 valid_fields;
1063 u8 manufacturing_location;
1064 u16 manufacturing_date;
1065 u8 reserved[2];
1066 u32 serial_number;
1067 u16 code;
1068 u16 windows;
1069 u64 window_size;
1070 u64 command_offset;
1071 u64 command_size;
1072 u64 status_offset;
1073 u64 status_size;
1074 u16 flags;
1075 u8 reserved1[6];
1076};
1077
1078
1079
1080#define ACPI_NFIT_CONTROL_BUFFERED (1)
1081
1082
1083
1084#define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1)
1085
1086
1087
1088struct acpi_nfit_data_region {
1089 struct acpi_nfit_header header;
1090 u16 region_index;
1091 u16 windows;
1092 u64 offset;
1093 u64 size;
1094 u64 capacity;
1095 u64 start_address;
1096};
1097
1098
1099
1100struct acpi_nfit_flush_address {
1101 struct acpi_nfit_header header;
1102 u32 device_handle;
1103 u16 hint_count;
1104 u8 reserved[6];
1105 u64 hint_address[1];
1106};
1107
1108
1109
1110struct acpi_nfit_capabilities {
1111 struct acpi_nfit_header header;
1112 u8 highest_capability;
1113 u8 reserved[3];
1114 u32 capabilities;
1115 u32 reserved2;
1116};
1117
1118
1119
1120#define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1)
1121#define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1)
1122#define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2)
1123
1124
1125
1126
1127struct nfit_device_handle {
1128 u32 handle;
1129};
1130
1131
1132
1133#define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F
1134#define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0
1135#define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00
1136#define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000
1137#define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000
1138
1139#define ACPI_NFIT_DIMM_NUMBER_OFFSET 0
1140#define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4
1141#define ACPI_NFIT_MEMORY_ID_OFFSET 8
1142#define ACPI_NFIT_SOCKET_ID_OFFSET 12
1143#define ACPI_NFIT_NODE_ID_OFFSET 16
1144
1145
1146
1147#define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \
1148 ((dimm) | \
1149 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \
1150 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \
1151 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \
1152 ((node) << ACPI_NFIT_NODE_ID_OFFSET))
1153
1154
1155
1156#define ACPI_NFIT_GET_DIMM_NUMBER(handle) \
1157 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK)
1158
1159#define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \
1160 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET)
1161
1162#define ACPI_NFIT_GET_MEMORY_ID(handle) \
1163 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET)
1164
1165#define ACPI_NFIT_GET_SOCKET_ID(handle) \
1166 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET)
1167
1168#define ACPI_NFIT_GET_NODE_ID(handle) \
1169 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET)
1170
1171
1172
1173
1174
1175
1176
1177
1178struct acpi_table_pcct {
1179 struct acpi_table_header header;
1180 u32 flags;
1181 u64 reserved;
1182};
1183
1184
1185
1186#define ACPI_PCCT_DOORBELL 1
1187
1188
1189
1190enum acpi_pcct_type {
1191 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,
1192 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,
1193 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,
1194 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,
1195 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,
1196 ACPI_PCCT_TYPE_RESERVED = 5
1197};
1198
1199
1200
1201
1202
1203
1204
1205struct acpi_pcct_subspace {
1206 struct acpi_subtable_header header;
1207 u8 reserved[6];
1208 u64 base_address;
1209 u64 length;
1210 struct acpi_generic_address doorbell_register;
1211 u64 preserve_mask;
1212 u64 write_mask;
1213 u32 latency;
1214 u32 max_access_rate;
1215 u16 min_turnaround_time;
1216};
1217
1218
1219
1220struct acpi_pcct_hw_reduced {
1221 struct acpi_subtable_header header;
1222 u32 platform_interrupt;
1223 u8 flags;
1224 u8 reserved;
1225 u64 base_address;
1226 u64 length;
1227 struct acpi_generic_address doorbell_register;
1228 u64 preserve_mask;
1229 u64 write_mask;
1230 u32 latency;
1231 u32 max_access_rate;
1232 u16 min_turnaround_time;
1233};
1234
1235
1236
1237struct acpi_pcct_hw_reduced_type2 {
1238 struct acpi_subtable_header header;
1239 u32 platform_interrupt;
1240 u8 flags;
1241 u8 reserved;
1242 u64 base_address;
1243 u64 length;
1244 struct acpi_generic_address doorbell_register;
1245 u64 preserve_mask;
1246 u64 write_mask;
1247 u32 latency;
1248 u32 max_access_rate;
1249 u16 min_turnaround_time;
1250 struct acpi_generic_address platform_ack_register;
1251 u64 ack_preserve_mask;
1252 u64 ack_write_mask;
1253};
1254
1255
1256
1257struct acpi_pcct_ext_pcc_master {
1258 struct acpi_subtable_header header;
1259 u32 platform_interrupt;
1260 u8 flags;
1261 u8 reserved1;
1262 u64 base_address;
1263 u32 length;
1264 struct acpi_generic_address doorbell_register;
1265 u64 preserve_mask;
1266 u64 write_mask;
1267 u32 latency;
1268 u32 max_access_rate;
1269 u32 min_turnaround_time;
1270 struct acpi_generic_address platform_ack_register;
1271 u64 ack_preserve_mask;
1272 u64 ack_set_mask;
1273 u64 reserved2;
1274 struct acpi_generic_address cmd_complete_register;
1275 u64 cmd_complete_mask;
1276 struct acpi_generic_address cmd_update_register;
1277 u64 cmd_update_preserve_mask;
1278 u64 cmd_update_set_mask;
1279 struct acpi_generic_address error_status_register;
1280 u64 error_status_mask;
1281};
1282
1283
1284
1285struct acpi_pcct_ext_pcc_slave {
1286 struct acpi_subtable_header header;
1287 u32 platform_interrupt;
1288 u8 flags;
1289 u8 reserved1;
1290 u64 base_address;
1291 u32 length;
1292 struct acpi_generic_address doorbell_register;
1293 u64 preserve_mask;
1294 u64 write_mask;
1295 u32 latency;
1296 u32 max_access_rate;
1297 u32 min_turnaround_time;
1298 struct acpi_generic_address platform_ack_register;
1299 u64 ack_preserve_mask;
1300 u64 ack_set_mask;
1301 u64 reserved2;
1302 struct acpi_generic_address cmd_complete_register;
1303 u64 cmd_complete_mask;
1304 struct acpi_generic_address cmd_update_register;
1305 u64 cmd_update_preserve_mask;
1306 u64 cmd_update_set_mask;
1307 struct acpi_generic_address error_status_register;
1308 u64 error_status_mask;
1309};
1310
1311
1312
1313#define ACPI_PCCT_INTERRUPT_POLARITY (1)
1314#define ACPI_PCCT_INTERRUPT_MODE (1<<1)
1315
1316
1317
1318
1319
1320
1321
1322struct acpi_pcct_shared_memory {
1323 u32 signature;
1324 u16 command;
1325 u16 status;
1326};
1327
1328
1329
1330struct acpi_pcct_ext_pcc_shared_memory {
1331 u32 signature;
1332 u32 flags;
1333 u32 length;
1334 u32 command;
1335};
1336
1337
1338
1339
1340
1341
1342
1343
1344struct acpi_table_pdtt {
1345 struct acpi_table_header header;
1346 u8 trigger_count;
1347 u8 reserved[3];
1348 u32 array_offset;
1349};
1350
1351
1352
1353
1354
1355
1356struct acpi_pdtt_channel {
1357 u8 subchannel_id;
1358 u8 flags;
1359};
1360
1361
1362
1363#define ACPI_PDTT_RUNTIME_TRIGGER (1)
1364#define ACPI_PDTT_WAIT_COMPLETION (1<<1)
1365#define ACPI_PDTT_TRIGGER_ORDER (1<<2)
1366
1367
1368
1369
1370
1371
1372
1373
1374struct acpi_table_pmtt {
1375 struct acpi_table_header header;
1376 u32 reserved;
1377};
1378
1379
1380
1381struct acpi_pmtt_header {
1382 u8 type;
1383 u8 reserved1;
1384 u16 length;
1385 u16 flags;
1386 u16 reserved2;
1387};
1388
1389
1390
1391#define ACPI_PMTT_TYPE_SOCKET 0
1392#define ACPI_PMTT_TYPE_CONTROLLER 1
1393#define ACPI_PMTT_TYPE_DIMM 2
1394#define ACPI_PMTT_TYPE_RESERVED 3
1395
1396
1397
1398#define ACPI_PMTT_TOP_LEVEL 0x0001
1399#define ACPI_PMTT_PHYSICAL 0x0002
1400#define ACPI_PMTT_MEMORY_TYPE 0x000C
1401
1402
1403
1404
1405
1406
1407
1408struct acpi_pmtt_socket {
1409 struct acpi_pmtt_header header;
1410 u16 socket_id;
1411 u16 reserved;
1412};
1413
1414
1415
1416struct acpi_pmtt_controller {
1417 struct acpi_pmtt_header header;
1418 u32 read_latency;
1419 u32 write_latency;
1420 u32 read_bandwidth;
1421 u32 write_bandwidth;
1422 u16 access_width;
1423 u16 alignment;
1424 u16 reserved;
1425 u16 domain_count;
1426};
1427
1428
1429
1430struct acpi_pmtt_domain {
1431 u32 proximity_domain;
1432};
1433
1434
1435
1436struct acpi_pmtt_physical_component {
1437 struct acpi_pmtt_header header;
1438 u16 component_id;
1439 u16 reserved;
1440 u32 memory_size;
1441 u32 bios_handle;
1442};
1443
1444
1445
1446
1447
1448
1449
1450
1451struct acpi_table_pptt {
1452 struct acpi_table_header header;
1453};
1454
1455
1456
1457enum acpi_pptt_type {
1458 ACPI_PPTT_TYPE_PROCESSOR = 0,
1459 ACPI_PPTT_TYPE_CACHE = 1,
1460 ACPI_PPTT_TYPE_ID = 2,
1461 ACPI_PPTT_TYPE_RESERVED = 3
1462};
1463
1464
1465
1466struct acpi_pptt_processor {
1467 struct acpi_subtable_header header;
1468 u16 reserved;
1469 u32 flags;
1470 u32 parent;
1471 u32 acpi_processor_id;
1472 u32 number_of_priv_resources;
1473};
1474
1475
1476
1477#define ACPI_PPTT_PHYSICAL_PACKAGE (1)
1478#define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1)
1479#define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2)
1480#define ACPI_PPTT_ACPI_LEAF_NODE (1<<3)
1481#define ACPI_PPTT_ACPI_IDENTICAL (1<<4)
1482
1483
1484
1485struct acpi_pptt_cache {
1486 struct acpi_subtable_header header;
1487 u16 reserved;
1488 u32 flags;
1489 u32 next_level_of_cache;
1490 u32 size;
1491 u32 number_of_sets;
1492 u8 associativity;
1493 u8 attributes;
1494 u16 line_size;
1495};
1496
1497
1498
1499#define ACPI_PPTT_SIZE_PROPERTY_VALID (1)
1500#define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1)
1501#define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2)
1502#define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3)
1503#define ACPI_PPTT_CACHE_TYPE_VALID (1<<4)
1504#define ACPI_PPTT_WRITE_POLICY_VALID (1<<5)
1505#define ACPI_PPTT_LINE_SIZE_VALID (1<<6)
1506
1507
1508
1509#define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03)
1510#define ACPI_PPTT_MASK_CACHE_TYPE (0x0C)
1511#define ACPI_PPTT_MASK_WRITE_POLICY (0x10)
1512
1513
1514#define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0)
1515#define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01)
1516#define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02)
1517#define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03)
1518
1519#define ACPI_PPTT_CACHE_TYPE_DATA (0x0)
1520#define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2)
1521#define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2)
1522#define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2)
1523
1524#define ACPI_PPTT_CACHE_POLICY_WB (0x0)
1525#define ACPI_PPTT_CACHE_POLICY_WT (1<<4)
1526
1527
1528
1529struct acpi_pptt_id {
1530 struct acpi_subtable_header header;
1531 u16 reserved;
1532 u32 vendor_id;
1533 u64 level1_id;
1534 u64 level2_id;
1535 u16 major_rev;
1536 u16 minor_rev;
1537 u16 spin_rev;
1538};
1539
1540
1541
1542
1543
1544
1545
1546
1547struct acpi_table_rasf {
1548 struct acpi_table_header header;
1549 u8 channel_id[12];
1550};
1551
1552
1553
1554struct acpi_rasf_shared_memory {
1555 u32 signature;
1556 u16 command;
1557 u16 status;
1558 u16 version;
1559 u8 capabilities[16];
1560 u8 set_capabilities[16];
1561 u16 num_parameter_blocks;
1562 u32 set_capabilities_status;
1563};
1564
1565
1566
1567struct acpi_rasf_parameter_block {
1568 u16 type;
1569 u16 version;
1570 u16 length;
1571};
1572
1573
1574
1575struct acpi_rasf_patrol_scrub_parameter {
1576 struct acpi_rasf_parameter_block header;
1577 u16 patrol_scrub_command;
1578 u64 requested_address_range[2];
1579 u64 actual_address_range[2];
1580 u16 flags;
1581 u8 requested_speed;
1582};
1583
1584
1585
1586#define ACPI_RASF_SCRUBBER_RUNNING 1
1587#define ACPI_RASF_SPEED (7<<1)
1588#define ACPI_RASF_SPEED_SLOW (0<<1)
1589#define ACPI_RASF_SPEED_MEDIUM (4<<1)
1590#define ACPI_RASF_SPEED_FAST (7<<1)
1591
1592
1593
1594enum acpi_rasf_commands {
1595 ACPI_RASF_EXECUTE_RASF_COMMAND = 1
1596};
1597
1598
1599
1600enum acpi_rasf_capabiliities {
1601 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0,
1602 ACPI_SW_PATROL_SCRUB_EXPOSED = 1
1603};
1604
1605
1606
1607enum acpi_rasf_patrol_scrub_commands {
1608 ACPI_RASF_GET_PATROL_PARAMETERS = 1,
1609 ACPI_RASF_START_PATROL_SCRUBBER = 2,
1610 ACPI_RASF_STOP_PATROL_SCRUBBER = 3
1611};
1612
1613
1614
1615#define ACPI_RASF_GENERATE_SCI (1<<15)
1616
1617
1618
1619enum acpi_rasf_status {
1620 ACPI_RASF_SUCCESS = 0,
1621 ACPI_RASF_NOT_VALID = 1,
1622 ACPI_RASF_NOT_SUPPORTED = 2,
1623 ACPI_RASF_BUSY = 3,
1624 ACPI_RASF_FAILED = 4,
1625 ACPI_RASF_ABORTED = 5,
1626 ACPI_RASF_INVALID_DATA = 6
1627};
1628
1629
1630
1631#define ACPI_RASF_COMMAND_COMPLETE (1)
1632#define ACPI_RASF_SCI_DOORBELL (1<<1)
1633#define ACPI_RASF_ERROR (1<<2)
1634#define ACPI_RASF_STATUS (0x1F<<3)
1635
1636
1637
1638
1639
1640
1641
1642
1643struct acpi_table_sbst {
1644 struct acpi_table_header header;
1645 u32 warning_level;
1646 u32 low_level;
1647 u32 critical_level;
1648};
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659struct acpi_table_sdei {
1660 struct acpi_table_header header;
1661};
1662
1663
1664
1665
1666
1667
1668
1669
1670struct acpi_table_sdev {
1671 struct acpi_table_header header;
1672};
1673
1674struct acpi_sdev_header {
1675 u8 type;
1676 u8 flags;
1677 u16 length;
1678};
1679
1680
1681
1682enum acpi_sdev_type {
1683 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0,
1684 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1,
1685 ACPI_SDEV_TYPE_RESERVED = 2
1686};
1687
1688
1689
1690#define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1)
1691
1692
1693
1694
1695
1696
1697
1698struct acpi_sdev_namespace {
1699 struct acpi_sdev_header header;
1700 u16 device_id_offset;
1701 u16 device_id_length;
1702 u16 vendor_data_offset;
1703 u16 vendor_data_length;
1704};
1705
1706
1707
1708struct acpi_sdev_pcie {
1709 struct acpi_sdev_header header;
1710 u16 segment;
1711 u16 start_bus;
1712 u16 path_offset;
1713 u16 path_length;
1714 u16 vendor_data_offset;
1715 u16 vendor_data_length;
1716};
1717
1718
1719
1720struct acpi_sdev_pcie_path {
1721 u8 device;
1722 u8 function;
1723};
1724
1725
1726
1727#pragma pack()
1728
1729#endif
1730