1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org> 4 * Steven J. Hill <sjhill@realitydiluted.com> 5 * Thomas Gleixner <tglx@linutronix.de> 6 * 7 * Info: 8 * Contains standard defines and IDs for NAND flash devices 9 * 10 * Changelog: 11 * See git changelog. 12 */ 13#ifndef __LINUX_MTD_RAWNAND_H 14#define __LINUX_MTD_RAWNAND_H 15 16#include <linux/mtd/mtd.h> 17#include <linux/mtd/flashchip.h> 18#include <linux/mtd/bbm.h> 19#include <linux/mtd/jedec.h> 20#include <linux/mtd/nand.h> 21#include <linux/mtd/onfi.h> 22#include <linux/mutex.h> 23#include <linux/of.h> 24#include <linux/types.h> 25 26struct nand_chip; 27 28/* The maximum number of NAND chips in an array */ 29#define NAND_MAX_CHIPS 8 30 31/* 32 * Constants for hardware specific CLE/ALE/NCE function 33 * 34 * These are bits which can be or'ed to set/clear multiple 35 * bits in one go. 36 */ 37/* Select the chip by setting nCE to low */ 38#define NAND_NCE 0x01 39/* Select the command latch by setting CLE to high */ 40#define NAND_CLE 0x02 41/* Select the address latch by setting ALE to high */ 42#define NAND_ALE 0x04 43 44#define NAND_CTRL_CLE (NAND_NCE | NAND_CLE) 45#define NAND_CTRL_ALE (NAND_NCE | NAND_ALE) 46#define NAND_CTRL_CHANGE 0x80 47 48/* 49 * Standard NAND flash commands 50 */ 51#define NAND_CMD_READ0 0 52#define NAND_CMD_READ1 1 53#define NAND_CMD_RNDOUT 5 54#define NAND_CMD_PAGEPROG 0x10 55#define NAND_CMD_READOOB 0x50 56#define NAND_CMD_ERASE1 0x60 57#define NAND_CMD_STATUS 0x70 58#define NAND_CMD_SEQIN 0x80 59#define NAND_CMD_RNDIN 0x85 60#define NAND_CMD_READID 0x90 61#define NAND_CMD_ERASE2 0xd0 62#define NAND_CMD_PARAM 0xec 63#define NAND_CMD_GET_FEATURES 0xee 64#define NAND_CMD_SET_FEATURES 0xef 65#define NAND_CMD_RESET 0xff 66 67/* Extended commands for large page devices */ 68#define NAND_CMD_READSTART 0x30 69#define NAND_CMD_RNDOUTSTART 0xE0 70#define NAND_CMD_CACHEDPROG 0x15 71 72#define NAND_CMD_NONE -1 73 74/* Status bits */ 75#define NAND_STATUS_FAIL 0x01 76#define NAND_STATUS_FAIL_N1 0x02 77#define NAND_STATUS_TRUE_READY 0x20 78#define NAND_STATUS_READY 0x40 79#define NAND_STATUS_WP 0x80 80 81#define NAND_DATA_IFACE_CHECK_ONLY -1 82 83/* 84 * Constants for ECC_MODES 85 */ 86typedef enum { 87 NAND_ECC_NONE, 88 NAND_ECC_SOFT, 89 NAND_ECC_HW, 90 NAND_ECC_HW_SYNDROME, 91 NAND_ECC_HW_OOB_FIRST, 92 NAND_ECC_ON_DIE, 93} nand_ecc_modes_t; 94 95enum nand_ecc_algo { 96 NAND_ECC_UNKNOWN, 97 NAND_ECC_HAMMING, 98 NAND_ECC_BCH, 99 NAND_ECC_RS, 100}; 101 102/* 103 * Constants for Hardware ECC 104 */ 105/* Reset Hardware ECC for read */ 106#define NAND_ECC_READ 0 107/* Reset Hardware ECC for write */ 108#define NAND_ECC_WRITE 1 109/* Enable Hardware ECC before syndrome is read back from flash */ 110#define NAND_ECC_READSYN 2 111 112/* 113 * Enable generic NAND 'page erased' check. This check is only done when 114 * ecc.correct() returns -EBADMSG. 115 * Set this flag if your implementation does not fix bitflips in erased 116 * pages and you want to rely on the default implementation. 117 */ 118#define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 119#define NAND_ECC_MAXIMIZE BIT(1) 120 121/* 122 * When using software implementation of Hamming, we can specify which byte 123 * ordering should be used. 124 */ 125#define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2) 126 127/* 128 * Option constants for bizarre disfunctionality and real 129 * features. 130 */ 131/* Buswidth is 16 bit */ 132#define NAND_BUSWIDTH_16 0x00000002 133/* Chip has cache program function */ 134#define NAND_CACHEPRG 0x00000008 135/* 136 * Chip requires ready check on read (for auto-incremented sequential read). 137 * True only for small page devices; large page devices do not support 138 * autoincrement. 139 */ 140#define NAND_NEED_READRDY 0x00000100 141 142/* Chip does not allow subpage writes */ 143#define NAND_NO_SUBPAGE_WRITE 0x00000200 144 145/* Device is one of 'new' xD cards that expose fake nand command set */ 146#define NAND_BROKEN_XD 0x00000400 147 148/* Device behaves just like nand, but is readonly */ 149#define NAND_ROM 0x00000800 150 151/* Device supports subpage reads */ 152#define NAND_SUBPAGE_READ 0x00001000 153 154/* 155 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated 156 * patterns. 157 */ 158#define NAND_NEED_SCRAMBLING 0x00002000 159 160/* Device needs 3rd row address cycle */ 161#define NAND_ROW_ADDR_3 0x00004000 162 163/* Options valid for Samsung large page devices */ 164#define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG 165 166/* Macros to identify the above */ 167#define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ)) 168 169/* 170 * There are different places where the manufacturer stores the factory bad 171 * block markers. 172 * 173 * Position within the block: Each of these pages needs to be checked for a 174 * bad block marking pattern. 175 */ 176#define NAND_BBM_FIRSTPAGE 0x01000000 177#define NAND_BBM_SECONDPAGE 0x02000000 178#define NAND_BBM_LASTPAGE 0x04000000 179 180/* Position within the OOB data of the page */ 181#define NAND_BBM_POS_SMALL 5 182#define NAND_BBM_POS_LARGE 0 183 184/* Non chip related options */ 185/* This option skips the bbt scan during initialization. */ 186#define NAND_SKIP_BBTSCAN 0x00010000 187/* Chip may not exist, so silence any errors in scan */ 188#define NAND_SCAN_SILENT_NODEV 0x00040000 189/* 190 * Autodetect nand buswidth with readid/onfi. 191 * This suppose the driver will configure the hardware in 8 bits mode 192 * when calling nand_scan_ident, and update its configuration 193 * before calling nand_scan_tail. 194 */ 195#define NAND_BUSWIDTH_AUTO 0x00080000 196/* 197 * This option could be defined by controller drivers to protect against 198 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers 199 */ 200#define NAND_USE_BOUNCE_BUFFER 0x00100000 201 202/* 203 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying 204 * on the default ->cmdfunc() implementation, you may want to let the core 205 * handle the tCCS delay which is required when a column change (RNDIN or 206 * RNDOUT) is requested. 207 * If your controller already takes care of this delay, you don't need to set 208 * this flag. 209 */ 210#define NAND_WAIT_TCCS 0x00200000 211 212/* 213 * Whether the NAND chip is a boot medium. Drivers might use this information 214 * to select ECC algorithms supported by the boot ROM or similar restrictions. 215 */ 216#define NAND_IS_BOOT_MEDIUM 0x00400000 217 218/* 219 * Do not try to tweak the timings at runtime. This is needed when the 220 * controller initializes the timings on itself or when it relies on 221 * configuration done by the bootloader. 222 */ 223#define NAND_KEEP_TIMINGS 0x00800000 224 225/* Cell info constants */ 226#define NAND_CI_CHIPNR_MSK 0x03 227#define NAND_CI_CELLTYPE_MSK 0x0C 228#define NAND_CI_CELLTYPE_SHIFT 2 229 230/** 231 * struct nand_parameters - NAND generic parameters from the parameter page 232 * @model: Model name 233 * @supports_set_get_features: The NAND chip supports setting/getting features 234 * @set_feature_list: Bitmap of features that can be set 235 * @get_feature_list: Bitmap of features that can be get 236 * @onfi: ONFI specific parameters 237 */ 238struct nand_parameters { 239 /* Generic parameters */ 240 const char *model; 241 bool supports_set_get_features; 242 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER); 243 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER); 244 245 /* ONFI parameters */ 246 struct onfi_params *onfi; 247}; 248 249/* The maximum expected count of bytes in the NAND ID sequence */ 250#define NAND_MAX_ID_LEN 8 251 252/** 253 * struct nand_id - NAND id structure 254 * @data: buffer containing the id bytes. 255 * @len: ID length. 256 */ 257struct nand_id { 258 u8 data[NAND_MAX_ID_LEN]; 259 int len; 260}; 261 262/** 263 * struct nand_ecc_step_info - ECC step information of ECC engine 264 * @stepsize: data bytes per ECC step 265 * @strengths: array of supported strengths 266 * @nstrengths: number of supported strengths 267 */ 268struct nand_ecc_step_info { 269 int stepsize; 270 const int *strengths; 271 int nstrengths; 272}; 273 274/** 275 * struct nand_ecc_caps - capability of ECC engine 276 * @stepinfos: array of ECC step information 277 * @nstepinfos: number of ECC step information 278 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step 279 */ 280struct nand_ecc_caps { 281 const struct nand_ecc_step_info *stepinfos; 282 int nstepinfos; 283 int (*calc_ecc_bytes)(int step_size, int strength); 284}; 285 286/* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */ 287#define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \ 288static const int __name##_strengths[] = { __VA_ARGS__ }; \ 289static const struct nand_ecc_step_info __name##_stepinfo = { \ 290 .stepsize = __step, \ 291 .strengths = __name##_strengths, \ 292 .nstrengths = ARRAY_SIZE(__name##_strengths), \ 293}; \ 294static const struct nand_ecc_caps __name = { \ 295 .stepinfos = &__name##_stepinfo, \ 296 .nstepinfos = 1, \ 297 .calc_ecc_bytes = __calc, \ 298} 299 300/** 301 * struct nand_ecc_ctrl - Control structure for ECC 302 * @mode: ECC mode 303 * @algo: ECC algorithm 304 * @steps: number of ECC steps per page 305 * @size: data bytes per ECC step 306 * @bytes: ECC bytes per step 307 * @strength: max number of correctible bits per ECC step 308 * @total: total number of ECC bytes per page 309 * @prepad: padding information for syndrome based ECC generators 310 * @postpad: padding information for syndrome based ECC generators 311 * @options: ECC specific options (see NAND_ECC_XXX flags defined above) 312 * @priv: pointer to private ECC control data 313 * @calc_buf: buffer for calculated ECC, size is oobsize. 314 * @code_buf: buffer for ECC read from flash, size is oobsize. 315 * @hwctl: function to control hardware ECC generator. Must only 316 * be provided if an hardware ECC is available 317 * @calculate: function for ECC calculation or readback from ECC hardware 318 * @correct: function for ECC correction, matching to ECC generator (sw/hw). 319 * Should return a positive number representing the number of 320 * corrected bitflips, -EBADMSG if the number of bitflips exceed 321 * ECC strength, or any other error code if the error is not 322 * directly related to correction. 323 * If -EBADMSG is returned the input buffers should be left 324 * untouched. 325 * @read_page_raw: function to read a raw page without ECC. This function 326 * should hide the specific layout used by the ECC 327 * controller and always return contiguous in-band and 328 * out-of-band data even if they're not stored 329 * contiguously on the NAND chip (e.g. 330 * NAND_ECC_HW_SYNDROME interleaves in-band and 331 * out-of-band data). 332 * @write_page_raw: function to write a raw page without ECC. This function 333 * should hide the specific layout used by the ECC 334 * controller and consider the passed data as contiguous 335 * in-band and out-of-band data. ECC controller is 336 * responsible for doing the appropriate transformations 337 * to adapt to its specific layout (e.g. 338 * NAND_ECC_HW_SYNDROME interleaves in-band and 339 * out-of-band data). 340 * @read_page: function to read a page according to the ECC generator 341 * requirements; returns maximum number of bitflips corrected in 342 * any single ECC step, -EIO hw error 343 * @read_subpage: function to read parts of the page covered by ECC; 344 * returns same as read_page() 345 * @write_subpage: function to write parts of the page covered by ECC. 346 * @write_page: function to write a page according to the ECC generator 347 * requirements. 348 * @write_oob_raw: function to write chip OOB data without ECC 349 * @read_oob_raw: function to read chip OOB data without ECC 350 * @read_oob: function to read chip OOB data 351 * @write_oob: function to write chip OOB data 352 */ 353struct nand_ecc_ctrl { 354 nand_ecc_modes_t mode; 355 enum nand_ecc_algo algo; 356 int steps; 357 int size; 358 int bytes; 359 int total; 360 int strength; 361 int prepad; 362 int postpad; 363 unsigned int options; 364 void *priv; 365 u8 *calc_buf; 366 u8 *code_buf; 367 void (*hwctl)(struct nand_chip *chip, int mode); 368 int (*calculate)(struct nand_chip *chip, const uint8_t *dat, 369 uint8_t *ecc_code); 370 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc, 371 uint8_t *calc_ecc); 372 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf, 373 int oob_required, int page); 374 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf, 375 int oob_required, int page); 376 int (*read_page)(struct nand_chip *chip, uint8_t *buf, 377 int oob_required, int page); 378 int (*read_subpage)(struct nand_chip *chip, uint32_t offs, 379 uint32_t len, uint8_t *buf, int page); 380 int (*write_subpage)(struct nand_chip *chip, uint32_t offset, 381 uint32_t data_len, const uint8_t *data_buf, 382 int oob_required, int page); 383 int (*write_page)(struct nand_chip *chip, const uint8_t *buf, 384 int oob_required, int page); 385 int (*write_oob_raw)(struct nand_chip *chip, int page); 386 int (*read_oob_raw)(struct nand_chip *chip, int page); 387 int (*read_oob)(struct nand_chip *chip, int page); 388 int (*write_oob)(struct nand_chip *chip, int page); 389}; 390 391/** 392 * struct nand_sdr_timings - SDR NAND chip timings 393 * 394 * This struct defines the timing requirements of a SDR NAND chip. 395 * These information can be found in every NAND datasheets and the timings 396 * meaning are described in the ONFI specifications: 397 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing 398 * Parameters) 399 * 400 * All these timings are expressed in picoseconds. 401 * 402 * @tBERS_max: Block erase time 403 * @tCCS_min: Change column setup time 404 * @tPROG_max: Page program time 405 * @tR_max: Page read time 406 * @tALH_min: ALE hold time 407 * @tADL_min: ALE to data loading time 408 * @tALS_min: ALE setup time 409 * @tAR_min: ALE to RE# delay 410 * @tCEA_max: CE# access time 411 * @tCEH_min: CE# high hold time 412 * @tCH_min: CE# hold time 413 * @tCHZ_max: CE# high to output hi-Z 414 * @tCLH_min: CLE hold time 415 * @tCLR_min: CLE to RE# delay 416 * @tCLS_min: CLE setup time 417 * @tCOH_min: CE# high to output hold 418 * @tCS_min: CE# setup time 419 * @tDH_min: Data hold time 420 * @tDS_min: Data setup time 421 * @tFEAT_max: Busy time for Set Features and Get Features 422 * @tIR_min: Output hi-Z to RE# low 423 * @tITC_max: Interface and Timing Mode Change time 424 * @tRC_min: RE# cycle time 425 * @tREA_max: RE# access time 426 * @tREH_min: RE# high hold time 427 * @tRHOH_min: RE# high to output hold 428 * @tRHW_min: RE# high to WE# low 429 * @tRHZ_max: RE# high to output hi-Z 430 * @tRLOH_min: RE# low to output hold 431 * @tRP_min: RE# pulse width 432 * @tRR_min: Ready to RE# low (data only) 433 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the 434 * rising edge of R/B#. 435 * @tWB_max: WE# high to SR[6] low 436 * @tWC_min: WE# cycle time 437 * @tWH_min: WE# high hold time 438 * @tWHR_min: WE# high to RE# low 439 * @tWP_min: WE# pulse width 440 * @tWW_min: WP# transition to WE# low 441 */ 442struct nand_sdr_timings { 443 u64 tBERS_max; 444 u32 tCCS_min; 445 u64 tPROG_max; 446 u64 tR_max; 447 u32 tALH_min; 448 u32 tADL_min; 449 u32 tALS_min; 450 u32 tAR_min; 451 u32 tCEA_max; 452 u32 tCEH_min; 453 u32 tCH_min; 454 u32 tCHZ_max; 455 u32 tCLH_min; 456 u32 tCLR_min; 457 u32 tCLS_min; 458 u32 tCOH_min; 459 u32 tCS_min; 460 u32 tDH_min; 461 u32 tDS_min; 462 u32 tFEAT_max; 463 u32 tIR_min; 464 u32 tITC_max; 465 u32 tRC_min; 466 u32 tREA_max; 467 u32 tREH_min; 468 u32 tRHOH_min; 469 u32 tRHW_min; 470 u32 tRHZ_max; 471 u32 tRLOH_min; 472 u32 tRP_min; 473 u32 tRR_min; 474 u64 tRST_max; 475 u32 tWB_max; 476 u32 tWC_min; 477 u32 tWH_min; 478 u32 tWHR_min; 479 u32 tWP_min; 480 u32 tWW_min; 481}; 482 483/** 484 * enum nand_data_interface_type - NAND interface timing type 485 * @NAND_SDR_IFACE: Single Data Rate interface 486 */ 487enum nand_data_interface_type { 488 NAND_SDR_IFACE, 489}; 490 491/** 492 * struct nand_data_interface - NAND interface timing 493 * @type: type of the timing 494 * @timings: The timing, type according to @type 495 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE. 496 */ 497struct nand_data_interface { 498 enum nand_data_interface_type type; 499 union { 500 struct nand_sdr_timings sdr; 501 } timings; 502}; 503 504/** 505 * nand_get_sdr_timings - get SDR timing from data interface 506 * @conf: The data interface 507 */ 508static inline const struct nand_sdr_timings * 509nand_get_sdr_timings(const struct nand_data_interface *conf) 510{ 511 if (conf->type != NAND_SDR_IFACE) 512 return ERR_PTR(-EINVAL); 513 514 return &conf->timings.sdr; 515} 516 517/** 518 * struct nand_op_cmd_instr - Definition of a command instruction 519 * @opcode: the command to issue in one cycle 520 */ 521struct nand_op_cmd_instr { 522 u8 opcode; 523}; 524 525/** 526 * struct nand_op_addr_instr - Definition of an address instruction 527 * @naddrs: length of the @addrs array 528 * @addrs: array containing the address cycles to issue 529 */ 530struct nand_op_addr_instr { 531 unsigned int naddrs; 532 const u8 *addrs; 533}; 534 535/** 536 * struct nand_op_data_instr - Definition of a data instruction 537 * @len: number of data bytes to move 538 * @buf: buffer to fill 539 * @buf.in: buffer to fill when reading from the NAND chip 540 * @buf.out: buffer to read from when writing to the NAND chip 541 * @force_8bit: force 8-bit access 542 * 543 * Please note that "in" and "out" are inverted from the ONFI specification 544 * and are from the controller perspective, so a "in" is a read from the NAND 545 * chip while a "out" is a write to the NAND chip. 546 */ 547struct nand_op_data_instr { 548 unsigned int len; 549 union { 550 void *in; 551 const void *out; 552 } buf; 553 bool force_8bit; 554}; 555 556/** 557 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction 558 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms 559 */ 560struct nand_op_waitrdy_instr { 561 unsigned int timeout_ms; 562}; 563 564/** 565 * enum nand_op_instr_type - Definition of all instruction types 566 * @NAND_OP_CMD_INSTR: command instruction 567 * @NAND_OP_ADDR_INSTR: address instruction 568 * @NAND_OP_DATA_IN_INSTR: data in instruction 569 * @NAND_OP_DATA_OUT_INSTR: data out instruction 570 * @NAND_OP_WAITRDY_INSTR: wait ready instruction 571 */ 572enum nand_op_instr_type { 573 NAND_OP_CMD_INSTR, 574 NAND_OP_ADDR_INSTR, 575 NAND_OP_DATA_IN_INSTR, 576 NAND_OP_DATA_OUT_INSTR, 577 NAND_OP_WAITRDY_INSTR, 578}; 579 580/** 581 * struct nand_op_instr - Instruction object 582 * @type: the instruction type 583 * @ctx: extra data associated to the instruction. You'll have to use the 584 * appropriate element depending on @type 585 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR 586 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR 587 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR 588 * or %NAND_OP_DATA_OUT_INSTR 589 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR 590 * @delay_ns: delay the controller should apply after the instruction has been 591 * issued on the bus. Most modern controllers have internal timings 592 * control logic, and in this case, the controller driver can ignore 593 * this field. 594 */ 595struct nand_op_instr { 596 enum nand_op_instr_type type; 597 union { 598 struct nand_op_cmd_instr cmd; 599 struct nand_op_addr_instr addr; 600 struct nand_op_data_instr data; 601 struct nand_op_waitrdy_instr waitrdy; 602 } ctx; 603 unsigned int delay_ns; 604}; 605 606/* 607 * Special handling must be done for the WAITRDY timeout parameter as it usually 608 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or 609 * tBERS (during an erase) which all of them are u64 values that cannot be 610 * divided by usual kernel macros and must be handled with the special 611 * DIV_ROUND_UP_ULL() macro. 612 * 613 * Cast to type of dividend is needed here to guarantee that the result won't 614 * be an unsigned long long when the dividend is an unsigned long (or smaller), 615 * which is what the compiler does when it sees ternary operator with 2 616 * different return types (picks the largest type to make sure there's no 617 * loss). 618 */ 619#define __DIVIDE(dividend, divisor) ({ \ 620 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \ 621 DIV_ROUND_UP(dividend, divisor) : \ 622 DIV_ROUND_UP_ULL(dividend, divisor)); \ 623 }) 624#define PSEC_TO_NSEC(x) __DIVIDE(x, 1000) 625#define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000) 626 627#define NAND_OP_CMD(id, ns) \ 628 { \ 629 .type = NAND_OP_CMD_INSTR, \ 630 .ctx.cmd.opcode = id, \ 631 .delay_ns = ns, \ 632 } 633 634#define NAND_OP_ADDR(ncycles, cycles, ns) \ 635 { \ 636 .type = NAND_OP_ADDR_INSTR, \ 637 .ctx.addr = { \ 638 .naddrs = ncycles, \ 639 .addrs = cycles, \ 640 }, \ 641 .delay_ns = ns, \ 642 } 643 644#define NAND_OP_DATA_IN(l, b, ns) \ 645 { \ 646 .type = NAND_OP_DATA_IN_INSTR, \ 647 .ctx.data = { \ 648 .len = l, \ 649 .buf.in = b, \ 650 .force_8bit = false, \ 651 }, \ 652 .delay_ns = ns, \ 653 } 654 655#define NAND_OP_DATA_OUT(l, b, ns) \ 656 { \ 657 .type = NAND_OP_DATA_OUT_INSTR, \ 658 .ctx.data = { \ 659 .len = l, \ 660 .buf.out = b, \ 661 .force_8bit = false, \ 662 }, \ 663 .delay_ns = ns, \ 664 } 665 666#define NAND_OP_8BIT_DATA_IN(l, b, ns) \ 667 { \ 668 .type = NAND_OP_DATA_IN_INSTR, \ 669 .ctx.data = { \ 670 .len = l, \ 671 .buf.in = b, \ 672 .force_8bit = true, \ 673 }, \ 674 .delay_ns = ns, \ 675 } 676 677#define NAND_OP_8BIT_DATA_OUT(l, b, ns) \ 678 { \ 679 .type = NAND_OP_DATA_OUT_INSTR, \ 680 .ctx.data = { \ 681 .len = l, \ 682 .buf.out = b, \ 683 .force_8bit = true, \ 684 }, \ 685 .delay_ns = ns, \ 686 } 687 688#define NAND_OP_WAIT_RDY(tout_ms, ns) \ 689 { \ 690 .type = NAND_OP_WAITRDY_INSTR, \ 691 .ctx.waitrdy.timeout_ms = tout_ms, \ 692 .delay_ns = ns, \ 693 } 694 695/** 696 * struct nand_subop - a sub operation 697 * @instrs: array of instructions 698 * @ninstrs: length of the @instrs array 699 * @first_instr_start_off: offset to start from for the first instruction 700 * of the sub-operation 701 * @last_instr_end_off: offset to end at (excluded) for the last instruction 702 * of the sub-operation 703 * 704 * Both @first_instr_start_off and @last_instr_end_off only apply to data or 705 * address instructions. 706 * 707 * When an operation cannot be handled as is by the NAND controller, it will 708 * be split by the parser into sub-operations which will be passed to the 709 * controller driver. 710 */ 711struct nand_subop { 712 const struct nand_op_instr *instrs; 713 unsigned int ninstrs; 714 unsigned int first_instr_start_off; 715 unsigned int last_instr_end_off; 716}; 717 718unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop, 719 unsigned int op_id); 720unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop, 721 unsigned int op_id); 722unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop, 723 unsigned int op_id); 724unsigned int nand_subop_get_data_len(const struct nand_subop *subop, 725 unsigned int op_id); 726 727/** 728 * struct nand_op_parser_addr_constraints - Constraints for address instructions 729 * @maxcycles: maximum number of address cycles the controller can issue in a 730 * single step 731 */ 732struct nand_op_parser_addr_constraints { 733 unsigned int maxcycles; 734}; 735 736/** 737 * struct nand_op_parser_data_constraints - Constraints for data instructions 738 * @maxlen: maximum data length that the controller can handle in a single step 739 */ 740struct nand_op_parser_data_constraints { 741 unsigned int maxlen; 742}; 743 744/** 745 * struct nand_op_parser_pattern_elem - One element of a pattern 746 * @type: the instructuction type 747 * @optional: whether this element of the pattern is optional or mandatory 748 * @ctx: address or data constraint 749 * @ctx.addr: address constraint (number of cycles) 750 * @ctx.data: data constraint (data length) 751 */ 752struct nand_op_parser_pattern_elem { 753 enum nand_op_instr_type type; 754 bool optional; 755 union { 756 struct nand_op_parser_addr_constraints addr; 757 struct nand_op_parser_data_constraints data; 758 } ctx; 759}; 760 761#define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \ 762 { \ 763 .type = NAND_OP_CMD_INSTR, \ 764 .optional = _opt, \ 765 } 766 767#define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \ 768 { \ 769 .type = NAND_OP_ADDR_INSTR, \ 770 .optional = _opt, \ 771 .ctx.addr.maxcycles = _maxcycles, \ 772 } 773 774#define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \ 775 { \ 776 .type = NAND_OP_DATA_IN_INSTR, \ 777 .optional = _opt, \ 778 .ctx.data.maxlen = _maxlen, \ 779 } 780 781#define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \ 782 { \ 783 .type = NAND_OP_DATA_OUT_INSTR, \ 784 .optional = _opt, \ 785 .ctx.data.maxlen = _maxlen, \ 786 } 787 788#define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \ 789 { \ 790 .type = NAND_OP_WAITRDY_INSTR, \ 791 .optional = _opt, \ 792 } 793 794/** 795 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor 796 * @elems: array of pattern elements 797 * @nelems: number of pattern elements in @elems array 798 * @exec: the function that will issue a sub-operation 799 * 800 * A pattern is a list of elements, each element reprensenting one instruction 801 * with its constraints. The pattern itself is used by the core to match NAND 802 * chip operation with NAND controller operations. 803 * Once a match between a NAND controller operation pattern and a NAND chip 804 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec() 805 * hook is called so that the controller driver can issue the operation on the 806 * bus. 807 * 808 * Controller drivers should declare as many patterns as they support and pass 809 * this list of patterns (created with the help of the following macro) to 810 * the nand_op_parser_exec_op() helper. 811 */ 812struct nand_op_parser_pattern { 813 const struct nand_op_parser_pattern_elem *elems; 814 unsigned int nelems; 815 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop); 816}; 817 818#define NAND_OP_PARSER_PATTERN(_exec, ...) \ 819 { \ 820 .exec = _exec, \ 821 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \ 822 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \ 823 sizeof(struct nand_op_parser_pattern_elem), \ 824 } 825 826/** 827 * struct nand_op_parser - NAND controller operation parser descriptor 828 * @patterns: array of supported patterns 829 * @npatterns: length of the @patterns array 830 * 831 * The parser descriptor is just an array of supported patterns which will be 832 * iterated by nand_op_parser_exec_op() everytime it tries to execute an 833 * NAND operation (or tries to determine if a specific operation is supported). 834 * 835 * It is worth mentioning that patterns will be tested in their declaration 836 * order, and the first match will be taken, so it's important to order patterns 837 * appropriately so that simple/inefficient patterns are placed at the end of 838 * the list. Usually, this is where you put single instruction patterns. 839 */ 840struct nand_op_parser { 841 const struct nand_op_parser_pattern *patterns; 842 unsigned int npatterns; 843}; 844 845#define NAND_OP_PARSER(...) \ 846 { \ 847 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \ 848 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \ 849 sizeof(struct nand_op_parser_pattern), \ 850 } 851 852/** 853 * struct nand_operation - NAND operation descriptor 854 * @cs: the CS line to select for this NAND operation 855 * @instrs: array of instructions to execute 856 * @ninstrs: length of the @instrs array 857 * 858 * The actual operation structure that will be passed to chip->exec_op(). 859 */ 860struct nand_operation { 861 unsigned int cs; 862 const struct nand_op_instr *instrs; 863 unsigned int ninstrs; 864}; 865 866#define NAND_OPERATION(_cs, _instrs) \ 867 { \ 868 .cs = _cs, \ 869 .instrs = _instrs, \ 870 .ninstrs = ARRAY_SIZE(_instrs), \ 871 } 872 873int nand_op_parser_exec_op(struct nand_chip *chip, 874 const struct nand_op_parser *parser, 875 const struct nand_operation *op, bool check_only); 876 877/** 878 * struct nand_controller_ops - Controller operations 879 * 880 * @attach_chip: this method is called after the NAND detection phase after 881 * flash ID and MTD fields such as erase size, page size and OOB 882 * size have been set up. ECC requirements are available if 883 * provided by the NAND chip or device tree. Typically used to 884 * choose the appropriate ECC configuration and allocate 885 * associated resources. 886 * This hook is optional. 887 * @detach_chip: free all resources allocated/claimed in 888 * nand_controller_ops->attach_chip(). 889 * This hook is optional. 890 * @exec_op: controller specific method to execute NAND operations. 891 * This method replaces chip->legacy.cmdfunc(), 892 * chip->legacy.{read,write}_{buf,byte,word}(), 893 * chip->legacy.dev_ready() and chip->legacy.waifunc(). 894 * @setup_data_interface: setup the data interface and timing. If 895 * chipnr is set to %NAND_DATA_IFACE_CHECK_ONLY this 896 * means the configuration should not be applied but 897 * only checked. 898 * This hook is optional. 899 */ 900struct nand_controller_ops { 901 int (*attach_chip)(struct nand_chip *chip); 902 void (*detach_chip)(struct nand_chip *chip); 903 int (*exec_op)(struct nand_chip *chip, 904 const struct nand_operation *op, 905 bool check_only); 906 int (*setup_data_interface)(struct nand_chip *chip, int chipnr, 907 const struct nand_data_interface *conf); 908}; 909 910/** 911 * struct nand_controller - Structure used to describe a NAND controller 912 * 913 * @lock: lock used to serialize accesses to the NAND controller 914 * @ops: NAND controller operations. 915 */ 916struct nand_controller { 917 struct mutex lock; 918 const struct nand_controller_ops *ops; 919}; 920 921static inline void nand_controller_init(struct nand_controller *nfc) 922{ 923 mutex_init(&nfc->lock); 924} 925 926/** 927 * struct nand_legacy - NAND chip legacy fields/hooks 928 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device 929 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device 930 * @select_chip: select/deselect a specific target/die 931 * @read_byte: read one byte from the chip 932 * @write_byte: write a single byte to the chip on the low 8 I/O lines 933 * @write_buf: write data from the buffer to the chip 934 * @read_buf: read data from the chip into the buffer 935 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used 936 * to write command and address 937 * @cmdfunc: hardware specific function for writing commands to the chip. 938 * @dev_ready: hardware specific function for accessing device ready/busy line. 939 * If set to NULL no access to ready/busy is available and the 940 * ready/busy information is read from the chip status register. 941 * @waitfunc: hardware specific function for wait on ready. 942 * @block_bad: check if a block is bad, using OOB markers 943 * @block_markbad: mark a block bad 944 * @set_features: set the NAND chip features 945 * @get_features: get the NAND chip features 946 * @chip_delay: chip dependent delay for transferring data from array to read 947 * regs (tR). 948 * @dummy_controller: dummy controller implementation for drivers that can 949 * only control a single chip 950 * 951 * If you look at this structure you're already wrong. These fields/hooks are 952 * all deprecated. 953 */ 954struct nand_legacy { 955 void __iomem *IO_ADDR_R; 956 void __iomem *IO_ADDR_W; 957 void (*select_chip)(struct nand_chip *chip, int cs); 958 u8 (*read_byte)(struct nand_chip *chip); 959 void (*write_byte)(struct nand_chip *chip, u8 byte); 960 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len); 961 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len); 962 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl); 963 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column, 964 int page_addr); 965 int (*dev_ready)(struct nand_chip *chip); 966 int (*waitfunc)(struct nand_chip *chip); 967 int (*block_bad)(struct nand_chip *chip, loff_t ofs); 968 int (*block_markbad)(struct nand_chip *chip, loff_t ofs); 969 int (*set_features)(struct nand_chip *chip, int feature_addr, 970 u8 *subfeature_para); 971 int (*get_features)(struct nand_chip *chip, int feature_addr, 972 u8 *subfeature_para); 973 int chip_delay; 974 struct nand_controller dummy_controller; 975}; 976 977/** 978 * struct nand_chip - NAND Private Flash Chip Data 979 * @base: Inherit from the generic NAND device 980 * @legacy: All legacy fields/hooks. If you develop a new driver, 981 * don't even try to use any of these fields/hooks, and if 982 * you're modifying an existing driver that is using those 983 * fields/hooks, you should consider reworking the driver 984 * avoid using them. 985 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for 986 * setting the read-retry mode. Mostly needed for MLC NAND. 987 * @ecc: [BOARDSPECIFIC] ECC control structure 988 * @buf_align: minimum buffer alignment required by a platform 989 * @oob_poi: "poison value buffer," used for laying out OOB data 990 * before writing 991 * @page_shift: [INTERN] number of address bits in a page (column 992 * address bits). 993 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock 994 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry 995 * @chip_shift: [INTERN] number of address bits in one chip 996 * @options: [BOARDSPECIFIC] various chip options. They can partly 997 * be set to inform nand_scan about special functionality. 998 * See the defines for further explanation. 999 * @bbt_options: [INTERN] bad block specific options. All options used 1000 * here must come from bbm.h. By default, these options
1001 * will be copied to the appropriate nand_bbt_descr's. 1002 * @badblockpos: [INTERN] position of the bad block marker in the oob 1003 * area. 1004 * @badblockbits: [INTERN] minimum number of set bits in a good block's 1005 * bad block marker position; i.e., BBM == 11110111b is 1006 * not bad when badblockbits == 7 1007 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is 1008 * set to the actually used ONFI mode if the chip is 1009 * ONFI compliant or deduced from the datasheet if 1010 * the NAND chip is not ONFI compliant. 1011 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1 1012 * @data_buf: [INTERN] buffer for data, size is (page size + oobsize). 1013 * @pagecache: Structure containing page cache related fields 1014 * @pagecache.bitflips: Number of bitflips of the cached page 1015 * @pagecache.page: Page number currently in the cache. -1 means no page is 1016 * currently cached 1017 * @subpagesize: [INTERN] holds the subpagesize 1018 * @id: [INTERN] holds NAND ID 1019 * @parameters: [INTERN] holds generic parameters under an easily 1020 * readable form. 1021 * @data_interface: [INTERN] NAND interface timing information 1022 * @cur_cs: currently selected target. -1 means no target selected, 1023 * otherwise we should always have cur_cs >= 0 && 1024 * cur_cs < nanddev_ntargets(). NAND Controller drivers 1025 * should not modify this value, but they're allowed to 1026 * read it. 1027 * @read_retries: [INTERN] the number of read retry modes supported 1028 * @lock: lock protecting the suspended field. Also used to 1029 * serialize accesses to the NAND device. 1030 * @suspended: set to 1 when the device is suspended, 0 when it's not. 1031 * @bbt: [INTERN] bad block table pointer 1032 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash 1033 * lookup. 1034 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 1035 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial 1036 * bad block scan. 1037 * @controller: [REPLACEABLE] a pointer to a hardware controller 1038 * structure which is shared among multiple independent 1039 * devices. 1040 * @priv: [OPTIONAL] pointer to private chip data 1041 * @manufacturer: [INTERN] Contains manufacturer information 1042 * @manufacturer.desc: [INTERN] Contains manufacturer's description 1043 * @manufacturer.priv: [INTERN] Contains manufacturer private information 1044 */ 1045 1046struct nand_chip { 1047 struct nand_device base; 1048 1049 struct nand_legacy legacy; 1050 1051 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode); 1052 1053 unsigned int options; 1054 unsigned int bbt_options; 1055 1056 int page_shift; 1057 int phys_erase_shift; 1058 int bbt_erase_shift; 1059 int chip_shift; 1060 int pagemask; 1061 u8 *data_buf; 1062 1063 struct { 1064 unsigned int bitflips; 1065 int page; 1066 } pagecache; 1067 1068 int subpagesize; 1069 int onfi_timing_mode_default; 1070 unsigned int badblockpos; 1071 int badblockbits; 1072 1073 struct nand_id id; 1074 struct nand_parameters parameters; 1075 1076 struct nand_data_interface data_interface; 1077 1078 int cur_cs; 1079 1080 int read_retries; 1081 1082 struct mutex lock; 1083 unsigned int suspended : 1; 1084 1085 uint8_t *oob_poi; 1086 struct nand_controller *controller; 1087 1088 struct nand_ecc_ctrl ecc; 1089 unsigned long buf_align; 1090 1091 uint8_t *bbt; 1092 struct nand_bbt_descr *bbt_td; 1093 struct nand_bbt_descr *bbt_md; 1094 1095 struct nand_bbt_descr *badblock_pattern; 1096 1097 void *priv; 1098 1099 struct { 1100 const struct nand_manufacturer *desc; 1101 void *priv; 1102 } manufacturer; 1103}; 1104 1105extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1106extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1107 1108static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1109{ 1110 return container_of(mtd, struct nand_chip, base.mtd); 1111} 1112 1113static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip) 1114{ 1115 return &chip->base.mtd; 1116} 1117 1118static inline void *nand_get_controller_data(struct nand_chip *chip) 1119{ 1120 return chip->priv; 1121} 1122 1123static inline void nand_set_controller_data(struct nand_chip *chip, void *priv) 1124{ 1125 chip->priv = priv; 1126} 1127 1128static inline void nand_set_manufacturer_data(struct nand_chip *chip, 1129 void *priv) 1130{ 1131 chip->manufacturer.priv = priv; 1132} 1133 1134static inline void *nand_get_manufacturer_data(struct nand_chip *chip) 1135{ 1136 return chip->manufacturer.priv; 1137} 1138 1139static inline void nand_set_flash_node(struct nand_chip *chip, 1140 struct device_node *np) 1141{ 1142 mtd_set_of_node(nand_to_mtd(chip), np); 1143} 1144 1145static inline struct device_node *nand_get_flash_node(struct nand_chip *chip) 1146{ 1147 return mtd_get_of_node(nand_to_mtd(chip)); 1148} 1149 1150/* 1151 * A helper for defining older NAND chips where the second ID byte fully 1152 * defined the chip, including the geometry (chip size, eraseblock size, page 1153 * size). All these chips have 512 bytes NAND page size. 1154 */ 1155#define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \ 1156 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \ 1157 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) } 1158 1159/* 1160 * A helper for defining newer chips which report their page size and 1161 * eraseblock size via the extended ID bytes. 1162 * 1163 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with 1164 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the 1165 * device ID now only represented a particular total chip size (and voltage, 1166 * buswidth), and the page size, eraseblock size, and OOB size could vary while 1167 * using the same device ID. 1168 */ 1169#define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \ 1170 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \ 1171 .options = (opts) } 1172 1173#define NAND_ECC_INFO(_strength, _step) \ 1174 { .strength_ds = (_strength), .step_ds = (_step) } 1175#define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds) 1176#define NAND_ECC_STEP(type) ((type)->ecc.step_ds) 1177 1178/** 1179 * struct nand_flash_dev - NAND Flash Device ID Structure 1180 * @name: a human-readable name of the NAND chip 1181 * @dev_id: the device ID (the second byte of the full chip ID array) 1182 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same 1183 * memory address as ``id[0]``) 1184 * @dev_id: device ID part of the full chip ID array (refers the same memory 1185 * address as ``id[1]``) 1186 * @id: full device ID array 1187 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as 1188 * well as the eraseblock size) is determined from the extended NAND 1189 * chip ID array) 1190 * @chipsize: total chip size in MiB 1191 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0) 1192 * @options: stores various chip bit options 1193 * @id_len: The valid length of the @id. 1194 * @oobsize: OOB size 1195 * @ecc: ECC correctability and step information from the datasheet. 1196 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the 1197 * @ecc_strength_ds in nand_chip{}. 1198 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the 1199 * @ecc_step_ds in nand_chip{}, also from the datasheet. 1200 * For example, the "4bit ECC for each 512Byte" can be set with 1201 * NAND_ECC_INFO(4, 512). 1202 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND 1203 * reset. Should be deduced from timings described 1204 * in the datasheet. 1205 * 1206 */ 1207struct nand_flash_dev { 1208 char *name; 1209 union { 1210 struct { 1211 uint8_t mfr_id; 1212 uint8_t dev_id; 1213 }; 1214 uint8_t id[NAND_MAX_ID_LEN]; 1215 }; 1216 unsigned int pagesize; 1217 unsigned int chipsize; 1218 unsigned int erasesize; 1219 unsigned int options; 1220 uint16_t id_len; 1221 uint16_t oobsize; 1222 struct { 1223 uint16_t strength_ds; 1224 uint16_t step_ds; 1225 } ecc; 1226 int onfi_timing_mode_default; 1227}; 1228 1229int nand_create_bbt(struct nand_chip *chip); 1230 1231/* 1232 * Check if it is a SLC nand. 1233 * The !nand_is_slc() can be used to check the MLC/TLC nand chips. 1234 * We do not distinguish the MLC and TLC now. 1235 */ 1236static inline bool nand_is_slc(struct nand_chip *chip) 1237{ 1238 WARN(nanddev_bits_per_cell(&chip->base) == 0, 1239 "chip->bits_per_cell is used uninitialized\n"); 1240 return nanddev_bits_per_cell(&chip->base) == 1; 1241} 1242 1243/** 1244 * Check if the opcode's address should be sent only on the lower 8 bits 1245 * @command: opcode to check 1246 */ 1247static inline int nand_opcode_8bits(unsigned int command) 1248{ 1249 switch (command) { 1250 case NAND_CMD_READID: 1251 case NAND_CMD_PARAM: 1252 case NAND_CMD_GET_FEATURES: 1253 case NAND_CMD_SET_FEATURES: 1254 return 1; 1255 default: 1256 break; 1257 } 1258 return 0; 1259} 1260 1261int nand_check_erased_ecc_chunk(void *data, int datalen, 1262 void *ecc, int ecclen, 1263 void *extraoob, int extraooblen, 1264 int threshold); 1265 1266int nand_ecc_choose_conf(struct nand_chip *chip, 1267 const struct nand_ecc_caps *caps, int oobavail); 1268 1269/* Default write_oob implementation */ 1270int nand_write_oob_std(struct nand_chip *chip, int page); 1271 1272/* Default read_oob implementation */ 1273int nand_read_oob_std(struct nand_chip *chip, int page); 1274 1275/* Stub used by drivers that do not support GET/SET FEATURES operations */ 1276int nand_get_set_features_notsupp(struct nand_chip *chip, int addr, 1277 u8 *subfeature_param); 1278 1279/* Default read_page_raw implementation */ 1280int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required, 1281 int page); 1282 1283/* Default write_page_raw implementation */ 1284int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf, 1285 int oob_required, int page); 1286 1287/* Reset and initialize a NAND device */ 1288int nand_reset(struct nand_chip *chip, int chipnr); 1289 1290/* NAND operation helpers */ 1291int nand_reset_op(struct nand_chip *chip); 1292int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf, 1293 unsigned int len); 1294int nand_status_op(struct nand_chip *chip, u8 *status); 1295int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock); 1296int nand_read_page_op(struct nand_chip *chip, unsigned int page, 1297 unsigned int offset_in_page, void *buf, unsigned int len); 1298int nand_change_read_column_op(struct nand_chip *chip, 1299 unsigned int offset_in_page, void *buf, 1300 unsigned int len, bool force_8bit); 1301int nand_read_oob_op(struct nand_chip *chip, unsigned int page, 1302 unsigned int offset_in_page, void *buf, unsigned int len); 1303int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page, 1304 unsigned int offset_in_page, const void *buf, 1305 unsigned int len); 1306int nand_prog_page_end_op(struct nand_chip *chip); 1307int nand_prog_page_op(struct nand_chip *chip, unsigned int page, 1308 unsigned int offset_in_page, const void *buf, 1309 unsigned int len); 1310int nand_change_write_column_op(struct nand_chip *chip, 1311 unsigned int offset_in_page, const void *buf, 1312 unsigned int len, bool force_8bit); 1313int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len, 1314 bool force_8bit); 1315int nand_write_data_op(struct nand_chip *chip, const void *buf, 1316 unsigned int len, bool force_8bit); 1317 1318/* Scan and identify a NAND device */ 1319int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips, 1320 struct nand_flash_dev *ids); 1321 1322static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips) 1323{ 1324 return nand_scan_with_ids(chip, max_chips, NULL); 1325} 1326 1327/* Internal helper for board drivers which need to override command function */ 1328void nand_wait_ready(struct nand_chip *chip); 1329 1330/* 1331 * Free resources held by the NAND device, must be called on error after a 1332 * sucessful nand_scan(). 1333 */ 1334void nand_cleanup(struct nand_chip *chip); 1335/* Unregister the MTD device and calls nand_cleanup() */ 1336void nand_release(struct nand_chip *chip); 1337 1338/* 1339 * External helper for controller drivers that have to implement the WAITRDY 1340 * instruction and have no physical pin to check it. 1341 */ 1342int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms); 1343struct gpio_desc; 1344int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod, 1345 unsigned long timeout_ms); 1346 1347/* Select/deselect a NAND target. */ 1348void nand_select_target(struct nand_chip *chip, unsigned int cs); 1349void nand_deselect_target(struct nand_chip *chip); 1350 1351/** 1352 * nand_get_data_buf() - Get the internal page buffer 1353 * @chip: NAND chip object 1354 * 1355 * Returns the pre-allocated page buffer after invalidating the cache. This 1356 * function should be used by drivers that do not want to allocate their own 1357 * bounce buffer and still need such a buffer for specific operations (most 1358 * commonly when reading OOB data only). 1359 * 1360 * Be careful to never call this function in the write/write_oob path, because 1361 * the core may have placed the data to be written out in this buffer. 1362 * 1363 * Return: pointer to the page cache buffer 1364 */ 1365static inline void *nand_get_data_buf(struct nand_chip *chip) 1366{ 1367 chip->pagecache.page = -1; 1368 1369 return chip->data_buf; 1370} 1371 1372#endif /* __LINUX_MTD_RAWNAND_H */ 1373