1/* SPDX-License-Identifier: GPL-2.0-or-later */ 2/* 3 * mv643xx.h - MV-643XX Internal registers definition file. 4 * 5 * Copyright 2002 Momentum Computer, Inc. 6 * Author: Matthew Dharm <mdharm@momenco.com> 7 * Copyright 2002 GALILEO TECHNOLOGY, LTD. 8 */ 9#ifndef __ASM_MV643XX_H 10#define __ASM_MV643XX_H 11 12#include <asm/types.h> 13#include <linux/mv643xx_eth.h> 14#include <linux/mv643xx_i2c.h> 15 16/****************************************/ 17/* Processor Address Space */ 18/****************************************/ 19 20/* DDR SDRAM BAR and size registers */ 21 22#define MV64340_CS_0_BASE_ADDR 0x008 23#define MV64340_CS_0_SIZE 0x010 24#define MV64340_CS_1_BASE_ADDR 0x208 25#define MV64340_CS_1_SIZE 0x210 26#define MV64340_CS_2_BASE_ADDR 0x018 27#define MV64340_CS_2_SIZE 0x020 28#define MV64340_CS_3_BASE_ADDR 0x218 29#define MV64340_CS_3_SIZE 0x220 30 31/* Devices BAR and size registers */ 32 33#define MV64340_DEV_CS0_BASE_ADDR 0x028 34#define MV64340_DEV_CS0_SIZE 0x030 35#define MV64340_DEV_CS1_BASE_ADDR 0x228 36#define MV64340_DEV_CS1_SIZE 0x230 37#define MV64340_DEV_CS2_BASE_ADDR 0x248 38#define MV64340_DEV_CS2_SIZE 0x250 39#define MV64340_DEV_CS3_BASE_ADDR 0x038 40#define MV64340_DEV_CS3_SIZE 0x040 41#define MV64340_BOOTCS_BASE_ADDR 0x238 42#define MV64340_BOOTCS_SIZE 0x240 43 44/* PCI 0 BAR and size registers */ 45 46#define MV64340_PCI_0_IO_BASE_ADDR 0x048 47#define MV64340_PCI_0_IO_SIZE 0x050 48#define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058 49#define MV64340_PCI_0_MEMORY0_SIZE 0x060 50#define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080 51#define MV64340_PCI_0_MEMORY1_SIZE 0x088 52#define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258 53#define MV64340_PCI_0_MEMORY2_SIZE 0x260 54#define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280 55#define MV64340_PCI_0_MEMORY3_SIZE 0x288 56 57/* PCI 1 BAR and size registers */ 58#define MV64340_PCI_1_IO_BASE_ADDR 0x090 59#define MV64340_PCI_1_IO_SIZE 0x098 60#define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0 61#define MV64340_PCI_1_MEMORY0_SIZE 0x0a8 62#define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0 63#define MV64340_PCI_1_MEMORY1_SIZE 0x0b8 64#define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0 65#define MV64340_PCI_1_MEMORY2_SIZE 0x2a8 66#define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0 67#define MV64340_PCI_1_MEMORY3_SIZE 0x2b8 68 69/* SRAM base address */ 70#define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268 71 72/* internal registers space base address */ 73#define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068 74 75/* Enables the CS , DEV_CS , PCI 0 and PCI 1 76 windows above */ 77#define MV64340_BASE_ADDR_ENABLE 0x278 78 79/****************************************/ 80/* PCI remap registers */ 81/****************************************/ 82 /* PCI 0 */ 83#define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0 84#define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8 85#define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320 86#define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100 87#define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328 88#define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8 89#define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330 90#define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300 91#define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338 92 /* PCI 1 */ 93#define MV64340_PCI_1_IO_ADDR_REMAP 0x108 94#define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110 95#define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340 96#define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118 97#define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348 98#define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310 99#define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350 100#define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318 101#define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358 102 103#define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0 104#define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8 105#define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0 106#define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8 107#define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0 108#define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8 109#define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0 110#define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8 111 112/****************************************/ 113/* CPU Control Registers */ 114/****************************************/ 115 116#define MV64340_CPU_CONFIG 0x000 117#define MV64340_CPU_MODE 0x120 118#define MV64340_CPU_MASTER_CONTROL 0x160 119#define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150 120#define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158 121#define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168 122 123/****************************************/ 124/* SMP RegisterS */ 125/****************************************/ 126 127#define MV64340_SMP_WHO_AM_I 0x200 128#define MV64340_SMP_CPU0_DOORBELL 0x214 129#define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C 130#define MV64340_SMP_CPU1_DOORBELL 0x224 131#define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C 132#define MV64340_SMP_CPU0_DOORBELL_MASK 0x234 133#define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C 134#define MV64340_SMP_SEMAPHOR0 0x244 135#define MV64340_SMP_SEMAPHOR1 0x24c 136#define MV64340_SMP_SEMAPHOR2 0x254 137#define MV64340_SMP_SEMAPHOR3 0x25c 138#define MV64340_SMP_SEMAPHOR4 0x264 139#define MV64340_SMP_SEMAPHOR5 0x26c 140#define MV64340_SMP_SEMAPHOR6 0x274 141#define MV64340_SMP_SEMAPHOR7 0x27c 142 143/****************************************/ 144/* CPU Sync Barrier Register */ 145/****************************************/ 146 147#define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0 148#define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8 149#define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0 150#define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8 151 152/****************************************/ 153/* CPU Access Protect */ 154/****************************************/ 155 156#define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180 157#define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188 158#define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190 159#define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198 160#define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0 161#define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8 162#define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0 163#define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8 164 165 166/****************************************/ 167/* CPU Error Report */ 168/****************************************/ 169 170#define MV64340_CPU_ERROR_ADDR_LOW 0x070 171#define MV64340_CPU_ERROR_ADDR_HIGH 0x078 172#define MV64340_CPU_ERROR_DATA_LOW 0x128 173#define MV64340_CPU_ERROR_DATA_HIGH 0x130 174#define MV64340_CPU_ERROR_PARITY 0x138 175#define MV64340_CPU_ERROR_CAUSE 0x140 176#define MV64340_CPU_ERROR_MASK 0x148 177 178/****************************************/ 179/* CPU Interface Debug Registers */ 180/****************************************/ 181 182#define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360 183#define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368 184#define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370 185#define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378 186#define MV64340_PUNIT_MMASK 0x3e4 187 188/****************************************/ 189/* Integrated SRAM Registers */ 190/****************************************/ 191 192#define MV64340_SRAM_CONFIG 0x380 193#define MV64340_SRAM_TEST_MODE 0X3F4 194#define MV64340_SRAM_ERROR_CAUSE 0x388 195#define MV64340_SRAM_ERROR_ADDR 0x390 196#define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8 197#define MV64340_SRAM_ERROR_DATA_LOW 0x398 198#define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0 199#define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8 200 201/****************************************/ 202/* SDRAM Configuration */ 203/****************************************/ 204 205#define MV64340_SDRAM_CONFIG 0x1400 206#define MV64340_D_UNIT_CONTROL_LOW 0x1404 207#define MV64340_D_UNIT_CONTROL_HIGH 0x1424 208#define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408 209#define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c 210#define MV64340_SDRAM_ADDR_CONTROL 0x1410 211#define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414 212#define MV64340_SDRAM_OPERATION 0x1418 213#define MV64340_SDRAM_MODE 0x141c 214#define MV64340_EXTENDED_DRAM_MODE 0x1420 215#define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430 216#define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434 217#define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438 218#define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0 219#define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4 220 221/****************************************/ 222/* SDRAM Error Report */ 223/****************************************/ 224 225#define MV64340_SDRAM_ERROR_DATA_LOW 0x1444 226#define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440 227#define MV64340_SDRAM_ERROR_ADDR 0x1450 228#define MV64340_SDRAM_RECEIVED_ECC 0x1448 229#define MV64340_SDRAM_CALCULATED_ECC 0x144c 230#define MV64340_SDRAM_ECC_CONTROL 0x1454 231#define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458 232 233/******************************************/ 234/* Controlled Delay Line (CDL) Registers */ 235/******************************************/ 236 237#define MV64340_DFCDL_CONFIG0 0x1480 238#define MV64340_DFCDL_CONFIG1 0x1484 239#define MV64340_DLL_WRITE 0x1488 240#define MV64340_DLL_READ 0x148c 241#define MV64340_SRAM_ADDR 0x1490 242#define MV64340_SRAM_DATA0 0x1494 243#define MV64340_SRAM_DATA1 0x1498 244#define MV64340_SRAM_DATA2 0x149c 245#define MV64340_DFCL_PROBE 0x14a0 246 247/******************************************/ 248/* Debug Registers */ 249/******************************************/ 250 251#define MV64340_DUNIT_DEBUG_LOW 0x1460 252#define MV64340_DUNIT_DEBUG_HIGH 0x1464 253#define MV64340_DUNIT_MMASK 0X1b40 254 255/****************************************/ 256/* Device Parameters */ 257/****************************************/ 258 259#define MV64340_DEVICE_BANK0_PARAMETERS 0x45c 260#define MV64340_DEVICE_BANK1_PARAMETERS 0x460 261#define MV64340_DEVICE_BANK2_PARAMETERS 0x464 262#define MV64340_DEVICE_BANK3_PARAMETERS 0x468 263#define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c 264#define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0 265#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8 266#define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc 267#define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4 268 269/****************************************/ 270/* Device interrupt registers */ 271/****************************************/ 272 273#define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0 274#define MV64340_DEVICE_INTERRUPT_MASK 0x4d4 275#define MV64340_DEVICE_ERROR_ADDR 0x4d8 276#define MV64340_DEVICE_ERROR_DATA 0x4dc 277#define MV64340_DEVICE_ERROR_PARITY 0x4e0 278 279/****************************************/ 280/* Device debug registers */ 281/****************************************/ 282 283#define MV64340_DEVICE_DEBUG_LOW 0x4e4 284#define MV64340_DEVICE_DEBUG_HIGH 0x4e8 285#define MV64340_RUNIT_MMASK 0x4f0 286 287/****************************************/ 288/* PCI Slave Address Decoding registers */ 289/****************************************/ 290 291#define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08 292#define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88 293#define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08 294#define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88 295#define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c 296#define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c 297#define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c 298#define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c 299#define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10 300#define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90 301#define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10 302#define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90 303#define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18 304#define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98 305#define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14 306#define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94 307#define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14 308#define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94 309#define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c 310#define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c 311#define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20 312#define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0 313#define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24 314#define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4 315#define MV64340_PCI_0_CPU_BAR_SIZE 0xd28 316#define MV64340_PCI_1_CPU_BAR_SIZE 0xda8 317#define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00 318#define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80 319#define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c 320#define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c 321#define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c 322#define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc 323#define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48 324#define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8 325#define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48 326#define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8 327#define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c 328#define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc 329#define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c 330#define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc 331#define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04 332#define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84 333#define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08 334#define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88 335#define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C 336#define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C 337#define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10 338#define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90 339#define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50 340#define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0 341#define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50 342#define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0 343#define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58 344#define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8 345#define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54 346#define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4 347#define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54 348#define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4 349#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c 350#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc 351#define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60 352#define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0 353#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64 354#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4 355#define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68 356#define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8 357#define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c 358#define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec 359#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70 360#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0 361#define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74 362#define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4 363#define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00 364#define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80 365#define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38 366#define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8 367#define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c 368#define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc 369#define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40 370#define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0 371#define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44 372#define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4 373#define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48 374#define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8 375 376/***********************************/ 377/* PCI Control Register Map */ 378/***********************************/ 379 380#define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20 381#define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0 382#define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C 383#define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C 384#define MV64340_PCI_0_COMMAND 0xc00 385#define MV64340_PCI_1_COMMAND 0xc80 386#define MV64340_PCI_0_MODE 0xd00 387#define MV64340_PCI_1_MODE 0xd80 388#define MV64340_PCI_0_RETRY 0xc04 389#define MV64340_PCI_1_RETRY 0xc84 390#define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04 391#define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84 392#define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38 393#define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8 394#define MV64340_PCI_0_ARBITER_CONTROL 0x1d00 395#define MV64340_PCI_1_ARBITER_CONTROL 0x1d80 396#define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08 397#define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88 398#define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c 399#define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c 400#define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04 401#define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84 402#define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18 403#define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98 404#define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10 405#define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90 406#define MV64340_PCI_0_P2P_CONFIG 0x1d14 407#define MV64340_PCI_1_P2P_CONFIG 0x1d94 408 409#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00 410#define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04 411#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08 412#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10 413#define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14 414#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18 415#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20 416#define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24 417#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28 418#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30 419#define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34 420#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38 421#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40 422#define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44 423#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48 424#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50 425#define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54 426#define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58 427 428#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80 429#define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84 430#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88 431#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90 432#define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94 433#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98 434#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0 435#define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4 436#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8 437#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0 438#define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4 439#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8 440#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0 441#define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4 442#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8 443#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0 444#define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4 445#define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8 446 447/****************************************/ 448/* PCI Configuration Access Registers */ 449/****************************************/ 450 451#define MV64340_PCI_0_CONFIG_ADDR 0xcf8 452#define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc 453#define MV64340_PCI_1_CONFIG_ADDR 0xc78 454#define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c 455#define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34 456#define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4 457 458/****************************************/ 459/* PCI Error Report Registers */ 460/****************************************/ 461 462#define MV64340_PCI_0_SERR_MASK 0xc28 463#define MV64340_PCI_1_SERR_MASK 0xca8 464#define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40 465#define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0 466#define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44 467#define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4 468#define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48 469#define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8 470#define MV64340_PCI_0_ERROR_COMMAND 0x1d50 471#define MV64340_PCI_1_ERROR_COMMAND 0x1dd0 472#define MV64340_PCI_0_ERROR_CAUSE 0x1d58 473#define MV64340_PCI_1_ERROR_CAUSE 0x1dd8 474#define MV64340_PCI_0_ERROR_MASK 0x1d5c 475#define MV64340_PCI_1_ERROR_MASK 0x1ddc 476 477/****************************************/ 478/* PCI Debug Registers */ 479/****************************************/ 480 481#define MV64340_PCI_0_MMASK 0X1D24 482#define MV64340_PCI_1_MMASK 0X1DA4 483 484/*********************************************/ 485/* PCI Configuration, Function 0, Registers */ 486/*********************************************/ 487 488#define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000 489#define MV64340_PCI_STATUS_AND_COMMAND 0x004 490#define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008 491#define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C 492 493#define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010 494#define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014 495#define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018 496#define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C 497#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020 498#define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024 499#define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c 500#define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030 501#define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034 502#define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C 503 /* capability list */ 504#define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040 505#define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044 506#define MV64340_PCI_VPD_ADDR 0x048 507#define MV64340_PCI_VPD_DATA 0x04c 508#define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050 509#define MV64340_PCI_MSI_MESSAGE_ADDR 0x054 510#define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058 511#define MV64340_PCI_MSI_MESSAGE_DATA 0x05c 512#define MV64340_PCI_X_COMMAND 0x060 513#define MV64340_PCI_X_STATUS 0x064 514#define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068 515 516/***********************************************/ 517/* PCI Configuration, Function 1, Registers */ 518/***********************************************/ 519 520#define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110 521#define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114 522#define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118 523#define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c 524#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120 525#define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124 526 527/***********************************************/ 528/* PCI Configuration, Function 2, Registers */ 529/***********************************************/ 530 531#define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210 532#define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214 533#define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218 534#define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c 535#define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220 536#define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224 537 538/***********************************************/ 539/* PCI Configuration, Function 3, Registers */ 540/***********************************************/ 541 542#define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310 543#define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314 544#define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318 545#define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c 546#define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220 547#define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224 548 549/***********************************************/ 550/* PCI Configuration, Function 4, Registers */ 551/***********************************************/ 552 553#define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410 554#define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414 555#define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418 556#define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c 557#define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420 558#define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424 559 560/****************************************/ 561/* Messaging Unit Registers (I20) */ 562/****************************************/ 563 564#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010 565#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014 566#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018 567#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C 568#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020 569#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024 570#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028 571#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C 572#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030 573#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034 574#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040 575#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044 576#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050 577#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054 578#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060 579#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064 580#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068 581#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C 582#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070 583#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074 584#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8 585#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC 586 587#define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090 588#define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094 589#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098 590#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C 591#define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0 592#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4 593#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8 594#define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC 595#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0 596#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4 597#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0 598#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4 599#define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0 600#define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4 601#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0 602#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4 603#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8 604#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC 605#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0 606#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4 607#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078 608#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C 609 610#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10 611#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14 612#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18 613#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C 614#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20 615#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24 616#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28 617#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C 618#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30 619#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34 620#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40 621#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44 622#define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50 623#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54 624#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60 625#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64 626#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68 627#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C 628#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70 629#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74 630#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8 631#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC 632#define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90 633#define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94 634#define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98 635#define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C 636#define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0 637#define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4 638#define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8 639#define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC 640#define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0 641#define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4 642#define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0 643#define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4 644#define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0 645#define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4 646#define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0 647#define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4 648#define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8 649#define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC 650#define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0 651#define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4 652#define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78 653#define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C 654 655/****************************************/ 656/* Ethernet Unit Registers */ 657/****************************************/ 658 659/*******************************************/ 660/* CUNIT Registers */ 661/*******************************************/ 662 663 /* Address Decoding Register Map */ 664 665#define MV64340_CUNIT_BASE_ADDR_REG0 0xf200 666#define MV64340_CUNIT_BASE_ADDR_REG1 0xf208 667#define MV64340_CUNIT_BASE_ADDR_REG2 0xf210 668#define MV64340_CUNIT_BASE_ADDR_REG3 0xf218 669#define MV64340_CUNIT_SIZE0 0xf204 670#define MV64340_CUNIT_SIZE1 0xf20c 671#define MV64340_CUNIT_SIZE2 0xf214 672#define MV64340_CUNIT_SIZE3 0xf21c 673#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240 674#define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244 675#define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250 676#define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254 677#define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258 678#define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C 679 680 /* Error Report Registers */ 681 682#define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310 683#define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314 684#define MV64340_CUNIT_ERROR_ADDR 0xf318 685 686 /* Cunit Control Registers */ 687 688#define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300 689#define MV64340_CUNIT_CONFIG_REG 0xb40c 690#define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304 691 692 /* Cunit Debug Registers */ 693 694#define MV64340_CUNIT_DEBUG_LOW 0xf340 695#define MV64340_CUNIT_DEBUG_HIGH 0xf344 696#define MV64340_CUNIT_MMASK 0xf380 697 698 /* MPSCs Clocks Routing Registers */ 699 700#define MV64340_MPSC_ROUTING_REG 0xb400 701#define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404 702#define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408 703 704 /* MPSCs Interrupts Registers */ 705 706#define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3)) 707#define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3)) 708 709#define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12)) 710#define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12)) 711#define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12)) 712#define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12)) 713#define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12)) 714#define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12)) 715#define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12)) 716#define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12)) 717#define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12)) 718#define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12)) 719#define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12)) 720#define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12)) 721#define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12)) 722 723 /* MPSC0 Registers */ 724 725 726/***************************************/ 727/* SDMA Registers */ 728/***************************************/ 729 730#define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13)) 731#define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13)) 732#define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13)) 733#define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13)) 734#define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13)) 735 736#define MV64340_SDMA_CAUSE_REG 0xb800 737#define MV64340_SDMA_MASK_REG 0xb880 738 739/* BRG Interrupts */ 740 741#define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3)) 742#define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3)) 743#define MV64340_BRG_CAUSE_REG 0xb834 744#define MV64340_BRG_MASK_REG 0xb8b4 745 746/****************************************/ 747/* DMA Channel Control */ 748/****************************************/ 749 750#define MV64340_DMA_CHANNEL0_CONTROL 0x840 751#define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880 752#define MV64340_DMA_CHANNEL1_CONTROL 0x844 753#define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884 754#define MV64340_DMA_CHANNEL2_CONTROL 0x848 755#define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888 756#define MV64340_DMA_CHANNEL3_CONTROL 0x84C 757#define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C 758 759 760/****************************************/ 761/* IDMA Registers */ 762/****************************************/ 763 764#define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800 765#define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804 766#define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808 767#define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C 768#define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810 769#define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814 770#define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818 771#define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c 772#define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820 773#define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824 774#define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828 775#define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C 776#define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830 777#define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834 778#define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838 779#define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C 780#define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870 781#define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874 782#define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878 783#define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C 784 785 /* IDMA Address Decoding Base Address Registers */ 786 787#define MV64340_DMA_BASE_ADDR_REG0 0xa00 788#define MV64340_DMA_BASE_ADDR_REG1 0xa08 789#define MV64340_DMA_BASE_ADDR_REG2 0xa10 790#define MV64340_DMA_BASE_ADDR_REG3 0xa18 791#define MV64340_DMA_BASE_ADDR_REG4 0xa20 792#define MV64340_DMA_BASE_ADDR_REG5 0xa28 793#define MV64340_DMA_BASE_ADDR_REG6 0xa30 794#define MV64340_DMA_BASE_ADDR_REG7 0xa38 795 796 /* IDMA Address Decoding Size Address Register */ 797 798#define MV64340_DMA_SIZE_REG0 0xa04 799#define MV64340_DMA_SIZE_REG1 0xa0c 800#define MV64340_DMA_SIZE_REG2 0xa14 801#define MV64340_DMA_SIZE_REG3 0xa1c 802#define MV64340_DMA_SIZE_REG4 0xa24 803#define MV64340_DMA_SIZE_REG5 0xa2c 804#define MV64340_DMA_SIZE_REG6 0xa34 805#define MV64340_DMA_SIZE_REG7 0xa3C 806 807 /* IDMA Address Decoding High Address Remap and Access 808 Protection Registers */ 809 810#define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60 811#define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64 812#define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68 813#define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C 814#define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80 815#define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70 816#define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74 817#define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78 818#define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c 819#define MV64340_DMA_ARBITER_CONTROL 0x860 820#define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0 821 822 /* IDMA Headers Retarget Registers */ 823 824#define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84 825#define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88 826 827 /* IDMA Interrupt Register */ 828 829#define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0 830#define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4 831#define MV64340_DMA_ERROR_ADDR 0x8c8 832#define MV64340_DMA_ERROR_SELECT 0x8cc 833 834 /* IDMA Debug Register ( for internal use ) */ 835 836#define MV64340_DMA_DEBUG_LOW 0x8e0 837#define MV64340_DMA_DEBUG_HIGH 0x8e4 838#define MV64340_DMA_SPARE 0xA8C 839 840/****************************************/ 841/* Timer_Counter */ 842/****************************************/ 843 844#define MV64340_TIMER_COUNTER0 0x850 845#define MV64340_TIMER_COUNTER1 0x854 846#define MV64340_TIMER_COUNTER2 0x858 847#define MV64340_TIMER_COUNTER3 0x85C 848#define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864 849#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868 850#define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c 851 852/****************************************/ 853/* Watchdog registers */ 854/****************************************/ 855 856#define MV64340_WATCHDOG_CONFIG_REG 0xb410 857#define MV64340_WATCHDOG_VALUE_REG 0xb414 858 859/****************************************/ 860/* I2C Registers */ 861/****************************************/ 862 863#define MV64XXX_I2C_OFFSET 0xc000 864#define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020 865 866/****************************************/ 867/* GPP Interface Registers */ 868/****************************************/ 869 870#define MV64340_GPP_IO_CONTROL 0xf100 871#define MV64340_GPP_LEVEL_CONTROL 0xf110 872#define MV64340_GPP_VALUE 0xf104 873#define MV64340_GPP_INTERRUPT_CAUSE 0xf108 874#define MV64340_GPP_INTERRUPT_MASK0 0xf10c 875#define MV64340_GPP_INTERRUPT_MASK1 0xf114 876#define MV64340_GPP_VALUE_SET 0xf118 877#define MV64340_GPP_VALUE_CLEAR 0xf11c 878 879/****************************************/ 880/* Interrupt Controller Registers */ 881/****************************************/ 882 883/****************************************/ 884/* Interrupts */ 885/****************************************/ 886 887#define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004 888#define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c 889#define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014 890#define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c 891#define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024 892#define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034 893#define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c 894#define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044 895#define MV64340_INTERRUPT0_MASK_0_LOW 0x054 896#define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c 897#define MV64340_INTERRUPT0_SELECT_CAUSE 0x064 898#define MV64340_INTERRUPT1_MASK_0_LOW 0x074 899#define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c 900#define MV64340_INTERRUPT1_SELECT_CAUSE 0x084 901 902/****************************************/ 903/* MPP Interface Registers */ 904/****************************************/ 905 906#define MV64340_MPP_CONTROL0 0xf000 907#define MV64340_MPP_CONTROL1 0xf004 908#define MV64340_MPP_CONTROL2 0xf008 909#define MV64340_MPP_CONTROL3 0xf00c 910 911/****************************************/ 912/* Serial Initialization registers */ 913/****************************************/ 914 915#define MV64340_SERIAL_INIT_LAST_DATA 0xf324 916#define MV64340_SERIAL_INIT_CONTROL 0xf328 917#define MV64340_SERIAL_INIT_STATUS 0xf32c 918 919extern void mv64340_irq_init(unsigned int base); 920 921/* MPSC Platform Device, Driver Data (Shared register regions) */ 922#define MPSC_SHARED_NAME "mpsc_shared" 923 924#define MPSC_ROUTING_BASE_ORDER 0 925#define MPSC_SDMA_INTR_BASE_ORDER 1 926 927#define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c 928#define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084 929 930struct mpsc_shared_pdata { 931 u32 mrr_val; 932 u32 rcrr_val; 933 u32 tcrr_val; 934 u32 intr_cause_val; 935 u32 intr_mask_val; 936}; 937 938/* MPSC Platform Device, Driver Data */ 939#define MPSC_CTLR_NAME "mpsc" 940 941#define MPSC_BASE_ORDER 0 942#define MPSC_SDMA_BASE_ORDER 1 943#define MPSC_BRG_BASE_ORDER 2 944 945#define MPSC_REG_BLOCK_SIZE 0x0038 946#define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18 947#define MPSC_BRG_REG_BLOCK_SIZE 0x0008 948 949struct mpsc_pdata { 950 u8 mirror_regs; 951 u8 cache_mgmt; 952 u8 max_idle; 953 int default_baud; 954 int default_bits; 955 int default_parity; 956 int default_flow; 957 u32 chr_1_val; 958 u32 chr_2_val; 959 u32 chr_10_val; 960 u32 mpcr_val; 961 u32 bcr_val; 962 u8 brg_can_tune; 963 u8 brg_clk_src; 964 u32 brg_clk_freq; 965}; 966 967/* Watchdog Platform Device, Driver Data */ 968#define MV64x60_WDT_NAME "mv64x60_wdt" 969 970struct mv64x60_wdt_pdata { 971 int timeout; /* watchdog expiry in seconds, default 10 */ 972 int bus_clk; /* bus clock in MHz, default 133 */ 973}; 974 975#endif /* __ASM_MV643XX_H */ 976