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17#ifndef LINUX_PCI_H
18#define LINUX_PCI_H
19
20
21#include <linux/mod_devicetable.h>
22
23#include <linux/types.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/list.h>
27#include <linux/compiler.h>
28#include <linux/errno.h>
29#include <linux/kobject.h>
30#include <linux/atomic.h>
31#include <linux/device.h>
32#include <linux/interrupt.h>
33#include <linux/io.h>
34#include <linux/resource_ext.h>
35#include <uapi/linux/pci.h>
36
37#include <linux/pci_ids.h>
38
39
40
41
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43
44
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46
47
48
49
50
51#define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
52
53#define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54
55
56struct pci_slot {
57 struct pci_bus *bus;
58 struct list_head list;
59 struct hotplug_slot *hotplug;
60 unsigned char number;
61 struct kobject kobj;
62};
63
64static inline const char *pci_slot_name(const struct pci_slot *slot)
65{
66 return kobject_name(&slot->kobj);
67}
68
69
70enum pci_mmap_state {
71 pci_mmap_io,
72 pci_mmap_mem
73};
74
75
76enum {
77
78 PCI_STD_RESOURCES,
79 PCI_STD_RESOURCE_END = 5,
80
81
82 PCI_ROM_RESOURCE,
83
84
85#ifdef CONFIG_PCI_IOV
86 PCI_IOV_RESOURCES,
87 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
88#endif
89
90
91#define PCI_BRIDGE_RESOURCE_NUM 4
92
93 PCI_BRIDGE_RESOURCES,
94 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
95 PCI_BRIDGE_RESOURCE_NUM - 1,
96
97
98 PCI_NUM_RESOURCES,
99
100
101 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
102};
103
104
105
106
107
108
109
110
111
112
113
114
115enum pci_interrupt_pin {
116 PCI_INTERRUPT_UNKNOWN,
117 PCI_INTERRUPT_INTA,
118 PCI_INTERRUPT_INTB,
119 PCI_INTERRUPT_INTC,
120 PCI_INTERRUPT_INTD,
121};
122
123
124#define PCI_NUM_INTX 4
125
126
127
128
129
130typedef int __bitwise pci_power_t;
131
132#define PCI_D0 ((pci_power_t __force) 0)
133#define PCI_D1 ((pci_power_t __force) 1)
134#define PCI_D2 ((pci_power_t __force) 2)
135#define PCI_D3hot ((pci_power_t __force) 3)
136#define PCI_D3cold ((pci_power_t __force) 4)
137#define PCI_UNKNOWN ((pci_power_t __force) 5)
138#define PCI_POWER_ERROR ((pci_power_t __force) -1)
139
140
141extern const char *pci_power_names[];
142
143static inline const char *pci_power_name(pci_power_t state)
144{
145 return pci_power_names[1 + (__force int) state];
146}
147
148#define PCI_PM_D2_DELAY 200
149#define PCI_PM_D3_WAIT 10
150#define PCI_PM_D3COLD_WAIT 100
151#define PCI_PM_BUS_WAIT 50
152
153
154
155
156
157
158typedef unsigned int __bitwise pci_channel_state_t;
159
160enum pci_channel_state {
161
162 pci_channel_io_normal = (__force pci_channel_state_t) 1,
163
164
165 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
166
167
168 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
169};
170
171typedef unsigned int __bitwise pcie_reset_state_t;
172
173enum pcie_reset_state {
174
175 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
176
177
178 pcie_warm_reset = (__force pcie_reset_state_t) 2,
179
180
181 pcie_hot_reset = (__force pcie_reset_state_t) 3
182};
183
184typedef unsigned short __bitwise pci_dev_flags_t;
185enum pci_dev_flags {
186
187 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
188
189 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
190
191 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
192
193 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
194
195 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
196
197 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
198
199 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
200
201 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
202
203 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
204
205 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
206
207 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 11),
208};
209
210enum pci_irq_reroute_variant {
211 INTEL_IRQ_REROUTE_VARIANT = 1,
212 MAX_IRQ_REROUTE_VARIANTS = 3
213};
214
215typedef unsigned short __bitwise pci_bus_flags_t;
216enum pci_bus_flags {
217 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
218 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
219 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
220 PCI_BUS_FLAGS_NO_EXTCFG = (__force pci_bus_flags_t) 8,
221};
222
223
224enum pcie_link_width {
225 PCIE_LNK_WIDTH_RESRV = 0x00,
226 PCIE_LNK_X1 = 0x01,
227 PCIE_LNK_X2 = 0x02,
228 PCIE_LNK_X4 = 0x04,
229 PCIE_LNK_X8 = 0x08,
230 PCIE_LNK_X12 = 0x0c,
231 PCIE_LNK_X16 = 0x10,
232 PCIE_LNK_X32 = 0x20,
233 PCIE_LNK_WIDTH_UNKNOWN = 0xff,
234};
235
236
237enum pci_bus_speed {
238 PCI_SPEED_33MHz = 0x00,
239 PCI_SPEED_66MHz = 0x01,
240 PCI_SPEED_66MHz_PCIX = 0x02,
241 PCI_SPEED_100MHz_PCIX = 0x03,
242 PCI_SPEED_133MHz_PCIX = 0x04,
243 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
244 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
245 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
246 PCI_SPEED_66MHz_PCIX_266 = 0x09,
247 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
248 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
249 AGP_UNKNOWN = 0x0c,
250 AGP_1X = 0x0d,
251 AGP_2X = 0x0e,
252 AGP_4X = 0x0f,
253 AGP_8X = 0x10,
254 PCI_SPEED_66MHz_PCIX_533 = 0x11,
255 PCI_SPEED_100MHz_PCIX_533 = 0x12,
256 PCI_SPEED_133MHz_PCIX_533 = 0x13,
257 PCIE_SPEED_2_5GT = 0x14,
258 PCIE_SPEED_5_0GT = 0x15,
259 PCIE_SPEED_8_0GT = 0x16,
260 PCIE_SPEED_16_0GT = 0x17,
261 PCI_SPEED_UNKNOWN = 0xff,
262};
263
264enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
265enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
266
267struct pci_cap_saved_data {
268 u16 cap_nr;
269 bool cap_extended;
270 unsigned int size;
271 u32 data[0];
272};
273
274struct pci_cap_saved_state {
275 struct hlist_node next;
276 struct pci_cap_saved_data cap;
277};
278
279struct irq_affinity;
280struct pcie_link_state;
281struct pci_vpd;
282struct pci_sriov;
283struct pci_ats;
284struct pci_p2pdma;
285
286
287struct pci_dev {
288 struct list_head bus_list;
289 struct pci_bus *bus;
290 struct pci_bus *subordinate;
291
292 void *sysdata;
293 struct proc_dir_entry *procent;
294 struct pci_slot *slot;
295
296 unsigned int devfn;
297 unsigned short vendor;
298 unsigned short device;
299 unsigned short subsystem_vendor;
300 unsigned short subsystem_device;
301 unsigned int class;
302 u8 revision;
303 u8 hdr_type;
304#ifdef CONFIG_PCIEAER
305 u16 aer_cap;
306 struct aer_stats *aer_stats;
307#endif
308 u8 pcie_cap;
309 u8 msi_cap;
310 u8 msix_cap;
311 u8 pcie_mpss:3;
312 u8 rom_base_reg;
313 u8 pin;
314 u16 pcie_flags_reg;
315 unsigned long *dma_alias_mask;
316
317 struct pci_driver *driver;
318 u64 dma_mask;
319
320
321
322
323
324 struct device_dma_parameters dma_parms;
325
326 pci_power_t current_state;
327
328
329 unsigned int imm_ready:1;
330 u8 pm_cap;
331 unsigned int pme_support:5;
332
333 unsigned int pme_poll:1;
334 unsigned int d1_support:1;
335 unsigned int d2_support:1;
336 unsigned int no_d1d2:1;
337 unsigned int no_d3cold:1;
338 unsigned int bridge_d3:1;
339 unsigned int d3cold_allowed:1;
340 unsigned int mmio_always_on:1;
341
342 unsigned int wakeup_prepared:1;
343 unsigned int runtime_d3cold:1;
344
345
346
347 unsigned int skip_bus_pm:1;
348 unsigned int ignore_hotplug:1;
349 unsigned int hotplug_user_indicators:1;
350
351
352 unsigned int clear_retrain_link:1;
353
354 unsigned int d3_delay;
355 unsigned int d3cold_delay;
356
357#ifdef CONFIG_PCIEASPM
358 struct pcie_link_state *link_state;
359 unsigned int ltr_path:1;
360
361#endif
362 unsigned int eetlp_prefix_path:1;
363
364 pci_channel_state_t error_state;
365 struct device dev;
366
367 int cfg_size;
368
369
370
371
372
373 unsigned int irq;
374 struct resource resource[DEVICE_COUNT_RESOURCE];
375
376 bool match_driver;
377
378 unsigned int transparent:1;
379 unsigned int io_window:1;
380 unsigned int pref_window:1;
381 unsigned int pref_64_window:1;
382 unsigned int multifunction:1;
383
384 unsigned int is_busmaster:1;
385 unsigned int no_msi:1;
386 unsigned int no_64bit_msi:1;
387 unsigned int block_cfg_access:1;
388 unsigned int broken_parity_status:1;
389 unsigned int irq_reroute_variant:2;
390 unsigned int msi_enabled:1;
391 unsigned int msix_enabled:1;
392 unsigned int ari_enabled:1;
393 unsigned int ats_enabled:1;
394 unsigned int pasid_enabled:1;
395 unsigned int pri_enabled:1;
396 unsigned int is_managed:1;
397 unsigned int needs_freset:1;
398 unsigned int state_saved:1;
399 unsigned int is_physfn:1;
400 unsigned int is_virtfn:1;
401 unsigned int reset_fn:1;
402 unsigned int is_hotplug_bridge:1;
403 unsigned int shpc_managed:1;
404 unsigned int is_thunderbolt:1;
405
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411
412 unsigned int untrusted:1;
413 unsigned int __aer_firmware_first_valid:1;
414 unsigned int __aer_firmware_first:1;
415 unsigned int broken_intx_masking:1;
416 unsigned int io_window_1k:1;
417 unsigned int irq_managed:1;
418 unsigned int has_secondary_link:1;
419 unsigned int non_compliant_bars:1;
420 unsigned int is_probed:1;
421 unsigned int link_active_reporting:1;
422 unsigned int no_vf_scan:1;
423 pci_dev_flags_t dev_flags;
424 atomic_t enable_cnt;
425
426 u32 saved_config_space[16];
427 struct hlist_head saved_cap_space;
428 struct bin_attribute *rom_attr;
429 int rom_attr_enabled;
430 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE];
431 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE];
432
433#ifdef CONFIG_HOTPLUG_PCI_PCIE
434 unsigned int broken_cmd_compl:1;
435#endif
436#ifdef CONFIG_PCIE_PTM
437 unsigned int ptm_root:1;
438 unsigned int ptm_enabled:1;
439 u8 ptm_granularity;
440#endif
441#ifdef CONFIG_PCI_MSI
442 const struct attribute_group **msi_irq_groups;
443#endif
444 struct pci_vpd *vpd;
445#ifdef CONFIG_PCI_ATS
446 union {
447 struct pci_sriov *sriov;
448 struct pci_dev *physfn;
449 };
450 u16 ats_cap;
451 u8 ats_stu;
452 atomic_t ats_ref_cnt;
453#endif
454#ifdef CONFIG_PCI_PRI
455 u32 pri_reqs_alloc;
456#endif
457#ifdef CONFIG_PCI_PASID
458 u16 pasid_features;
459#endif
460#ifdef CONFIG_PCI_P2PDMA
461 struct pci_p2pdma *p2pdma;
462#endif
463 phys_addr_t rom;
464 size_t romlen;
465 char *driver_override;
466
467 unsigned long priv_flags;
468};
469
470static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
471{
472#ifdef CONFIG_PCI_IOV
473 if (dev->is_virtfn)
474 dev = dev->physfn;
475#endif
476 return dev;
477}
478
479struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
480
481#define to_pci_dev(n) container_of(n, struct pci_dev, dev)
482#define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
483
484static inline int pci_channel_offline(struct pci_dev *pdev)
485{
486 return (pdev->error_state != pci_channel_io_normal);
487}
488
489struct pci_host_bridge {
490 struct device dev;
491 struct pci_bus *bus;
492 struct pci_ops *ops;
493 void *sysdata;
494 int busnr;
495 struct list_head windows;
496 struct list_head dma_ranges;
497 u8 (*swizzle_irq)(struct pci_dev *, u8 *);
498 int (*map_irq)(const struct pci_dev *, u8, u8);
499 void (*release_fn)(struct pci_host_bridge *);
500 void *release_data;
501 struct msi_controller *msi;
502 unsigned int ignore_reset_delay:1;
503 unsigned int no_ext_tags:1;
504 unsigned int native_aer:1;
505 unsigned int native_pcie_hotplug:1;
506 unsigned int native_shpc_hotplug:1;
507 unsigned int native_pme:1;
508 unsigned int native_ltr:1;
509
510 resource_size_t (*align_resource)(struct pci_dev *dev,
511 const struct resource *res,
512 resource_size_t start,
513 resource_size_t size,
514 resource_size_t align);
515 unsigned long private[0] ____cacheline_aligned;
516};
517
518#define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
519
520static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
521{
522 return (void *)bridge->private;
523}
524
525static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
526{
527 return container_of(priv, struct pci_host_bridge, private);
528}
529
530struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
531struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
532 size_t priv);
533void pci_free_host_bridge(struct pci_host_bridge *bridge);
534struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
535
536void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
537 void (*release_fn)(struct pci_host_bridge *),
538 void *release_data);
539
540int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
541
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554
555#define PCI_SUBTRACTIVE_DECODE 0x1
556
557struct pci_bus_resource {
558 struct list_head list;
559 struct resource *res;
560 unsigned int flags;
561};
562
563#define PCI_REGION_FLAG_MASK 0x0fU
564
565struct pci_bus {
566 struct list_head node;
567 struct pci_bus *parent;
568 struct list_head children;
569 struct list_head devices;
570 struct pci_dev *self;
571 struct list_head slots;
572
573 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
574 struct list_head resources;
575 struct resource busn_res;
576
577 struct pci_ops *ops;
578 struct msi_controller *msi;
579 void *sysdata;
580 struct proc_dir_entry *procdir;
581
582 unsigned char number;
583 unsigned char primary;
584 unsigned char max_bus_speed;
585 unsigned char cur_bus_speed;
586#ifdef CONFIG_PCI_DOMAINS_GENERIC
587 int domain_nr;
588#endif
589
590 char name[48];
591
592 unsigned short bridge_ctl;
593 pci_bus_flags_t bus_flags;
594 struct device *bridge;
595 struct device dev;
596 struct bin_attribute *legacy_io;
597 struct bin_attribute *legacy_mem;
598 unsigned int is_added:1;
599};
600
601#define to_pci_bus(n) container_of(n, struct pci_bus, dev)
602
603static inline u16 pci_dev_id(struct pci_dev *dev)
604{
605 return PCI_DEVID(dev->bus->number, dev->devfn);
606}
607
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614
615
616static inline bool pci_is_root_bus(struct pci_bus *pbus)
617{
618 return !(pbus->parent);
619}
620
621
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623
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627
628static inline bool pci_is_bridge(struct pci_dev *dev)
629{
630 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
631 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
632}
633
634#define for_each_pci_bridge(dev, bus) \
635 list_for_each_entry(dev, &bus->devices, bus_list) \
636 if (!pci_is_bridge(dev)) {} else
637
638static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
639{
640 dev = pci_physfn(dev);
641 if (pci_is_root_bus(dev->bus))
642 return NULL;
643
644 return dev->bus->self;
645}
646
647struct device *pci_get_host_bridge_device(struct pci_dev *dev);
648void pci_put_host_bridge_device(struct device *dev);
649
650#ifdef CONFIG_PCI_MSI
651static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
652{
653 return pci_dev->msi_enabled || pci_dev->msix_enabled;
654}
655#else
656static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
657#endif
658
659
660#define PCIBIOS_SUCCESSFUL 0x00
661#define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
662#define PCIBIOS_BAD_VENDOR_ID 0x83
663#define PCIBIOS_DEVICE_NOT_FOUND 0x86
664#define PCIBIOS_BAD_REGISTER_NUMBER 0x87
665#define PCIBIOS_SET_FAILED 0x88
666#define PCIBIOS_BUFFER_TOO_SMALL 0x89
667
668
669static inline int pcibios_err_to_errno(int err)
670{
671 if (err <= PCIBIOS_SUCCESSFUL)
672 return err;
673
674 switch (err) {
675 case PCIBIOS_FUNC_NOT_SUPPORTED:
676 return -ENOENT;
677 case PCIBIOS_BAD_VENDOR_ID:
678 return -ENOTTY;
679 case PCIBIOS_DEVICE_NOT_FOUND:
680 return -ENODEV;
681 case PCIBIOS_BAD_REGISTER_NUMBER:
682 return -EFAULT;
683 case PCIBIOS_SET_FAILED:
684 return -EIO;
685 case PCIBIOS_BUFFER_TOO_SMALL:
686 return -ENOSPC;
687 }
688
689 return -ERANGE;
690}
691
692
693
694struct pci_ops {
695 int (*add_bus)(struct pci_bus *bus);
696 void (*remove_bus)(struct pci_bus *bus);
697 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
698 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
699 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
700};
701
702
703
704
705
706int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
707 int reg, int len, u32 *val);
708int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
709 int reg, int len, u32 val);
710
711#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
712typedef u64 pci_bus_addr_t;
713#else
714typedef u32 pci_bus_addr_t;
715#endif
716
717struct pci_bus_region {
718 pci_bus_addr_t start;
719 pci_bus_addr_t end;
720};
721
722struct pci_dynids {
723 spinlock_t lock;
724 struct list_head list;
725};
726
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731
732
733
734
735typedef unsigned int __bitwise pci_ers_result_t;
736
737enum pci_ers_result {
738
739 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
740
741
742 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
743
744
745 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
746
747
748 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
749
750
751 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
752
753
754 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
755};
756
757
758struct pci_error_handlers {
759
760 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
761 enum pci_channel_state error);
762
763
764 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
765
766
767 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
768
769
770 void (*reset_prepare)(struct pci_dev *dev);
771 void (*reset_done)(struct pci_dev *dev);
772
773
774 void (*resume)(struct pci_dev *dev);
775};
776
777
778struct module;
779struct pci_driver {
780 struct list_head node;
781 const char *name;
782 const struct pci_device_id *id_table;
783 int (*probe)(struct pci_dev *dev, const struct pci_device_id *id);
784 void (*remove)(struct pci_dev *dev);
785 int (*suspend)(struct pci_dev *dev, pm_message_t state);
786 int (*suspend_late)(struct pci_dev *dev, pm_message_t state);
787 int (*resume_early)(struct pci_dev *dev);
788 int (*resume)(struct pci_dev *dev);
789 void (*shutdown)(struct pci_dev *dev);
790 int (*sriov_configure)(struct pci_dev *dev, int num_vfs);
791 const struct pci_error_handlers *err_handler;
792 const struct attribute_group **groups;
793 struct device_driver driver;
794 struct pci_dynids dynids;
795};
796
797#define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
798
799
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806
807
808#define PCI_DEVICE(vend,dev) \
809 .vendor = (vend), .device = (dev), \
810 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
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818
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821
822#define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
823 .vendor = (vend), .device = (dev), \
824 .subvendor = (subvend), .subdevice = (subdev)
825
826
827
828
829
830
831
832
833
834
835#define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
836 .class = (dev_class), .class_mask = (dev_class_mask), \
837 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
838 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
839
840
841
842
843
844
845
846
847
848
849
850#define PCI_VDEVICE(vend, dev) \
851 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
852 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
853
854
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857
858
859
860
861
862
863
864#define PCI_DEVICE_DATA(vend, dev, data) \
865 .vendor = PCI_VENDOR_ID_##vend, .device = PCI_DEVICE_ID_##vend##_##dev, \
866 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0, \
867 .driver_data = (kernel_ulong_t)(data)
868
869enum {
870 PCI_REASSIGN_ALL_RSRC = 0x00000001,
871 PCI_REASSIGN_ALL_BUS = 0x00000002,
872 PCI_PROBE_ONLY = 0x00000004,
873 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008,
874 PCI_ENABLE_PROC_DOMAINS = 0x00000010,
875 PCI_COMPAT_DOMAIN_0 = 0x00000020,
876 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040,
877};
878
879
880#ifdef CONFIG_PCI
881
882extern unsigned int pci_flags;
883
884static inline void pci_set_flags(int flags) { pci_flags = flags; }
885static inline void pci_add_flags(int flags) { pci_flags |= flags; }
886static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
887static inline int pci_has_flag(int flag) { return pci_flags & flag; }
888
889void pcie_bus_configure_settings(struct pci_bus *bus);
890
891enum pcie_bus_config_types {
892 PCIE_BUS_TUNE_OFF,
893 PCIE_BUS_DEFAULT,
894 PCIE_BUS_SAFE,
895 PCIE_BUS_PERFORMANCE,
896 PCIE_BUS_PEER2PEER,
897};
898
899extern enum pcie_bus_config_types pcie_bus_config;
900
901extern struct bus_type pci_bus_type;
902
903
904
905extern struct list_head pci_root_buses;
906
907int no_pci_devices(void);
908
909void pcibios_resource_survey_bus(struct pci_bus *bus);
910void pcibios_bus_add_device(struct pci_dev *pdev);
911void pcibios_add_bus(struct pci_bus *bus);
912void pcibios_remove_bus(struct pci_bus *bus);
913void pcibios_fixup_bus(struct pci_bus *);
914int __must_check pcibios_enable_device(struct pci_dev *, int mask);
915
916char *pcibios_setup(char *str);
917
918
919resource_size_t pcibios_align_resource(void *, const struct resource *,
920 resource_size_t,
921 resource_size_t);
922
923
924void pci_fixup_cardbus(struct pci_bus *);
925
926
927
928void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
929 struct resource *res);
930void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
931 struct pci_bus_region *region);
932void pcibios_scan_specific_bus(int busn);
933struct pci_bus *pci_find_bus(int domain, int busnr);
934void pci_bus_add_devices(const struct pci_bus *bus);
935struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
936struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
937 struct pci_ops *ops, void *sysdata,
938 struct list_head *resources);
939int pci_host_probe(struct pci_host_bridge *bridge);
940int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
941int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
942void pci_bus_release_busn_res(struct pci_bus *b);
943struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
944 struct pci_ops *ops, void *sysdata,
945 struct list_head *resources);
946int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
947struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
948 int busnr);
949void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
950struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
951 const char *name,
952 struct hotplug_slot *hotplug);
953void pci_destroy_slot(struct pci_slot *slot);
954#ifdef CONFIG_SYSFS
955void pci_dev_assign_slot(struct pci_dev *dev);
956#else
957static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
958#endif
959int pci_scan_slot(struct pci_bus *bus, int devfn);
960struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
961void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
962unsigned int pci_scan_child_bus(struct pci_bus *bus);
963void pci_bus_add_device(struct pci_dev *dev);
964void pci_read_bridge_bases(struct pci_bus *child);
965struct resource *pci_find_parent_resource(const struct pci_dev *dev,
966 struct resource *res);
967struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
968u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
969int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
970u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
971struct pci_dev *pci_dev_get(struct pci_dev *dev);
972void pci_dev_put(struct pci_dev *dev);
973void pci_remove_bus(struct pci_bus *b);
974void pci_stop_and_remove_bus_device(struct pci_dev *dev);
975void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
976void pci_stop_root_bus(struct pci_bus *bus);
977void pci_remove_root_bus(struct pci_bus *bus);
978void pci_setup_cardbus(struct pci_bus *bus);
979void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
980void pci_sort_breadthfirst(void);
981#define dev_is_pci(d) ((d)->bus == &pci_bus_type)
982#define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
983
984
985
986enum pci_lost_interrupt_reason {
987 PCI_LOST_IRQ_NO_INFORMATION = 0,
988 PCI_LOST_IRQ_DISABLE_MSI,
989 PCI_LOST_IRQ_DISABLE_MSIX,
990 PCI_LOST_IRQ_DISABLE_ACPI,
991};
992enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
993int pci_find_capability(struct pci_dev *dev, int cap);
994int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
995int pci_find_ext_capability(struct pci_dev *dev, int cap);
996int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
997int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
998int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
999struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
1000
1001struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
1002 struct pci_dev *from);
1003struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
1004 unsigned int ss_vendor, unsigned int ss_device,
1005 struct pci_dev *from);
1006struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
1007struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
1008 unsigned int devfn);
1009struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
1010int pci_dev_present(const struct pci_device_id *ids);
1011
1012int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
1013 int where, u8 *val);
1014int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
1015 int where, u16 *val);
1016int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
1017 int where, u32 *val);
1018int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
1019 int where, u8 val);
1020int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
1021 int where, u16 val);
1022int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
1023 int where, u32 val);
1024
1025int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
1026 int where, int size, u32 *val);
1027int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
1028 int where, int size, u32 val);
1029int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
1030 int where, int size, u32 *val);
1031int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
1032 int where, int size, u32 val);
1033
1034struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
1035
1036int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
1037int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
1038int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
1039int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
1040int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
1041int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
1042
1043int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
1044int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
1045int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
1046int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
1047int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
1048 u16 clear, u16 set);
1049int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
1050 u32 clear, u32 set);
1051
1052static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
1053 u16 set)
1054{
1055 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
1056}
1057
1058static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
1059 u32 set)
1060{
1061 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
1062}
1063
1064static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
1065 u16 clear)
1066{
1067 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1068}
1069
1070static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1071 u32 clear)
1072{
1073 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1074}
1075
1076
1077int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1078int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1079int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1080int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1081int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1082int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1083
1084int __must_check pci_enable_device(struct pci_dev *dev);
1085int __must_check pci_enable_device_io(struct pci_dev *dev);
1086int __must_check pci_enable_device_mem(struct pci_dev *dev);
1087int __must_check pci_reenable_device(struct pci_dev *);
1088int __must_check pcim_enable_device(struct pci_dev *pdev);
1089void pcim_pin_device(struct pci_dev *pdev);
1090
1091static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1092{
1093
1094
1095
1096
1097 return !pdev->broken_intx_masking;
1098}
1099
1100static inline int pci_is_enabled(struct pci_dev *pdev)
1101{
1102 return (atomic_read(&pdev->enable_cnt) > 0);
1103}
1104
1105static inline int pci_is_managed(struct pci_dev *pdev)
1106{
1107 return pdev->is_managed;
1108}
1109
1110void pci_disable_device(struct pci_dev *dev);
1111
1112extern unsigned int pcibios_max_latency;
1113void pci_set_master(struct pci_dev *dev);
1114void pci_clear_master(struct pci_dev *dev);
1115
1116int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1117int pci_set_cacheline_size(struct pci_dev *dev);
1118#define HAVE_PCI_SET_MWI
1119int __must_check pci_set_mwi(struct pci_dev *dev);
1120int __must_check pcim_set_mwi(struct pci_dev *dev);
1121int pci_try_set_mwi(struct pci_dev *dev);
1122void pci_clear_mwi(struct pci_dev *dev);
1123void pci_intx(struct pci_dev *dev, int enable);
1124bool pci_check_and_mask_intx(struct pci_dev *dev);
1125bool pci_check_and_unmask_intx(struct pci_dev *dev);
1126int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1127int pci_wait_for_pending_transaction(struct pci_dev *dev);
1128int pcix_get_max_mmrbc(struct pci_dev *dev);
1129int pcix_get_mmrbc(struct pci_dev *dev);
1130int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1131int pcie_get_readrq(struct pci_dev *dev);
1132int pcie_set_readrq(struct pci_dev *dev, int rq);
1133int pcie_get_mps(struct pci_dev *dev);
1134int pcie_set_mps(struct pci_dev *dev, int mps);
1135u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
1136 enum pci_bus_speed *speed,
1137 enum pcie_link_width *width);
1138void pcie_print_link_status(struct pci_dev *dev);
1139bool pcie_has_flr(struct pci_dev *dev);
1140int pcie_flr(struct pci_dev *dev);
1141int __pci_reset_function_locked(struct pci_dev *dev);
1142int pci_reset_function(struct pci_dev *dev);
1143int pci_reset_function_locked(struct pci_dev *dev);
1144int pci_try_reset_function(struct pci_dev *dev);
1145int pci_probe_reset_slot(struct pci_slot *slot);
1146int pci_probe_reset_bus(struct pci_bus *bus);
1147int pci_reset_bus(struct pci_dev *dev);
1148void pci_reset_secondary_bus(struct pci_dev *dev);
1149void pcibios_reset_secondary_bus(struct pci_dev *dev);
1150void pci_update_resource(struct pci_dev *dev, int resno);
1151int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1152int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1153void pci_release_resource(struct pci_dev *dev, int resno);
1154int __must_check pci_resize_resource(struct pci_dev *dev, int i, int size);
1155int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1156bool pci_device_is_present(struct pci_dev *pdev);
1157void pci_ignore_hotplug(struct pci_dev *dev);
1158
1159int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1160 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1161 const char *fmt, ...);
1162void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1163
1164
1165int pci_enable_rom(struct pci_dev *pdev);
1166void pci_disable_rom(struct pci_dev *pdev);
1167void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1168void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1169void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1170
1171
1172int pci_save_state(struct pci_dev *dev);
1173void pci_restore_state(struct pci_dev *dev);
1174struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1175int pci_load_saved_state(struct pci_dev *dev,
1176 struct pci_saved_state *state);
1177int pci_load_and_free_saved_state(struct pci_dev *dev,
1178 struct pci_saved_state **state);
1179struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1180struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1181 u16 cap);
1182int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1183int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1184 u16 cap, unsigned int size);
1185int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1186int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1187pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1188bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1189void pci_pme_active(struct pci_dev *dev, bool enable);
1190int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1191int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1192int pci_prepare_to_sleep(struct pci_dev *dev);
1193int pci_back_from_sleep(struct pci_dev *dev);
1194bool pci_dev_run_wake(struct pci_dev *dev);
1195bool pci_check_pme_status(struct pci_dev *dev);
1196void pci_pme_wakeup_bus(struct pci_bus *bus);
1197void pci_d3cold_enable(struct pci_dev *dev);
1198void pci_d3cold_disable(struct pci_dev *dev);
1199bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1200void pci_wakeup_bus(struct pci_bus *bus);
1201void pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state);
1202
1203
1204int pci_save_vc_state(struct pci_dev *dev);
1205void pci_restore_vc_state(struct pci_dev *dev);
1206void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1207
1208
1209void set_pcie_port_type(struct pci_dev *pdev);
1210void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1211
1212
1213int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1214unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1215unsigned int pci_rescan_bus(struct pci_bus *bus);
1216void pci_lock_rescan_remove(void);
1217void pci_unlock_rescan_remove(void);
1218
1219
1220ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1221ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1222int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1223
1224
1225resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1226void pci_bus_assign_resources(const struct pci_bus *bus);
1227void pci_bus_claim_resources(struct pci_bus *bus);
1228void pci_bus_size_bridges(struct pci_bus *bus);
1229int pci_claim_resource(struct pci_dev *, int);
1230int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1231void pci_assign_unassigned_resources(void);
1232void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1233void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1234void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1235int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type);
1236void pdev_enable_device(struct pci_dev *);
1237int pci_enable_resources(struct pci_dev *, int mask);
1238void pci_assign_irq(struct pci_dev *dev);
1239struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1240#define HAVE_PCI_REQ_REGIONS 2
1241int __must_check pci_request_regions(struct pci_dev *, const char *);
1242int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1243void pci_release_regions(struct pci_dev *);
1244int __must_check pci_request_region(struct pci_dev *, int, const char *);
1245void pci_release_region(struct pci_dev *, int);
1246int pci_request_selected_regions(struct pci_dev *, int, const char *);
1247int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1248void pci_release_selected_regions(struct pci_dev *, int);
1249
1250
1251struct pci_bus *pci_bus_get(struct pci_bus *bus);
1252void pci_bus_put(struct pci_bus *bus);
1253void pci_add_resource(struct list_head *resources, struct resource *res);
1254void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1255 resource_size_t offset);
1256void pci_free_resource_list(struct list_head *resources);
1257void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1258 unsigned int flags);
1259struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1260void pci_bus_remove_resources(struct pci_bus *bus);
1261int devm_request_pci_bus_resources(struct device *dev,
1262 struct list_head *resources);
1263
1264
1265int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
1266
1267#define pci_bus_for_each_resource(bus, res, i) \
1268 for (i = 0; \
1269 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1270 i++)
1271
1272int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1273 struct resource *res, resource_size_t size,
1274 resource_size_t align, resource_size_t min,
1275 unsigned long type_mask,
1276 resource_size_t (*alignf)(void *,
1277 const struct resource *,
1278 resource_size_t,
1279 resource_size_t),
1280 void *alignf_data);
1281
1282
1283int pci_register_io_range(struct fwnode_handle *fwnode, phys_addr_t addr,
1284 resource_size_t size);
1285unsigned long pci_address_to_pio(phys_addr_t addr);
1286phys_addr_t pci_pio_to_address(unsigned long pio);
1287int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1288int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
1289 phys_addr_t phys_addr);
1290void pci_unmap_iospace(struct resource *res);
1291void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1292 resource_size_t offset,
1293 resource_size_t size);
1294void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1295 struct resource *res);
1296
1297static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1298{
1299 struct pci_bus_region region;
1300
1301 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1302 return region.start;
1303}
1304
1305
1306int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1307 const char *mod_name);
1308
1309
1310#define pci_register_driver(driver) \
1311 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1312
1313void pci_unregister_driver(struct pci_driver *dev);
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323#define module_pci_driver(__pci_driver) \
1324 module_driver(__pci_driver, pci_register_driver, pci_unregister_driver)
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334#define builtin_pci_driver(__pci_driver) \
1335 builtin_driver(__pci_driver, pci_register_driver)
1336
1337struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1338int pci_add_dynid(struct pci_driver *drv,
1339 unsigned int vendor, unsigned int device,
1340 unsigned int subvendor, unsigned int subdevice,
1341 unsigned int class, unsigned int class_mask,
1342 unsigned long driver_data);
1343const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1344 struct pci_dev *dev);
1345int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1346 int pass);
1347
1348void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1349 void *userdata);
1350int pci_cfg_space_size(struct pci_dev *dev);
1351unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1352void pci_setup_bridge(struct pci_bus *bus);
1353resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1354 unsigned long type);
1355
1356#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1357#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1358
1359int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1360 unsigned int command_bits, u32 flags);
1361
1362#define PCI_IRQ_LEGACY (1 << 0)
1363#define PCI_IRQ_MSI (1 << 1)
1364#define PCI_IRQ_MSIX (1 << 2)
1365#define PCI_IRQ_AFFINITY (1 << 3)
1366#define PCI_IRQ_ALL_TYPES \
1367 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1368
1369
1370
1371#include <linux/dmapool.h>
1372
1373#define pci_pool dma_pool
1374#define pci_pool_create(name, pdev, size, align, allocation) \
1375 dma_pool_create(name, &pdev->dev, size, align, allocation)
1376#define pci_pool_destroy(pool) dma_pool_destroy(pool)
1377#define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1378#define pci_pool_zalloc(pool, flags, handle) \
1379 dma_pool_zalloc(pool, flags, handle)
1380#define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1381
1382struct msix_entry {
1383 u32 vector;
1384 u16 entry;
1385};
1386
1387#ifdef CONFIG_PCI_MSI
1388int pci_msi_vec_count(struct pci_dev *dev);
1389void pci_disable_msi(struct pci_dev *dev);
1390int pci_msix_vec_count(struct pci_dev *dev);
1391void pci_disable_msix(struct pci_dev *dev);
1392void pci_restore_msi_state(struct pci_dev *dev);
1393int pci_msi_enabled(void);
1394int pci_enable_msi(struct pci_dev *dev);
1395int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1396 int minvec, int maxvec);
1397static inline int pci_enable_msix_exact(struct pci_dev *dev,
1398 struct msix_entry *entries, int nvec)
1399{
1400 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1401 if (rc < 0)
1402 return rc;
1403 return 0;
1404}
1405int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1406 unsigned int max_vecs, unsigned int flags,
1407 struct irq_affinity *affd);
1408
1409void pci_free_irq_vectors(struct pci_dev *dev);
1410int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1411const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1412int pci_irq_get_node(struct pci_dev *pdev, int vec);
1413
1414#else
1415static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1416static inline void pci_disable_msi(struct pci_dev *dev) { }
1417static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1418static inline void pci_disable_msix(struct pci_dev *dev) { }
1419static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1420static inline int pci_msi_enabled(void) { return 0; }
1421static inline int pci_enable_msi(struct pci_dev *dev)
1422{ return -ENOSYS; }
1423static inline int pci_enable_msix_range(struct pci_dev *dev,
1424 struct msix_entry *entries, int minvec, int maxvec)
1425{ return -ENOSYS; }
1426static inline int pci_enable_msix_exact(struct pci_dev *dev,
1427 struct msix_entry *entries, int nvec)
1428{ return -ENOSYS; }
1429
1430static inline int
1431pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1432 unsigned int max_vecs, unsigned int flags,
1433 struct irq_affinity *aff_desc)
1434{
1435 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1436 return 1;
1437 return -ENOSPC;
1438}
1439
1440static inline void pci_free_irq_vectors(struct pci_dev *dev)
1441{
1442}
1443
1444static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1445{
1446 if (WARN_ON_ONCE(nr > 0))
1447 return -EINVAL;
1448 return dev->irq;
1449}
1450static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1451 int vec)
1452{
1453 return cpu_possible_mask;
1454}
1455
1456static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1457{
1458 return first_online_node;
1459}
1460#endif
1461
1462static inline int
1463pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1464 unsigned int max_vecs, unsigned int flags)
1465{
1466 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1467 NULL);
1468}
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1487 struct device_node *node,
1488 const u32 *intspec,
1489 unsigned int intsize,
1490 unsigned long *out_hwirq,
1491 unsigned int *out_type)
1492{
1493 const u32 intx = intspec[0];
1494
1495 if (intx < PCI_INTERRUPT_INTA || intx > PCI_INTERRUPT_INTD)
1496 return -EINVAL;
1497
1498 *out_hwirq = intx - PCI_INTERRUPT_INTA;
1499 return 0;
1500}
1501
1502#ifdef CONFIG_PCIEPORTBUS
1503extern bool pcie_ports_disabled;
1504extern bool pcie_ports_native;
1505#else
1506#define pcie_ports_disabled true
1507#define pcie_ports_native false
1508#endif
1509
1510#ifdef CONFIG_PCIEASPM
1511bool pcie_aspm_support_enabled(void);
1512#else
1513static inline bool pcie_aspm_support_enabled(void) { return false; }
1514#endif
1515
1516#ifdef CONFIG_PCIEAER
1517bool pci_aer_available(void);
1518#else
1519static inline bool pci_aer_available(void) { return false; }
1520#endif
1521
1522#ifdef CONFIG_PCIE_ECRC
1523void pcie_set_ecrc_checking(struct pci_dev *dev);
1524void pcie_ecrc_get_policy(char *str);
1525#else
1526static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1527static inline void pcie_ecrc_get_policy(char *str) { }
1528#endif
1529
1530bool pci_ats_disabled(void);
1531
1532#ifdef CONFIG_PCIE_PTM
1533int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1534#else
1535static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1536{ return -EINVAL; }
1537#endif
1538
1539void pci_cfg_access_lock(struct pci_dev *dev);
1540bool pci_cfg_access_trylock(struct pci_dev *dev);
1541void pci_cfg_access_unlock(struct pci_dev *dev);
1542
1543
1544
1545
1546
1547
1548#ifdef CONFIG_PCI_DOMAINS
1549extern int pci_domains_supported;
1550#else
1551enum { pci_domains_supported = 0 };
1552static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1553static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1554#endif
1555
1556
1557
1558
1559
1560
1561#ifdef CONFIG_PCI_DOMAINS_GENERIC
1562static inline int pci_domain_nr(struct pci_bus *bus)
1563{
1564 return bus->domain_nr;
1565}
1566#ifdef CONFIG_ACPI
1567int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1568#else
1569static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1570{ return 0; }
1571#endif
1572int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1573#endif
1574
1575
1576typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1577 unsigned int command_bits, u32 flags);
1578void pci_register_set_vga_state(arch_set_vga_state_t func);
1579
1580static inline int
1581pci_request_io_regions(struct pci_dev *pdev, const char *name)
1582{
1583 return pci_request_selected_regions(pdev,
1584 pci_select_bars(pdev, IORESOURCE_IO), name);
1585}
1586
1587static inline void
1588pci_release_io_regions(struct pci_dev *pdev)
1589{
1590 return pci_release_selected_regions(pdev,
1591 pci_select_bars(pdev, IORESOURCE_IO));
1592}
1593
1594static inline int
1595pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1596{
1597 return pci_request_selected_regions(pdev,
1598 pci_select_bars(pdev, IORESOURCE_MEM), name);
1599}
1600
1601static inline void
1602pci_release_mem_regions(struct pci_dev *pdev)
1603{
1604 return pci_release_selected_regions(pdev,
1605 pci_select_bars(pdev, IORESOURCE_MEM));
1606}
1607
1608#else
1609
1610static inline void pci_set_flags(int flags) { }
1611static inline void pci_add_flags(int flags) { }
1612static inline void pci_clear_flags(int flags) { }
1613static inline int pci_has_flag(int flag) { return 0; }
1614
1615
1616
1617
1618
1619#define _PCI_NOP(o, s, t) \
1620 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1621 int where, t val) \
1622 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1623
1624#define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1625 _PCI_NOP(o, word, u16 x) \
1626 _PCI_NOP(o, dword, u32 x)
1627_PCI_NOP_ALL(read, *)
1628_PCI_NOP_ALL(write,)
1629
1630static inline struct pci_dev *pci_get_device(unsigned int vendor,
1631 unsigned int device,
1632 struct pci_dev *from)
1633{ return NULL; }
1634
1635static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1636 unsigned int device,
1637 unsigned int ss_vendor,
1638 unsigned int ss_device,
1639 struct pci_dev *from)
1640{ return NULL; }
1641
1642static inline struct pci_dev *pci_get_class(unsigned int class,
1643 struct pci_dev *from)
1644{ return NULL; }
1645
1646#define pci_dev_present(ids) (0)
1647#define no_pci_devices() (1)
1648#define pci_dev_put(dev) do { } while (0)
1649
1650static inline void pci_set_master(struct pci_dev *dev) { }
1651static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1652static inline void pci_disable_device(struct pci_dev *dev) { }
1653static inline int pci_assign_resource(struct pci_dev *dev, int i)
1654{ return -EBUSY; }
1655static inline int __pci_register_driver(struct pci_driver *drv,
1656 struct module *owner)
1657{ return 0; }
1658static inline int pci_register_driver(struct pci_driver *drv)
1659{ return 0; }
1660static inline void pci_unregister_driver(struct pci_driver *drv) { }
1661static inline int pci_find_capability(struct pci_dev *dev, int cap)
1662{ return 0; }
1663static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1664 int cap)
1665{ return 0; }
1666static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1667{ return 0; }
1668
1669
1670static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1671static inline void pci_restore_state(struct pci_dev *dev) { }
1672static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1673{ return 0; }
1674static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1675{ return 0; }
1676static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1677 pm_message_t state)
1678{ return PCI_D0; }
1679static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1680 int enable)
1681{ return 0; }
1682
1683static inline struct resource *pci_find_resource(struct pci_dev *dev,
1684 struct resource *res)
1685{ return NULL; }
1686static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1687{ return -EIO; }
1688static inline void pci_release_regions(struct pci_dev *dev) { }
1689
1690static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1691
1692static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1693static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1694{ return 0; }
1695static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1696
1697static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1698{ return NULL; }
1699static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1700 unsigned int devfn)
1701{ return NULL; }
1702static inline struct pci_dev *pci_get_domain_bus_and_slot(int domain,
1703 unsigned int bus, unsigned int devfn)
1704{ return NULL; }
1705
1706static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1707static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1708
1709#define dev_is_pci(d) (false)
1710#define dev_is_pf(d) (false)
1711static inline bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
1712{ return false; }
1713static inline int pci_irqd_intx_xlate(struct irq_domain *d,
1714 struct device_node *node,
1715 const u32 *intspec,
1716 unsigned int intsize,
1717 unsigned long *out_hwirq,
1718 unsigned int *out_type)
1719{ return -EINVAL; }
1720
1721static inline const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1722 struct pci_dev *dev)
1723{ return NULL; }
1724static inline bool pci_ats_disabled(void) { return true; }
1725#endif
1726
1727#ifdef CONFIG_PCI_ATS
1728
1729void pci_ats_init(struct pci_dev *dev);
1730int pci_enable_ats(struct pci_dev *dev, int ps);
1731void pci_disable_ats(struct pci_dev *dev);
1732int pci_ats_queue_depth(struct pci_dev *dev);
1733int pci_ats_page_aligned(struct pci_dev *dev);
1734#else
1735static inline void pci_ats_init(struct pci_dev *d) { }
1736static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1737static inline void pci_disable_ats(struct pci_dev *d) { }
1738static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1739static inline int pci_ats_page_aligned(struct pci_dev *dev) { return 0; }
1740#endif
1741
1742
1743
1744#include <asm/pci.h>
1745
1746
1747
1748
1749
1750
1751
1752
1753
1754
1755
1756
1757
1758int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1759 struct vm_area_struct *vma,
1760 enum pci_mmap_state mmap_state, int write_combine);
1761int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1762 struct vm_area_struct *vma,
1763 enum pci_mmap_state mmap_state, int write_combine);
1764
1765#ifndef arch_can_pci_mmap_wc
1766#define arch_can_pci_mmap_wc() 0
1767#endif
1768
1769#ifndef arch_can_pci_mmap_io
1770#define arch_can_pci_mmap_io() 0
1771#define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1772#else
1773int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1774#endif
1775
1776#ifndef pci_root_bus_fwnode
1777#define pci_root_bus_fwnode(bus) NULL
1778#endif
1779
1780
1781
1782
1783
1784#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1785#define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1786#define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1787#define pci_resource_len(dev,bar) \
1788 ((pci_resource_start((dev), (bar)) == 0 && \
1789 pci_resource_end((dev), (bar)) == \
1790 pci_resource_start((dev), (bar))) ? 0 : \
1791 \
1792 (pci_resource_end((dev), (bar)) - \
1793 pci_resource_start((dev), (bar)) + 1))
1794
1795
1796
1797
1798
1799
1800static inline void *pci_get_drvdata(struct pci_dev *pdev)
1801{
1802 return dev_get_drvdata(&pdev->dev);
1803}
1804
1805static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1806{
1807 dev_set_drvdata(&pdev->dev, data);
1808}
1809
1810static inline const char *pci_name(const struct pci_dev *pdev)
1811{
1812 return dev_name(&pdev->dev);
1813}
1814
1815
1816
1817
1818
1819
1820#ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1821void pci_resource_to_user(const struct pci_dev *dev, int bar,
1822 const struct resource *rsrc,
1823 resource_size_t *start, resource_size_t *end);
1824#else
1825static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1826 const struct resource *rsrc, resource_size_t *start,
1827 resource_size_t *end)
1828{
1829 *start = rsrc->start;
1830 *end = rsrc->end;
1831}
1832#endif
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842struct pci_fixup {
1843 u16 vendor;
1844 u16 device;
1845 u32 class;
1846 unsigned int class_shift;
1847#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1848 int hook_offset;
1849#else
1850 void (*hook)(struct pci_dev *dev);
1851#endif
1852};
1853
1854enum pci_fixup_pass {
1855 pci_fixup_early,
1856 pci_fixup_header,
1857 pci_fixup_final,
1858 pci_fixup_enable,
1859 pci_fixup_resume,
1860 pci_fixup_suspend,
1861 pci_fixup_resume_early,
1862 pci_fixup_suspend_late,
1863};
1864
1865#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS
1866#define __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1867 class_shift, hook) \
1868 __ADDRESSABLE(hook) \
1869 asm(".section " #sec ", \"a\" \n" \
1870 ".balign 16 \n" \
1871 ".short " #vendor ", " #device " \n" \
1872 ".long " #class ", " #class_shift " \n" \
1873 ".long " #hook " - . \n" \
1874 ".previous \n");
1875#define DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1876 class_shift, hook) \
1877 __DECLARE_PCI_FIXUP_SECTION(sec, name, vendor, device, class, \
1878 class_shift, hook)
1879#else
1880
1881#define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1882 class_shift, hook) \
1883 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1884 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1885 = { vendor, device, class, class_shift, hook };
1886#endif
1887
1888#define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1889 class_shift, hook) \
1890 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1891 hook, vendor, device, class, class_shift, hook)
1892#define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1893 class_shift, hook) \
1894 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1895 hook, vendor, device, class, class_shift, hook)
1896#define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1897 class_shift, hook) \
1898 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1899 hook, vendor, device, class, class_shift, hook)
1900#define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1901 class_shift, hook) \
1902 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1903 hook, vendor, device, class, class_shift, hook)
1904#define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1905 class_shift, hook) \
1906 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1907 resume##hook, vendor, device, class, class_shift, hook)
1908#define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1909 class_shift, hook) \
1910 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1911 resume_early##hook, vendor, device, class, class_shift, hook)
1912#define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1913 class_shift, hook) \
1914 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1915 suspend##hook, vendor, device, class, class_shift, hook)
1916#define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1917 class_shift, hook) \
1918 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1919 suspend_late##hook, vendor, device, class, class_shift, hook)
1920
1921#define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1922 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1923 hook, vendor, device, PCI_ANY_ID, 0, hook)
1924#define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1925 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1926 hook, vendor, device, PCI_ANY_ID, 0, hook)
1927#define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1928 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1929 hook, vendor, device, PCI_ANY_ID, 0, hook)
1930#define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1931 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1932 hook, vendor, device, PCI_ANY_ID, 0, hook)
1933#define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1934 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1935 resume##hook, vendor, device, PCI_ANY_ID, 0, hook)
1936#define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1937 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1938 resume_early##hook, vendor, device, PCI_ANY_ID, 0, hook)
1939#define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1940 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1941 suspend##hook, vendor, device, PCI_ANY_ID, 0, hook)
1942#define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1943 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1944 suspend_late##hook, vendor, device, PCI_ANY_ID, 0, hook)
1945
1946#ifdef CONFIG_PCI_QUIRKS
1947void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1948#else
1949static inline void pci_fixup_device(enum pci_fixup_pass pass,
1950 struct pci_dev *dev) { }
1951#endif
1952
1953void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1954void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1955void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1956int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1957int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1958 const char *name);
1959void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1960
1961extern int pci_pci_problems;
1962#define PCIPCI_FAIL 1
1963#define PCIPCI_TRITON 2
1964#define PCIPCI_NATOMA 4
1965#define PCIPCI_VIAETBF 8
1966#define PCIPCI_VSFX 16
1967#define PCIPCI_ALIMAGIK 32
1968#define PCIAGP_FAIL 64
1969
1970extern unsigned long pci_cardbus_io_size;
1971extern unsigned long pci_cardbus_mem_size;
1972extern u8 pci_dfl_cache_line_size;
1973extern u8 pci_cache_line_size;
1974
1975extern unsigned long pci_hotplug_io_size;
1976extern unsigned long pci_hotplug_mem_size;
1977extern unsigned long pci_hotplug_bus_size;
1978
1979
1980void pcibios_disable_device(struct pci_dev *dev);
1981void pcibios_set_master(struct pci_dev *dev);
1982int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1983 enum pcie_reset_state state);
1984int pcibios_add_device(struct pci_dev *dev);
1985void pcibios_release_device(struct pci_dev *dev);
1986#ifdef CONFIG_PCI
1987void pcibios_penalize_isa_irq(int irq, int active);
1988#else
1989static inline void pcibios_penalize_isa_irq(int irq, int active) {}
1990#endif
1991int pcibios_alloc_irq(struct pci_dev *dev);
1992void pcibios_free_irq(struct pci_dev *dev);
1993resource_size_t pcibios_default_alignment(void);
1994
1995#ifdef CONFIG_HIBERNATE_CALLBACKS
1996extern struct dev_pm_ops pcibios_pm_ops;
1997#endif
1998
1999#if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
2000void __init pci_mmcfg_early_init(void);
2001void __init pci_mmcfg_late_init(void);
2002#else
2003static inline void pci_mmcfg_early_init(void) { }
2004static inline void pci_mmcfg_late_init(void) { }
2005#endif
2006
2007int pci_ext_cfg_avail(void);
2008
2009void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
2010void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
2011
2012#ifdef CONFIG_PCI_IOV
2013int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
2014int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
2015
2016int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
2017void pci_disable_sriov(struct pci_dev *dev);
2018int pci_iov_add_virtfn(struct pci_dev *dev, int id);
2019void pci_iov_remove_virtfn(struct pci_dev *dev, int id);
2020int pci_num_vf(struct pci_dev *dev);
2021int pci_vfs_assigned(struct pci_dev *dev);
2022int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
2023int pci_sriov_get_totalvfs(struct pci_dev *dev);
2024int pci_sriov_configure_simple(struct pci_dev *dev, int nr_virtfn);
2025resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
2026void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe);
2027
2028
2029int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs);
2030int pcibios_sriov_disable(struct pci_dev *pdev);
2031resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
2032#else
2033static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
2034{
2035 return -ENOSYS;
2036}
2037static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
2038{
2039 return -ENOSYS;
2040}
2041static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
2042{ return -ENODEV; }
2043static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id)
2044{
2045 return -ENOSYS;
2046}
2047static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
2048 int id) { }
2049static inline void pci_disable_sriov(struct pci_dev *dev) { }
2050static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
2051static inline int pci_vfs_assigned(struct pci_dev *dev)
2052{ return 0; }
2053static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
2054{ return 0; }
2055static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
2056{ return 0; }
2057#define pci_sriov_configure_simple NULL
2058static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
2059{ return 0; }
2060static inline void pci_vf_drivers_autoprobe(struct pci_dev *dev, bool probe) { }
2061#endif
2062
2063#if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
2064void pci_hp_create_module_link(struct pci_slot *pci_slot);
2065void pci_hp_remove_module_link(struct pci_slot *pci_slot);
2066#endif
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078
2079static inline int pci_pcie_cap(struct pci_dev *dev)
2080{
2081 return dev->pcie_cap;
2082}
2083
2084
2085
2086
2087
2088
2089
2090static inline bool pci_is_pcie(struct pci_dev *dev)
2091{
2092 return pci_pcie_cap(dev);
2093}
2094
2095
2096
2097
2098
2099static inline u16 pcie_caps_reg(const struct pci_dev *dev)
2100{
2101 return dev->pcie_flags_reg;
2102}
2103
2104
2105
2106
2107
2108static inline int pci_pcie_type(const struct pci_dev *dev)
2109{
2110 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
2111}
2112
2113static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
2114{
2115 while (1) {
2116 if (!pci_is_pcie(dev))
2117 break;
2118 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
2119 return dev;
2120 if (!dev->bus->self)
2121 break;
2122 dev = dev->bus->self;
2123 }
2124 return NULL;
2125}
2126
2127void pci_request_acs(void);
2128bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2129bool pci_acs_path_enabled(struct pci_dev *start,
2130 struct pci_dev *end, u16 acs_flags);
2131int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask);
2132
2133#define PCI_VPD_LRDT 0x80
2134#define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2135
2136
2137#define PCI_VPD_LTIN_ID_STRING 0x02
2138#define PCI_VPD_LTIN_RO_DATA 0x10
2139#define PCI_VPD_LTIN_RW_DATA 0x11
2140
2141#define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2142#define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2143#define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2144
2145
2146#define PCI_VPD_STIN_END 0x0f
2147
2148#define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2149
2150#define PCI_VPD_SRDT_TIN_MASK 0x78
2151#define PCI_VPD_SRDT_LEN_MASK 0x07
2152#define PCI_VPD_LRDT_TIN_MASK 0x7f
2153
2154#define PCI_VPD_LRDT_TAG_SIZE 3
2155#define PCI_VPD_SRDT_TAG_SIZE 1
2156
2157#define PCI_VPD_INFO_FLD_HDR_SIZE 3
2158
2159#define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2160#define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2161#define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2162#define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2163
2164
2165
2166
2167
2168
2169
2170static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2171{
2172 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2173}
2174
2175
2176
2177
2178
2179
2180
2181static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2182{
2183 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2184}
2185
2186
2187
2188
2189
2190
2191
2192static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2193{
2194 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2195}
2196
2197
2198
2199
2200
2201
2202
2203static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2204{
2205 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2206}
2207
2208
2209
2210
2211
2212
2213
2214static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2215{
2216 return info_field[2];
2217}
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2242 unsigned int len, const char *kw);
2243
2244
2245#ifdef CONFIG_OF
2246struct device_node;
2247struct irq_domain;
2248void pci_set_of_node(struct pci_dev *dev);
2249void pci_release_of_node(struct pci_dev *dev);
2250void pci_set_bus_of_node(struct pci_bus *bus);
2251void pci_release_bus_of_node(struct pci_bus *bus);
2252struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2253int pci_parse_request_of_pci_ranges(struct device *dev,
2254 struct list_head *resources,
2255 struct resource **bus_range);
2256
2257
2258struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2259
2260#else
2261static inline void pci_set_of_node(struct pci_dev *dev) { }
2262static inline void pci_release_of_node(struct pci_dev *dev) { }
2263static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2264static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2265static inline struct irq_domain *
2266pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2267static inline int pci_parse_request_of_pci_ranges(struct device *dev,
2268 struct list_head *resources,
2269 struct resource **bus_range)
2270{
2271 return -EINVAL;
2272}
2273#endif
2274
2275static inline struct device_node *
2276pci_device_to_OF_node(const struct pci_dev *pdev)
2277{
2278 return pdev ? pdev->dev.of_node : NULL;
2279}
2280
2281static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2282{
2283 return bus ? bus->dev.of_node : NULL;
2284}
2285
2286#ifdef CONFIG_ACPI
2287struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2288
2289void
2290pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2291#else
2292static inline struct irq_domain *
2293pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2294#endif
2295
2296#ifdef CONFIG_EEH
2297static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2298{
2299 return pdev->dev.archdata.edev;
2300}
2301#endif
2302
2303void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2304bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2305int pci_for_each_dma_alias(struct pci_dev *pdev,
2306 int (*fn)(struct pci_dev *pdev,
2307 u16 alias, void *data), void *data);
2308
2309
2310static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2311{
2312 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2313}
2314static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2315{
2316 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2317}
2318static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2319{
2320 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2321}
2322
2323
2324
2325
2326
2327
2328
2329static inline bool pci_ari_enabled(struct pci_bus *bus)
2330{
2331 return bus->self && bus->self->ari_enabled;
2332}
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2343{
2344 struct pci_dev *parent = pdev;
2345
2346 if (pdev->is_thunderbolt)
2347 return true;
2348
2349 while ((parent = pci_upstream_bridge(parent)))
2350 if (parent->is_thunderbolt)
2351 return true;
2352
2353 return false;
2354}
2355
2356#if defined(CONFIG_PCIEPORTBUS) || defined(CONFIG_EEH)
2357void pci_uevent_ers(struct pci_dev *pdev, enum pci_ers_result err_type);
2358#endif
2359
2360
2361#include <linux/pci-dma-compat.h>
2362
2363#define pci_printk(level, pdev, fmt, arg...) \
2364 dev_printk(level, &(pdev)->dev, fmt, ##arg)
2365
2366#define pci_emerg(pdev, fmt, arg...) dev_emerg(&(pdev)->dev, fmt, ##arg)
2367#define pci_alert(pdev, fmt, arg...) dev_alert(&(pdev)->dev, fmt, ##arg)
2368#define pci_crit(pdev, fmt, arg...) dev_crit(&(pdev)->dev, fmt, ##arg)
2369#define pci_err(pdev, fmt, arg...) dev_err(&(pdev)->dev, fmt, ##arg)
2370#define pci_warn(pdev, fmt, arg...) dev_warn(&(pdev)->dev, fmt, ##arg)
2371#define pci_notice(pdev, fmt, arg...) dev_notice(&(pdev)->dev, fmt, ##arg)
2372#define pci_info(pdev, fmt, arg...) dev_info(&(pdev)->dev, fmt, ##arg)
2373#define pci_dbg(pdev, fmt, arg...) dev_dbg(&(pdev)->dev, fmt, ##arg)
2374
2375#define pci_notice_ratelimited(pdev, fmt, arg...) \
2376 dev_notice_ratelimited(&(pdev)->dev, fmt, ##arg)
2377
2378#endif
2379