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33#ifndef _QED_IF_H
34#define _QED_IF_H
35
36#include <linux/types.h>
37#include <linux/interrupt.h>
38#include <linux/netdevice.h>
39#include <linux/pci.h>
40#include <linux/skbuff.h>
41#include <asm/byteorder.h>
42#include <linux/io.h>
43#include <linux/compiler.h>
44#include <linux/kernel.h>
45#include <linux/list.h>
46#include <linux/slab.h>
47#include <linux/qed/common_hsi.h>
48#include <linux/qed/qed_chain.h>
49#include <linux/io-64-nonatomic-lo-hi.h>
50
51enum dcbx_protocol_type {
52 DCBX_PROTOCOL_ISCSI,
53 DCBX_PROTOCOL_FCOE,
54 DCBX_PROTOCOL_ROCE,
55 DCBX_PROTOCOL_ROCE_V2,
56 DCBX_PROTOCOL_ETH,
57 DCBX_MAX_PROTOCOL_TYPE
58};
59
60#define QED_ROCE_PROTOCOL_INDEX (3)
61
62#define QED_LLDP_CHASSIS_ID_STAT_LEN 4
63#define QED_LLDP_PORT_ID_STAT_LEN 4
64#define QED_DCBX_MAX_APP_PROTOCOL 32
65#define QED_MAX_PFC_PRIORITIES 8
66#define QED_DCBX_DSCP_SIZE 64
67
68struct qed_dcbx_lldp_remote {
69 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
70 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
71 bool enable_rx;
72 bool enable_tx;
73 u32 tx_interval;
74 u32 max_credit;
75};
76
77struct qed_dcbx_lldp_local {
78 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
79 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
80};
81
82struct qed_dcbx_app_prio {
83 u8 roce;
84 u8 roce_v2;
85 u8 fcoe;
86 u8 iscsi;
87 u8 eth;
88};
89
90struct qed_dbcx_pfc_params {
91 bool willing;
92 bool enabled;
93 u8 prio[QED_MAX_PFC_PRIORITIES];
94 u8 max_tc;
95};
96
97enum qed_dcbx_sf_ieee_type {
98 QED_DCBX_SF_IEEE_ETHTYPE,
99 QED_DCBX_SF_IEEE_TCP_PORT,
100 QED_DCBX_SF_IEEE_UDP_PORT,
101 QED_DCBX_SF_IEEE_TCP_UDP_PORT
102};
103
104struct qed_app_entry {
105 bool ethtype;
106 enum qed_dcbx_sf_ieee_type sf_ieee;
107 bool enabled;
108 u8 prio;
109 u16 proto_id;
110 enum dcbx_protocol_type proto_type;
111};
112
113struct qed_dcbx_params {
114 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
115 u16 num_app_entries;
116 bool app_willing;
117 bool app_valid;
118 bool app_error;
119 bool ets_willing;
120 bool ets_enabled;
121 bool ets_cbs;
122 bool valid;
123 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
124 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
125 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
126 struct qed_dbcx_pfc_params pfc;
127 u8 max_ets_tc;
128};
129
130struct qed_dcbx_admin_params {
131 struct qed_dcbx_params params;
132 bool valid;
133};
134
135struct qed_dcbx_remote_params {
136 struct qed_dcbx_params params;
137 bool valid;
138};
139
140struct qed_dcbx_operational_params {
141 struct qed_dcbx_app_prio app_prio;
142 struct qed_dcbx_params params;
143 bool valid;
144 bool enabled;
145 bool ieee;
146 bool cee;
147 bool local;
148 u32 err;
149};
150
151struct qed_dcbx_get {
152 struct qed_dcbx_operational_params operational;
153 struct qed_dcbx_lldp_remote lldp_remote;
154 struct qed_dcbx_lldp_local lldp_local;
155 struct qed_dcbx_remote_params remote;
156 struct qed_dcbx_admin_params local;
157};
158
159enum qed_nvm_images {
160 QED_NVM_IMAGE_ISCSI_CFG,
161 QED_NVM_IMAGE_FCOE_CFG,
162 QED_NVM_IMAGE_NVM_CFG1,
163 QED_NVM_IMAGE_DEFAULT_CFG,
164 QED_NVM_IMAGE_NVM_META,
165};
166
167struct qed_link_eee_params {
168 u32 tx_lpi_timer;
169#define QED_EEE_1G_ADV BIT(0)
170#define QED_EEE_10G_ADV BIT(1)
171
172
173 u8 adv_caps;
174 u8 lp_adv_caps;
175 bool enable;
176 bool tx_lpi_enable;
177};
178
179enum qed_led_mode {
180 QED_LED_MODE_OFF,
181 QED_LED_MODE_ON,
182 QED_LED_MODE_RESTORE
183};
184
185struct qed_mfw_tlv_eth {
186 u16 lso_maxoff_size;
187 bool lso_maxoff_size_set;
188 u16 lso_minseg_size;
189 bool lso_minseg_size_set;
190 u8 prom_mode;
191 bool prom_mode_set;
192 u16 tx_descr_size;
193 bool tx_descr_size_set;
194 u16 rx_descr_size;
195 bool rx_descr_size_set;
196 u16 netq_count;
197 bool netq_count_set;
198 u32 tcp4_offloads;
199 bool tcp4_offloads_set;
200 u32 tcp6_offloads;
201 bool tcp6_offloads_set;
202 u16 tx_descr_qdepth;
203 bool tx_descr_qdepth_set;
204 u16 rx_descr_qdepth;
205 bool rx_descr_qdepth_set;
206 u8 iov_offload;
207#define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
208#define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
209#define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
210#define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
211 bool iov_offload_set;
212 u8 txqs_empty;
213 bool txqs_empty_set;
214 u8 rxqs_empty;
215 bool rxqs_empty_set;
216 u8 num_txqs_full;
217 bool num_txqs_full_set;
218 u8 num_rxqs_full;
219 bool num_rxqs_full_set;
220};
221
222#define QED_MFW_TLV_TIME_SIZE 14
223struct qed_mfw_tlv_time {
224 bool b_set;
225 u8 month;
226 u8 day;
227 u8 hour;
228 u8 min;
229 u16 msec;
230 u16 usec;
231};
232
233struct qed_mfw_tlv_fcoe {
234 u8 scsi_timeout;
235 bool scsi_timeout_set;
236 u32 rt_tov;
237 bool rt_tov_set;
238 u32 ra_tov;
239 bool ra_tov_set;
240 u32 ed_tov;
241 bool ed_tov_set;
242 u32 cr_tov;
243 bool cr_tov_set;
244 u8 boot_type;
245 bool boot_type_set;
246 u8 npiv_state;
247 bool npiv_state_set;
248 u32 num_npiv_ids;
249 bool num_npiv_ids_set;
250 u8 switch_name[8];
251 bool switch_name_set;
252 u16 switch_portnum;
253 bool switch_portnum_set;
254 u8 switch_portid[3];
255 bool switch_portid_set;
256 u8 vendor_name[8];
257 bool vendor_name_set;
258 u8 switch_model[8];
259 bool switch_model_set;
260 u8 switch_fw_version[8];
261 bool switch_fw_version_set;
262 u8 qos_pri;
263 bool qos_pri_set;
264 u8 port_alias[3];
265 bool port_alias_set;
266 u8 port_state;
267#define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
268#define QED_MFW_TLV_PORT_STATE_LOOP (1)
269#define QED_MFW_TLV_PORT_STATE_P2P (2)
270#define QED_MFW_TLV_PORT_STATE_FABRIC (3)
271 bool port_state_set;
272 u16 fip_tx_descr_size;
273 bool fip_tx_descr_size_set;
274 u16 fip_rx_descr_size;
275 bool fip_rx_descr_size_set;
276 u16 link_failures;
277 bool link_failures_set;
278 u8 fcoe_boot_progress;
279 bool fcoe_boot_progress_set;
280 u64 rx_bcast;
281 bool rx_bcast_set;
282 u64 tx_bcast;
283 bool tx_bcast_set;
284 u16 fcoe_txq_depth;
285 bool fcoe_txq_depth_set;
286 u16 fcoe_rxq_depth;
287 bool fcoe_rxq_depth_set;
288 u64 fcoe_rx_frames;
289 bool fcoe_rx_frames_set;
290 u64 fcoe_rx_bytes;
291 bool fcoe_rx_bytes_set;
292 u64 fcoe_tx_frames;
293 bool fcoe_tx_frames_set;
294 u64 fcoe_tx_bytes;
295 bool fcoe_tx_bytes_set;
296 u16 crc_count;
297 bool crc_count_set;
298 u32 crc_err_src_fcid[5];
299 bool crc_err_src_fcid_set[5];
300 struct qed_mfw_tlv_time crc_err[5];
301 u16 losync_err;
302 bool losync_err_set;
303 u16 losig_err;
304 bool losig_err_set;
305 u16 primtive_err;
306 bool primtive_err_set;
307 u16 disparity_err;
308 bool disparity_err_set;
309 u16 code_violation_err;
310 bool code_violation_err_set;
311 u32 flogi_param[4];
312 bool flogi_param_set[4];
313 struct qed_mfw_tlv_time flogi_tstamp;
314 u32 flogi_acc_param[4];
315 bool flogi_acc_param_set[4];
316 struct qed_mfw_tlv_time flogi_acc_tstamp;
317 u32 flogi_rjt;
318 bool flogi_rjt_set;
319 struct qed_mfw_tlv_time flogi_rjt_tstamp;
320 u32 fdiscs;
321 bool fdiscs_set;
322 u8 fdisc_acc;
323 bool fdisc_acc_set;
324 u8 fdisc_rjt;
325 bool fdisc_rjt_set;
326 u8 plogi;
327 bool plogi_set;
328 u8 plogi_acc;
329 bool plogi_acc_set;
330 u8 plogi_rjt;
331 bool plogi_rjt_set;
332 u32 plogi_dst_fcid[5];
333 bool plogi_dst_fcid_set[5];
334 struct qed_mfw_tlv_time plogi_tstamp[5];
335 u32 plogi_acc_src_fcid[5];
336 bool plogi_acc_src_fcid_set[5];
337 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
338 u8 tx_plogos;
339 bool tx_plogos_set;
340 u8 plogo_acc;
341 bool plogo_acc_set;
342 u8 plogo_rjt;
343 bool plogo_rjt_set;
344 u32 plogo_src_fcid[5];
345 bool plogo_src_fcid_set[5];
346 struct qed_mfw_tlv_time plogo_tstamp[5];
347 u8 rx_logos;
348 bool rx_logos_set;
349 u8 tx_accs;
350 bool tx_accs_set;
351 u8 tx_prlis;
352 bool tx_prlis_set;
353 u8 rx_accs;
354 bool rx_accs_set;
355 u8 tx_abts;
356 bool tx_abts_set;
357 u8 rx_abts_acc;
358 bool rx_abts_acc_set;
359 u8 rx_abts_rjt;
360 bool rx_abts_rjt_set;
361 u32 abts_dst_fcid[5];
362 bool abts_dst_fcid_set[5];
363 struct qed_mfw_tlv_time abts_tstamp[5];
364 u8 rx_rscn;
365 bool rx_rscn_set;
366 u32 rx_rscn_nport[4];
367 bool rx_rscn_nport_set[4];
368 u8 tx_lun_rst;
369 bool tx_lun_rst_set;
370 u8 abort_task_sets;
371 bool abort_task_sets_set;
372 u8 tx_tprlos;
373 bool tx_tprlos_set;
374 u8 tx_nos;
375 bool tx_nos_set;
376 u8 rx_nos;
377 bool rx_nos_set;
378 u8 ols;
379 bool ols_set;
380 u8 lr;
381 bool lr_set;
382 u8 lrr;
383 bool lrr_set;
384 u8 tx_lip;
385 bool tx_lip_set;
386 u8 rx_lip;
387 bool rx_lip_set;
388 u8 eofa;
389 bool eofa_set;
390 u8 eofni;
391 bool eofni_set;
392 u8 scsi_chks;
393 bool scsi_chks_set;
394 u8 scsi_cond_met;
395 bool scsi_cond_met_set;
396 u8 scsi_busy;
397 bool scsi_busy_set;
398 u8 scsi_inter;
399 bool scsi_inter_set;
400 u8 scsi_inter_cond_met;
401 bool scsi_inter_cond_met_set;
402 u8 scsi_rsv_conflicts;
403 bool scsi_rsv_conflicts_set;
404 u8 scsi_tsk_full;
405 bool scsi_tsk_full_set;
406 u8 scsi_aca_active;
407 bool scsi_aca_active_set;
408 u8 scsi_tsk_abort;
409 bool scsi_tsk_abort_set;
410 u32 scsi_rx_chk[5];
411 bool scsi_rx_chk_set[5];
412 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
413};
414
415struct qed_mfw_tlv_iscsi {
416 u8 target_llmnr;
417 bool target_llmnr_set;
418 u8 header_digest;
419 bool header_digest_set;
420 u8 data_digest;
421 bool data_digest_set;
422 u8 auth_method;
423#define QED_MFW_TLV_AUTH_METHOD_NONE (1)
424#define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
425#define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
426 bool auth_method_set;
427 u16 boot_taget_portal;
428 bool boot_taget_portal_set;
429 u16 frame_size;
430 bool frame_size_set;
431 u16 tx_desc_size;
432 bool tx_desc_size_set;
433 u16 rx_desc_size;
434 bool rx_desc_size_set;
435 u8 boot_progress;
436 bool boot_progress_set;
437 u16 tx_desc_qdepth;
438 bool tx_desc_qdepth_set;
439 u16 rx_desc_qdepth;
440 bool rx_desc_qdepth_set;
441 u64 rx_frames;
442 bool rx_frames_set;
443 u64 rx_bytes;
444 bool rx_bytes_set;
445 u64 tx_frames;
446 bool tx_frames_set;
447 u64 tx_bytes;
448 bool tx_bytes_set;
449};
450
451enum qed_db_rec_width {
452 DB_REC_WIDTH_32B,
453 DB_REC_WIDTH_64B,
454};
455
456enum qed_db_rec_space {
457 DB_REC_KERNEL,
458 DB_REC_USER,
459};
460
461#define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
462 (void __iomem *)(reg_addr))
463
464#define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
465
466#define DIRECT_REG_WR64(reg_addr, val) writeq((u32)val, \
467 (void __iomem *)(reg_addr))
468
469#define QED_COALESCE_MAX 0x1FF
470#define QED_DEFAULT_RX_USECS 12
471#define QED_DEFAULT_TX_USECS 48
472
473
474struct qed_dev;
475
476struct qed_eth_pf_params {
477
478
479
480
481 u16 num_cons;
482
483
484 u8 num_vf_cons;
485#define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
486
487
488
489
490
491 u32 num_arfs_filters;
492};
493
494struct qed_fcoe_pf_params {
495
496 u64 glbl_q_params_addr;
497 u64 bdq_pbl_base_addr[2];
498
499
500
501
502
503 u16 num_cons;
504 u16 num_tasks;
505
506
507 u16 sq_num_pbl_pages;
508
509 u16 cq_num_entries;
510 u16 cmdq_num_entries;
511 u16 rq_buffer_log_size;
512 u16 mtu;
513 u16 dummy_icid;
514 u16 bdq_xoff_threshold[2];
515 u16 bdq_xon_threshold[2];
516 u16 rq_buffer_size;
517 u8 num_cqs;
518 u8 log_page_size;
519 u8 gl_rq_pi;
520 u8 gl_cmd_pi;
521 u8 debug_mode;
522 u8 is_target;
523 u8 bdq_pbl_num_entries[2];
524};
525
526
527struct qed_iscsi_pf_params {
528 u64 glbl_q_params_addr;
529 u64 bdq_pbl_base_addr[3];
530 u16 cq_num_entries;
531 u16 cmdq_num_entries;
532 u32 two_msl_timer;
533 u16 tx_sws_timer;
534
535
536
537
538
539 u16 num_cons;
540 u16 num_tasks;
541
542
543 u16 half_way_close_timeout;
544 u16 bdq_xoff_threshold[3];
545 u16 bdq_xon_threshold[3];
546 u16 cmdq_xoff_threshold;
547 u16 cmdq_xon_threshold;
548 u16 rq_buffer_size;
549
550 u8 num_sq_pages_in_ring;
551 u8 num_r2tq_pages_in_ring;
552 u8 num_uhq_pages_in_ring;
553 u8 num_queues;
554 u8 log_page_size;
555 u8 rqe_log_size;
556 u8 max_fin_rt;
557 u8 gl_rq_pi;
558 u8 gl_cmd_pi;
559 u8 debug_mode;
560 u8 ll2_ooo_queue_id;
561
562 u8 is_target;
563 u8 is_soc_en;
564 u8 soc_num_of_blocks_log;
565 u8 bdq_pbl_num_entries[3];
566};
567
568struct qed_rdma_pf_params {
569
570
571
572 u32 min_dpis;
573 u32 num_qps;
574 u32 num_srqs;
575 u8 roce_edpm_mode;
576 u8 gl_pi;
577
578
579 u8 enable_dcqcn;
580};
581
582struct qed_pf_params {
583 struct qed_eth_pf_params eth_pf_params;
584 struct qed_fcoe_pf_params fcoe_pf_params;
585 struct qed_iscsi_pf_params iscsi_pf_params;
586 struct qed_rdma_pf_params rdma_pf_params;
587};
588
589enum qed_int_mode {
590 QED_INT_MODE_INTA,
591 QED_INT_MODE_MSIX,
592 QED_INT_MODE_MSI,
593 QED_INT_MODE_POLL,
594};
595
596struct qed_sb_info {
597 struct status_block_e4 *sb_virt;
598 dma_addr_t sb_phys;
599 u32 sb_ack;
600 u16 igu_sb_id;
601 void __iomem *igu_addr;
602 u8 flags;
603#define QED_SB_INFO_INIT 0x1
604#define QED_SB_INFO_SETUP 0x2
605
606 struct qed_dev *cdev;
607};
608
609enum qed_dev_type {
610 QED_DEV_TYPE_BB,
611 QED_DEV_TYPE_AH,
612};
613
614struct qed_dev_info {
615 unsigned long pci_mem_start;
616 unsigned long pci_mem_end;
617 unsigned int pci_irq;
618 u8 num_hwfns;
619
620 u8 hw_mac[ETH_ALEN];
621
622
623 u16 fw_major;
624 u16 fw_minor;
625 u16 fw_rev;
626 u16 fw_eng;
627
628
629 u32 mfw_rev;
630#define QED_MFW_VERSION_0_MASK 0x000000FF
631#define QED_MFW_VERSION_0_OFFSET 0
632#define QED_MFW_VERSION_1_MASK 0x0000FF00
633#define QED_MFW_VERSION_1_OFFSET 8
634#define QED_MFW_VERSION_2_MASK 0x00FF0000
635#define QED_MFW_VERSION_2_OFFSET 16
636#define QED_MFW_VERSION_3_MASK 0xFF000000
637#define QED_MFW_VERSION_3_OFFSET 24
638
639 u32 flash_size;
640 bool b_inter_pf_switch;
641 bool tx_switching;
642 bool rdma_supported;
643 u16 mtu;
644
645 bool wol_support;
646 bool smart_an;
647
648
649 u32 mbi_version;
650#define QED_MBI_VERSION_0_MASK 0x000000FF
651#define QED_MBI_VERSION_0_OFFSET 0
652#define QED_MBI_VERSION_1_MASK 0x0000FF00
653#define QED_MBI_VERSION_1_OFFSET 8
654#define QED_MBI_VERSION_2_MASK 0x00FF0000
655#define QED_MBI_VERSION_2_OFFSET 16
656
657 enum qed_dev_type dev_type;
658
659
660 bool vxlan_enable;
661 bool gre_enable;
662 bool geneve_enable;
663
664 u8 abs_pf_id;
665};
666
667enum qed_sb_type {
668 QED_SB_TYPE_L2_QUEUE,
669 QED_SB_TYPE_CNQ,
670 QED_SB_TYPE_STORAGE,
671};
672
673enum qed_protocol {
674 QED_PROTOCOL_ETH,
675 QED_PROTOCOL_ISCSI,
676 QED_PROTOCOL_FCOE,
677};
678
679enum qed_link_mode_bits {
680 QED_LM_FIBRE_BIT = BIT(0),
681 QED_LM_Autoneg_BIT = BIT(1),
682 QED_LM_Asym_Pause_BIT = BIT(2),
683 QED_LM_Pause_BIT = BIT(3),
684 QED_LM_1000baseT_Full_BIT = BIT(4),
685 QED_LM_10000baseT_Full_BIT = BIT(5),
686 QED_LM_10000baseKR_Full_BIT = BIT(6),
687 QED_LM_20000baseKR2_Full_BIT = BIT(7),
688 QED_LM_25000baseKR_Full_BIT = BIT(8),
689 QED_LM_40000baseLR4_Full_BIT = BIT(9),
690 QED_LM_50000baseKR2_Full_BIT = BIT(10),
691 QED_LM_100000baseKR4_Full_BIT = BIT(11),
692 QED_LM_2500baseX_Full_BIT = BIT(12),
693 QED_LM_Backplane_BIT = BIT(13),
694 QED_LM_1000baseKX_Full_BIT = BIT(14),
695 QED_LM_10000baseKX4_Full_BIT = BIT(15),
696 QED_LM_10000baseR_FEC_BIT = BIT(16),
697 QED_LM_40000baseKR4_Full_BIT = BIT(17),
698 QED_LM_40000baseCR4_Full_BIT = BIT(18),
699 QED_LM_40000baseSR4_Full_BIT = BIT(19),
700 QED_LM_25000baseCR_Full_BIT = BIT(20),
701 QED_LM_25000baseSR_Full_BIT = BIT(21),
702 QED_LM_50000baseCR2_Full_BIT = BIT(22),
703 QED_LM_100000baseSR4_Full_BIT = BIT(23),
704 QED_LM_100000baseCR4_Full_BIT = BIT(24),
705 QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
706 QED_LM_50000baseSR2_Full_BIT = BIT(26),
707 QED_LM_1000baseX_Full_BIT = BIT(27),
708 QED_LM_10000baseCR_Full_BIT = BIT(28),
709 QED_LM_10000baseSR_Full_BIT = BIT(29),
710 QED_LM_10000baseLR_Full_BIT = BIT(30),
711 QED_LM_10000baseLRM_Full_BIT = BIT(31),
712 QED_LM_COUNT = 32
713};
714
715struct qed_link_params {
716 bool link_up;
717
718#define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
719#define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
720#define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
721#define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
722#define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
723#define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
724 u32 override_flags;
725 bool autoneg;
726 u32 adv_speeds;
727 u32 forced_speed;
728#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
729#define QED_LINK_PAUSE_RX_ENABLE BIT(1)
730#define QED_LINK_PAUSE_TX_ENABLE BIT(2)
731 u32 pause_config;
732#define QED_LINK_LOOPBACK_NONE BIT(0)
733#define QED_LINK_LOOPBACK_INT_PHY BIT(1)
734#define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
735#define QED_LINK_LOOPBACK_EXT BIT(3)
736#define QED_LINK_LOOPBACK_MAC BIT(4)
737 u32 loopback_mode;
738 struct qed_link_eee_params eee;
739};
740
741struct qed_link_output {
742 bool link_up;
743
744
745 u32 supported_caps;
746 u32 advertised_caps;
747 u32 lp_caps;
748
749 u32 speed;
750 u8 duplex;
751 u8 port;
752 bool autoneg;
753 u32 pause_config;
754
755
756 bool eee_supported;
757 bool eee_active;
758 u8 sup_caps;
759 struct qed_link_eee_params eee;
760};
761
762struct qed_probe_params {
763 enum qed_protocol protocol;
764 u32 dp_module;
765 u8 dp_level;
766 bool is_vf;
767 bool recov_in_prog;
768};
769
770#define QED_DRV_VER_STR_SIZE 12
771struct qed_slowpath_params {
772 u32 int_mode;
773 u8 drv_major;
774 u8 drv_minor;
775 u8 drv_rev;
776 u8 drv_eng;
777 u8 name[QED_DRV_VER_STR_SIZE];
778};
779
780#define ILT_PAGE_SIZE_TCFC 0x8000
781
782struct qed_int_info {
783 struct msix_entry *msix;
784 u8 msix_cnt;
785
786
787 u8 used_cnt;
788};
789
790struct qed_generic_tlvs {
791#define QED_TLV_IP_CSUM BIT(0)
792#define QED_TLV_LSO BIT(1)
793 u16 feat_flags;
794#define QED_TLV_MAC_COUNT 3
795 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
796};
797
798#define QED_I2C_DEV_ADDR_A0 0xA0
799#define QED_I2C_DEV_ADDR_A2 0xA2
800
801#define QED_NVM_SIGNATURE 0x12435687
802
803enum qed_nvm_flash_cmd {
804 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
805 QED_NVM_FLASH_CMD_FILE_START = 0x3,
806 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
807 QED_NVM_FLASH_CMD_NVM_MAX,
808};
809
810struct qed_common_cb_ops {
811 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
812 void (*link_update)(void *dev,
813 struct qed_link_output *link);
814 void (*schedule_recovery_handler)(void *dev);
815 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
816 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
817 void (*get_protocol_tlv_data)(void *dev, void *data);
818};
819
820struct qed_selftest_ops {
821
822
823
824
825
826
827
828 int (*selftest_interrupt)(struct qed_dev *cdev);
829
830
831
832
833
834
835
836
837 int (*selftest_memory)(struct qed_dev *cdev);
838
839
840
841
842
843
844
845
846 int (*selftest_register)(struct qed_dev *cdev);
847
848
849
850
851
852
853
854
855 int (*selftest_clock)(struct qed_dev *cdev);
856
857
858
859
860
861
862
863
864 int (*selftest_nvram) (struct qed_dev *cdev);
865};
866
867struct qed_common_ops {
868 struct qed_selftest_ops *selftest;
869
870 struct qed_dev* (*probe)(struct pci_dev *dev,
871 struct qed_probe_params *params);
872
873 void (*remove)(struct qed_dev *cdev);
874
875 int (*set_power_state)(struct qed_dev *cdev,
876 pci_power_t state);
877
878 void (*set_name) (struct qed_dev *cdev, char name[]);
879
880
881
882
883
884 void (*update_pf_params)(struct qed_dev *cdev,
885 struct qed_pf_params *params);
886 int (*slowpath_start)(struct qed_dev *cdev,
887 struct qed_slowpath_params *params);
888
889 int (*slowpath_stop)(struct qed_dev *cdev);
890
891
892
893
894 int (*set_fp_int)(struct qed_dev *cdev,
895 u16 cnt);
896
897
898 int (*get_fp_int)(struct qed_dev *cdev,
899 struct qed_int_info *info);
900
901 u32 (*sb_init)(struct qed_dev *cdev,
902 struct qed_sb_info *sb_info,
903 void *sb_virt_addr,
904 dma_addr_t sb_phy_addr,
905 u16 sb_id,
906 enum qed_sb_type type);
907
908 u32 (*sb_release)(struct qed_dev *cdev,
909 struct qed_sb_info *sb_info,
910 u16 sb_id);
911
912 void (*simd_handler_config)(struct qed_dev *cdev,
913 void *token,
914 int index,
915 void (*handler)(void *));
916
917 void (*simd_handler_clean)(struct qed_dev *cdev,
918 int index);
919 int (*dbg_grc)(struct qed_dev *cdev,
920 void *buffer, u32 *num_dumped_bytes);
921
922 int (*dbg_grc_size)(struct qed_dev *cdev);
923
924 int (*dbg_all_data) (struct qed_dev *cdev, void *buffer);
925
926 int (*dbg_all_data_size) (struct qed_dev *cdev);
927
928
929
930
931
932
933
934
935 bool (*can_link_change)(struct qed_dev *cdev);
936
937
938
939
940
941
942
943
944
945 int (*set_link)(struct qed_dev *cdev,
946 struct qed_link_params *params);
947
948
949
950
951
952
953
954 void (*get_link)(struct qed_dev *cdev,
955 struct qed_link_output *if_link);
956
957
958
959
960
961
962 int (*drain)(struct qed_dev *cdev);
963
964
965
966
967
968
969
970
971 void (*update_msglvl)(struct qed_dev *cdev,
972 u32 dp_module,
973 u8 dp_level);
974
975 int (*chain_alloc)(struct qed_dev *cdev,
976 enum qed_chain_use_mode intended_use,
977 enum qed_chain_mode mode,
978 enum qed_chain_cnt_type cnt_type,
979 u32 num_elems,
980 size_t elem_size,
981 struct qed_chain *p_chain,
982 struct qed_chain_ext_pbl *ext_pbl);
983
984 void (*chain_free)(struct qed_dev *cdev,
985 struct qed_chain *p_chain);
986
987
988
989
990
991
992
993
994
995 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007 int (*nvm_get_image)(struct qed_dev *cdev,
1008 enum qed_nvm_images type, u8 *buf, u16 len);
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021 int (*set_coalesce)(struct qed_dev *cdev,
1022 u16 rx_coal, u16 tx_coal, void *handle);
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032 int (*set_led)(struct qed_dev *cdev,
1033 enum qed_led_mode mode);
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 int (*db_recovery_add)(struct qed_dev *cdev,
1045 void __iomem *db_addr,
1046 void *db_data,
1047 enum qed_db_rec_width db_width,
1048 enum qed_db_rec_space db_space);
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059 int (*db_recovery_del)(struct qed_dev *cdev,
1060 void __iomem *db_addr, void *db_data);
1061
1062
1063
1064
1065
1066
1067
1068
1069 int (*recovery_process)(struct qed_dev *cdev);
1070
1071
1072
1073
1074
1075
1076
1077
1078 int (*recovery_prolog)(struct qed_dev *cdev);
1079
1080
1081
1082
1083
1084
1085
1086
1087 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1088
1089
1090
1091
1092
1093
1094
1095
1096 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1097
1098
1099
1100
1101
1102
1103
1104
1105 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1106
1107
1108
1109
1110
1111
1112
1113 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124 int (*read_module_eeprom)(struct qed_dev *cdev,
1125 char *buf, u8 dev_addr, u32 offset, u32 len);
1126};
1127
1128#define MASK_FIELD(_name, _value) \
1129 ((_value) &= (_name ## _MASK))
1130
1131#define FIELD_VALUE(_name, _value) \
1132 ((_value & _name ## _MASK) << _name ## _SHIFT)
1133
1134#define SET_FIELD(value, name, flag) \
1135 do { \
1136 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1137 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1138 } while (0)
1139
1140#define GET_FIELD(value, name) \
1141 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1142
1143
1144#define DP_ERR(cdev, fmt, ...) \
1145 do { \
1146 pr_err("[%s:%d(%s)]" fmt, \
1147 __func__, __LINE__, \
1148 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1149 ## __VA_ARGS__); \
1150 } while (0)
1151
1152#define DP_NOTICE(cdev, fmt, ...) \
1153 do { \
1154 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1155 pr_notice("[%s:%d(%s)]" fmt, \
1156 __func__, __LINE__, \
1157 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1158 ## __VA_ARGS__); \
1159 \
1160 } \
1161 } while (0)
1162
1163#define DP_INFO(cdev, fmt, ...) \
1164 do { \
1165 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1166 pr_notice("[%s:%d(%s)]" fmt, \
1167 __func__, __LINE__, \
1168 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1169 ## __VA_ARGS__); \
1170 } \
1171 } while (0)
1172
1173#define DP_VERBOSE(cdev, module, fmt, ...) \
1174 do { \
1175 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1176 ((cdev)->dp_module & module))) { \
1177 pr_notice("[%s:%d(%s)]" fmt, \
1178 __func__, __LINE__, \
1179 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1180 ## __VA_ARGS__); \
1181 } \
1182 } while (0)
1183
1184enum DP_LEVEL {
1185 QED_LEVEL_VERBOSE = 0x0,
1186 QED_LEVEL_INFO = 0x1,
1187 QED_LEVEL_NOTICE = 0x2,
1188 QED_LEVEL_ERR = 0x3,
1189};
1190
1191#define QED_LOG_LEVEL_SHIFT (30)
1192#define QED_LOG_VERBOSE_MASK (0x3fffffff)
1193#define QED_LOG_INFO_MASK (0x40000000)
1194#define QED_LOG_NOTICE_MASK (0x80000000)
1195
1196enum DP_MODULE {
1197 QED_MSG_SPQ = 0x10000,
1198 QED_MSG_STATS = 0x20000,
1199 QED_MSG_DCB = 0x40000,
1200 QED_MSG_IOV = 0x80000,
1201 QED_MSG_SP = 0x100000,
1202 QED_MSG_STORAGE = 0x200000,
1203 QED_MSG_CXT = 0x800000,
1204 QED_MSG_LL2 = 0x1000000,
1205 QED_MSG_ILT = 0x2000000,
1206 QED_MSG_RDMA = 0x4000000,
1207 QED_MSG_DEBUG = 0x8000000,
1208
1209};
1210
1211enum qed_mf_mode {
1212 QED_MF_DEFAULT,
1213 QED_MF_OVLAN,
1214 QED_MF_NPAR,
1215};
1216
1217struct qed_eth_stats_common {
1218 u64 no_buff_discards;
1219 u64 packet_too_big_discard;
1220 u64 ttl0_discard;
1221 u64 rx_ucast_bytes;
1222 u64 rx_mcast_bytes;
1223 u64 rx_bcast_bytes;
1224 u64 rx_ucast_pkts;
1225 u64 rx_mcast_pkts;
1226 u64 rx_bcast_pkts;
1227 u64 mftag_filter_discards;
1228 u64 mac_filter_discards;
1229 u64 gft_filter_drop;
1230 u64 tx_ucast_bytes;
1231 u64 tx_mcast_bytes;
1232 u64 tx_bcast_bytes;
1233 u64 tx_ucast_pkts;
1234 u64 tx_mcast_pkts;
1235 u64 tx_bcast_pkts;
1236 u64 tx_err_drop_pkts;
1237 u64 tpa_coalesced_pkts;
1238 u64 tpa_coalesced_events;
1239 u64 tpa_aborts_num;
1240 u64 tpa_not_coalesced_pkts;
1241 u64 tpa_coalesced_bytes;
1242
1243
1244 u64 rx_64_byte_packets;
1245 u64 rx_65_to_127_byte_packets;
1246 u64 rx_128_to_255_byte_packets;
1247 u64 rx_256_to_511_byte_packets;
1248 u64 rx_512_to_1023_byte_packets;
1249 u64 rx_1024_to_1518_byte_packets;
1250 u64 rx_crc_errors;
1251 u64 rx_mac_crtl_frames;
1252 u64 rx_pause_frames;
1253 u64 rx_pfc_frames;
1254 u64 rx_align_errors;
1255 u64 rx_carrier_errors;
1256 u64 rx_oversize_packets;
1257 u64 rx_jabbers;
1258 u64 rx_undersize_packets;
1259 u64 rx_fragments;
1260 u64 tx_64_byte_packets;
1261 u64 tx_65_to_127_byte_packets;
1262 u64 tx_128_to_255_byte_packets;
1263 u64 tx_256_to_511_byte_packets;
1264 u64 tx_512_to_1023_byte_packets;
1265 u64 tx_1024_to_1518_byte_packets;
1266 u64 tx_pause_frames;
1267 u64 tx_pfc_frames;
1268 u64 brb_truncates;
1269 u64 brb_discards;
1270 u64 rx_mac_bytes;
1271 u64 rx_mac_uc_packets;
1272 u64 rx_mac_mc_packets;
1273 u64 rx_mac_bc_packets;
1274 u64 rx_mac_frames_ok;
1275 u64 tx_mac_bytes;
1276 u64 tx_mac_uc_packets;
1277 u64 tx_mac_mc_packets;
1278 u64 tx_mac_bc_packets;
1279 u64 tx_mac_ctrl_frames;
1280 u64 link_change_count;
1281};
1282
1283struct qed_eth_stats_bb {
1284 u64 rx_1519_to_1522_byte_packets;
1285 u64 rx_1519_to_2047_byte_packets;
1286 u64 rx_2048_to_4095_byte_packets;
1287 u64 rx_4096_to_9216_byte_packets;
1288 u64 rx_9217_to_16383_byte_packets;
1289 u64 tx_1519_to_2047_byte_packets;
1290 u64 tx_2048_to_4095_byte_packets;
1291 u64 tx_4096_to_9216_byte_packets;
1292 u64 tx_9217_to_16383_byte_packets;
1293 u64 tx_lpi_entry_count;
1294 u64 tx_total_collisions;
1295};
1296
1297struct qed_eth_stats_ah {
1298 u64 rx_1519_to_max_byte_packets;
1299 u64 tx_1519_to_max_byte_packets;
1300};
1301
1302struct qed_eth_stats {
1303 struct qed_eth_stats_common common;
1304
1305 union {
1306 struct qed_eth_stats_bb bb;
1307 struct qed_eth_stats_ah ah;
1308 };
1309};
1310
1311#define QED_SB_IDX 0x0002
1312
1313#define RX_PI 0
1314#define TX_PI(tc) (RX_PI + 1 + tc)
1315
1316struct qed_sb_cnt_info {
1317
1318 int orig;
1319 int cnt;
1320 int free_cnt;
1321
1322
1323 int iov_orig;
1324 int iov_cnt;
1325 int free_cnt_iov;
1326};
1327
1328static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1329{
1330 u32 prod = 0;
1331 u16 rc = 0;
1332
1333 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1334 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1335 if (sb_info->sb_ack != prod) {
1336 sb_info->sb_ack = prod;
1337 rc |= QED_SB_IDX;
1338 }
1339
1340
1341 return rc;
1342}
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1359 enum igu_int_cmd int_cmd,
1360 u8 upd_flg)
1361{
1362 struct igu_prod_cons_update igu_ack = { 0 };
1363
1364 igu_ack.sb_id_and_flags =
1365 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1366 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1367 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1368 (IGU_SEG_ACCESS_REG <<
1369 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1370
1371 DIRECT_REG_WR(sb_info->igu_addr, igu_ack.sb_id_and_flags);
1372
1373
1374
1375
1376 barrier();
1377}
1378
1379static inline void __internal_ram_wr(void *p_hwfn,
1380 void __iomem *addr,
1381 int size,
1382 u32 *data)
1383
1384{
1385 unsigned int i;
1386
1387 for (i = 0; i < size / sizeof(*data); i++)
1388 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1389}
1390
1391static inline void internal_ram_wr(void __iomem *addr,
1392 int size,
1393 u32 *data)
1394{
1395 __internal_ram_wr(NULL, addr, size, data);
1396}
1397
1398enum qed_rss_caps {
1399 QED_RSS_IPV4 = 0x1,
1400 QED_RSS_IPV6 = 0x2,
1401 QED_RSS_IPV4_TCP = 0x4,
1402 QED_RSS_IPV6_TCP = 0x8,
1403 QED_RSS_IPV4_UDP = 0x10,
1404 QED_RSS_IPV6_UDP = 0x20,
1405};
1406
1407#define QED_RSS_IND_TABLE_SIZE 128
1408#define QED_RSS_KEY_SIZE 10
1409#endif
1410
