1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * cisreg.h 4 * 5 * The initial developer of the original code is David A. Hinds 6 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 7 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 8 * 9 * (C) 1999 David A. Hinds 10 */ 11 12#ifndef _LINUX_CISREG_H 13#define _LINUX_CISREG_H 14 15/* 16 * Offsets from ConfigBase for CIS registers 17 */ 18#define CISREG_COR 0x00 19#define CISREG_CCSR 0x02 20#define CISREG_PRR 0x04 21#define CISREG_SCR 0x06 22#define CISREG_ESR 0x08 23#define CISREG_IOBASE_0 0x0a 24#define CISREG_IOBASE_1 0x0c 25#define CISREG_IOBASE_2 0x0e 26#define CISREG_IOBASE_3 0x10 27#define CISREG_IOSIZE 0x12 28 29/* 30 * Configuration Option Register 31 */ 32#define COR_CONFIG_MASK 0x3f 33#define COR_MFC_CONFIG_MASK 0x38 34#define COR_FUNC_ENA 0x01 35#define COR_ADDR_DECODE 0x02 36#define COR_IREQ_ENA 0x04 37#define COR_LEVEL_REQ 0x40 38#define COR_SOFT_RESET 0x80 39 40/* 41 * Card Configuration and Status Register 42 */ 43#define CCSR_INTR_ACK 0x01 44#define CCSR_INTR_PENDING 0x02 45#define CCSR_POWER_DOWN 0x04 46#define CCSR_AUDIO_ENA 0x08 47#define CCSR_IOIS8 0x20 48#define CCSR_SIGCHG_ENA 0x40 49#define CCSR_CHANGED 0x80 50 51/* 52 * Pin Replacement Register 53 */ 54#define PRR_WP_STATUS 0x01 55#define PRR_READY_STATUS 0x02 56#define PRR_BVD2_STATUS 0x04 57#define PRR_BVD1_STATUS 0x08 58#define PRR_WP_EVENT 0x10 59#define PRR_READY_EVENT 0x20 60#define PRR_BVD2_EVENT 0x40 61#define PRR_BVD1_EVENT 0x80 62 63/* 64 * Socket and Copy Register 65 */ 66#define SCR_SOCKET_NUM 0x0f 67#define SCR_COPY_NUM 0x70 68 69/* 70 * Extended Status Register 71 */ 72#define ESR_REQ_ATTN_ENA 0x01 73#define ESR_REQ_ATTN 0x10 74 75/* 76 * CardBus Function Status Registers 77 */ 78#define CBFN_EVENT 0x00 79#define CBFN_MASK 0x04 80#define CBFN_STATE 0x08 81#define CBFN_FORCE 0x0c 82 83/* 84 * These apply to all the CardBus function registers 85 */ 86#define CBFN_WP 0x0001 87#define CBFN_READY 0x0002 88#define CBFN_BVD2 0x0004 89#define CBFN_BVD1 0x0008 90#define CBFN_GWAKE 0x0010 91#define CBFN_INTR 0x8000 92 93/* 94 * Extra bits in the Function Event Mask Register 95 */ 96#define FEMR_BAM_ENA 0x0020 97#define FEMR_PWM_ENA 0x0040 98#define FEMR_WKUP_MASK 0x4000 99 100/* 101 * Indirect Addressing Registers for Zoomed Video: these are addresses 102 * in common memory space 103 */ 104#define CISREG_ICTRL0 0x02 /* control registers */ 105#define CISREG_ICTRL1 0x03 106#define CISREG_IADDR0 0x04 /* address registers */ 107#define CISREG_IADDR1 0x05 108#define CISREG_IADDR2 0x06 109#define CISREG_IADDR3 0x07 110#define CISREG_IDATA0 0x08 /* data registers */ 111#define CISREG_IDATA1 0x09 112 113#define ICTRL0_COMMON 0x01 114#define ICTRL0_AUTOINC 0x02 115#define ICTRL0_BYTEGRAN 0x04 116 117#endif /* _LINUX_CISREG_H */ 118