LXR linux/sound/soc/meson/axg-fifo.h

   1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
   2/*
   3 * Copyright (c) 2018 BayLibre, SAS.
   4 * Author: Jerome Brunet <jbrunet@baylibre.com>
   5 */
   6
   7#ifndef _MESON_AXG_FIFO_H
   8#define _MESON_AXG_FIFO_H
   9
  10struct clk;
  11struct platform_device;
  12struct regmap;
  13struct reset_control;
  14
  15struct snd_soc_component_driver;
  16struct snd_soc_dai;
  17struct snd_soc_dai_driver;
  18struct snd_pcm_ops;
  19struct snd_soc_pcm_runtime;
  20
  21#define AXG_FIFO_CH_MAX                 128
  22#define AXG_FIFO_RATES                  (SNDRV_PCM_RATE_5512 |          \
  23                                         SNDRV_PCM_RATE_8000_192000)
  24#define AXG_FIFO_FORMATS                (SNDRV_PCM_FMTBIT_S8 |          \
  25                                         SNDRV_PCM_FMTBIT_S16_LE |      \
  26                                         SNDRV_PCM_FMTBIT_S20_LE |      \
  27                                         SNDRV_PCM_FMTBIT_S24_LE |      \
  28                                         SNDRV_PCM_FMTBIT_S32_LE |      \
  29                                         SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE)
  30
  31#define AXG_FIFO_BURST                  8
  32#define AXG_FIFO_MIN_CNT                64
  33#define AXG_FIFO_MIN_DEPTH              (AXG_FIFO_BURST * AXG_FIFO_MIN_CNT)
  34
  35#define FIFO_INT_ADDR_FINISH            BIT(0)
  36#define FIFO_INT_ADDR_INT               BIT(1)
  37#define FIFO_INT_COUNT_REPEAT           BIT(2)
  38#define FIFO_INT_COUNT_ONCE             BIT(3)
  39#define FIFO_INT_FIFO_ZERO              BIT(4)
  40#define FIFO_INT_FIFO_DEPTH             BIT(5)
  41#define FIFO_INT_MASK                   GENMASK(7, 0)
  42
  43#define FIFO_CTRL0                      0x00
  44#define  CTRL0_DMA_EN                   BIT(31)
  45#define  CTRL0_INT_EN(x)                ((x) << 16)
  46#define  CTRL0_SEL_MASK                 GENMASK(2, 0)
  47#define  CTRL0_SEL_SHIFT                0
  48#define FIFO_CTRL1                      0x04
  49#define  CTRL1_INT_CLR(x)               ((x) << 0)
  50#define  CTRL1_STATUS2_SEL_MASK         GENMASK(11, 8)
  51#define  CTRL1_STATUS2_SEL(x)           ((x) << 8)
  52#define   STATUS2_SEL_DDR_READ          0
  53#define  CTRL1_THRESHOLD_MASK           GENMASK(23, 16)
  54#define  CTRL1_THRESHOLD(x)             ((x) << 16)
  55#define  CTRL1_FRDDR_DEPTH_MASK         GENMASK(31, 24)
  56#define  CTRL1_FRDDR_DEPTH(x)           ((x) << 24)
  57#define FIFO_START_ADDR                 0x08
  58#define FIFO_FINISH_ADDR                0x0c
  59#define FIFO_INT_ADDR                   0x10
  60#define FIFO_STATUS1                    0x14
  61#define  STATUS1_INT_STS(x)             ((x) << 0)
  62#define FIFO_STATUS2                    0x18
  63#define FIFO_INIT_ADDR                  0x24
  64
  65struct axg_fifo {
  66        struct regmap *map;
  67        struct clk *pclk;
  68        struct reset_control *arb;
  69        int irq;
  70};
  71
  72struct axg_fifo_match_data {
  73        const struct snd_soc_component_driver *component_drv;
  74        struct snd_soc_dai_driver *dai_drv;
  75};
  76
  77extern const struct snd_pcm_ops axg_fifo_pcm_ops;
  78extern const struct snd_pcm_ops g12a_fifo_pcm_ops;
  79
  80int axg_fifo_pcm_new(struct snd_soc_pcm_runtime *rtd, unsigned int type);
  81int axg_fifo_probe(struct platform_device *pdev);
  82
  83#endif /* _MESON_AXG_FIFO_H */
  84