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9#include <linux/clk.h>
10#include <linux/completion.h>
11#include <linux/delay.h>
12#include <linux/module.h>
13#include <linux/of_platform.h>
14#include <linux/pinctrl/consumer.h>
15#include <linux/regmap.h>
16#include <linux/reset.h>
17
18#include <sound/dmaengine_pcm.h>
19#include <sound/pcm_params.h>
20
21
22#define STM32_SPDIFRX_CR 0x00
23#define STM32_SPDIFRX_IMR 0x04
24#define STM32_SPDIFRX_SR 0x08
25#define STM32_SPDIFRX_IFCR 0x0C
26#define STM32_SPDIFRX_DR 0x10
27#define STM32_SPDIFRX_CSR 0x14
28#define STM32_SPDIFRX_DIR 0x18
29
30
31#define SPDIFRX_CR_SPDIFEN_SHIFT 0
32#define SPDIFRX_CR_SPDIFEN_MASK GENMASK(1, SPDIFRX_CR_SPDIFEN_SHIFT)
33#define SPDIFRX_CR_SPDIFENSET(x) ((x) << SPDIFRX_CR_SPDIFEN_SHIFT)
34
35#define SPDIFRX_CR_RXDMAEN BIT(2)
36#define SPDIFRX_CR_RXSTEO BIT(3)
37
38#define SPDIFRX_CR_DRFMT_SHIFT 4
39#define SPDIFRX_CR_DRFMT_MASK GENMASK(5, SPDIFRX_CR_DRFMT_SHIFT)
40#define SPDIFRX_CR_DRFMTSET(x) ((x) << SPDIFRX_CR_DRFMT_SHIFT)
41
42#define SPDIFRX_CR_PMSK BIT(6)
43#define SPDIFRX_CR_VMSK BIT(7)
44#define SPDIFRX_CR_CUMSK BIT(8)
45#define SPDIFRX_CR_PTMSK BIT(9)
46#define SPDIFRX_CR_CBDMAEN BIT(10)
47#define SPDIFRX_CR_CHSEL_SHIFT 11
48#define SPDIFRX_CR_CHSEL BIT(SPDIFRX_CR_CHSEL_SHIFT)
49
50#define SPDIFRX_CR_NBTR_SHIFT 12
51#define SPDIFRX_CR_NBTR_MASK GENMASK(13, SPDIFRX_CR_NBTR_SHIFT)
52#define SPDIFRX_CR_NBTRSET(x) ((x) << SPDIFRX_CR_NBTR_SHIFT)
53
54#define SPDIFRX_CR_WFA BIT(14)
55
56#define SPDIFRX_CR_INSEL_SHIFT 16
57#define SPDIFRX_CR_INSEL_MASK GENMASK(18, PDIFRX_CR_INSEL_SHIFT)
58#define SPDIFRX_CR_INSELSET(x) ((x) << SPDIFRX_CR_INSEL_SHIFT)
59
60#define SPDIFRX_CR_CKSEN_SHIFT 20
61#define SPDIFRX_CR_CKSEN BIT(20)
62#define SPDIFRX_CR_CKSBKPEN BIT(21)
63
64
65#define SPDIFRX_IMR_RXNEI BIT(0)
66#define SPDIFRX_IMR_CSRNEIE BIT(1)
67#define SPDIFRX_IMR_PERRIE BIT(2)
68#define SPDIFRX_IMR_OVRIE BIT(3)
69#define SPDIFRX_IMR_SBLKIE BIT(4)
70#define SPDIFRX_IMR_SYNCDIE BIT(5)
71#define SPDIFRX_IMR_IFEIE BIT(6)
72
73#define SPDIFRX_XIMR_MASK GENMASK(6, 0)
74
75
76#define SPDIFRX_SR_RXNE BIT(0)
77#define SPDIFRX_SR_CSRNE BIT(1)
78#define SPDIFRX_SR_PERR BIT(2)
79#define SPDIFRX_SR_OVR BIT(3)
80#define SPDIFRX_SR_SBD BIT(4)
81#define SPDIFRX_SR_SYNCD BIT(5)
82#define SPDIFRX_SR_FERR BIT(6)
83#define SPDIFRX_SR_SERR BIT(7)
84#define SPDIFRX_SR_TERR BIT(8)
85
86#define SPDIFRX_SR_WIDTH5_SHIFT 16
87#define SPDIFRX_SR_WIDTH5_MASK GENMASK(30, PDIFRX_SR_WIDTH5_SHIFT)
88#define SPDIFRX_SR_WIDTH5SET(x) ((x) << SPDIFRX_SR_WIDTH5_SHIFT)
89
90
91#define SPDIFRX_IFCR_PERRCF BIT(2)
92#define SPDIFRX_IFCR_OVRCF BIT(3)
93#define SPDIFRX_IFCR_SBDCF BIT(4)
94#define SPDIFRX_IFCR_SYNCDCF BIT(5)
95
96#define SPDIFRX_XIFCR_MASK GENMASK(5, 2)
97
98
99#define SPDIFRX_DR0_DR_SHIFT 0
100#define SPDIFRX_DR0_DR_MASK GENMASK(23, SPDIFRX_DR0_DR_SHIFT)
101#define SPDIFRX_DR0_DRSET(x) ((x) << SPDIFRX_DR0_DR_SHIFT)
102
103#define SPDIFRX_DR0_PE BIT(24)
104
105#define SPDIFRX_DR0_V BIT(25)
106#define SPDIFRX_DR0_U BIT(26)
107#define SPDIFRX_DR0_C BIT(27)
108
109#define SPDIFRX_DR0_PT_SHIFT 28
110#define SPDIFRX_DR0_PT_MASK GENMASK(29, SPDIFRX_DR0_PT_SHIFT)
111#define SPDIFRX_DR0_PTSET(x) ((x) << SPDIFRX_DR0_PT_SHIFT)
112
113
114#define SPDIFRX_DR1_PE BIT(0)
115#define SPDIFRX_DR1_V BIT(1)
116#define SPDIFRX_DR1_U BIT(2)
117#define SPDIFRX_DR1_C BIT(3)
118
119#define SPDIFRX_DR1_PT_SHIFT 4
120#define SPDIFRX_DR1_PT_MASK GENMASK(5, SPDIFRX_DR1_PT_SHIFT)
121#define SPDIFRX_DR1_PTSET(x) ((x) << SPDIFRX_DR1_PT_SHIFT)
122
123#define SPDIFRX_DR1_DR_SHIFT 8
124#define SPDIFRX_DR1_DR_MASK GENMASK(31, SPDIFRX_DR1_DR_SHIFT)
125#define SPDIFRX_DR1_DRSET(x) ((x) << SPDIFRX_DR1_DR_SHIFT)
126
127
128#define SPDIFRX_DR1_DRNL1_SHIFT 0
129#define SPDIFRX_DR1_DRNL1_MASK GENMASK(15, SPDIFRX_DR1_DRNL1_SHIFT)
130#define SPDIFRX_DR1_DRNL1SET(x) ((x) << SPDIFRX_DR1_DRNL1_SHIFT)
131
132#define SPDIFRX_DR1_DRNL2_SHIFT 16
133#define SPDIFRX_DR1_DRNL2_MASK GENMASK(31, SPDIFRX_DR1_DRNL2_SHIFT)
134#define SPDIFRX_DR1_DRNL2SET(x) ((x) << SPDIFRX_DR1_DRNL2_SHIFT)
135
136
137#define SPDIFRX_CSR_USR_SHIFT 0
138#define SPDIFRX_CSR_USR_MASK GENMASK(15, SPDIFRX_CSR_USR_SHIFT)
139#define SPDIFRX_CSR_USRGET(x) (((x) & SPDIFRX_CSR_USR_MASK)\
140 >> SPDIFRX_CSR_USR_SHIFT)
141
142#define SPDIFRX_CSR_CS_SHIFT 16
143#define SPDIFRX_CSR_CS_MASK GENMASK(23, SPDIFRX_CSR_CS_SHIFT)
144#define SPDIFRX_CSR_CSGET(x) (((x) & SPDIFRX_CSR_CS_MASK)\
145 >> SPDIFRX_CSR_CS_SHIFT)
146
147#define SPDIFRX_CSR_SOB BIT(24)
148
149
150#define SPDIFRX_DIR_THI_SHIFT 0
151#define SPDIFRX_DIR_THI_MASK GENMASK(12, SPDIFRX_DIR_THI_SHIFT)
152#define SPDIFRX_DIR_THI_SET(x) ((x) << SPDIFRX_DIR_THI_SHIFT)
153
154#define SPDIFRX_DIR_TLO_SHIFT 16
155#define SPDIFRX_DIR_TLO_MASK GENMASK(28, SPDIFRX_DIR_TLO_SHIFT)
156#define SPDIFRX_DIR_TLO_SET(x) ((x) << SPDIFRX_DIR_TLO_SHIFT)
157
158#define SPDIFRX_SPDIFEN_DISABLE 0x0
159#define SPDIFRX_SPDIFEN_SYNC 0x1
160#define SPDIFRX_SPDIFEN_ENABLE 0x3
161
162#define SPDIFRX_IN1 0x1
163#define SPDIFRX_IN2 0x2
164#define SPDIFRX_IN3 0x3
165#define SPDIFRX_IN4 0x4
166#define SPDIFRX_IN5 0x5
167#define SPDIFRX_IN6 0x6
168#define SPDIFRX_IN7 0x7
169#define SPDIFRX_IN8 0x8
170
171#define SPDIFRX_NBTR_NONE 0x0
172#define SPDIFRX_NBTR_3 0x1
173#define SPDIFRX_NBTR_15 0x2
174#define SPDIFRX_NBTR_63 0x3
175
176#define SPDIFRX_DRFMT_RIGHT 0x0
177#define SPDIFRX_DRFMT_LEFT 0x1
178#define SPDIFRX_DRFMT_PACKED 0x2
179
180
181#define SPDIFRX_CS_BYTES_NB 24
182#define SPDIFRX_UB_BYTES_NB 48
183
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188
189#define SPDIFRX_CSR_BUF_LENGTH (SPDIFRX_CS_BYTES_NB * 4 * 2)
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212struct stm32_spdifrx_data {
213 struct platform_device *pdev;
214 void __iomem *base;
215 struct regmap *regmap;
216 const struct regmap_config *regmap_conf;
217 struct completion cs_completion;
218 struct clk *kclk;
219 struct snd_dmaengine_dai_dma_data dma_params;
220 struct snd_pcm_substream *substream;
221 struct snd_dma_buffer *dmab;
222 struct dma_chan *ctrl_chan;
223 struct dma_async_tx_descriptor *desc;
224 struct dma_slave_config slave_config;
225 dma_addr_t phys_addr;
226 spinlock_t lock;
227 unsigned char cs[SPDIFRX_CS_BYTES_NB];
228 unsigned char ub[SPDIFRX_UB_BYTES_NB];
229 int irq;
230 int refcount;
231};
232
233static void stm32_spdifrx_dma_complete(void *data)
234{
235 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)data;
236 struct platform_device *pdev = spdifrx->pdev;
237 u32 *p_start = (u32 *)spdifrx->dmab->area;
238 u32 *p_end = p_start + (2 * SPDIFRX_CS_BYTES_NB) - 1;
239 u32 *ptr = p_start;
240 u16 *ub_ptr = (short *)spdifrx->ub;
241 int i = 0;
242
243 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
244 SPDIFRX_CR_CBDMAEN,
245 (unsigned int)~SPDIFRX_CR_CBDMAEN);
246
247 if (!spdifrx->dmab->area)
248 return;
249
250 while (ptr <= p_end) {
251 if (*ptr & SPDIFRX_CSR_SOB)
252 break;
253 ptr++;
254 }
255
256 if (ptr > p_end) {
257 dev_err(&pdev->dev, "Start of S/PDIF block not found\n");
258 return;
259 }
260
261 while (i < SPDIFRX_CS_BYTES_NB) {
262 spdifrx->cs[i] = (unsigned char)SPDIFRX_CSR_CSGET(*ptr);
263 *ub_ptr++ = SPDIFRX_CSR_USRGET(*ptr++);
264 if (ptr > p_end) {
265 dev_err(&pdev->dev, "Failed to get channel status\n");
266 return;
267 }
268 i++;
269 }
270
271 complete(&spdifrx->cs_completion);
272}
273
274static int stm32_spdifrx_dma_ctrl_start(struct stm32_spdifrx_data *spdifrx)
275{
276 dma_cookie_t cookie;
277 int err;
278
279 spdifrx->desc = dmaengine_prep_slave_single(spdifrx->ctrl_chan,
280 spdifrx->dmab->addr,
281 SPDIFRX_CSR_BUF_LENGTH,
282 DMA_DEV_TO_MEM,
283 DMA_CTRL_ACK);
284 if (!spdifrx->desc)
285 return -EINVAL;
286
287 spdifrx->desc->callback = stm32_spdifrx_dma_complete;
288 spdifrx->desc->callback_param = spdifrx;
289 cookie = dmaengine_submit(spdifrx->desc);
290 err = dma_submit_error(cookie);
291 if (err)
292 return -EINVAL;
293
294 dma_async_issue_pending(spdifrx->ctrl_chan);
295
296 return 0;
297}
298
299static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
300{
301 dmaengine_terminate_async(spdifrx->ctrl_chan);
302}
303
304static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
305{
306 int cr, cr_mask, imr, ret;
307
308
309 imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
310 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR, imr, imr);
311 if (ret)
312 return ret;
313
314 spin_lock(&spdifrx->lock);
315
316 spdifrx->refcount++;
317
318 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CR, &cr);
319
320 if (!(cr & SPDIFRX_CR_SPDIFEN_MASK)) {
321
322
323
324
325 dev_dbg(&spdifrx->pdev->dev, "start synchronization\n");
326
327
328
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330
331
332
333
334 cr = SPDIFRX_CR_WFA | SPDIFRX_CR_PMSK | SPDIFRX_CR_VMSK |
335 SPDIFRX_CR_CUMSK | SPDIFRX_CR_PTMSK | SPDIFRX_CR_RXSTEO;
336 cr_mask = cr;
337
338 cr |= SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_SYNC);
339 cr_mask |= SPDIFRX_CR_SPDIFEN_MASK;
340 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
341 cr_mask, cr);
342 if (ret < 0)
343 dev_err(&spdifrx->pdev->dev,
344 "Failed to start synchronization\n");
345 }
346
347 spin_unlock(&spdifrx->lock);
348
349 return ret;
350}
351
352static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
353{
354 int cr, cr_mask, reg;
355
356 spin_lock(&spdifrx->lock);
357
358 if (--spdifrx->refcount) {
359 spin_unlock(&spdifrx->lock);
360 return;
361 }
362
363 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
364 cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
365
366 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR, cr_mask, cr);
367
368 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
369 SPDIFRX_XIMR_MASK, 0);
370
371 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
372 SPDIFRX_XIFCR_MASK, SPDIFRX_XIFCR_MASK);
373
374
375 regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
376 regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
377
378 spin_unlock(&spdifrx->lock);
379}
380
381static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
382 struct stm32_spdifrx_data *spdifrx)
383{
384 int ret;
385
386 spdifrx->ctrl_chan = dma_request_chan(dev, "rx-ctrl");
387 if (IS_ERR(spdifrx->ctrl_chan)) {
388 dev_err(dev, "dma_request_slave_channel failed\n");
389 return PTR_ERR(spdifrx->ctrl_chan);
390 }
391
392 spdifrx->dmab = devm_kzalloc(dev, sizeof(struct snd_dma_buffer),
393 GFP_KERNEL);
394 if (!spdifrx->dmab)
395 return -ENOMEM;
396
397 spdifrx->dmab->dev.type = SNDRV_DMA_TYPE_DEV_IRAM;
398 spdifrx->dmab->dev.dev = dev;
399 ret = snd_dma_alloc_pages(spdifrx->dmab->dev.type, dev,
400 SPDIFRX_CSR_BUF_LENGTH, spdifrx->dmab);
401 if (ret < 0) {
402 dev_err(dev, "snd_dma_alloc_pages returned error %d\n", ret);
403 return ret;
404 }
405
406 spdifrx->slave_config.direction = DMA_DEV_TO_MEM;
407 spdifrx->slave_config.src_addr = (dma_addr_t)(spdifrx->phys_addr +
408 STM32_SPDIFRX_CSR);
409 spdifrx->slave_config.dst_addr = spdifrx->dmab->addr;
410 spdifrx->slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
411 spdifrx->slave_config.src_maxburst = 1;
412
413 ret = dmaengine_slave_config(spdifrx->ctrl_chan,
414 &spdifrx->slave_config);
415 if (ret < 0) {
416 dev_err(dev, "dmaengine_slave_config returned error %d\n", ret);
417 spdifrx->ctrl_chan = NULL;
418 }
419
420 return ret;
421};
422
423static const char * const spdifrx_enum_input[] = {
424 "in0", "in1", "in2", "in3"
425};
426
427
428static const char * const spdifrx_enum_cs_channel[] = {
429 "A", "B"
430};
431
432static SOC_ENUM_SINGLE_DECL(ctrl_enum_input,
433 STM32_SPDIFRX_CR, SPDIFRX_CR_INSEL_SHIFT,
434 spdifrx_enum_input);
435
436static SOC_ENUM_SINGLE_DECL(ctrl_enum_cs_channel,
437 STM32_SPDIFRX_CR, SPDIFRX_CR_CHSEL_SHIFT,
438 spdifrx_enum_cs_channel);
439
440static int stm32_spdifrx_info(struct snd_kcontrol *kcontrol,
441 struct snd_ctl_elem_info *uinfo)
442{
443 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
444 uinfo->count = 1;
445
446 return 0;
447}
448
449static int stm32_spdifrx_ub_info(struct snd_kcontrol *kcontrol,
450 struct snd_ctl_elem_info *uinfo)
451{
452 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
453 uinfo->count = 1;
454
455 return 0;
456}
457
458static int stm32_spdifrx_get_ctrl_data(struct stm32_spdifrx_data *spdifrx)
459{
460 int ret = 0;
461
462 memset(spdifrx->cs, 0, SPDIFRX_CS_BYTES_NB);
463 memset(spdifrx->ub, 0, SPDIFRX_UB_BYTES_NB);
464
465 pinctrl_pm_select_default_state(&spdifrx->pdev->dev);
466
467 ret = stm32_spdifrx_dma_ctrl_start(spdifrx);
468 if (ret < 0)
469 return ret;
470
471 ret = clk_prepare_enable(spdifrx->kclk);
472 if (ret) {
473 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
474 return ret;
475 }
476
477 ret = regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
478 SPDIFRX_CR_CBDMAEN, SPDIFRX_CR_CBDMAEN);
479 if (ret < 0)
480 goto end;
481
482 ret = stm32_spdifrx_start_sync(spdifrx);
483 if (ret < 0)
484 goto end;
485
486 if (wait_for_completion_interruptible_timeout(&spdifrx->cs_completion,
487 msecs_to_jiffies(100))
488 <= 0) {
489 dev_dbg(&spdifrx->pdev->dev, "Failed to get control data\n");
490 ret = -EAGAIN;
491 }
492
493 stm32_spdifrx_stop(spdifrx);
494 stm32_spdifrx_dma_ctrl_stop(spdifrx);
495
496end:
497 clk_disable_unprepare(spdifrx->kclk);
498 pinctrl_pm_select_sleep_state(&spdifrx->pdev->dev);
499
500 return ret;
501}
502
503static int stm32_spdifrx_capture_get(struct snd_kcontrol *kcontrol,
504 struct snd_ctl_elem_value *ucontrol)
505{
506 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
507 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
508
509 stm32_spdifrx_get_ctrl_data(spdifrx);
510
511 ucontrol->value.iec958.status[0] = spdifrx->cs[0];
512 ucontrol->value.iec958.status[1] = spdifrx->cs[1];
513 ucontrol->value.iec958.status[2] = spdifrx->cs[2];
514 ucontrol->value.iec958.status[3] = spdifrx->cs[3];
515 ucontrol->value.iec958.status[4] = spdifrx->cs[4];
516
517 return 0;
518}
519
520static int stm32_spdif_user_bits_get(struct snd_kcontrol *kcontrol,
521 struct snd_ctl_elem_value *ucontrol)
522{
523 struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
524 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
525
526 stm32_spdifrx_get_ctrl_data(spdifrx);
527
528 ucontrol->value.iec958.status[0] = spdifrx->ub[0];
529 ucontrol->value.iec958.status[1] = spdifrx->ub[1];
530 ucontrol->value.iec958.status[2] = spdifrx->ub[2];
531 ucontrol->value.iec958.status[3] = spdifrx->ub[3];
532 ucontrol->value.iec958.status[4] = spdifrx->ub[4];
533
534 return 0;
535}
536
537static struct snd_kcontrol_new stm32_spdifrx_iec_ctrls[] = {
538
539 {
540 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
541 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT),
542 .access = SNDRV_CTL_ELEM_ACCESS_READ |
543 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
544 .info = stm32_spdifrx_info,
545 .get = stm32_spdifrx_capture_get,
546 },
547
548 {
549 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
550 .name = "IEC958 User Bit Capture Default",
551 .access = SNDRV_CTL_ELEM_ACCESS_READ |
552 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
553 .info = stm32_spdifrx_ub_info,
554 .get = stm32_spdif_user_bits_get,
555 },
556};
557
558static struct snd_kcontrol_new stm32_spdifrx_ctrls[] = {
559 SOC_ENUM("SPDIFRX input", ctrl_enum_input),
560 SOC_ENUM("SPDIFRX CS channel", ctrl_enum_cs_channel),
561};
562
563static int stm32_spdifrx_dai_register_ctrls(struct snd_soc_dai *cpu_dai)
564{
565 int ret;
566
567 ret = snd_soc_add_dai_controls(cpu_dai, stm32_spdifrx_iec_ctrls,
568 ARRAY_SIZE(stm32_spdifrx_iec_ctrls));
569 if (ret < 0)
570 return ret;
571
572 return snd_soc_add_component_controls(cpu_dai->component,
573 stm32_spdifrx_ctrls,
574 ARRAY_SIZE(stm32_spdifrx_ctrls));
575}
576
577static int stm32_spdifrx_dai_probe(struct snd_soc_dai *cpu_dai)
578{
579 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(cpu_dai->dev);
580
581 spdifrx->dma_params.addr = (dma_addr_t)(spdifrx->phys_addr +
582 STM32_SPDIFRX_DR);
583 spdifrx->dma_params.maxburst = 1;
584
585 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
586
587 return stm32_spdifrx_dai_register_ctrls(cpu_dai);
588}
589
590static bool stm32_spdifrx_readable_reg(struct device *dev, unsigned int reg)
591{
592 switch (reg) {
593 case STM32_SPDIFRX_CR:
594 case STM32_SPDIFRX_IMR:
595 case STM32_SPDIFRX_SR:
596 case STM32_SPDIFRX_IFCR:
597 case STM32_SPDIFRX_DR:
598 case STM32_SPDIFRX_CSR:
599 case STM32_SPDIFRX_DIR:
600 return true;
601 default:
602 return false;
603 }
604}
605
606static bool stm32_spdifrx_volatile_reg(struct device *dev, unsigned int reg)
607{
608 switch (reg) {
609 case STM32_SPDIFRX_DR:
610 case STM32_SPDIFRX_CSR:
611 case STM32_SPDIFRX_SR:
612 case STM32_SPDIFRX_DIR:
613 return true;
614 default:
615 return false;
616 }
617}
618
619static bool stm32_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
620{
621 switch (reg) {
622 case STM32_SPDIFRX_CR:
623 case STM32_SPDIFRX_IMR:
624 case STM32_SPDIFRX_IFCR:
625 return true;
626 default:
627 return false;
628 }
629}
630
631static const struct regmap_config stm32_h7_spdifrx_regmap_conf = {
632 .reg_bits = 32,
633 .reg_stride = 4,
634 .val_bits = 32,
635 .max_register = STM32_SPDIFRX_DIR,
636 .readable_reg = stm32_spdifrx_readable_reg,
637 .volatile_reg = stm32_spdifrx_volatile_reg,
638 .writeable_reg = stm32_spdifrx_writeable_reg,
639 .fast_io = true,
640 .cache_type = REGCACHE_FLAT,
641};
642
643static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
644{
645 struct stm32_spdifrx_data *spdifrx = (struct stm32_spdifrx_data *)devid;
646 struct snd_pcm_substream *substream = spdifrx->substream;
647 struct platform_device *pdev = spdifrx->pdev;
648 unsigned int cr, mask, sr, imr;
649 unsigned int flags;
650 int err = 0, err_xrun = 0;
651
652 regmap_read(spdifrx->regmap, STM32_SPDIFRX_SR, &sr);
653 regmap_read(spdifrx->regmap, STM32_SPDIFRX_IMR, &imr);
654
655 mask = imr & SPDIFRX_XIMR_MASK;
656
657 if (mask & SPDIFRX_IMR_IFEIE)
658 mask |= (SPDIFRX_IMR_IFEIE << 1) | (SPDIFRX_IMR_IFEIE << 2);
659
660 flags = sr & mask;
661 if (!flags) {
662 dev_err(&pdev->dev, "Unexpected IRQ. rflags=%#x, imr=%#x\n",
663 sr, imr);
664 return IRQ_NONE;
665 }
666
667
668 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IFCR,
669 SPDIFRX_XIFCR_MASK, flags);
670
671 if (flags & SPDIFRX_SR_PERR) {
672 dev_dbg(&pdev->dev, "Parity error\n");
673 err_xrun = 1;
674 }
675
676 if (flags & SPDIFRX_SR_OVR) {
677 dev_dbg(&pdev->dev, "Overrun error\n");
678 err_xrun = 1;
679 }
680
681 if (flags & SPDIFRX_SR_SBD)
682 dev_dbg(&pdev->dev, "Synchronization block detected\n");
683
684 if (flags & SPDIFRX_SR_SYNCD) {
685 dev_dbg(&pdev->dev, "Synchronization done\n");
686
687
688 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_ENABLE);
689 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
690 SPDIFRX_CR_SPDIFEN_MASK, cr);
691 }
692
693 if (flags & SPDIFRX_SR_FERR) {
694 dev_dbg(&pdev->dev, "Frame error\n");
695 err = 1;
696 }
697
698 if (flags & SPDIFRX_SR_SERR) {
699 dev_dbg(&pdev->dev, "Synchronization error\n");
700 err = 1;
701 }
702
703 if (flags & SPDIFRX_SR_TERR) {
704 dev_dbg(&pdev->dev, "Timeout error\n");
705 err = 1;
706 }
707
708 if (err) {
709
710 cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
711 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
712 SPDIFRX_CR_SPDIFEN_MASK, cr);
713
714 if (substream)
715 snd_pcm_stop(substream, SNDRV_PCM_STATE_DISCONNECTED);
716
717 return IRQ_HANDLED;
718 }
719
720 if (err_xrun && substream)
721 snd_pcm_stop_xrun(substream);
722
723 return IRQ_HANDLED;
724}
725
726static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
727 struct snd_soc_dai *cpu_dai)
728{
729 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
730 int ret;
731
732 spdifrx->substream = substream;
733
734 ret = clk_prepare_enable(spdifrx->kclk);
735 if (ret)
736 dev_err(&spdifrx->pdev->dev, "Enable kclk failed: %d\n", ret);
737
738 return ret;
739}
740
741static int stm32_spdifrx_hw_params(struct snd_pcm_substream *substream,
742 struct snd_pcm_hw_params *params,
743 struct snd_soc_dai *cpu_dai)
744{
745 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
746 int data_size = params_width(params);
747 int fmt;
748
749 switch (data_size) {
750 case 16:
751 fmt = SPDIFRX_DRFMT_PACKED;
752 break;
753 case 32:
754 fmt = SPDIFRX_DRFMT_LEFT;
755 break;
756 default:
757 dev_err(&spdifrx->pdev->dev, "Unexpected data format\n");
758 return -EINVAL;
759 }
760
761
762
763
764
765
766 spdifrx->dma_params.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
767 snd_soc_dai_init_dma_data(cpu_dai, NULL, &spdifrx->dma_params);
768
769 return regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
770 SPDIFRX_CR_DRFMT_MASK,
771 SPDIFRX_CR_DRFMTSET(fmt));
772}
773
774static int stm32_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
775 struct snd_soc_dai *cpu_dai)
776{
777 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
778 int ret = 0;
779
780 switch (cmd) {
781 case SNDRV_PCM_TRIGGER_START:
782 case SNDRV_PCM_TRIGGER_RESUME:
783 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
784 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_IMR,
785 SPDIFRX_IMR_OVRIE, SPDIFRX_IMR_OVRIE);
786
787 regmap_update_bits(spdifrx->regmap, STM32_SPDIFRX_CR,
788 SPDIFRX_CR_RXDMAEN, SPDIFRX_CR_RXDMAEN);
789
790 ret = stm32_spdifrx_start_sync(spdifrx);
791 break;
792 case SNDRV_PCM_TRIGGER_SUSPEND:
793 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
794 case SNDRV_PCM_TRIGGER_STOP:
795 stm32_spdifrx_stop(spdifrx);
796 break;
797 default:
798 return -EINVAL;
799 }
800
801 return ret;
802}
803
804static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
805 struct snd_soc_dai *cpu_dai)
806{
807 struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
808
809 spdifrx->substream = NULL;
810 clk_disable_unprepare(spdifrx->kclk);
811}
812
813static const struct snd_soc_dai_ops stm32_spdifrx_pcm_dai_ops = {
814 .startup = stm32_spdifrx_startup,
815 .hw_params = stm32_spdifrx_hw_params,
816 .trigger = stm32_spdifrx_trigger,
817 .shutdown = stm32_spdifrx_shutdown,
818};
819
820static struct snd_soc_dai_driver stm32_spdifrx_dai[] = {
821 {
822 .probe = stm32_spdifrx_dai_probe,
823 .capture = {
824 .stream_name = "CPU-Capture",
825 .channels_min = 1,
826 .channels_max = 2,
827 .rates = SNDRV_PCM_RATE_8000_192000,
828 .formats = SNDRV_PCM_FMTBIT_S32_LE |
829 SNDRV_PCM_FMTBIT_S16_LE,
830 },
831 .ops = &stm32_spdifrx_pcm_dai_ops,
832 }
833};
834
835static const struct snd_pcm_hardware stm32_spdifrx_pcm_hw = {
836 .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_MMAP,
837 .buffer_bytes_max = 8 * PAGE_SIZE,
838 .period_bytes_min = 1024,
839 .period_bytes_max = 4 * PAGE_SIZE,
840 .periods_min = 2,
841 .periods_max = 8,
842};
843
844static const struct snd_soc_component_driver stm32_spdifrx_component = {
845 .name = "stm32-spdifrx",
846};
847
848static const struct snd_dmaengine_pcm_config stm32_spdifrx_pcm_config = {
849 .pcm_hardware = &stm32_spdifrx_pcm_hw,
850 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
851};
852
853static const struct of_device_id stm32_spdifrx_ids[] = {
854 {
855 .compatible = "st,stm32h7-spdifrx",
856 .data = &stm32_h7_spdifrx_regmap_conf
857 },
858 {}
859};
860
861static int stm32_spdifrx_parse_of(struct platform_device *pdev,
862 struct stm32_spdifrx_data *spdifrx)
863{
864 struct device_node *np = pdev->dev.of_node;
865 const struct of_device_id *of_id;
866 struct resource *res;
867
868 if (!np)
869 return -ENODEV;
870
871 of_id = of_match_device(stm32_spdifrx_ids, &pdev->dev);
872 if (of_id)
873 spdifrx->regmap_conf =
874 (const struct regmap_config *)of_id->data;
875 else
876 return -EINVAL;
877
878 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
879 spdifrx->base = devm_ioremap_resource(&pdev->dev, res);
880 if (IS_ERR(spdifrx->base))
881 return PTR_ERR(spdifrx->base);
882
883 spdifrx->phys_addr = res->start;
884
885 spdifrx->kclk = devm_clk_get(&pdev->dev, "kclk");
886 if (IS_ERR(spdifrx->kclk)) {
887 dev_err(&pdev->dev, "Could not get kclk\n");
888 return PTR_ERR(spdifrx->kclk);
889 }
890
891 spdifrx->irq = platform_get_irq(pdev, 0);
892 if (spdifrx->irq < 0) {
893 dev_err(&pdev->dev, "No irq for node %s\n", pdev->name);
894 return spdifrx->irq;
895 }
896
897 return 0;
898}
899
900static int stm32_spdifrx_probe(struct platform_device *pdev)
901{
902 struct stm32_spdifrx_data *spdifrx;
903 struct reset_control *rst;
904 const struct snd_dmaengine_pcm_config *pcm_config = NULL;
905 int ret;
906
907 spdifrx = devm_kzalloc(&pdev->dev, sizeof(*spdifrx), GFP_KERNEL);
908 if (!spdifrx)
909 return -ENOMEM;
910
911 spdifrx->pdev = pdev;
912 init_completion(&spdifrx->cs_completion);
913 spin_lock_init(&spdifrx->lock);
914
915 platform_set_drvdata(pdev, spdifrx);
916
917 ret = stm32_spdifrx_parse_of(pdev, spdifrx);
918 if (ret)
919 return ret;
920
921 spdifrx->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "kclk",
922 spdifrx->base,
923 spdifrx->regmap_conf);
924 if (IS_ERR(spdifrx->regmap)) {
925 dev_err(&pdev->dev, "Regmap init failed\n");
926 return PTR_ERR(spdifrx->regmap);
927 }
928
929 ret = devm_request_irq(&pdev->dev, spdifrx->irq, stm32_spdifrx_isr, 0,
930 dev_name(&pdev->dev), spdifrx);
931 if (ret) {
932 dev_err(&pdev->dev, "IRQ request returned %d\n", ret);
933 return ret;
934 }
935
936 rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
937 if (!IS_ERR(rst)) {
938 reset_control_assert(rst);
939 udelay(2);
940 reset_control_deassert(rst);
941 }
942
943 ret = devm_snd_soc_register_component(&pdev->dev,
944 &stm32_spdifrx_component,
945 stm32_spdifrx_dai,
946 ARRAY_SIZE(stm32_spdifrx_dai));
947 if (ret)
948 return ret;
949
950 ret = stm32_spdifrx_dma_ctrl_register(&pdev->dev, spdifrx);
951 if (ret)
952 goto error;
953
954 pcm_config = &stm32_spdifrx_pcm_config;
955 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, pcm_config, 0);
956 if (ret) {
957 dev_err(&pdev->dev, "PCM DMA register returned %d\n", ret);
958 goto error;
959 }
960
961 return 0;
962
963error:
964 if (!IS_ERR(spdifrx->ctrl_chan))
965 dma_release_channel(spdifrx->ctrl_chan);
966 if (spdifrx->dmab)
967 snd_dma_free_pages(spdifrx->dmab);
968
969 return ret;
970}
971
972static int stm32_spdifrx_remove(struct platform_device *pdev)
973{
974 struct stm32_spdifrx_data *spdifrx = platform_get_drvdata(pdev);
975
976 if (spdifrx->ctrl_chan)
977 dma_release_channel(spdifrx->ctrl_chan);
978
979 if (spdifrx->dmab)
980 snd_dma_free_pages(spdifrx->dmab);
981
982 return 0;
983}
984
985MODULE_DEVICE_TABLE(of, stm32_spdifrx_ids);
986
987#ifdef CONFIG_PM_SLEEP
988static int stm32_spdifrx_suspend(struct device *dev)
989{
990 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
991
992 regcache_cache_only(spdifrx->regmap, true);
993 regcache_mark_dirty(spdifrx->regmap);
994
995 return 0;
996}
997
998static int stm32_spdifrx_resume(struct device *dev)
999{
1000 struct stm32_spdifrx_data *spdifrx = dev_get_drvdata(dev);
1001
1002 regcache_cache_only(spdifrx->regmap, false);
1003
1004 return regcache_sync(spdifrx->regmap);
1005}
1006#endif
1007
1008static const struct dev_pm_ops stm32_spdifrx_pm_ops = {
1009 SET_SYSTEM_SLEEP_PM_OPS(stm32_spdifrx_suspend, stm32_spdifrx_resume)
1010};
1011
1012static struct platform_driver stm32_spdifrx_driver = {
1013 .driver = {
1014 .name = "st,stm32-spdifrx",
1015 .of_match_table = stm32_spdifrx_ids,
1016 .pm = &stm32_spdifrx_pm_ops,
1017 },
1018 .probe = stm32_spdifrx_probe,
1019 .remove = stm32_spdifrx_remove,
1020};
1021
1022module_platform_driver(stm32_spdifrx_driver);
1023
1024MODULE_DESCRIPTION("STM32 Soc spdifrx Interface");
1025MODULE_AUTHOR("Olivier Moysan, <olivier.moysan@st.com>");
1026MODULE_ALIAS("platform:stm32-spdifrx");
1027MODULE_LICENSE("GPL v2");
1028
