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10#include <linux/clk.h>
11#include <linux/dmaengine.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/platform_device.h>
15#include <linux/pm_runtime.h>
16#include <linux/regmap.h>
17#include <linux/reset.h>
18
19#include <sound/dmaengine_pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <sound/soc-dai.h>
23
24#define SUN4I_I2S_CTRL_REG 0x00
25#define SUN4I_I2S_CTRL_SDO_EN_MASK GENMASK(11, 8)
26#define SUN4I_I2S_CTRL_SDO_EN(sdo) BIT(8 + (sdo))
27#define SUN4I_I2S_CTRL_MODE_MASK BIT(5)
28#define SUN4I_I2S_CTRL_MODE_SLAVE (1 << 5)
29#define SUN4I_I2S_CTRL_MODE_MASTER (0 << 5)
30#define SUN4I_I2S_CTRL_TX_EN BIT(2)
31#define SUN4I_I2S_CTRL_RX_EN BIT(1)
32#define SUN4I_I2S_CTRL_GL_EN BIT(0)
33
34#define SUN4I_I2S_FMT0_REG 0x04
35#define SUN4I_I2S_FMT0_LRCLK_POLARITY_MASK BIT(7)
36#define SUN4I_I2S_FMT0_LRCLK_POLARITY_INVERTED (1 << 7)
37#define SUN4I_I2S_FMT0_LRCLK_POLARITY_NORMAL (0 << 7)
38#define SUN4I_I2S_FMT0_BCLK_POLARITY_MASK BIT(6)
39#define SUN4I_I2S_FMT0_BCLK_POLARITY_INVERTED (1 << 6)
40#define SUN4I_I2S_FMT0_BCLK_POLARITY_NORMAL (0 << 6)
41#define SUN4I_I2S_FMT0_SR_MASK GENMASK(5, 4)
42#define SUN4I_I2S_FMT0_SR(sr) ((sr) << 4)
43#define SUN4I_I2S_FMT0_WSS_MASK GENMASK(3, 2)
44#define SUN4I_I2S_FMT0_WSS(wss) ((wss) << 2)
45#define SUN4I_I2S_FMT0_FMT_MASK GENMASK(1, 0)
46#define SUN4I_I2S_FMT0_FMT_RIGHT_J (2 << 0)
47#define SUN4I_I2S_FMT0_FMT_LEFT_J (1 << 0)
48#define SUN4I_I2S_FMT0_FMT_I2S (0 << 0)
49#define SUN4I_I2S_FMT0_POLARITY_INVERTED (1)
50#define SUN4I_I2S_FMT0_POLARITY_NORMAL (0)
51
52#define SUN4I_I2S_FMT1_REG 0x08
53#define SUN4I_I2S_FIFO_TX_REG 0x0c
54#define SUN4I_I2S_FIFO_RX_REG 0x10
55
56#define SUN4I_I2S_FIFO_CTRL_REG 0x14
57#define SUN4I_I2S_FIFO_CTRL_FLUSH_TX BIT(25)
58#define SUN4I_I2S_FIFO_CTRL_FLUSH_RX BIT(24)
59#define SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK BIT(2)
60#define SUN4I_I2S_FIFO_CTRL_TX_MODE(mode) ((mode) << 2)
61#define SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK GENMASK(1, 0)
62#define SUN4I_I2S_FIFO_CTRL_RX_MODE(mode) (mode)
63
64#define SUN4I_I2S_FIFO_STA_REG 0x18
65
66#define SUN4I_I2S_DMA_INT_CTRL_REG 0x1c
67#define SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN BIT(7)
68#define SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN BIT(3)
69
70#define SUN4I_I2S_INT_STA_REG 0x20
71
72#define SUN4I_I2S_CLK_DIV_REG 0x24
73#define SUN4I_I2S_CLK_DIV_MCLK_EN BIT(7)
74#define SUN4I_I2S_CLK_DIV_BCLK_MASK GENMASK(6, 4)
75#define SUN4I_I2S_CLK_DIV_BCLK(bclk) ((bclk) << 4)
76#define SUN4I_I2S_CLK_DIV_MCLK_MASK GENMASK(3, 0)
77#define SUN4I_I2S_CLK_DIV_MCLK(mclk) ((mclk) << 0)
78
79#define SUN4I_I2S_RX_CNT_REG 0x28
80#define SUN4I_I2S_TX_CNT_REG 0x2c
81
82#define SUN4I_I2S_TX_CHAN_SEL_REG 0x30
83#define SUN4I_I2S_CHAN_SEL(num_chan) (((num_chan) - 1) << 0)
84
85#define SUN4I_I2S_TX_CHAN_MAP_REG 0x34
86#define SUN4I_I2S_TX_CHAN_MAP(chan, sample) ((sample) << (chan << 2))
87
88#define SUN4I_I2S_RX_CHAN_SEL_REG 0x38
89#define SUN4I_I2S_RX_CHAN_MAP_REG 0x3c
90
91
92#define SUN8I_I2S_CTRL_BCLK_OUT BIT(18)
93#define SUN8I_I2S_CTRL_LRCK_OUT BIT(17)
94
95#define SUN8I_I2S_FMT0_LRCK_PERIOD_MASK GENMASK(17, 8)
96#define SUN8I_I2S_FMT0_LRCK_PERIOD(period) ((period - 1) << 8)
97
98#define SUN8I_I2S_INT_STA_REG 0x0c
99#define SUN8I_I2S_FIFO_TX_REG 0x20
100
101#define SUN8I_I2S_CHAN_CFG_REG 0x30
102#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK GENMASK(6, 4)
103#define SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(chan) ((chan - 1) << 4)
104#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK GENMASK(2, 0)
105#define SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(chan) (chan - 1)
106
107#define SUN8I_I2S_TX_CHAN_MAP_REG 0x44
108#define SUN8I_I2S_TX_CHAN_SEL_REG 0x34
109#define SUN8I_I2S_TX_CHAN_OFFSET_MASK GENMASK(13, 12)
110#define SUN8I_I2S_TX_CHAN_OFFSET(offset) (offset << 12)
111#define SUN8I_I2S_TX_CHAN_EN_MASK GENMASK(11, 4)
112#define SUN8I_I2S_TX_CHAN_EN(num_chan) (((1 << num_chan) - 1) << 4)
113
114#define SUN8I_I2S_RX_CHAN_SEL_REG 0x54
115#define SUN8I_I2S_RX_CHAN_MAP_REG 0x58
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142struct sun4i_i2s_quirks {
143 bool has_reset;
144 bool has_slave_select_bit;
145 bool has_fmt_set_lrck_period;
146 bool has_chcfg;
147 bool has_chsel_tx_chen;
148 bool has_chsel_offset;
149 unsigned int reg_offset_txdata;
150 const struct regmap_config *sun4i_i2s_regmap;
151 unsigned int mclk_offset;
152 unsigned int bclk_offset;
153 unsigned int fmt_offset;
154
155
156 struct reg_field field_clkdiv_mclk_en;
157 struct reg_field field_fmt_wss;
158 struct reg_field field_fmt_sr;
159 struct reg_field field_fmt_bclk;
160 struct reg_field field_fmt_lrclk;
161 struct reg_field field_fmt_mode;
162 struct reg_field field_txchanmap;
163 struct reg_field field_rxchanmap;
164 struct reg_field field_txchansel;
165 struct reg_field field_rxchansel;
166};
167
168struct sun4i_i2s {
169 struct clk *bus_clk;
170 struct clk *mod_clk;
171 struct regmap *regmap;
172 struct reset_control *rst;
173
174 unsigned int mclk_freq;
175
176 struct snd_dmaengine_dai_dma_data capture_dma_data;
177 struct snd_dmaengine_dai_dma_data playback_dma_data;
178
179
180 struct regmap_field *field_clkdiv_mclk_en;
181 struct regmap_field *field_fmt_wss;
182 struct regmap_field *field_fmt_sr;
183 struct regmap_field *field_fmt_bclk;
184 struct regmap_field *field_fmt_lrclk;
185 struct regmap_field *field_fmt_mode;
186 struct regmap_field *field_txchanmap;
187 struct regmap_field *field_rxchanmap;
188 struct regmap_field *field_txchansel;
189 struct regmap_field *field_rxchansel;
190
191 const struct sun4i_i2s_quirks *variant;
192};
193
194struct sun4i_i2s_clk_div {
195 u8 div;
196 u8 val;
197};
198
199static const struct sun4i_i2s_clk_div sun4i_i2s_bclk_div[] = {
200 { .div = 2, .val = 0 },
201 { .div = 4, .val = 1 },
202 { .div = 6, .val = 2 },
203 { .div = 8, .val = 3 },
204 { .div = 12, .val = 4 },
205 { .div = 16, .val = 5 },
206
207};
208
209static const struct sun4i_i2s_clk_div sun4i_i2s_mclk_div[] = {
210 { .div = 1, .val = 0 },
211 { .div = 2, .val = 1 },
212 { .div = 4, .val = 2 },
213 { .div = 6, .val = 3 },
214 { .div = 8, .val = 4 },
215 { .div = 12, .val = 5 },
216 { .div = 16, .val = 6 },
217 { .div = 24, .val = 7 },
218
219};
220
221static int sun4i_i2s_get_bclk_div(struct sun4i_i2s *i2s,
222 unsigned int oversample_rate,
223 unsigned int word_size)
224{
225 int div = oversample_rate / word_size / 2;
226 int i;
227
228 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_bclk_div); i++) {
229 const struct sun4i_i2s_clk_div *bdiv = &sun4i_i2s_bclk_div[i];
230
231 if (bdiv->div == div)
232 return bdiv->val;
233 }
234
235 return -EINVAL;
236}
237
238static int sun4i_i2s_get_mclk_div(struct sun4i_i2s *i2s,
239 unsigned int oversample_rate,
240 unsigned int module_rate,
241 unsigned int sampling_rate)
242{
243 int div = module_rate / sampling_rate / oversample_rate;
244 int i;
245
246 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_mclk_div); i++) {
247 const struct sun4i_i2s_clk_div *mdiv = &sun4i_i2s_mclk_div[i];
248
249 if (mdiv->div == div)
250 return mdiv->val;
251 }
252
253 return -EINVAL;
254}
255
256static int sun4i_i2s_oversample_rates[] = { 128, 192, 256, 384, 512, 768 };
257static bool sun4i_i2s_oversample_is_valid(unsigned int oversample)
258{
259 int i;
260
261 for (i = 0; i < ARRAY_SIZE(sun4i_i2s_oversample_rates); i++)
262 if (sun4i_i2s_oversample_rates[i] == oversample)
263 return true;
264
265 return false;
266}
267
268static int sun4i_i2s_set_clk_rate(struct snd_soc_dai *dai,
269 unsigned int rate,
270 unsigned int word_size)
271{
272 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
273 unsigned int oversample_rate, clk_rate;
274 int bclk_div, mclk_div;
275 int ret;
276
277 switch (rate) {
278 case 176400:
279 case 88200:
280 case 44100:
281 case 22050:
282 case 11025:
283 clk_rate = 22579200;
284 break;
285
286 case 192000:
287 case 128000:
288 case 96000:
289 case 64000:
290 case 48000:
291 case 32000:
292 case 24000:
293 case 16000:
294 case 12000:
295 case 8000:
296 clk_rate = 24576000;
297 break;
298
299 default:
300 dev_err(dai->dev, "Unsupported sample rate: %u\n", rate);
301 return -EINVAL;
302 }
303
304 ret = clk_set_rate(i2s->mod_clk, clk_rate);
305 if (ret)
306 return ret;
307
308 oversample_rate = i2s->mclk_freq / rate;
309 if (!sun4i_i2s_oversample_is_valid(oversample_rate)) {
310 dev_err(dai->dev, "Unsupported oversample rate: %d\n",
311 oversample_rate);
312 return -EINVAL;
313 }
314
315 bclk_div = sun4i_i2s_get_bclk_div(i2s, oversample_rate,
316 word_size);
317 if (bclk_div < 0) {
318 dev_err(dai->dev, "Unsupported BCLK divider: %d\n", bclk_div);
319 return -EINVAL;
320 }
321
322 mclk_div = sun4i_i2s_get_mclk_div(i2s, oversample_rate,
323 clk_rate, rate);
324 if (mclk_div < 0) {
325 dev_err(dai->dev, "Unsupported MCLK divider: %d\n", mclk_div);
326 return -EINVAL;
327 }
328
329
330 bclk_div += i2s->variant->bclk_offset;
331 mclk_div += i2s->variant->mclk_offset;
332
333 regmap_write(i2s->regmap, SUN4I_I2S_CLK_DIV_REG,
334 SUN4I_I2S_CLK_DIV_BCLK(bclk_div) |
335 SUN4I_I2S_CLK_DIV_MCLK(mclk_div));
336
337 regmap_field_write(i2s->field_clkdiv_mclk_en, 1);
338
339
340 if (i2s->variant->has_fmt_set_lrck_period)
341 regmap_update_bits(i2s->regmap, SUN4I_I2S_FMT0_REG,
342 SUN8I_I2S_FMT0_LRCK_PERIOD_MASK,
343 SUN8I_I2S_FMT0_LRCK_PERIOD(32));
344
345 return 0;
346}
347
348static int sun4i_i2s_hw_params(struct snd_pcm_substream *substream,
349 struct snd_pcm_hw_params *params,
350 struct snd_soc_dai *dai)
351{
352 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
353 int sr, wss, channels;
354 u32 width;
355
356 channels = params_channels(params);
357 if (channels != 2) {
358 dev_err(dai->dev, "Unsupported number of channels: %d\n",
359 channels);
360 return -EINVAL;
361 }
362
363 if (i2s->variant->has_chcfg) {
364 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
365 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM_MASK,
366 SUN8I_I2S_CHAN_CFG_TX_SLOT_NUM(channels));
367 regmap_update_bits(i2s->regmap, SUN8I_I2S_CHAN_CFG_REG,
368 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM_MASK,
369 SUN8I_I2S_CHAN_CFG_RX_SLOT_NUM(channels));
370 }
371
372
373 regmap_field_write(i2s->field_txchanmap, 0x76543210);
374 regmap_field_write(i2s->field_rxchanmap, 0x00003210);
375
376
377 regmap_field_write(i2s->field_txchansel,
378 SUN4I_I2S_CHAN_SEL(params_channels(params)));
379
380 regmap_field_write(i2s->field_rxchansel,
381 SUN4I_I2S_CHAN_SEL(params_channels(params)));
382
383 if (i2s->variant->has_chsel_tx_chen)
384 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
385 SUN8I_I2S_TX_CHAN_EN_MASK,
386 SUN8I_I2S_TX_CHAN_EN(channels));
387
388 switch (params_physical_width(params)) {
389 case 16:
390 width = DMA_SLAVE_BUSWIDTH_2_BYTES;
391 break;
392 default:
393 dev_err(dai->dev, "Unsupported physical sample width: %d\n",
394 params_physical_width(params));
395 return -EINVAL;
396 }
397 i2s->playback_dma_data.addr_width = width;
398
399 switch (params_width(params)) {
400 case 16:
401 sr = 0;
402 wss = 0;
403 break;
404
405 default:
406 dev_err(dai->dev, "Unsupported sample width: %d\n",
407 params_width(params));
408 return -EINVAL;
409 }
410
411 regmap_field_write(i2s->field_fmt_wss,
412 wss + i2s->variant->fmt_offset);
413 regmap_field_write(i2s->field_fmt_sr,
414 sr + i2s->variant->fmt_offset);
415
416 return sun4i_i2s_set_clk_rate(dai, params_rate(params),
417 params_width(params));
418}
419
420static int sun4i_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
421{
422 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
423 u32 val;
424 u32 offset = 0;
425 u32 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
426 u32 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_NORMAL;
427
428
429 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
430 case SND_SOC_DAIFMT_I2S:
431 val = SUN4I_I2S_FMT0_FMT_I2S;
432 offset = 1;
433 break;
434 case SND_SOC_DAIFMT_LEFT_J:
435 val = SUN4I_I2S_FMT0_FMT_LEFT_J;
436 break;
437 case SND_SOC_DAIFMT_RIGHT_J:
438 val = SUN4I_I2S_FMT0_FMT_RIGHT_J;
439 break;
440 default:
441 dev_err(dai->dev, "Unsupported format: %d\n",
442 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
443 return -EINVAL;
444 }
445
446 if (i2s->variant->has_chsel_offset) {
447
448
449
450
451
452
453 if (offset > 0)
454 val++;
455
456 regmap_update_bits(i2s->regmap, SUN8I_I2S_TX_CHAN_SEL_REG,
457 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
458 SUN8I_I2S_TX_CHAN_OFFSET(offset));
459
460 regmap_update_bits(i2s->regmap, SUN8I_I2S_RX_CHAN_SEL_REG,
461 SUN8I_I2S_TX_CHAN_OFFSET_MASK,
462 SUN8I_I2S_TX_CHAN_OFFSET(offset));
463 }
464
465 regmap_field_write(i2s->field_fmt_mode, val);
466
467
468 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
469 case SND_SOC_DAIFMT_IB_IF:
470
471 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
472 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
473 break;
474 case SND_SOC_DAIFMT_IB_NF:
475
476 bclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
477 break;
478 case SND_SOC_DAIFMT_NB_IF:
479
480 lrclk_polarity = SUN4I_I2S_FMT0_POLARITY_INVERTED;
481 break;
482 case SND_SOC_DAIFMT_NB_NF:
483 break;
484 default:
485 dev_err(dai->dev, "Unsupported clock polarity: %d\n",
486 fmt & SND_SOC_DAIFMT_INV_MASK);
487 return -EINVAL;
488 }
489
490 regmap_field_write(i2s->field_fmt_bclk, bclk_polarity);
491 regmap_field_write(i2s->field_fmt_lrclk, lrclk_polarity);
492
493 if (i2s->variant->has_slave_select_bit) {
494
495 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
496 case SND_SOC_DAIFMT_CBS_CFS:
497
498 val = SUN4I_I2S_CTRL_MODE_MASTER;
499 break;
500 case SND_SOC_DAIFMT_CBM_CFM:
501
502 val = SUN4I_I2S_CTRL_MODE_SLAVE;
503 break;
504 default:
505 dev_err(dai->dev, "Unsupported slave setting: %d\n",
506 fmt & SND_SOC_DAIFMT_MASTER_MASK);
507 return -EINVAL;
508 }
509 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
510 SUN4I_I2S_CTRL_MODE_MASK,
511 val);
512 } else {
513
514
515
516
517
518 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
519 case SND_SOC_DAIFMT_CBS_CFS:
520
521 val = SUN8I_I2S_CTRL_BCLK_OUT |
522 SUN8I_I2S_CTRL_LRCK_OUT;
523 break;
524 case SND_SOC_DAIFMT_CBM_CFM:
525
526 val = 0;
527 break;
528 default:
529 dev_err(dai->dev, "Unsupported slave setting: %d\n",
530 fmt & SND_SOC_DAIFMT_MASTER_MASK);
531 return -EINVAL;
532 }
533 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
534 SUN8I_I2S_CTRL_BCLK_OUT |
535 SUN8I_I2S_CTRL_LRCK_OUT,
536 val);
537 }
538
539
540 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
541 SUN4I_I2S_FIFO_CTRL_TX_MODE_MASK |
542 SUN4I_I2S_FIFO_CTRL_RX_MODE_MASK,
543 SUN4I_I2S_FIFO_CTRL_TX_MODE(1) |
544 SUN4I_I2S_FIFO_CTRL_RX_MODE(1));
545 return 0;
546}
547
548static void sun4i_i2s_start_capture(struct sun4i_i2s *i2s)
549{
550
551 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
552 SUN4I_I2S_FIFO_CTRL_FLUSH_RX,
553 SUN4I_I2S_FIFO_CTRL_FLUSH_RX);
554
555
556 regmap_write(i2s->regmap, SUN4I_I2S_RX_CNT_REG, 0);
557
558
559 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
560 SUN4I_I2S_CTRL_RX_EN,
561 SUN4I_I2S_CTRL_RX_EN);
562
563
564 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
565 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
566 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN);
567}
568
569static void sun4i_i2s_start_playback(struct sun4i_i2s *i2s)
570{
571
572 regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG,
573 SUN4I_I2S_FIFO_CTRL_FLUSH_TX,
574 SUN4I_I2S_FIFO_CTRL_FLUSH_TX);
575
576
577 regmap_write(i2s->regmap, SUN4I_I2S_TX_CNT_REG, 0);
578
579
580 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
581 SUN4I_I2S_CTRL_TX_EN,
582 SUN4I_I2S_CTRL_TX_EN);
583
584
585 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
586 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
587 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN);
588}
589
590static void sun4i_i2s_stop_capture(struct sun4i_i2s *i2s)
591{
592
593 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
594 SUN4I_I2S_CTRL_RX_EN,
595 0);
596
597
598 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
599 SUN4I_I2S_DMA_INT_CTRL_RX_DRQ_EN,
600 0);
601}
602
603static void sun4i_i2s_stop_playback(struct sun4i_i2s *i2s)
604{
605
606 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
607 SUN4I_I2S_CTRL_TX_EN,
608 0);
609
610
611 regmap_update_bits(i2s->regmap, SUN4I_I2S_DMA_INT_CTRL_REG,
612 SUN4I_I2S_DMA_INT_CTRL_TX_DRQ_EN,
613 0);
614}
615
616static int sun4i_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
617 struct snd_soc_dai *dai)
618{
619 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
620
621 switch (cmd) {
622 case SNDRV_PCM_TRIGGER_START:
623 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
624 case SNDRV_PCM_TRIGGER_RESUME:
625 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
626 sun4i_i2s_start_playback(i2s);
627 else
628 sun4i_i2s_start_capture(i2s);
629 break;
630
631 case SNDRV_PCM_TRIGGER_STOP:
632 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
633 case SNDRV_PCM_TRIGGER_SUSPEND:
634 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
635 sun4i_i2s_stop_playback(i2s);
636 else
637 sun4i_i2s_stop_capture(i2s);
638 break;
639
640 default:
641 return -EINVAL;
642 }
643
644 return 0;
645}
646
647static int sun4i_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
648 unsigned int freq, int dir)
649{
650 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
651
652 if (clk_id != 0)
653 return -EINVAL;
654
655 i2s->mclk_freq = freq;
656
657 return 0;
658}
659
660static const struct snd_soc_dai_ops sun4i_i2s_dai_ops = {
661 .hw_params = sun4i_i2s_hw_params,
662 .set_fmt = sun4i_i2s_set_fmt,
663 .set_sysclk = sun4i_i2s_set_sysclk,
664 .trigger = sun4i_i2s_trigger,
665};
666
667static int sun4i_i2s_dai_probe(struct snd_soc_dai *dai)
668{
669 struct sun4i_i2s *i2s = snd_soc_dai_get_drvdata(dai);
670
671 snd_soc_dai_init_dma_data(dai,
672 &i2s->playback_dma_data,
673 &i2s->capture_dma_data);
674
675 snd_soc_dai_set_drvdata(dai, i2s);
676
677 return 0;
678}
679
680static struct snd_soc_dai_driver sun4i_i2s_dai = {
681 .probe = sun4i_i2s_dai_probe,
682 .capture = {
683 .stream_name = "Capture",
684 .channels_min = 2,
685 .channels_max = 2,
686 .rates = SNDRV_PCM_RATE_8000_192000,
687 .formats = SNDRV_PCM_FMTBIT_S16_LE,
688 },
689 .playback = {
690 .stream_name = "Playback",
691 .channels_min = 2,
692 .channels_max = 2,
693 .rates = SNDRV_PCM_RATE_8000_192000,
694 .formats = SNDRV_PCM_FMTBIT_S16_LE,
695 },
696 .ops = &sun4i_i2s_dai_ops,
697 .symmetric_rates = 1,
698};
699
700static const struct snd_soc_component_driver sun4i_i2s_component = {
701 .name = "sun4i-dai",
702};
703
704static bool sun4i_i2s_rd_reg(struct device *dev, unsigned int reg)
705{
706 switch (reg) {
707 case SUN4I_I2S_FIFO_TX_REG:
708 return false;
709
710 default:
711 return true;
712 }
713}
714
715static bool sun4i_i2s_wr_reg(struct device *dev, unsigned int reg)
716{
717 switch (reg) {
718 case SUN4I_I2S_FIFO_RX_REG:
719 case SUN4I_I2S_FIFO_STA_REG:
720 return false;
721
722 default:
723 return true;
724 }
725}
726
727static bool sun4i_i2s_volatile_reg(struct device *dev, unsigned int reg)
728{
729 switch (reg) {
730 case SUN4I_I2S_FIFO_RX_REG:
731 case SUN4I_I2S_INT_STA_REG:
732 case SUN4I_I2S_RX_CNT_REG:
733 case SUN4I_I2S_TX_CNT_REG:
734 return true;
735
736 default:
737 return false;
738 }
739}
740
741static bool sun8i_i2s_rd_reg(struct device *dev, unsigned int reg)
742{
743 switch (reg) {
744 case SUN8I_I2S_FIFO_TX_REG:
745 return false;
746
747 default:
748 return true;
749 }
750}
751
752static bool sun8i_i2s_volatile_reg(struct device *dev, unsigned int reg)
753{
754 if (reg == SUN8I_I2S_INT_STA_REG)
755 return true;
756 if (reg == SUN8I_I2S_FIFO_TX_REG)
757 return false;
758
759 return sun4i_i2s_volatile_reg(dev, reg);
760}
761
762static const struct reg_default sun4i_i2s_reg_defaults[] = {
763 { SUN4I_I2S_CTRL_REG, 0x00000000 },
764 { SUN4I_I2S_FMT0_REG, 0x0000000c },
765 { SUN4I_I2S_FMT1_REG, 0x00004020 },
766 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
767 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
768 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
769 { SUN4I_I2S_TX_CHAN_SEL_REG, 0x00000001 },
770 { SUN4I_I2S_TX_CHAN_MAP_REG, 0x76543210 },
771 { SUN4I_I2S_RX_CHAN_SEL_REG, 0x00000001 },
772 { SUN4I_I2S_RX_CHAN_MAP_REG, 0x00003210 },
773};
774
775static const struct reg_default sun8i_i2s_reg_defaults[] = {
776 { SUN4I_I2S_CTRL_REG, 0x00060000 },
777 { SUN4I_I2S_FMT0_REG, 0x00000033 },
778 { SUN4I_I2S_FMT1_REG, 0x00000030 },
779 { SUN4I_I2S_FIFO_CTRL_REG, 0x000400f0 },
780 { SUN4I_I2S_DMA_INT_CTRL_REG, 0x00000000 },
781 { SUN4I_I2S_CLK_DIV_REG, 0x00000000 },
782 { SUN8I_I2S_CHAN_CFG_REG, 0x00000000 },
783 { SUN8I_I2S_TX_CHAN_SEL_REG, 0x00000000 },
784 { SUN8I_I2S_TX_CHAN_MAP_REG, 0x00000000 },
785 { SUN8I_I2S_RX_CHAN_SEL_REG, 0x00000000 },
786 { SUN8I_I2S_RX_CHAN_MAP_REG, 0x00000000 },
787};
788
789static const struct regmap_config sun4i_i2s_regmap_config = {
790 .reg_bits = 32,
791 .reg_stride = 4,
792 .val_bits = 32,
793 .max_register = SUN4I_I2S_RX_CHAN_MAP_REG,
794
795 .cache_type = REGCACHE_FLAT,
796 .reg_defaults = sun4i_i2s_reg_defaults,
797 .num_reg_defaults = ARRAY_SIZE(sun4i_i2s_reg_defaults),
798 .writeable_reg = sun4i_i2s_wr_reg,
799 .readable_reg = sun4i_i2s_rd_reg,
800 .volatile_reg = sun4i_i2s_volatile_reg,
801};
802
803static const struct regmap_config sun8i_i2s_regmap_config = {
804 .reg_bits = 32,
805 .reg_stride = 4,
806 .val_bits = 32,
807 .max_register = SUN8I_I2S_RX_CHAN_MAP_REG,
808 .cache_type = REGCACHE_FLAT,
809 .reg_defaults = sun8i_i2s_reg_defaults,
810 .num_reg_defaults = ARRAY_SIZE(sun8i_i2s_reg_defaults),
811 .writeable_reg = sun4i_i2s_wr_reg,
812 .readable_reg = sun8i_i2s_rd_reg,
813 .volatile_reg = sun8i_i2s_volatile_reg,
814};
815
816static int sun4i_i2s_runtime_resume(struct device *dev)
817{
818 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
819 int ret;
820
821 ret = clk_prepare_enable(i2s->bus_clk);
822 if (ret) {
823 dev_err(dev, "Failed to enable bus clock\n");
824 return ret;
825 }
826
827 regcache_cache_only(i2s->regmap, false);
828 regcache_mark_dirty(i2s->regmap);
829
830 ret = regcache_sync(i2s->regmap);
831 if (ret) {
832 dev_err(dev, "Failed to sync regmap cache\n");
833 goto err_disable_clk;
834 }
835
836
837 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
838 SUN4I_I2S_CTRL_GL_EN, SUN4I_I2S_CTRL_GL_EN);
839
840
841 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
842 SUN4I_I2S_CTRL_SDO_EN_MASK,
843 SUN4I_I2S_CTRL_SDO_EN(0));
844
845 ret = clk_prepare_enable(i2s->mod_clk);
846 if (ret) {
847 dev_err(dev, "Failed to enable module clock\n");
848 goto err_disable_clk;
849 }
850
851 return 0;
852
853err_disable_clk:
854 clk_disable_unprepare(i2s->bus_clk);
855 return ret;
856}
857
858static int sun4i_i2s_runtime_suspend(struct device *dev)
859{
860 struct sun4i_i2s *i2s = dev_get_drvdata(dev);
861
862 clk_disable_unprepare(i2s->mod_clk);
863
864
865 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
866 SUN4I_I2S_CTRL_SDO_EN_MASK, 0);
867
868
869 regmap_update_bits(i2s->regmap, SUN4I_I2S_CTRL_REG,
870 SUN4I_I2S_CTRL_GL_EN, 0);
871
872 regcache_cache_only(i2s->regmap, true);
873
874 clk_disable_unprepare(i2s->bus_clk);
875
876 return 0;
877}
878
879static const struct sun4i_i2s_quirks sun4i_a10_i2s_quirks = {
880 .has_reset = false,
881 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
882 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
883 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
884 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
885 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
886 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
887 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
888 .has_slave_select_bit = true,
889 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
890 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
891 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
892 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
893 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
894};
895
896static const struct sun4i_i2s_quirks sun6i_a31_i2s_quirks = {
897 .has_reset = true,
898 .reg_offset_txdata = SUN4I_I2S_FIFO_TX_REG,
899 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
900 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
901 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
902 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
903 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
904 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
905 .has_slave_select_bit = true,
906 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
907 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
908 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
909 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
910 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
911};
912
913static const struct sun4i_i2s_quirks sun8i_a83t_i2s_quirks = {
914 .has_reset = true,
915 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
916 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
917 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
918 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
919 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
920 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
921 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
922 .has_slave_select_bit = true,
923 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
924 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
925 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
926 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
927 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
928};
929
930static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
931 .has_reset = true,
932 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
933 .sun4i_i2s_regmap = &sun8i_i2s_regmap_config,
934 .mclk_offset = 1,
935 .bclk_offset = 2,
936 .fmt_offset = 3,
937 .has_fmt_set_lrck_period = true,
938 .has_chcfg = true,
939 .has_chsel_tx_chen = true,
940 .has_chsel_offset = true,
941 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 8, 8),
942 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 2),
943 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 6),
944 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
945 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 19, 19),
946 .field_fmt_mode = REG_FIELD(SUN4I_I2S_CTRL_REG, 4, 5),
947 .field_txchanmap = REG_FIELD(SUN8I_I2S_TX_CHAN_MAP_REG, 0, 31),
948 .field_rxchanmap = REG_FIELD(SUN8I_I2S_RX_CHAN_MAP_REG, 0, 31),
949 .field_txchansel = REG_FIELD(SUN8I_I2S_TX_CHAN_SEL_REG, 0, 2),
950 .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
951};
952
953static const struct sun4i_i2s_quirks sun50i_a64_codec_i2s_quirks = {
954 .has_reset = true,
955 .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
956 .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
957 .has_slave_select_bit = true,
958 .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
959 .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
960 .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
961 .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
962 .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
963 .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
964 .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
965 .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
966 .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
967 .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
968};
969
970static int sun4i_i2s_init_regmap_fields(struct device *dev,
971 struct sun4i_i2s *i2s)
972{
973 i2s->field_clkdiv_mclk_en =
974 devm_regmap_field_alloc(dev, i2s->regmap,
975 i2s->variant->field_clkdiv_mclk_en);
976 if (IS_ERR(i2s->field_clkdiv_mclk_en))
977 return PTR_ERR(i2s->field_clkdiv_mclk_en);
978
979 i2s->field_fmt_wss =
980 devm_regmap_field_alloc(dev, i2s->regmap,
981 i2s->variant->field_fmt_wss);
982 if (IS_ERR(i2s->field_fmt_wss))
983 return PTR_ERR(i2s->field_fmt_wss);
984
985 i2s->field_fmt_sr =
986 devm_regmap_field_alloc(dev, i2s->regmap,
987 i2s->variant->field_fmt_sr);
988 if (IS_ERR(i2s->field_fmt_sr))
989 return PTR_ERR(i2s->field_fmt_sr);
990
991 i2s->field_fmt_bclk =
992 devm_regmap_field_alloc(dev, i2s->regmap,
993 i2s->variant->field_fmt_bclk);
994 if (IS_ERR(i2s->field_fmt_bclk))
995 return PTR_ERR(i2s->field_fmt_bclk);
996
997 i2s->field_fmt_lrclk =
998 devm_regmap_field_alloc(dev, i2s->regmap,
999 i2s->variant->field_fmt_lrclk);
1000 if (IS_ERR(i2s->field_fmt_lrclk))
1001 return PTR_ERR(i2s->field_fmt_lrclk);
1002
1003 i2s->field_fmt_mode =
1004 devm_regmap_field_alloc(dev, i2s->regmap,
1005 i2s->variant->field_fmt_mode);
1006 if (IS_ERR(i2s->field_fmt_mode))
1007 return PTR_ERR(i2s->field_fmt_mode);
1008
1009 i2s->field_txchanmap =
1010 devm_regmap_field_alloc(dev, i2s->regmap,
1011 i2s->variant->field_txchanmap);
1012 if (IS_ERR(i2s->field_txchanmap))
1013 return PTR_ERR(i2s->field_txchanmap);
1014
1015 i2s->field_rxchanmap =
1016 devm_regmap_field_alloc(dev, i2s->regmap,
1017 i2s->variant->field_rxchanmap);
1018 if (IS_ERR(i2s->field_rxchanmap))
1019 return PTR_ERR(i2s->field_rxchanmap);
1020
1021 i2s->field_txchansel =
1022 devm_regmap_field_alloc(dev, i2s->regmap,
1023 i2s->variant->field_txchansel);
1024 if (IS_ERR(i2s->field_txchansel))
1025 return PTR_ERR(i2s->field_txchansel);
1026
1027 i2s->field_rxchansel =
1028 devm_regmap_field_alloc(dev, i2s->regmap,
1029 i2s->variant->field_rxchansel);
1030 return PTR_ERR_OR_ZERO(i2s->field_rxchansel);
1031}
1032
1033static int sun4i_i2s_probe(struct platform_device *pdev)
1034{
1035 struct sun4i_i2s *i2s;
1036 struct resource *res;
1037 void __iomem *regs;
1038 int irq, ret;
1039
1040 i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
1041 if (!i2s)
1042 return -ENOMEM;
1043 platform_set_drvdata(pdev, i2s);
1044
1045 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 regs = devm_ioremap_resource(&pdev->dev, res);
1047 if (IS_ERR(regs))
1048 return PTR_ERR(regs);
1049
1050 irq = platform_get_irq(pdev, 0);
1051 if (irq < 0) {
1052 dev_err(&pdev->dev, "Can't retrieve our interrupt\n");
1053 return irq;
1054 }
1055
1056 i2s->variant = of_device_get_match_data(&pdev->dev);
1057 if (!i2s->variant) {
1058 dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
1059 return -ENODEV;
1060 }
1061
1062 i2s->bus_clk = devm_clk_get(&pdev->dev, "apb");
1063 if (IS_ERR(i2s->bus_clk)) {
1064 dev_err(&pdev->dev, "Can't get our bus clock\n");
1065 return PTR_ERR(i2s->bus_clk);
1066 }
1067
1068 i2s->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1069 i2s->variant->sun4i_i2s_regmap);
1070 if (IS_ERR(i2s->regmap)) {
1071 dev_err(&pdev->dev, "Regmap initialisation failed\n");
1072 return PTR_ERR(i2s->regmap);
1073 }
1074
1075 i2s->mod_clk = devm_clk_get(&pdev->dev, "mod");
1076 if (IS_ERR(i2s->mod_clk)) {
1077 dev_err(&pdev->dev, "Can't get our mod clock\n");
1078 return PTR_ERR(i2s->mod_clk);
1079 }
1080
1081 if (i2s->variant->has_reset) {
1082 i2s->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
1083 if (IS_ERR(i2s->rst)) {
1084 dev_err(&pdev->dev, "Failed to get reset control\n");
1085 return PTR_ERR(i2s->rst);
1086 }
1087 }
1088
1089 if (!IS_ERR(i2s->rst)) {
1090 ret = reset_control_deassert(i2s->rst);
1091 if (ret) {
1092 dev_err(&pdev->dev,
1093 "Failed to deassert the reset control\n");
1094 return -EINVAL;
1095 }
1096 }
1097
1098 i2s->playback_dma_data.addr = res->start +
1099 i2s->variant->reg_offset_txdata;
1100 i2s->playback_dma_data.maxburst = 8;
1101
1102 i2s->capture_dma_data.addr = res->start + SUN4I_I2S_FIFO_RX_REG;
1103 i2s->capture_dma_data.maxburst = 8;
1104
1105 pm_runtime_enable(&pdev->dev);
1106 if (!pm_runtime_enabled(&pdev->dev)) {
1107 ret = sun4i_i2s_runtime_resume(&pdev->dev);
1108 if (ret)
1109 goto err_pm_disable;
1110 }
1111
1112 ret = devm_snd_soc_register_component(&pdev->dev,
1113 &sun4i_i2s_component,
1114 &sun4i_i2s_dai, 1);
1115 if (ret) {
1116 dev_err(&pdev->dev, "Could not register DAI\n");
1117 goto err_suspend;
1118 }
1119
1120 ret = snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1121 if (ret) {
1122 dev_err(&pdev->dev, "Could not register PCM\n");
1123 goto err_suspend;
1124 }
1125
1126 ret = sun4i_i2s_init_regmap_fields(&pdev->dev, i2s);
1127 if (ret) {
1128 dev_err(&pdev->dev, "Could not initialise regmap fields\n");
1129 goto err_suspend;
1130 }
1131
1132 return 0;
1133
1134err_suspend:
1135 if (!pm_runtime_status_suspended(&pdev->dev))
1136 sun4i_i2s_runtime_suspend(&pdev->dev);
1137err_pm_disable:
1138 pm_runtime_disable(&pdev->dev);
1139 if (!IS_ERR(i2s->rst))
1140 reset_control_assert(i2s->rst);
1141
1142 return ret;
1143}
1144
1145static int sun4i_i2s_remove(struct platform_device *pdev)
1146{
1147 struct sun4i_i2s *i2s = dev_get_drvdata(&pdev->dev);
1148
1149 snd_dmaengine_pcm_unregister(&pdev->dev);
1150
1151 pm_runtime_disable(&pdev->dev);
1152 if (!pm_runtime_status_suspended(&pdev->dev))
1153 sun4i_i2s_runtime_suspend(&pdev->dev);
1154
1155 if (!IS_ERR(i2s->rst))
1156 reset_control_assert(i2s->rst);
1157
1158 return 0;
1159}
1160
1161static const struct of_device_id sun4i_i2s_match[] = {
1162 {
1163 .compatible = "allwinner,sun4i-a10-i2s",
1164 .data = &sun4i_a10_i2s_quirks,
1165 },
1166 {
1167 .compatible = "allwinner,sun6i-a31-i2s",
1168 .data = &sun6i_a31_i2s_quirks,
1169 },
1170 {
1171 .compatible = "allwinner,sun8i-a83t-i2s",
1172 .data = &sun8i_a83t_i2s_quirks,
1173 },
1174 {
1175 .compatible = "allwinner,sun8i-h3-i2s",
1176 .data = &sun8i_h3_i2s_quirks,
1177 },
1178 {
1179 .compatible = "allwinner,sun50i-a64-codec-i2s",
1180 .data = &sun50i_a64_codec_i2s_quirks,
1181 },
1182 {}
1183};
1184MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
1185
1186static const struct dev_pm_ops sun4i_i2s_pm_ops = {
1187 .runtime_resume = sun4i_i2s_runtime_resume,
1188 .runtime_suspend = sun4i_i2s_runtime_suspend,
1189};
1190
1191static struct platform_driver sun4i_i2s_driver = {
1192 .probe = sun4i_i2s_probe,
1193 .remove = sun4i_i2s_remove,
1194 .driver = {
1195 .name = "sun4i-i2s",
1196 .of_match_table = sun4i_i2s_match,
1197 .pm = &sun4i_i2s_pm_ops,
1198 },
1199};
1200module_platform_driver(sun4i_i2s_driver);
1201
1202MODULE_AUTHOR("Andrea Venturi <be17068@iperbole.bo.it>");
1203MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1204MODULE_DESCRIPTION("Allwinner A10 I2S driver");
1205MODULE_LICENSE("GPL");
1206
