LXR linux/arch/arc/include/asm/arcregs.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   4 */
   5
   6#ifndef _ASM_ARC_ARCREGS_H
   7#define _ASM_ARC_ARCREGS_H
   8
   9/* Build Configuration Registers */
  10#define ARC_REG_AUX_DCCM        0x18    /* DCCM Base Addr ARCv2 */
  11#define ARC_REG_ERP_CTRL        0x3F    /* ARCv2 Error protection control */
  12#define ARC_REG_DCCM_BASE_BUILD 0x61    /* DCCM Base Addr ARCompact */
  13#define ARC_REG_CRC_BCR         0x62
  14#define ARC_REG_VECBASE_BCR     0x68
  15#define ARC_REG_PERIBASE_BCR    0x69
  16#define ARC_REG_FP_BCR          0x6B    /* ARCompact: Single-Precision FPU */
  17#define ARC_REG_DPFP_BCR        0x6C    /* ARCompact: Dbl Precision FPU */
  18#define ARC_REG_ERP_BUILD       0xc7    /* ARCv2 Error protection Build: ECC/Parity */
  19#define ARC_REG_FP_V2_BCR       0xc8    /* ARCv2 FPU */
  20#define ARC_REG_SLC_BCR         0xce
  21#define ARC_REG_DCCM_BUILD      0x74    /* DCCM size (common) */
  22#define ARC_REG_AP_BCR          0x76
  23#define ARC_REG_ICCM_BUILD      0x78    /* ICCM size (common) */
  24#define ARC_REG_XY_MEM_BCR      0x79
  25#define ARC_REG_MAC_BCR         0x7a
  26#define ARC_REG_MUL_BCR         0x7b
  27#define ARC_REG_SWAP_BCR        0x7c
  28#define ARC_REG_NORM_BCR        0x7d
  29#define ARC_REG_MIXMAX_BCR      0x7e
  30#define ARC_REG_BARREL_BCR      0x7f
  31#define ARC_REG_D_UNCACH_BCR    0x6A
  32#define ARC_REG_BPU_BCR         0xc0
  33#define ARC_REG_ISA_CFG_BCR     0xc1
  34#define ARC_REG_LPB_BUILD       0xE9    /* ARCv2 Loop Buffer Build */
  35#define ARC_REG_RTT_BCR         0xF2
  36#define ARC_REG_IRQ_BCR         0xF3
  37#define ARC_REG_MICRO_ARCH_BCR  0xF9    /* ARCv2 Product revision */
  38#define ARC_REG_SMART_BCR       0xFF
  39#define ARC_REG_CLUSTER_BCR     0xcf
  40#define ARC_REG_AUX_ICCM        0x208   /* ICCM Base Addr (ARCv2) */
  41#define ARC_REG_LPB_CTRL        0x488   /* ARCv2 Loop Buffer control */
  42
  43/* Common for ARCompact and ARCv2 status register */
  44#define ARC_REG_STATUS32        0x0A
  45
  46/* status32 Bits Positions */
  47#define STATUS_AE_BIT           5       /* Exception active */
  48#define STATUS_DE_BIT           6       /* PC is in delay slot */
  49#define STATUS_U_BIT            7       /* User/Kernel mode */
  50#define STATUS_Z_BIT            11
  51#define STATUS_L_BIT            12      /* Loop inhibit */
  52
  53/* These masks correspond to the status word(STATUS_32) bits */
  54#define STATUS_AE_MASK          (1<<STATUS_AE_BIT)
  55#define STATUS_DE_MASK          (1<<STATUS_DE_BIT)
  56#define STATUS_U_MASK           (1<<STATUS_U_BIT)
  57#define STATUS_Z_MASK           (1<<STATUS_Z_BIT)
  58#define STATUS_L_MASK           (1<<STATUS_L_BIT)
  59
  60/*
  61 * ECR: Exception Cause Reg bits-n-pieces
  62 * [23:16] = Exception Vector
  63 * [15: 8] = Exception Cause Code
  64 * [ 7: 0] = Exception Parameters (for certain types only)
  65 */
  66#ifdef CONFIG_ISA_ARCOMPACT
  67#define ECR_V_MEM_ERR                   0x01
  68#define ECR_V_INSN_ERR                  0x02
  69#define ECR_V_MACH_CHK                  0x20
  70#define ECR_V_ITLB_MISS                 0x21
  71#define ECR_V_DTLB_MISS                 0x22
  72#define ECR_V_PROTV                     0x23
  73#define ECR_V_TRAP                      0x25
  74#else
  75#define ECR_V_MEM_ERR                   0x01
  76#define ECR_V_INSN_ERR                  0x02
  77#define ECR_V_MACH_CHK                  0x03
  78#define ECR_V_ITLB_MISS                 0x04
  79#define ECR_V_DTLB_MISS                 0x05
  80#define ECR_V_PROTV                     0x06
  81#define ECR_V_TRAP                      0x09
  82#define ECR_V_MISALIGN                  0x0d
  83#endif
  84
  85/* DTLB Miss and Protection Violation Cause Codes */
  86
  87#define ECR_C_PROTV_INST_FETCH          0x00
  88#define ECR_C_PROTV_LOAD                0x01
  89#define ECR_C_PROTV_STORE               0x02
  90#define ECR_C_PROTV_XCHG                0x03
  91#define ECR_C_PROTV_MISALIG_DATA        0x04
  92
  93#define ECR_C_BIT_PROTV_MISALIG_DATA    10
  94
  95/* Machine Check Cause Code Values */
  96#define ECR_C_MCHK_DUP_TLB              0x01
  97
  98/* DTLB Miss Exception Cause Code Values */
  99#define ECR_C_BIT_DTLB_LD_MISS          8
 100#define ECR_C_BIT_DTLB_ST_MISS          9
 101
 102/* Auxiliary registers */
 103#define AUX_IDENTITY            4
 104#define AUX_EXEC_CTRL           8
 105#define AUX_INTR_VEC_BASE       0x25
 106#define AUX_VOL                 0x5e
 107
 108/*
 109 * Floating Pt Registers
 110 * Status regs are read-only (build-time) so need not be saved/restored
 111 */
 112#define ARC_AUX_FP_STAT         0x300
 113#define ARC_AUX_DPFP_1L         0x301
 114#define ARC_AUX_DPFP_1H         0x302
 115#define ARC_AUX_DPFP_2L         0x303
 116#define ARC_AUX_DPFP_2H         0x304
 117#define ARC_AUX_DPFP_STAT       0x305
 118
 119#ifndef __ASSEMBLY__
 120
 121#include <soc/arc/aux.h>
 122
 123/* Helpers */
 124#define TO_KB(bytes)            ((bytes) >> 10)
 125#define TO_MB(bytes)            (TO_KB(bytes) >> 10)
 126#define PAGES_TO_KB(n_pages)    ((n_pages) << (PAGE_SHIFT - 10))
 127#define PAGES_TO_MB(n_pages)    (PAGES_TO_KB(n_pages) >> 10)
 128
 129
 130/*
 131 ***************************************************************
 132 * Build Configuration Registers, with encoded hardware config
 133 */
 134struct bcr_identity {
 135#ifdef CONFIG_CPU_BIG_ENDIAN
 136        unsigned int chip_id:16, cpu_id:8, family:8;
 137#else
 138        unsigned int family:8, cpu_id:8, chip_id:16;
 139#endif
 140};
 141
 142struct bcr_isa_arcv2 {
 143#ifdef CONFIG_CPU_BIG_ENDIAN
 144        unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
 145                     pad1:12, ver:8;
 146#else
 147        unsigned int ver:8, pad1:12, be:1, atomic:1, unalign:1,
 148                     ldd:1, pad2:4, div_rem:4;
 149#endif
 150};
 151
 152struct bcr_uarch_build_arcv2 {
 153#ifdef CONFIG_CPU_BIG_ENDIAN
 154        unsigned int pad:8, prod:8, maj:8, min:8;
 155#else
 156        unsigned int min:8, maj:8, prod:8, pad:8;
 157#endif
 158};
 159
 160struct bcr_mpy {
 161#ifdef CONFIG_CPU_BIG_ENDIAN
 162        unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
 163#else
 164        unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
 165#endif
 166};
 167
 168struct bcr_iccm_arcompact {
 169#ifdef CONFIG_CPU_BIG_ENDIAN
 170        unsigned int base:16, pad:5, sz:3, ver:8;
 171#else
 172        unsigned int ver:8, sz:3, pad:5, base:16;
 173#endif
 174};
 175
 176struct bcr_iccm_arcv2 {
 177#ifdef CONFIG_CPU_BIG_ENDIAN
 178        unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
 179#else
 180        unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
 181#endif
 182};
 183
 184struct bcr_dccm_arcompact {
 185#ifdef CONFIG_CPU_BIG_ENDIAN
 186        unsigned int res:21, sz:3, ver:8;
 187#else
 188        unsigned int ver:8, sz:3, res:21;
 189#endif
 190};
 191
 192struct bcr_dccm_arcv2 {
 193#ifdef CONFIG_CPU_BIG_ENDIAN
 194        unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
 195#else
 196        unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
 197#endif
 198};
 199
 200/* ARCompact: Both SP and DP FPU BCRs have same format */
 201struct bcr_fp_arcompact {
 202#ifdef CONFIG_CPU_BIG_ENDIAN
 203        unsigned int fast:1, ver:8;
 204#else
 205        unsigned int ver:8, fast:1;
 206#endif
 207};
 208
 209struct bcr_fp_arcv2 {
 210#ifdef CONFIG_CPU_BIG_ENDIAN
 211        unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
 212#else
 213        unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
 214#endif
 215};
 216
 217struct bcr_actionpoint {
 218#ifdef CONFIG_CPU_BIG_ENDIAN
 219        unsigned int pad:21, min:1, num:2, ver:8;
 220#else
 221        unsigned int ver:8, num:2, min:1, pad:21;
 222#endif
 223};
 224
 225#include <soc/arc/timers.h>
 226
 227struct bcr_bpu_arcompact {
 228#ifdef CONFIG_CPU_BIG_ENDIAN
 229        unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
 230#else
 231        unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
 232#endif
 233};
 234
 235struct bcr_bpu_arcv2 {
 236#ifdef CONFIG_CPU_BIG_ENDIAN
 237        unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
 238#else
 239        unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
 240#endif
 241};
 242
 243/* Error Protection Build: ECC/Parity */
 244struct bcr_erp {
 245#ifdef CONFIG_CPU_BIG_ENDIAN
 246        unsigned int pad3:5, mmu:3, pad2:4, ic:3, dc:3, pad1:6, ver:8;
 247#else
 248        unsigned int ver:8, pad1:6, dc:3, ic:3, pad2:4, mmu:3, pad3:5;
 249#endif
 250};
 251
 252/* Error Protection Control */
 253struct ctl_erp {
 254#ifdef CONFIG_CPU_BIG_ENDIAN
 255        unsigned int pad2:27, mpd:1, pad1:2, dpd:1, dpi:1;
 256#else
 257        unsigned int dpi:1, dpd:1, pad1:2, mpd:1, pad2:27;
 258#endif
 259};
 260
 261struct bcr_lpb {
 262#ifdef CONFIG_CPU_BIG_ENDIAN
 263        unsigned int pad:16, entries:8, ver:8;
 264#else
 265        unsigned int ver:8, entries:8, pad:16;
 266#endif
 267};
 268
 269struct bcr_generic {
 270#ifdef CONFIG_CPU_BIG_ENDIAN
 271        unsigned int info:24, ver:8;
 272#else
 273        unsigned int ver:8, info:24;
 274#endif
 275};
 276
 277/*
 278 *******************************************************************
 279 * Generic structures to hold build configuration used at runtime
 280 */
 281
 282struct cpuinfo_arc_mmu {
 283        unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
 284        unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
 285};
 286
 287struct cpuinfo_arc_cache {
 288        unsigned int sz_k:14, line_len:8, assoc:4, alias:1, vipt:1, pad:4;
 289};
 290
 291struct cpuinfo_arc_bpu {
 292        unsigned int ver, full, num_cache, num_pred, ret_stk;
 293};
 294
 295struct cpuinfo_arc_ccm {
 296        unsigned int base_addr, sz;
 297};
 298
 299struct cpuinfo_arc {
 300        struct cpuinfo_arc_cache icache, dcache, slc;
 301        struct cpuinfo_arc_mmu mmu;
 302        struct cpuinfo_arc_bpu bpu;
 303        struct bcr_identity core;
 304        struct bcr_isa_arcv2 isa;
 305        const char *release, *name;
 306        unsigned int vec_base;
 307        struct cpuinfo_arc_ccm iccm, dccm;
 308        struct {
 309                unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
 310                             fpu_sp:1, fpu_dp:1, dual:1, dual_enb:1, pad2:4,
 311                             ap_num:4, ap_full:1, smart:1, rtt:1, pad3:1,
 312                             timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
 313        } extn;
 314        struct bcr_mpy extn_mpy;
 315};
 316
 317extern struct cpuinfo_arc cpuinfo_arc700[];
 318
 319static inline int is_isa_arcv2(void)
 320{
 321        return IS_ENABLED(CONFIG_ISA_ARCV2);
 322}
 323
 324static inline int is_isa_arcompact(void)
 325{
 326        return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
 327}
 328
 329#endif /* __ASEMBLY__ */
 330
 331#endif /* _ASM_ARC_ARCREGS_H */
 332