1
2
3
4
5
6#ifndef _PLAT_EZNPS_CTOP_H
7#define _PLAT_EZNPS_CTOP_H
8
9#ifndef CONFIG_ARC_PLAT_EZNPS
10#error "Incorrect ctop.h include"
11#endif
12
13#include <linux/bits.h>
14#include <linux/types.h>
15#include <soc/nps/common.h>
16
17
18#ifdef __ASSEMBLY__
19#define CTOP_AUX_BASE (-0x800)
20#else
21#define CTOP_AUX_BASE 0xFFFFF800
22#endif
23
24#define CTOP_AUX_GLOBAL_ID (CTOP_AUX_BASE + 0x000)
25#define CTOP_AUX_CLUSTER_ID (CTOP_AUX_BASE + 0x004)
26#define CTOP_AUX_CORE_ID (CTOP_AUX_BASE + 0x008)
27#define CTOP_AUX_THREAD_ID (CTOP_AUX_BASE + 0x00C)
28#define CTOP_AUX_LOGIC_GLOBAL_ID (CTOP_AUX_BASE + 0x010)
29#define CTOP_AUX_LOGIC_CLUSTER_ID (CTOP_AUX_BASE + 0x014)
30#define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
31#define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
32#define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
33#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
34#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
35#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
36#define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
37#define CTOP_AUX_GPA1 (CTOP_AUX_BASE + 0x08C)
38#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
39
40
41#define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
42#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
43#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
44#define CTOP_INST_SCHD_RW 0x3E6F7004
45#define CTOP_INST_SCHD_RD 0x3E6F7084
46#define CTOP_INST_ASRI_0_R3 0x3B56003E
47#define CTOP_INST_XEX_DI_R2_R2_R3 0x4A664C00
48#define CTOP_INST_EXC_DI_R2_R2_R3 0x4A664C01
49#define CTOP_INST_AADD_DI_R2_R2_R3 0x4A664C02
50#define CTOP_INST_AAND_DI_R2_R2_R3 0x4A664C04
51#define CTOP_INST_AOR_DI_R2_R2_R3 0x4A664C05
52#define CTOP_INST_AXOR_DI_R2_R2_R3 0x4A664C06
53
54
55#define HW_COMPLY_KRN_NOT_D_CACHED BIT(28)
56
57#define NPS_MSU_EN_CFG 0x80
58#define NPS_CRG_BLKID 0x480
59#define NPS_CRG_SYNC_BIT BIT(0)
60#define NPS_GIM_BLKID 0x5C0
61
62
63#define NPS_GIM_UART_LINE BIT(7)
64#define NPS_GIM_DBG_LAN_EAST_TX_DONE_LINE BIT(10)
65#define NPS_GIM_DBG_LAN_EAST_RX_RDY_LINE BIT(11)
66#define NPS_GIM_DBG_LAN_WEST_TX_DONE_LINE BIT(25)
67#define NPS_GIM_DBG_LAN_WEST_RX_RDY_LINE BIT(26)
68
69#ifndef __ASSEMBLY__
70
71struct nps_host_reg_mtm_cfg {
72 union {
73 struct {
74 u32 gen:1, gdis:1, clk_gate_dis:1, asb:1,
75 __reserved:9, nat:3, ten:16;
76 };
77 u32 value;
78 };
79};
80
81struct nps_host_reg_mtm_cpu_cfg {
82 union {
83 struct {
84 u32 csa:22, dmsid:6, __reserved:3, cs:1;
85 };
86 u32 value;
87 };
88};
89
90struct nps_host_reg_thr_init {
91 union {
92 struct {
93 u32 str:1, __reserved:27, thr_id:4;
94 };
95 u32 value;
96 };
97};
98
99struct nps_host_reg_thr_init_sts {
100 union {
101 struct {
102 u32 bsy:1, err:1, __reserved:26, thr_id:4;
103 };
104 u32 value;
105 };
106};
107
108struct nps_host_reg_msu_en_cfg {
109 union {
110 struct {
111 u32 __reserved1:11,
112 rtc_en:1, ipc_en:1, gim_1_en:1,
113 gim_0_en:1, ipi_en:1, buff_e_rls_bmuw:1,
114 buff_e_alc_bmuw:1, buff_i_rls_bmuw:1, buff_i_alc_bmuw:1,
115 buff_e_rls_bmue:1, buff_e_alc_bmue:1, buff_i_rls_bmue:1,
116 buff_i_alc_bmue:1, __reserved2:1, buff_e_pre_en:1,
117 buff_i_pre_en:1, pmuw_ja_en:1, pmue_ja_en:1,
118 pmuw_nj_en:1, pmue_nj_en:1, msu_en:1;
119 };
120 u32 value;
121 };
122};
123
124struct nps_host_reg_gim_p_int_dst {
125 union {
126 struct {
127 u32 int_out_en:1, __reserved1:4,
128 is:1, intm:2, __reserved2:4,
129 nid:4, __reserved3:4, cid:4,
130 __reserved4:4, tid:4;
131 };
132 u32 value;
133 };
134};
135
136
137struct nps_host_reg_aux_dpc {
138 union {
139 struct {
140 u32 ien:1, men:1, hen:1, reserved:29;
141 };
142 u32 value;
143 };
144};
145
146struct nps_host_reg_aux_udmc {
147 union {
148 struct {
149 u32 dcp:1, cme:1, __reserved:19, nat:3,
150 __reserved2:5, dcas:3;
151 };
152 u32 value;
153 };
154};
155
156struct nps_host_reg_aux_mt_ctrl {
157 union {
158 struct {
159 u32 mten:1, hsen:1, scd:1, sten:1,
160 st_cnt:8, __reserved:8,
161 hs_cnt:8, __reserved1:4;
162 };
163 u32 value;
164 };
165};
166
167struct nps_host_reg_aux_hw_comply {
168 union {
169 struct {
170 u32 me:1, le:1, te:1, knc:1, __reserved:28;
171 };
172 u32 value;
173 };
174};
175
176struct nps_host_reg_aux_lpc {
177 union {
178 struct {
179 u32 mep:1, __reserved:31;
180 };
181 u32 value;
182 };
183};
184
185
186#define REG_GEN_PURP_0 nps_host_reg_non_cl(NPS_CRG_BLKID, 0x1BF)
187
188
189#define REG_GIM_P_INT_EN_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x100)
190#define REG_GIM_P_INT_POL_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x110)
191#define REG_GIM_P_INT_SENS_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x114)
192#define REG_GIM_P_INT_BLK_0 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x118)
193#define REG_GIM_P_INT_DST_10 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13A)
194#define REG_GIM_P_INT_DST_11 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x13B)
195#define REG_GIM_P_INT_DST_25 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x149)
196#define REG_GIM_P_INT_DST_26 nps_host_reg_non_cl(NPS_GIM_BLKID, 0x14A)
197
198#else
199
200.macro GET_CPU_ID reg
201 lr \reg, [CTOP_AUX_LOGIC_GLOBAL_ID]
202#ifndef CONFIG_EZNPS_MTM_EXT
203 lsr \reg, \reg, 4
204#endif
205.endm
206
207#endif
208
209#endif
210
