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16#include <linux/clk-provider.h>
17#include <linux/clk/davinci.h>
18#include <linux/clkdev.h>
19#include <linux/dma-mapping.h>
20#include <linux/dmaengine.h>
21#include <linux/init.h>
22#include <linux/io.h>
23#include <linux/irqchip/irq-davinci-aintc.h>
24#include <linux/platform_data/edma.h>
25#include <linux/platform_data/gpio-davinci.h>
26#include <linux/platform_data/keyscan-davinci.h>
27#include <linux/platform_data/spi-davinci.h>
28#include <linux/platform_device.h>
29#include <linux/serial_8250.h>
30#include <linux/spi/spi.h>
31
32#include <asm/mach/map.h>
33
34#include <mach/common.h>
35#include <mach/cputype.h>
36#include <mach/mux.h>
37#include <mach/serial.h>
38#include <mach/time.h>
39
40#include "asp.h"
41#include "davinci.h"
42#include "irqs.h"
43#include "mux.h"
44
45#define DM365_REF_FREQ 24000000
46#define DM365_RTC_BASE 0x01c69000
47#define DM365_KEYSCAN_BASE 0x01c69400
48#define DM365_OSD_BASE 0x01c71c00
49#define DM365_VENC_BASE 0x01c71e00
50#define DAVINCI_DM365_VC_BASE 0x01d0c000
51#define DAVINCI_DMA_VC_TX 2
52#define DAVINCI_DMA_VC_RX 3
53#define DM365_EMAC_BASE 0x01d07000
54#define DM365_EMAC_MDIO_BASE (DM365_EMAC_BASE + 0x4000)
55#define DM365_EMAC_CNTRL_OFFSET 0x0000
56#define DM365_EMAC_CNTRL_MOD_OFFSET 0x3000
57#define DM365_EMAC_CNTRL_RAM_OFFSET 0x1000
58#define DM365_EMAC_CNTRL_RAM_SIZE 0x2000
59
60#define INTMUX 0x18
61#define EVTMUX 0x1c
62
63
64static const struct mux_config dm365_pins[] = {
65#ifdef CONFIG_DAVINCI_MUX
66MUX_CFG(DM365, MMCSD0, 0, 24, 1, 0, false)
67
68MUX_CFG(DM365, SD1_CLK, 0, 16, 3, 1, false)
69MUX_CFG(DM365, SD1_CMD, 4, 30, 3, 1, false)
70MUX_CFG(DM365, SD1_DATA3, 4, 28, 3, 1, false)
71MUX_CFG(DM365, SD1_DATA2, 4, 26, 3, 1, false)
72MUX_CFG(DM365, SD1_DATA1, 4, 24, 3, 1, false)
73MUX_CFG(DM365, SD1_DATA0, 4, 22, 3, 1, false)
74
75MUX_CFG(DM365, I2C_SDA, 3, 23, 3, 2, false)
76MUX_CFG(DM365, I2C_SCL, 3, 21, 3, 2, false)
77
78MUX_CFG(DM365, AEMIF_AR_A14, 2, 0, 3, 1, false)
79MUX_CFG(DM365, AEMIF_AR_BA0, 2, 0, 3, 2, false)
80MUX_CFG(DM365, AEMIF_A3, 2, 2, 3, 1, false)
81MUX_CFG(DM365, AEMIF_A7, 2, 4, 3, 1, false)
82MUX_CFG(DM365, AEMIF_D15_8, 2, 6, 1, 1, false)
83MUX_CFG(DM365, AEMIF_CE0, 2, 7, 1, 0, false)
84MUX_CFG(DM365, AEMIF_CE1, 2, 8, 1, 0, false)
85MUX_CFG(DM365, AEMIF_WE_OE, 2, 9, 1, 0, false)
86
87MUX_CFG(DM365, MCBSP0_BDX, 0, 23, 1, 1, false)
88MUX_CFG(DM365, MCBSP0_X, 0, 22, 1, 1, false)
89MUX_CFG(DM365, MCBSP0_BFSX, 0, 21, 1, 1, false)
90MUX_CFG(DM365, MCBSP0_BDR, 0, 20, 1, 1, false)
91MUX_CFG(DM365, MCBSP0_R, 0, 19, 1, 1, false)
92MUX_CFG(DM365, MCBSP0_BFSR, 0, 18, 1, 1, false)
93
94MUX_CFG(DM365, SPI0_SCLK, 3, 28, 1, 1, false)
95MUX_CFG(DM365, SPI0_SDI, 3, 26, 3, 1, false)
96MUX_CFG(DM365, SPI0_SDO, 3, 25, 1, 1, false)
97MUX_CFG(DM365, SPI0_SDENA0, 3, 29, 3, 1, false)
98MUX_CFG(DM365, SPI0_SDENA1, 3, 26, 3, 2, false)
99
100MUX_CFG(DM365, UART0_RXD, 3, 20, 1, 1, false)
101MUX_CFG(DM365, UART0_TXD, 3, 19, 1, 1, false)
102MUX_CFG(DM365, UART1_RXD, 3, 17, 3, 2, false)
103MUX_CFG(DM365, UART1_TXD, 3, 15, 3, 2, false)
104MUX_CFG(DM365, UART1_RTS, 3, 23, 3, 1, false)
105MUX_CFG(DM365, UART1_CTS, 3, 21, 3, 1, false)
106
107MUX_CFG(DM365, EMAC_TX_EN, 3, 17, 3, 1, false)
108MUX_CFG(DM365, EMAC_TX_CLK, 3, 15, 3, 1, false)
109MUX_CFG(DM365, EMAC_COL, 3, 14, 1, 1, false)
110MUX_CFG(DM365, EMAC_TXD3, 3, 13, 1, 1, false)
111MUX_CFG(DM365, EMAC_TXD2, 3, 12, 1, 1, false)
112MUX_CFG(DM365, EMAC_TXD1, 3, 11, 1, 1, false)
113MUX_CFG(DM365, EMAC_TXD0, 3, 10, 1, 1, false)
114MUX_CFG(DM365, EMAC_RXD3, 3, 9, 1, 1, false)
115MUX_CFG(DM365, EMAC_RXD2, 3, 8, 1, 1, false)
116MUX_CFG(DM365, EMAC_RXD1, 3, 7, 1, 1, false)
117MUX_CFG(DM365, EMAC_RXD0, 3, 6, 1, 1, false)
118MUX_CFG(DM365, EMAC_RX_CLK, 3, 5, 1, 1, false)
119MUX_CFG(DM365, EMAC_RX_DV, 3, 4, 1, 1, false)
120MUX_CFG(DM365, EMAC_RX_ER, 3, 3, 1, 1, false)
121MUX_CFG(DM365, EMAC_CRS, 3, 2, 1, 1, false)
122MUX_CFG(DM365, EMAC_MDIO, 3, 1, 1, 1, false)
123MUX_CFG(DM365, EMAC_MDCLK, 3, 0, 1, 1, false)
124
125MUX_CFG(DM365, KEYSCAN, 2, 0, 0x3f, 0x3f, false)
126
127MUX_CFG(DM365, PWM0, 1, 0, 3, 2, false)
128MUX_CFG(DM365, PWM0_G23, 3, 26, 3, 3, false)
129MUX_CFG(DM365, PWM1, 1, 2, 3, 2, false)
130MUX_CFG(DM365, PWM1_G25, 3, 29, 3, 2, false)
131MUX_CFG(DM365, PWM2_G87, 1, 10, 3, 2, false)
132MUX_CFG(DM365, PWM2_G88, 1, 8, 3, 2, false)
133MUX_CFG(DM365, PWM2_G89, 1, 6, 3, 2, false)
134MUX_CFG(DM365, PWM2_G90, 1, 4, 3, 2, false)
135MUX_CFG(DM365, PWM3_G80, 1, 20, 3, 3, false)
136MUX_CFG(DM365, PWM3_G81, 1, 18, 3, 3, false)
137MUX_CFG(DM365, PWM3_G85, 1, 14, 3, 2, false)
138MUX_CFG(DM365, PWM3_G86, 1, 12, 3, 2, false)
139
140MUX_CFG(DM365, SPI1_SCLK, 4, 2, 3, 1, false)
141MUX_CFG(DM365, SPI1_SDI, 3, 31, 1, 1, false)
142MUX_CFG(DM365, SPI1_SDO, 4, 0, 3, 1, false)
143MUX_CFG(DM365, SPI1_SDENA0, 4, 4, 3, 1, false)
144MUX_CFG(DM365, SPI1_SDENA1, 4, 0, 3, 2, false)
145
146MUX_CFG(DM365, SPI2_SCLK, 4, 10, 3, 1, false)
147MUX_CFG(DM365, SPI2_SDI, 4, 6, 3, 1, false)
148MUX_CFG(DM365, SPI2_SDO, 4, 8, 3, 1, false)
149MUX_CFG(DM365, SPI2_SDENA0, 4, 12, 3, 1, false)
150MUX_CFG(DM365, SPI2_SDENA1, 4, 8, 3, 2, false)
151
152MUX_CFG(DM365, SPI3_SCLK, 0, 0, 3, 2, false)
153MUX_CFG(DM365, SPI3_SDI, 0, 2, 3, 2, false)
154MUX_CFG(DM365, SPI3_SDO, 0, 6, 3, 2, false)
155MUX_CFG(DM365, SPI3_SDENA0, 0, 4, 3, 2, false)
156MUX_CFG(DM365, SPI3_SDENA1, 0, 6, 3, 3, false)
157
158MUX_CFG(DM365, SPI4_SCLK, 4, 18, 3, 1, false)
159MUX_CFG(DM365, SPI4_SDI, 4, 14, 3, 1, false)
160MUX_CFG(DM365, SPI4_SDO, 4, 16, 3, 1, false)
161MUX_CFG(DM365, SPI4_SDENA0, 4, 20, 3, 1, false)
162MUX_CFG(DM365, SPI4_SDENA1, 4, 16, 3, 2, false)
163
164MUX_CFG(DM365, CLKOUT0, 4, 20, 3, 3, false)
165MUX_CFG(DM365, CLKOUT1, 4, 16, 3, 3, false)
166MUX_CFG(DM365, CLKOUT2, 4, 8, 3, 3, false)
167
168MUX_CFG(DM365, GPIO20, 3, 21, 3, 0, false)
169MUX_CFG(DM365, GPIO30, 4, 6, 3, 0, false)
170MUX_CFG(DM365, GPIO31, 4, 8, 3, 0, false)
171MUX_CFG(DM365, GPIO32, 4, 10, 3, 0, false)
172MUX_CFG(DM365, GPIO33, 4, 12, 3, 0, false)
173MUX_CFG(DM365, GPIO40, 4, 26, 3, 0, false)
174MUX_CFG(DM365, GPIO64_57, 2, 6, 1, 0, false)
175
176MUX_CFG(DM365, VOUT_FIELD, 1, 18, 3, 1, false)
177MUX_CFG(DM365, VOUT_FIELD_G81, 1, 18, 3, 0, false)
178MUX_CFG(DM365, VOUT_HVSYNC, 1, 16, 1, 0, false)
179MUX_CFG(DM365, VOUT_COUTL_EN, 1, 0, 0xff, 0x55, false)
180MUX_CFG(DM365, VOUT_COUTH_EN, 1, 8, 0xff, 0x55, false)
181MUX_CFG(DM365, VIN_CAM_WEN, 0, 14, 3, 0, false)
182MUX_CFG(DM365, VIN_CAM_VD, 0, 13, 1, 0, false)
183MUX_CFG(DM365, VIN_CAM_HD, 0, 12, 1, 0, false)
184MUX_CFG(DM365, VIN_YIN4_7_EN, 0, 0, 0xff, 0, false)
185MUX_CFG(DM365, VIN_YIN0_3_EN, 0, 8, 0xf, 0, false)
186
187INT_CFG(DM365, INT_EDMA_CC, 2, 1, 1, false)
188INT_CFG(DM365, INT_EDMA_TC0_ERR, 3, 1, 1, false)
189INT_CFG(DM365, INT_EDMA_TC1_ERR, 4, 1, 1, false)
190INT_CFG(DM365, INT_EDMA_TC2_ERR, 22, 1, 1, false)
191INT_CFG(DM365, INT_EDMA_TC3_ERR, 23, 1, 1, false)
192INT_CFG(DM365, INT_PRTCSS, 10, 1, 1, false)
193INT_CFG(DM365, INT_EMAC_RXTHRESH, 14, 1, 1, false)
194INT_CFG(DM365, INT_EMAC_RXPULSE, 15, 1, 1, false)
195INT_CFG(DM365, INT_EMAC_TXPULSE, 16, 1, 1, false)
196INT_CFG(DM365, INT_EMAC_MISCPULSE, 17, 1, 1, false)
197INT_CFG(DM365, INT_IMX0_ENABLE, 0, 1, 0, false)
198INT_CFG(DM365, INT_IMX0_DISABLE, 0, 1, 1, false)
199INT_CFG(DM365, INT_HDVICP_ENABLE, 0, 1, 1, false)
200INT_CFG(DM365, INT_HDVICP_DISABLE, 0, 1, 0, false)
201INT_CFG(DM365, INT_IMX1_ENABLE, 24, 1, 1, false)
202INT_CFG(DM365, INT_IMX1_DISABLE, 24, 1, 0, false)
203INT_CFG(DM365, INT_NSF_ENABLE, 25, 1, 1, false)
204INT_CFG(DM365, INT_NSF_DISABLE, 25, 1, 0, false)
205
206EVT_CFG(DM365, EVT2_ASP_TX, 0, 1, 0, false)
207EVT_CFG(DM365, EVT3_ASP_RX, 1, 1, 0, false)
208EVT_CFG(DM365, EVT2_VC_TX, 0, 1, 1, false)
209EVT_CFG(DM365, EVT3_VC_RX, 1, 1, 1, false)
210#endif
211};
212
213static u64 dm365_spi0_dma_mask = DMA_BIT_MASK(32);
214
215static struct davinci_spi_platform_data dm365_spi0_pdata = {
216 .version = SPI_VERSION_1,
217 .num_chipselect = 2,
218 .dma_event_q = EVENTQ_3,
219 .prescaler_limit = 1,
220};
221
222static struct resource dm365_spi0_resources[] = {
223 {
224 .start = 0x01c66000,
225 .end = 0x01c667ff,
226 .flags = IORESOURCE_MEM,
227 },
228 {
229 .start = DAVINCI_INTC_IRQ(IRQ_DM365_SPIINT0_0),
230 .flags = IORESOURCE_IRQ,
231 },
232};
233
234static struct platform_device dm365_spi0_device = {
235 .name = "spi_davinci",
236 .id = 0,
237 .dev = {
238 .dma_mask = &dm365_spi0_dma_mask,
239 .coherent_dma_mask = DMA_BIT_MASK(32),
240 .platform_data = &dm365_spi0_pdata,
241 },
242 .num_resources = ARRAY_SIZE(dm365_spi0_resources),
243 .resource = dm365_spi0_resources,
244};
245
246void __init dm365_init_spi0(unsigned chipselect_mask,
247 const struct spi_board_info *info, unsigned len)
248{
249 davinci_cfg_reg(DM365_SPI0_SCLK);
250 davinci_cfg_reg(DM365_SPI0_SDI);
251 davinci_cfg_reg(DM365_SPI0_SDO);
252
253
254 if (chipselect_mask & BIT(0))
255 davinci_cfg_reg(DM365_SPI0_SDENA0);
256 if (chipselect_mask & BIT(1))
257 davinci_cfg_reg(DM365_SPI0_SDENA1);
258
259 spi_register_board_info(info, len);
260
261 platform_device_register(&dm365_spi0_device);
262}
263
264static struct resource dm365_gpio_resources[] = {
265 {
266 .start = DAVINCI_GPIO_BASE,
267 .end = DAVINCI_GPIO_BASE + SZ_4K - 1,
268 .flags = IORESOURCE_MEM,
269 },
270 {
271 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
272 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO0),
273 .flags = IORESOURCE_IRQ,
274 },
275 {
276 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
277 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO1),
278 .flags = IORESOURCE_IRQ,
279 },
280 {
281 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
282 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO2),
283 .flags = IORESOURCE_IRQ,
284 },
285 {
286 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
287 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO3),
288 .flags = IORESOURCE_IRQ,
289 },
290 {
291 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
292 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO4),
293 .flags = IORESOURCE_IRQ,
294 },
295 {
296 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
297 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO5),
298 .flags = IORESOURCE_IRQ,
299 },
300 {
301 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
302 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO6),
303 .flags = IORESOURCE_IRQ,
304 },
305 {
306 .start = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
307 .end = DAVINCI_INTC_IRQ(IRQ_DM365_GPIO7),
308 .flags = IORESOURCE_IRQ,
309 },
310};
311
312static struct davinci_gpio_platform_data dm365_gpio_platform_data = {
313 .no_auto_base = true,
314 .base = 0,
315 .ngpio = 104,
316 .gpio_unbanked = 8,
317};
318
319int __init dm365_gpio_register(void)
320{
321 return davinci_gpio_register(dm365_gpio_resources,
322 ARRAY_SIZE(dm365_gpio_resources),
323 &dm365_gpio_platform_data);
324}
325
326static struct emac_platform_data dm365_emac_pdata = {
327 .ctrl_reg_offset = DM365_EMAC_CNTRL_OFFSET,
328 .ctrl_mod_reg_offset = DM365_EMAC_CNTRL_MOD_OFFSET,
329 .ctrl_ram_offset = DM365_EMAC_CNTRL_RAM_OFFSET,
330 .ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE,
331 .version = EMAC_VERSION_2,
332};
333
334static struct resource dm365_emac_resources[] = {
335 {
336 .start = DM365_EMAC_BASE,
337 .end = DM365_EMAC_BASE + SZ_16K - 1,
338 .flags = IORESOURCE_MEM,
339 },
340 {
341 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
342 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXTHRESH),
343 .flags = IORESOURCE_IRQ,
344 },
345 {
346 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
347 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_RXPULSE),
348 .flags = IORESOURCE_IRQ,
349 },
350 {
351 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
352 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_TXPULSE),
353 .flags = IORESOURCE_IRQ,
354 },
355 {
356 .start = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
357 .end = DAVINCI_INTC_IRQ(IRQ_DM365_EMAC_MISCPULSE),
358 .flags = IORESOURCE_IRQ,
359 },
360};
361
362static struct platform_device dm365_emac_device = {
363 .name = "davinci_emac",
364 .id = 1,
365 .dev = {
366 .platform_data = &dm365_emac_pdata,
367 },
368 .num_resources = ARRAY_SIZE(dm365_emac_resources),
369 .resource = dm365_emac_resources,
370};
371
372static struct resource dm365_mdio_resources[] = {
373 {
374 .start = DM365_EMAC_MDIO_BASE,
375 .end = DM365_EMAC_MDIO_BASE + SZ_4K - 1,
376 .flags = IORESOURCE_MEM,
377 },
378};
379
380static struct platform_device dm365_mdio_device = {
381 .name = "davinci_mdio",
382 .id = 0,
383 .num_resources = ARRAY_SIZE(dm365_mdio_resources),
384 .resource = dm365_mdio_resources,
385};
386
387static u8 dm365_default_priorities[DAVINCI_N_AINTC_IRQ] = {
388 [IRQ_VDINT0] = 2,
389 [IRQ_VDINT1] = 6,
390 [IRQ_VDINT2] = 6,
391 [IRQ_HISTINT] = 6,
392 [IRQ_H3AINT] = 6,
393 [IRQ_PRVUINT] = 6,
394 [IRQ_RSZINT] = 6,
395 [IRQ_DM365_INSFINT] = 7,
396 [IRQ_VENCINT] = 6,
397 [IRQ_ASQINT] = 6,
398 [IRQ_IMXINT] = 6,
399 [IRQ_DM365_IMCOPINT] = 4,
400 [IRQ_USBINT] = 4,
401 [IRQ_DM365_RTOINT] = 7,
402 [IRQ_DM365_TINT5] = 7,
403 [IRQ_DM365_TINT6] = 5,
404 [IRQ_CCINT0] = 5,
405 [IRQ_CCERRINT] = 5,
406 [IRQ_TCERRINT0] = 5,
407 [IRQ_TCERRINT] = 7,
408 [IRQ_PSCIN] = 4,
409 [IRQ_DM365_SPINT2_1] = 7,
410 [IRQ_DM365_TINT7] = 7,
411 [IRQ_DM365_SDIOINT0] = 7,
412 [IRQ_MBXINT] = 7,
413 [IRQ_MBRINT] = 7,
414 [IRQ_MMCINT] = 7,
415 [IRQ_DM365_MMCINT1] = 7,
416 [IRQ_DM365_PWMINT3] = 7,
417 [IRQ_AEMIFINT] = 2,
418 [IRQ_DM365_SDIOINT1] = 2,
419 [IRQ_TINT0_TINT12] = 7,
420 [IRQ_TINT0_TINT34] = 7,
421 [IRQ_TINT1_TINT12] = 7,
422 [IRQ_TINT1_TINT34] = 7,
423 [IRQ_PWMINT0] = 7,
424 [IRQ_PWMINT1] = 3,
425 [IRQ_PWMINT2] = 3,
426 [IRQ_I2C] = 3,
427 [IRQ_UARTINT0] = 3,
428 [IRQ_UARTINT1] = 3,
429 [IRQ_DM365_RTCINT] = 3,
430 [IRQ_DM365_SPIINT0_0] = 3,
431 [IRQ_DM365_SPIINT3_0] = 3,
432 [IRQ_DM365_GPIO0] = 3,
433 [IRQ_DM365_GPIO1] = 7,
434 [IRQ_DM365_GPIO2] = 4,
435 [IRQ_DM365_GPIO3] = 4,
436 [IRQ_DM365_GPIO4] = 7,
437 [IRQ_DM365_GPIO5] = 7,
438 [IRQ_DM365_GPIO6] = 7,
439 [IRQ_DM365_GPIO7] = 7,
440 [IRQ_DM365_EMAC_RXTHRESH] = 7,
441 [IRQ_DM365_EMAC_RXPULSE] = 7,
442 [IRQ_DM365_EMAC_TXPULSE] = 7,
443 [IRQ_DM365_EMAC_MISCPULSE] = 7,
444 [IRQ_DM365_GPIO12] = 7,
445 [IRQ_DM365_GPIO13] = 7,
446 [IRQ_DM365_GPIO14] = 7,
447 [IRQ_DM365_GPIO15] = 7,
448 [IRQ_DM365_KEYINT] = 7,
449 [IRQ_DM365_TCERRINT2] = 7,
450 [IRQ_DM365_TCERRINT3] = 7,
451 [IRQ_DM365_EMUINT] = 7,
452};
453
454
455static s8 dm365_queue_priority_mapping[][2] = {
456
457 {0, 7},
458 {1, 7},
459 {2, 7},
460 {3, 0},
461 {-1, -1},
462};
463
464static const struct dma_slave_map dm365_edma_map[] = {
465 { "davinci-mcbsp.0", "tx", EDMA_FILTER_PARAM(0, 2) },
466 { "davinci-mcbsp.0", "rx", EDMA_FILTER_PARAM(0, 3) },
467 { "davinci_voicecodec", "tx", EDMA_FILTER_PARAM(0, 2) },
468 { "davinci_voicecodec", "rx", EDMA_FILTER_PARAM(0, 3) },
469 { "spi_davinci.2", "tx", EDMA_FILTER_PARAM(0, 10) },
470 { "spi_davinci.2", "rx", EDMA_FILTER_PARAM(0, 11) },
471 { "spi_davinci.1", "tx", EDMA_FILTER_PARAM(0, 14) },
472 { "spi_davinci.1", "rx", EDMA_FILTER_PARAM(0, 15) },
473 { "spi_davinci.0", "tx", EDMA_FILTER_PARAM(0, 16) },
474 { "spi_davinci.0", "rx", EDMA_FILTER_PARAM(0, 17) },
475 { "spi_davinci.3", "tx", EDMA_FILTER_PARAM(0, 18) },
476 { "spi_davinci.3", "rx", EDMA_FILTER_PARAM(0, 19) },
477 { "da830-mmc.0", "rx", EDMA_FILTER_PARAM(0, 26) },
478 { "da830-mmc.0", "tx", EDMA_FILTER_PARAM(0, 27) },
479 { "da830-mmc.1", "rx", EDMA_FILTER_PARAM(0, 30) },
480 { "da830-mmc.1", "tx", EDMA_FILTER_PARAM(0, 31) },
481};
482
483static struct edma_soc_info dm365_edma_pdata = {
484 .queue_priority_mapping = dm365_queue_priority_mapping,
485 .default_queue = EVENTQ_3,
486 .slave_map = dm365_edma_map,
487 .slavecnt = ARRAY_SIZE(dm365_edma_map),
488};
489
490static struct resource edma_resources[] = {
491 {
492 .name = "edma3_cc",
493 .start = 0x01c00000,
494 .end = 0x01c00000 + SZ_64K - 1,
495 .flags = IORESOURCE_MEM,
496 },
497 {
498 .name = "edma3_tc0",
499 .start = 0x01c10000,
500 .end = 0x01c10000 + SZ_1K - 1,
501 .flags = IORESOURCE_MEM,
502 },
503 {
504 .name = "edma3_tc1",
505 .start = 0x01c10400,
506 .end = 0x01c10400 + SZ_1K - 1,
507 .flags = IORESOURCE_MEM,
508 },
509 {
510 .name = "edma3_tc2",
511 .start = 0x01c10800,
512 .end = 0x01c10800 + SZ_1K - 1,
513 .flags = IORESOURCE_MEM,
514 },
515 {
516 .name = "edma3_tc3",
517 .start = 0x01c10c00,
518 .end = 0x01c10c00 + SZ_1K - 1,
519 .flags = IORESOURCE_MEM,
520 },
521 {
522 .name = "edma3_ccint",
523 .start = DAVINCI_INTC_IRQ(IRQ_CCINT0),
524 .flags = IORESOURCE_IRQ,
525 },
526 {
527 .name = "edma3_ccerrint",
528 .start = DAVINCI_INTC_IRQ(IRQ_CCERRINT),
529 .flags = IORESOURCE_IRQ,
530 },
531
532};
533
534static const struct platform_device_info dm365_edma_device __initconst = {
535 .name = "edma",
536 .id = 0,
537 .dma_mask = DMA_BIT_MASK(32),
538 .res = edma_resources,
539 .num_res = ARRAY_SIZE(edma_resources),
540 .data = &dm365_edma_pdata,
541 .size_data = sizeof(dm365_edma_pdata),
542};
543
544static struct resource dm365_asp_resources[] = {
545 {
546 .name = "mpu",
547 .start = DAVINCI_DM365_ASP0_BASE,
548 .end = DAVINCI_DM365_ASP0_BASE + SZ_8K - 1,
549 .flags = IORESOURCE_MEM,
550 },
551 {
552 .start = DAVINCI_DMA_ASP0_TX,
553 .end = DAVINCI_DMA_ASP0_TX,
554 .flags = IORESOURCE_DMA,
555 },
556 {
557 .start = DAVINCI_DMA_ASP0_RX,
558 .end = DAVINCI_DMA_ASP0_RX,
559 .flags = IORESOURCE_DMA,
560 },
561};
562
563static struct platform_device dm365_asp_device = {
564 .name = "davinci-mcbsp",
565 .id = -1,
566 .num_resources = ARRAY_SIZE(dm365_asp_resources),
567 .resource = dm365_asp_resources,
568};
569
570static struct resource dm365_vc_resources[] = {
571 {
572 .start = DAVINCI_DM365_VC_BASE,
573 .end = DAVINCI_DM365_VC_BASE + SZ_1K - 1,
574 .flags = IORESOURCE_MEM,
575 },
576 {
577 .start = DAVINCI_DMA_VC_TX,
578 .end = DAVINCI_DMA_VC_TX,
579 .flags = IORESOURCE_DMA,
580 },
581 {
582 .start = DAVINCI_DMA_VC_RX,
583 .end = DAVINCI_DMA_VC_RX,
584 .flags = IORESOURCE_DMA,
585 },
586};
587
588static struct platform_device dm365_vc_device = {
589 .name = "davinci_voicecodec",
590 .id = -1,
591 .num_resources = ARRAY_SIZE(dm365_vc_resources),
592 .resource = dm365_vc_resources,
593};
594
595static struct resource dm365_rtc_resources[] = {
596 {
597 .start = DM365_RTC_BASE,
598 .end = DM365_RTC_BASE + SZ_1K - 1,
599 .flags = IORESOURCE_MEM,
600 },
601 {
602 .start = DAVINCI_INTC_IRQ(IRQ_DM365_RTCINT),
603 .flags = IORESOURCE_IRQ,
604 },
605};
606
607static struct platform_device dm365_rtc_device = {
608 .name = "rtc_davinci",
609 .id = 0,
610 .num_resources = ARRAY_SIZE(dm365_rtc_resources),
611 .resource = dm365_rtc_resources,
612};
613
614static struct map_desc dm365_io_desc[] = {
615 {
616 .virtual = IO_VIRT,
617 .pfn = __phys_to_pfn(IO_PHYS),
618 .length = IO_SIZE,
619 .type = MT_DEVICE
620 },
621};
622
623static struct resource dm365_ks_resources[] = {
624 {
625
626 .start = DM365_KEYSCAN_BASE,
627 .end = DM365_KEYSCAN_BASE + SZ_1K - 1,
628 .flags = IORESOURCE_MEM,
629 },
630 {
631
632 .start = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
633 .end = DAVINCI_INTC_IRQ(IRQ_DM365_KEYINT),
634 .flags = IORESOURCE_IRQ,
635 },
636};
637
638static struct platform_device dm365_ks_device = {
639 .name = "davinci_keyscan",
640 .id = 0,
641 .num_resources = ARRAY_SIZE(dm365_ks_resources),
642 .resource = dm365_ks_resources,
643};
644
645
646static struct davinci_id dm365_ids[] = {
647 {
648 .variant = 0x0,
649 .part_no = 0xb83e,
650 .manufacturer = 0x017,
651 .cpu_id = DAVINCI_CPU_ID_DM365,
652 .name = "dm365_rev1.1",
653 },
654 {
655 .variant = 0x8,
656 .part_no = 0xb83e,
657 .manufacturer = 0x017,
658 .cpu_id = DAVINCI_CPU_ID_DM365,
659 .name = "dm365_rev1.2",
660 },
661};
662
663static struct davinci_timer_info dm365_timer_info = {
664 .timers = davinci_timer_instance,
665 .clockevent_id = T0_BOT,
666 .clocksource_id = T0_TOP,
667};
668
669#define DM365_UART1_BASE (IO_PHYS + 0x106000)
670
671static struct plat_serial8250_port dm365_serial0_platform_data[] = {
672 {
673 .mapbase = DAVINCI_UART0_BASE,
674 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT0),
675 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
676 UPF_IOREMAP,
677 .iotype = UPIO_MEM,
678 .regshift = 2,
679 },
680 {
681 .flags = 0,
682 }
683};
684static struct plat_serial8250_port dm365_serial1_platform_data[] = {
685 {
686 .mapbase = DM365_UART1_BASE,
687 .irq = DAVINCI_INTC_IRQ(IRQ_UARTINT1),
688 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
689 UPF_IOREMAP,
690 .iotype = UPIO_MEM,
691 .regshift = 2,
692 },
693 {
694 .flags = 0,
695 }
696};
697
698struct platform_device dm365_serial_device[] = {
699 {
700 .name = "serial8250",
701 .id = PLAT8250_DEV_PLATFORM,
702 .dev = {
703 .platform_data = dm365_serial0_platform_data,
704 }
705 },
706 {
707 .name = "serial8250",
708 .id = PLAT8250_DEV_PLATFORM1,
709 .dev = {
710 .platform_data = dm365_serial1_platform_data,
711 }
712 },
713 {
714 }
715};
716
717static const struct davinci_soc_info davinci_soc_info_dm365 = {
718 .io_desc = dm365_io_desc,
719 .io_desc_num = ARRAY_SIZE(dm365_io_desc),
720 .jtag_id_reg = 0x01c40028,
721 .ids = dm365_ids,
722 .ids_num = ARRAY_SIZE(dm365_ids),
723 .pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
724 .pinmux_pins = dm365_pins,
725 .pinmux_pins_num = ARRAY_SIZE(dm365_pins),
726 .timer_info = &dm365_timer_info,
727 .emac_pdata = &dm365_emac_pdata,
728 .sram_dma = 0x00010000,
729 .sram_len = SZ_32K,
730};
731
732void __init dm365_init_asp(void)
733{
734 davinci_cfg_reg(DM365_MCBSP0_BDX);
735 davinci_cfg_reg(DM365_MCBSP0_X);
736 davinci_cfg_reg(DM365_MCBSP0_BFSX);
737 davinci_cfg_reg(DM365_MCBSP0_BDR);
738 davinci_cfg_reg(DM365_MCBSP0_R);
739 davinci_cfg_reg(DM365_MCBSP0_BFSR);
740 davinci_cfg_reg(DM365_EVT2_ASP_TX);
741 davinci_cfg_reg(DM365_EVT3_ASP_RX);
742 platform_device_register(&dm365_asp_device);
743}
744
745void __init dm365_init_vc(void)
746{
747 davinci_cfg_reg(DM365_EVT2_VC_TX);
748 davinci_cfg_reg(DM365_EVT3_VC_RX);
749 platform_device_register(&dm365_vc_device);
750}
751
752void __init dm365_init_ks(struct davinci_ks_platform_data *pdata)
753{
754 dm365_ks_device.dev.platform_data = pdata;
755 platform_device_register(&dm365_ks_device);
756}
757
758void __init dm365_init_rtc(void)
759{
760 davinci_cfg_reg(DM365_INT_PRTCSS);
761 platform_device_register(&dm365_rtc_device);
762}
763
764void __init dm365_init(void)
765{
766 davinci_common_init(&davinci_soc_info_dm365);
767 davinci_map_sysmod();
768}
769
770void __init dm365_init_time(void)
771{
772 void __iomem *pll1, *pll2, *psc;
773 struct clk *clk;
774
775 clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DM365_REF_FREQ);
776
777 pll1 = ioremap(DAVINCI_PLL1_BASE, SZ_1K);
778 dm365_pll1_init(NULL, pll1, NULL);
779
780 pll2 = ioremap(DAVINCI_PLL2_BASE, SZ_1K);
781 dm365_pll2_init(NULL, pll2, NULL);
782
783 psc = ioremap(DAVINCI_PWR_SLEEP_CNTRL_BASE, SZ_4K);
784 dm365_psc_init(NULL, psc);
785
786 clk = clk_get(NULL, "timer0");
787
788 davinci_timer_init(clk);
789}
790
791void __init dm365_register_clocks(void)
792{
793
794}
795
796static struct resource dm365_vpss_resources[] = {
797 {
798
799 .name = "isp5",
800 .start = 0x01c70000,
801 .end = 0x01c70000 + 0xff,
802 .flags = IORESOURCE_MEM,
803 },
804 {
805
806 .name = "vpss",
807 .start = 0x01c70200,
808 .end = 0x01c70200 + 0xff,
809 .flags = IORESOURCE_MEM,
810 },
811};
812
813static struct platform_device dm365_vpss_device = {
814 .name = "vpss",
815 .id = -1,
816 .dev.platform_data = "dm365_vpss",
817 .num_resources = ARRAY_SIZE(dm365_vpss_resources),
818 .resource = dm365_vpss_resources,
819};
820
821static struct resource vpfe_resources[] = {
822 {
823 .start = DAVINCI_INTC_IRQ(IRQ_VDINT0),
824 .end = DAVINCI_INTC_IRQ(IRQ_VDINT0),
825 .flags = IORESOURCE_IRQ,
826 },
827 {
828 .start = DAVINCI_INTC_IRQ(IRQ_VDINT1),
829 .end = DAVINCI_INTC_IRQ(IRQ_VDINT1),
830 .flags = IORESOURCE_IRQ,
831 },
832};
833
834static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
835static struct platform_device vpfe_capture_dev = {
836 .name = CAPTURE_DRV_NAME,
837 .id = -1,
838 .num_resources = ARRAY_SIZE(vpfe_resources),
839 .resource = vpfe_resources,
840 .dev = {
841 .dma_mask = &vpfe_capture_dma_mask,
842 .coherent_dma_mask = DMA_BIT_MASK(32),
843 },
844};
845
846static void dm365_isif_setup_pinmux(void)
847{
848 davinci_cfg_reg(DM365_VIN_CAM_WEN);
849 davinci_cfg_reg(DM365_VIN_CAM_VD);
850 davinci_cfg_reg(DM365_VIN_CAM_HD);
851 davinci_cfg_reg(DM365_VIN_YIN4_7_EN);
852 davinci_cfg_reg(DM365_VIN_YIN0_3_EN);
853}
854
855static struct resource isif_resource[] = {
856
857 {
858 .start = 0x01c71000,
859 .end = 0x01c71000 + 0x1ff,
860 .flags = IORESOURCE_MEM,
861 },
862
863 {
864 .start = 0x1C7C000,
865 .end = 0x1C7C000 + 0x2ff,
866 .flags = IORESOURCE_MEM,
867 },
868
869 {
870 .start = 0x1C7C400,
871 .end = 0x1C7C400 + 0x2ff,
872 .flags = IORESOURCE_MEM,
873 },
874};
875static struct platform_device dm365_isif_dev = {
876 .name = "isif",
877 .id = -1,
878 .num_resources = ARRAY_SIZE(isif_resource),
879 .resource = isif_resource,
880 .dev = {
881 .dma_mask = &vpfe_capture_dma_mask,
882 .coherent_dma_mask = DMA_BIT_MASK(32),
883 .platform_data = dm365_isif_setup_pinmux,
884 },
885};
886
887static struct resource dm365_osd_resources[] = {
888 {
889 .start = DM365_OSD_BASE,
890 .end = DM365_OSD_BASE + 0xff,
891 .flags = IORESOURCE_MEM,
892 },
893};
894
895static u64 dm365_video_dma_mask = DMA_BIT_MASK(32);
896
897static struct platform_device dm365_osd_dev = {
898 .name = DM365_VPBE_OSD_SUBDEV_NAME,
899 .id = -1,
900 .num_resources = ARRAY_SIZE(dm365_osd_resources),
901 .resource = dm365_osd_resources,
902 .dev = {
903 .dma_mask = &dm365_video_dma_mask,
904 .coherent_dma_mask = DMA_BIT_MASK(32),
905 },
906};
907
908static struct resource dm365_venc_resources[] = {
909 {
910 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
911 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
912 .flags = IORESOURCE_IRQ,
913 },
914
915 {
916 .start = DM365_VENC_BASE,
917 .end = DM365_VENC_BASE + 0x177,
918 .flags = IORESOURCE_MEM,
919 },
920
921 {
922 .start = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG,
923 .end = DAVINCI_SYSTEM_MODULE_BASE + SYSMOD_VDAC_CONFIG + 3,
924 .flags = IORESOURCE_MEM,
925 },
926};
927
928static struct resource dm365_v4l2_disp_resources[] = {
929 {
930 .start = DAVINCI_INTC_IRQ(IRQ_VENCINT),
931 .end = DAVINCI_INTC_IRQ(IRQ_VENCINT),
932 .flags = IORESOURCE_IRQ,
933 },
934
935 {
936 .start = DM365_VENC_BASE,
937 .end = DM365_VENC_BASE + 0x177,
938 .flags = IORESOURCE_MEM,
939 },
940};
941
942static int dm365_vpbe_setup_pinmux(u32 if_type, int field)
943{
944 switch (if_type) {
945 case MEDIA_BUS_FMT_SGRBG8_1X8:
946 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
947 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
948 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
949 break;
950 case MEDIA_BUS_FMT_YUYV10_1X20:
951 if (field)
952 davinci_cfg_reg(DM365_VOUT_FIELD);
953 else
954 davinci_cfg_reg(DM365_VOUT_FIELD_G81);
955 davinci_cfg_reg(DM365_VOUT_COUTL_EN);
956 davinci_cfg_reg(DM365_VOUT_COUTH_EN);
957 break;
958 default:
959 return -EINVAL;
960 }
961
962 return 0;
963}
964
965static int dm365_venc_setup_clock(enum vpbe_enc_timings_type type,
966 unsigned int pclock)
967{
968 void __iomem *vpss_clkctl_reg;
969 u32 val;
970
971 vpss_clkctl_reg = DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL);
972
973 switch (type) {
974 case VPBE_ENC_STD:
975 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
976 break;
977 case VPBE_ENC_DV_TIMINGS:
978 if (pclock <= 27000000) {
979 val = VPSS_VENCCLKEN_ENABLE | VPSS_DACCLKEN_ENABLE;
980 } else {
981
982 val = VPSS_PLLC2SYSCLK5_ENABLE | VPSS_DACCLKEN_ENABLE |
983 VPSS_VENCCLKEN_ENABLE;
984 }
985 break;
986 default:
987 return -EINVAL;
988 }
989 writel(val, vpss_clkctl_reg);
990
991 return 0;
992}
993
994static struct platform_device dm365_vpbe_display = {
995 .name = "vpbe-v4l2",
996 .id = -1,
997 .num_resources = ARRAY_SIZE(dm365_v4l2_disp_resources),
998 .resource = dm365_v4l2_disp_resources,
999 .dev = {
1000 .dma_mask = &dm365_video_dma_mask,
1001 .coherent_dma_mask = DMA_BIT_MASK(32),
1002 },
1003};
1004
1005static struct venc_platform_data dm365_venc_pdata = {
1006 .setup_pinmux = dm365_vpbe_setup_pinmux,
1007 .setup_clock = dm365_venc_setup_clock,
1008};
1009
1010static struct platform_device dm365_venc_dev = {
1011 .name = DM365_VPBE_VENC_SUBDEV_NAME,
1012 .id = -1,
1013 .num_resources = ARRAY_SIZE(dm365_venc_resources),
1014 .resource = dm365_venc_resources,
1015 .dev = {
1016 .dma_mask = &dm365_video_dma_mask,
1017 .coherent_dma_mask = DMA_BIT_MASK(32),
1018 .platform_data = (void *)&dm365_venc_pdata,
1019 },
1020};
1021
1022static struct platform_device dm365_vpbe_dev = {
1023 .name = "vpbe_controller",
1024 .id = -1,
1025 .dev = {
1026 .dma_mask = &dm365_video_dma_mask,
1027 .coherent_dma_mask = DMA_BIT_MASK(32),
1028 },
1029};
1030
1031int __init dm365_init_video(struct vpfe_config *vpfe_cfg,
1032 struct vpbe_config *vpbe_cfg)
1033{
1034 if (vpfe_cfg || vpbe_cfg)
1035 platform_device_register(&dm365_vpss_device);
1036
1037 if (vpfe_cfg) {
1038 vpfe_capture_dev.dev.platform_data = vpfe_cfg;
1039 platform_device_register(&dm365_isif_dev);
1040 platform_device_register(&vpfe_capture_dev);
1041 }
1042 if (vpbe_cfg) {
1043 dm365_vpbe_dev.dev.platform_data = vpbe_cfg;
1044 platform_device_register(&dm365_osd_dev);
1045 platform_device_register(&dm365_venc_dev);
1046 platform_device_register(&dm365_vpbe_dev);
1047 platform_device_register(&dm365_vpbe_display);
1048 }
1049
1050 return 0;
1051}
1052
1053static const struct davinci_aintc_config dm365_aintc_config = {
1054 .reg = {
1055 .start = DAVINCI_ARM_INTC_BASE,
1056 .end = DAVINCI_ARM_INTC_BASE + SZ_4K - 1,
1057 .flags = IORESOURCE_MEM,
1058 },
1059 .num_irqs = 64,
1060 .prios = dm365_default_priorities,
1061};
1062
1063void __init dm365_init_irq(void)
1064{
1065 davinci_aintc_init(&dm365_aintc_config);
1066}
1067
1068static int __init dm365_init_devices(void)
1069{
1070 struct platform_device *edma_pdev;
1071 int ret = 0;
1072
1073 if (!cpu_is_davinci_dm365())
1074 return 0;
1075
1076 davinci_cfg_reg(DM365_INT_EDMA_CC);
1077 edma_pdev = platform_device_register_full(&dm365_edma_device);
1078 if (IS_ERR(edma_pdev)) {
1079 pr_warn("%s: Failed to register eDMA\n", __func__);
1080 return PTR_ERR(edma_pdev);
1081 }
1082
1083 platform_device_register(&dm365_mdio_device);
1084 platform_device_register(&dm365_emac_device);
1085
1086 ret = davinci_init_wdt();
1087 if (ret)
1088 pr_warn("%s: watchdog init failed: %d\n", __func__, ret);
1089
1090 return ret;
1091}
1092postcore_initcall(dm365_init_devices);
1093
