1
2
3
4
5
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/dma-mapping.h>
11#include <linux/io.h>
12#include <asm/irq.h>
13#include <linux/sizes.h>
14#include <mach/irqs.h>
15
16
17#define IOP13XX_TPMI_MMR(dev) IOP13XX_REG_ADDR32_PHYS(0x48000 + (dev << 12))
18#define IOP13XX_TPMI_MEM(dev) IOP13XX_REG_ADDR32_PHYS(0x60000 + (dev << 13))
19#define IOP13XX_TPMI_CTRL(dev) IOP13XX_REG_ADDR32_PHYS(0x50000 + (dev << 10))
20#define IOP13XX_TPMI_IOP_CTRL(dev) (IOP13XX_TPMI_CTRL(dev) + 0x2000)
21#define IOP13XX_TPMI_MMR_SIZE (SZ_4K - 1)
22#define IOP13XX_TPMI_MEM_SIZE (255)
23#define IOP13XX_TPMI_MEM_CTRL (SZ_1K - 1)
24#define IOP13XX_TPMI_RESOURCE_MMR 0
25#define IOP13XX_TPMI_RESOURCE_MEM 1
26#define IOP13XX_TPMI_RESOURCE_CTRL 2
27#define IOP13XX_TPMI_RESOURCE_IOP_CTRL 3
28#define IOP13XX_TPMI_RESOURCE_IRQ 4
29
30static struct resource iop13xx_tpmi_0_resources[] = {
31 [IOP13XX_TPMI_RESOURCE_MMR] = {
32 .start = IOP13XX_TPMI_MMR(4),
33 .end = IOP13XX_TPMI_MMR(4) + IOP13XX_TPMI_MMR_SIZE,
34 .flags = IORESOURCE_MEM,
35 },
36 [IOP13XX_TPMI_RESOURCE_MEM] = {
37 .start = IOP13XX_TPMI_MEM(0),
38 .end = IOP13XX_TPMI_MEM(0) + IOP13XX_TPMI_MEM_SIZE,
39 .flags = IORESOURCE_MEM,
40 },
41 [IOP13XX_TPMI_RESOURCE_CTRL] = {
42 .start = IOP13XX_TPMI_CTRL(0),
43 .end = IOP13XX_TPMI_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
44 .flags = IORESOURCE_MEM,
45 },
46 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
47 .start = IOP13XX_TPMI_IOP_CTRL(0),
48 .end = IOP13XX_TPMI_IOP_CTRL(0) + IOP13XX_TPMI_MEM_CTRL,
49 .flags = IORESOURCE_MEM,
50 },
51 [IOP13XX_TPMI_RESOURCE_IRQ] = {
52 .start = IRQ_IOP13XX_TPMI0_OUT,
53 .end = IRQ_IOP13XX_TPMI0_OUT,
54 .flags = IORESOURCE_IRQ
55 }
56};
57
58static struct resource iop13xx_tpmi_1_resources[] = {
59 [IOP13XX_TPMI_RESOURCE_MMR] = {
60 .start = IOP13XX_TPMI_MMR(1),
61 .end = IOP13XX_TPMI_MMR(1) + IOP13XX_TPMI_MMR_SIZE,
62 .flags = IORESOURCE_MEM,
63 },
64 [IOP13XX_TPMI_RESOURCE_MEM] = {
65 .start = IOP13XX_TPMI_MEM(1),
66 .end = IOP13XX_TPMI_MEM(1) + IOP13XX_TPMI_MEM_SIZE,
67 .flags = IORESOURCE_MEM,
68 },
69 [IOP13XX_TPMI_RESOURCE_CTRL] = {
70 .start = IOP13XX_TPMI_CTRL(1),
71 .end = IOP13XX_TPMI_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
72 .flags = IORESOURCE_MEM,
73 },
74 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
75 .start = IOP13XX_TPMI_IOP_CTRL(1),
76 .end = IOP13XX_TPMI_IOP_CTRL(1) + IOP13XX_TPMI_MEM_CTRL,
77 .flags = IORESOURCE_MEM,
78 },
79 [IOP13XX_TPMI_RESOURCE_IRQ] = {
80 .start = IRQ_IOP13XX_TPMI1_OUT,
81 .end = IRQ_IOP13XX_TPMI1_OUT,
82 .flags = IORESOURCE_IRQ
83 }
84};
85
86static struct resource iop13xx_tpmi_2_resources[] = {
87 [IOP13XX_TPMI_RESOURCE_MMR] = {
88 .start = IOP13XX_TPMI_MMR(2),
89 .end = IOP13XX_TPMI_MMR(2) + IOP13XX_TPMI_MMR_SIZE,
90 .flags = IORESOURCE_MEM,
91 },
92 [IOP13XX_TPMI_RESOURCE_MEM] = {
93 .start = IOP13XX_TPMI_MEM(2),
94 .end = IOP13XX_TPMI_MEM(2) + IOP13XX_TPMI_MEM_SIZE,
95 .flags = IORESOURCE_MEM,
96 },
97 [IOP13XX_TPMI_RESOURCE_CTRL] = {
98 .start = IOP13XX_TPMI_CTRL(2),
99 .end = IOP13XX_TPMI_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
100 .flags = IORESOURCE_MEM,
101 },
102 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
103 .start = IOP13XX_TPMI_IOP_CTRL(2),
104 .end = IOP13XX_TPMI_IOP_CTRL(2) + IOP13XX_TPMI_MEM_CTRL,
105 .flags = IORESOURCE_MEM,
106 },
107 [IOP13XX_TPMI_RESOURCE_IRQ] = {
108 .start = IRQ_IOP13XX_TPMI2_OUT,
109 .end = IRQ_IOP13XX_TPMI2_OUT,
110 .flags = IORESOURCE_IRQ
111 }
112};
113
114static struct resource iop13xx_tpmi_3_resources[] = {
115 [IOP13XX_TPMI_RESOURCE_MMR] = {
116 .start = IOP13XX_TPMI_MMR(3),
117 .end = IOP13XX_TPMI_MMR(3) + IOP13XX_TPMI_MMR_SIZE,
118 .flags = IORESOURCE_MEM,
119 },
120 [IOP13XX_TPMI_RESOURCE_MEM] = {
121 .start = IOP13XX_TPMI_MEM(3),
122 .end = IOP13XX_TPMI_MEM(3) + IOP13XX_TPMI_MEM_SIZE,
123 .flags = IORESOURCE_MEM,
124 },
125 [IOP13XX_TPMI_RESOURCE_CTRL] = {
126 .start = IOP13XX_TPMI_CTRL(3),
127 .end = IOP13XX_TPMI_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
128 .flags = IORESOURCE_MEM,
129 },
130 [IOP13XX_TPMI_RESOURCE_IOP_CTRL] = {
131 .start = IOP13XX_TPMI_IOP_CTRL(3),
132 .end = IOP13XX_TPMI_IOP_CTRL(3) + IOP13XX_TPMI_MEM_CTRL,
133 .flags = IORESOURCE_MEM,
134 },
135 [IOP13XX_TPMI_RESOURCE_IRQ] = {
136 .start = IRQ_IOP13XX_TPMI3_OUT,
137 .end = IRQ_IOP13XX_TPMI3_OUT,
138 .flags = IORESOURCE_IRQ
139 }
140};
141
142u64 iop13xx_tpmi_mask = DMA_BIT_MASK(32);
143static struct platform_device iop13xx_tpmi_0_device = {
144 .name = "iop-tpmi",
145 .id = 0,
146 .num_resources = ARRAY_SIZE(iop13xx_tpmi_0_resources),
147 .resource = iop13xx_tpmi_0_resources,
148 .dev = {
149 .dma_mask = &iop13xx_tpmi_mask,
150 .coherent_dma_mask = DMA_BIT_MASK(32),
151 },
152};
153
154static struct platform_device iop13xx_tpmi_1_device = {
155 .name = "iop-tpmi",
156 .id = 1,
157 .num_resources = ARRAY_SIZE(iop13xx_tpmi_1_resources),
158 .resource = iop13xx_tpmi_1_resources,
159 .dev = {
160 .dma_mask = &iop13xx_tpmi_mask,
161 .coherent_dma_mask = DMA_BIT_MASK(32),
162 },
163};
164
165static struct platform_device iop13xx_tpmi_2_device = {
166 .name = "iop-tpmi",
167 .id = 2,
168 .num_resources = ARRAY_SIZE(iop13xx_tpmi_2_resources),
169 .resource = iop13xx_tpmi_2_resources,
170 .dev = {
171 .dma_mask = &iop13xx_tpmi_mask,
172 .coherent_dma_mask = DMA_BIT_MASK(32),
173 },
174};
175
176static struct platform_device iop13xx_tpmi_3_device = {
177 .name = "iop-tpmi",
178 .id = 3,
179 .num_resources = ARRAY_SIZE(iop13xx_tpmi_3_resources),
180 .resource = iop13xx_tpmi_3_resources,
181 .dev = {
182 .dma_mask = &iop13xx_tpmi_mask,
183 .coherent_dma_mask = DMA_BIT_MASK(32),
184 },
185};
186
187__init void iop13xx_add_tpmi_devices(void)
188{
189 unsigned short device_id;
190
191
192 if (__raw_readl(IOP13XX_ESSR0) & IOP13XX_INTERFACE_SEL_PCIX)
193
194 device_id = __raw_readw(IOP13XX_ATUE_DID);
195 else
196
197 device_id = __raw_readw(IOP13XX_ATUX_DID);
198
199 switch (device_id) {
200
201 case 0x3380:
202 case 0x3384:
203 case 0x3388:
204 case 0x338c:
205 case 0x3382:
206 case 0x3386:
207 case 0x338a:
208 case 0x338e:
209 return;
210
211 case 0x3310:
212 case 0x3312:
213 case 0x3314:
214 case 0x3318:
215 case 0x331a:
216 case 0x331c:
217 case 0x33c0:
218 case 0x33c2:
219 case 0x33c4:
220 case 0x33c8:
221 case 0x33ca:
222 case 0x33cc:
223 case 0x33b0:
224 case 0x33b2:
225 case 0x33b4:
226 case 0x33b8:
227 case 0x33ba:
228 case 0x33bc:
229 case 0x3320:
230 case 0x3322:
231 case 0x3324:
232 case 0x3328:
233 case 0x332a:
234 case 0x332c:
235 platform_device_register(&iop13xx_tpmi_0_device);
236 return;
237 default:
238 platform_device_register(&iop13xx_tpmi_0_device);
239 platform_device_register(&iop13xx_tpmi_1_device);
240 platform_device_register(&iop13xx_tpmi_2_device);
241 platform_device_register(&iop13xx_tpmi_3_device);
242 return;
243 }
244}
245
