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14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/io.h>
18#include <linux/random.h>
19#include <linux/slab.h>
20
21#ifdef CONFIG_SOC_BUS
22#include <linux/sys_soc.h>
23#endif
24
25#include <asm/cputype.h>
26
27#include "common.h"
28
29#include "id.h"
30
31#include "soc.h"
32#include "control.h"
33
34#define OMAP4_SILICON_TYPE_STANDARD 0x01
35#define OMAP4_SILICON_TYPE_PERFORMANCE 0x02
36
37#define OMAP_SOC_MAX_NAME_LENGTH 16
38
39static unsigned int omap_revision;
40static char soc_name[OMAP_SOC_MAX_NAME_LENGTH];
41static char soc_rev[OMAP_SOC_MAX_NAME_LENGTH];
42u32 omap_features;
43
44unsigned int omap_rev(void)
45{
46 return omap_revision;
47}
48EXPORT_SYMBOL(omap_rev);
49
50int omap_type(void)
51{
52 static u32 val = OMAP2_DEVICETYPE_MASK;
53
54 if (val < OMAP2_DEVICETYPE_MASK)
55 return val;
56
57 if (soc_is_omap24xx()) {
58 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
59 } else if (soc_is_ti81xx()) {
60 val = omap_ctrl_readl(TI81XX_CONTROL_STATUS);
61 } else if (soc_is_am33xx() || soc_is_am43xx()) {
62 val = omap_ctrl_readl(AM33XX_CONTROL_STATUS);
63 } else if (soc_is_omap34xx()) {
64 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
65 } else if (soc_is_omap44xx()) {
66 val = omap_ctrl_readl(OMAP4_CTRL_MODULE_CORE_STATUS);
67 } else if (soc_is_omap54xx() || soc_is_dra7xx()) {
68 val = omap_ctrl_readl(OMAP5XXX_CONTROL_STATUS);
69 val &= OMAP5_DEVICETYPE_MASK;
70 val >>= 6;
71 goto out;
72 } else {
73 pr_err("Cannot detect omap type!\n");
74 goto out;
75 }
76
77 val &= OMAP2_DEVICETYPE_MASK;
78 val >>= 8;
79
80out:
81 return val;
82}
83EXPORT_SYMBOL(omap_type);
84
85
86
87
88#define OMAP_TAP_IDCODE 0x0204
89#define OMAP_TAP_DIE_ID_0 0x0218
90#define OMAP_TAP_DIE_ID_1 0x021C
91#define OMAP_TAP_DIE_ID_2 0x0220
92#define OMAP_TAP_DIE_ID_3 0x0224
93
94#define OMAP_TAP_DIE_ID_44XX_0 0x0200
95#define OMAP_TAP_DIE_ID_44XX_1 0x0208
96#define OMAP_TAP_DIE_ID_44XX_2 0x020c
97#define OMAP_TAP_DIE_ID_44XX_3 0x0210
98
99#define read_tap_reg(reg) readl_relaxed(tap_base + (reg))
100
101struct omap_id {
102 u16 hawkeye;
103 u8 dev;
104 u32 type;
105};
106
107
108static struct omap_id omap_ids[] __initdata = {
109 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
110 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
111 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
112 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
113 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
114 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
115};
116
117static void __iomem *tap_base;
118static u16 tap_prod_id;
119
120void omap_get_die_id(struct omap_die_id *odi)
121{
122 if (soc_is_omap44xx() || soc_is_omap54xx() || soc_is_dra7xx()) {
123 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_0);
124 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_1);
125 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_2);
126 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_44XX_3);
127
128 return;
129 }
130 odi->id_0 = read_tap_reg(OMAP_TAP_DIE_ID_0);
131 odi->id_1 = read_tap_reg(OMAP_TAP_DIE_ID_1);
132 odi->id_2 = read_tap_reg(OMAP_TAP_DIE_ID_2);
133 odi->id_3 = read_tap_reg(OMAP_TAP_DIE_ID_3);
134}
135
136static int __init omap_feed_randpool(void)
137{
138 struct omap_die_id odi;
139
140
141 omap_get_die_id(&odi);
142 add_device_randomness(&odi, sizeof(odi));
143 return 0;
144}
145omap_device_initcall(omap_feed_randpool);
146
147void __init omap2xxx_check_revision(void)
148{
149 int i, j;
150 u32 idcode, prod_id;
151 u16 hawkeye;
152 u8 dev_type, rev;
153 struct omap_die_id odi;
154
155 idcode = read_tap_reg(OMAP_TAP_IDCODE);
156 prod_id = read_tap_reg(tap_prod_id);
157 hawkeye = (idcode >> 12) & 0xffff;
158 rev = (idcode >> 28) & 0x0f;
159 dev_type = (prod_id >> 16) & 0x0f;
160 omap_get_die_id(&odi);
161
162 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
163 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
164 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n", odi.id_0);
165 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
166 odi.id_1, (odi.id_1 >> 28) & 0xf);
167 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n", odi.id_2);
168 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n", odi.id_3);
169 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
170 prod_id, dev_type);
171
172
173 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
174 if (hawkeye == omap_ids[i].hawkeye)
175 break;
176 }
177
178 if (i == ARRAY_SIZE(omap_ids)) {
179 printk(KERN_ERR "Unknown OMAP CPU id\n");
180 return;
181 }
182
183 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
184 if (dev_type == omap_ids[j].dev)
185 break;
186 }
187
188 if (j == ARRAY_SIZE(omap_ids)) {
189 pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
190 omap_ids[i].type >> 16);
191 j = i;
192 }
193
194 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
195 sprintf(soc_rev, "ES%x", (omap_rev() >> 12) & 0xf);
196
197 pr_info("%s", soc_name);
198 if ((omap_rev() >> 8) & 0x0f)
199 pr_cont("%s", soc_rev);
200 pr_cont("\n");
201}
202
203#define OMAP3_SHOW_FEATURE(feat) \
204 if (omap3_has_ ##feat()) \
205 n += scnprintf(buf + n, sizeof(buf) - n, #feat " ");
206
207static void __init omap3_cpuinfo(void)
208{
209 const char *cpu_name;
210 char buf[64];
211 int n = 0;
212
213 memset(buf, 0, sizeof(buf));
214
215
216
217
218
219
220
221
222 if (soc_is_omap3630()) {
223 if (omap3_has_iva() && omap3_has_sgx()) {
224 cpu_name = (omap3_has_isp()) ? "OMAP3630/DM3730" : "OMAP3621";
225 } else if (omap3_has_iva()) {
226 cpu_name = "DM3725";
227 } else if (omap3_has_sgx()) {
228 cpu_name = "OMAP3615/AM3715";
229 } else {
230 cpu_name = (omap3_has_isp()) ? "AM3703" : "OMAP3611";
231 }
232 } else if (soc_is_am35xx()) {
233 cpu_name = (omap3_has_sgx()) ? "AM3517" : "AM3505";
234 } else if (soc_is_ti816x()) {
235 cpu_name = "TI816X";
236 } else if (soc_is_am335x()) {
237 cpu_name = "AM335X";
238 } else if (soc_is_am437x()) {
239 cpu_name = "AM437x";
240 } else if (soc_is_ti814x()) {
241 cpu_name = "TI814X";
242 } else if (omap3_has_iva() && omap3_has_sgx()) {
243
244 cpu_name = "OMAP3430/3530";
245 } else if (omap3_has_iva()) {
246 cpu_name = "OMAP3525";
247 } else if (omap3_has_sgx()) {
248 cpu_name = "OMAP3515";
249 } else {
250 cpu_name = "OMAP3503";
251 }
252
253 scnprintf(soc_name, sizeof(soc_name), "%s", cpu_name);
254
255
256 n += scnprintf(buf, sizeof(buf) - n, "%s %s (", soc_name, soc_rev);
257
258 OMAP3_SHOW_FEATURE(l2cache);
259 OMAP3_SHOW_FEATURE(iva);
260 OMAP3_SHOW_FEATURE(sgx);
261 OMAP3_SHOW_FEATURE(neon);
262 OMAP3_SHOW_FEATURE(isp);
263 OMAP3_SHOW_FEATURE(192mhz_clk);
264 if (*(buf + n - 1) == ' ')
265 n--;
266 n += scnprintf(buf + n, sizeof(buf) - n, ")\n");
267 pr_info("%s", buf);
268}
269
270#define OMAP3_CHECK_FEATURE(status,feat) \
271 if (((status & OMAP3_ ##feat## _MASK) \
272 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
273 omap_features |= OMAP3_HAS_ ##feat; \
274 }
275
276void __init omap3xxx_check_features(void)
277{
278 u32 status;
279
280 omap_features = 0;
281
282 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
283
284 OMAP3_CHECK_FEATURE(status, L2CACHE);
285 OMAP3_CHECK_FEATURE(status, IVA);
286 OMAP3_CHECK_FEATURE(status, SGX);
287 OMAP3_CHECK_FEATURE(status, NEON);
288 OMAP3_CHECK_FEATURE(status, ISP);
289 if (soc_is_omap3630())
290 omap_features |= OMAP3_HAS_192MHZ_CLK;
291 if (soc_is_omap3430() || soc_is_omap3630())
292 omap_features |= OMAP3_HAS_IO_WAKEUP;
293 if (soc_is_omap3630() || omap_rev() == OMAP3430_REV_ES3_1 ||
294 omap_rev() == OMAP3430_REV_ES3_1_2)
295 omap_features |= OMAP3_HAS_IO_CHAIN_CTRL;
296
297 omap_features |= OMAP3_HAS_SDRC;
298
299
300
301
302
303
304
305
306
307 if (soc_is_am35xx())
308 omap_features &= ~(OMAP3_HAS_IVA | OMAP3_HAS_ISP);
309
310
311
312
313
314
315 omap3_cpuinfo();
316}
317
318void __init omap4xxx_check_features(void)
319{
320 u32 si_type;
321
322 si_type =
323 (read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1) >> 16) & 0x03;
324
325 if (si_type == OMAP4_SILICON_TYPE_PERFORMANCE)
326 omap_features = OMAP4_HAS_PERF_SILICON;
327}
328
329void __init ti81xx_check_features(void)
330{
331 omap_features = OMAP3_HAS_NEON;
332 omap3_cpuinfo();
333}
334
335void __init am33xx_check_features(void)
336{
337 u32 status;
338
339 omap_features = OMAP3_HAS_NEON;
340
341 status = omap_ctrl_readl(AM33XX_DEV_FEATURE);
342 if (status & AM33XX_SGX_MASK)
343 omap_features |= OMAP3_HAS_SGX;
344
345 omap3_cpuinfo();
346}
347
348void __init omap3xxx_check_revision(void)
349{
350 const char *cpu_rev;
351 u32 cpuid, idcode;
352 u16 hawkeye;
353 u8 rev;
354
355
356
357
358
359
360 cpuid = read_cpuid_id();
361 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
362 omap_revision = OMAP3430_REV_ES1_0;
363 cpu_rev = "1.0";
364 return;
365 }
366
367
368
369
370
371
372
373 idcode = read_tap_reg(OMAP_TAP_IDCODE);
374 hawkeye = (idcode >> 12) & 0xffff;
375 rev = (idcode >> 28) & 0xff;
376
377 switch (hawkeye) {
378 case 0xb7ae:
379
380 switch (rev) {
381 case 0:
382 case 1:
383 omap_revision = OMAP3430_REV_ES2_0;
384 cpu_rev = "2.0";
385 break;
386 case 2:
387 omap_revision = OMAP3430_REV_ES2_1;
388 cpu_rev = "2.1";
389 break;
390 case 3:
391 omap_revision = OMAP3430_REV_ES3_0;
392 cpu_rev = "3.0";
393 break;
394 case 4:
395 omap_revision = OMAP3430_REV_ES3_1;
396 cpu_rev = "3.1";
397 break;
398 case 7:
399
400 default:
401
402 omap_revision = OMAP3430_REV_ES3_1_2;
403 cpu_rev = "3.1.2";
404 }
405 break;
406 case 0xb868:
407
408
409
410
411
412
413 switch (rev) {
414 case 0:
415 omap_revision = AM35XX_REV_ES1_0;
416 cpu_rev = "1.0";
417 break;
418 case 1:
419
420 default:
421 omap_revision = AM35XX_REV_ES1_1;
422 cpu_rev = "1.1";
423 }
424 break;
425 case 0xb891:
426
427
428 switch(rev) {
429 case 0:
430 omap_revision = OMAP3630_REV_ES1_0;
431 cpu_rev = "1.0";
432 break;
433 case 1:
434 omap_revision = OMAP3630_REV_ES1_1;
435 cpu_rev = "1.1";
436 break;
437 case 2:
438
439 default:
440 omap_revision = OMAP3630_REV_ES1_2;
441 cpu_rev = "1.2";
442 }
443 break;
444 case 0xb81e:
445 switch (rev) {
446 case 0:
447 omap_revision = TI8168_REV_ES1_0;
448 cpu_rev = "1.0";
449 break;
450 case 1:
451 omap_revision = TI8168_REV_ES1_1;
452 cpu_rev = "1.1";
453 break;
454 case 2:
455 omap_revision = TI8168_REV_ES2_0;
456 cpu_rev = "2.0";
457 break;
458 case 3:
459
460 default:
461 omap_revision = TI8168_REV_ES2_1;
462 cpu_rev = "2.1";
463 }
464 break;
465 case 0xb944:
466 switch (rev) {
467 case 0:
468 omap_revision = AM335X_REV_ES1_0;
469 cpu_rev = "1.0";
470 break;
471 case 1:
472 omap_revision = AM335X_REV_ES2_0;
473 cpu_rev = "2.0";
474 break;
475 case 2:
476
477 default:
478 omap_revision = AM335X_REV_ES2_1;
479 cpu_rev = "2.1";
480 break;
481 }
482 break;
483 case 0xb98c:
484 switch (rev) {
485 case 0:
486 omap_revision = AM437X_REV_ES1_0;
487 cpu_rev = "1.0";
488 break;
489 case 1:
490 omap_revision = AM437X_REV_ES1_1;
491 cpu_rev = "1.1";
492 break;
493 case 2:
494
495 default:
496 omap_revision = AM437X_REV_ES1_2;
497 cpu_rev = "1.2";
498 break;
499 }
500 break;
501 case 0xb8f2:
502 case 0xb968:
503 switch (rev) {
504 case 0:
505
506 case 1:
507 omap_revision = TI8148_REV_ES1_0;
508 cpu_rev = "1.0";
509 break;
510 case 2:
511 omap_revision = TI8148_REV_ES2_0;
512 cpu_rev = "2.0";
513 break;
514 case 3:
515
516 default:
517 omap_revision = TI8148_REV_ES2_1;
518 cpu_rev = "2.1";
519 break;
520 }
521 break;
522 default:
523
524 omap_revision = OMAP3630_REV_ES1_2;
525 cpu_rev = "1.2";
526 pr_warn("Warning: unknown chip type: hawkeye %04x, assuming OMAP3630ES1.2\n",
527 hawkeye);
528 }
529 sprintf(soc_rev, "ES%s", cpu_rev);
530}
531
532void __init omap4xxx_check_revision(void)
533{
534 u32 idcode;
535 u16 hawkeye;
536 u8 rev;
537
538
539
540
541
542
543 idcode = read_tap_reg(OMAP_TAP_IDCODE);
544 hawkeye = (idcode >> 12) & 0xffff;
545 rev = (idcode >> 28) & 0xf;
546
547
548
549
550
551 if (!rev && (hawkeye != 0xb94e) && (hawkeye != 0xb975)) {
552 idcode = read_cpuid_id();
553 rev = (idcode & 0xf) - 1;
554 }
555
556 switch (hawkeye) {
557 case 0xb852:
558 switch (rev) {
559 case 0:
560 omap_revision = OMAP4430_REV_ES1_0;
561 break;
562 case 1:
563 default:
564 omap_revision = OMAP4430_REV_ES2_0;
565 }
566 break;
567 case 0xb95c:
568 switch (rev) {
569 case 3:
570 omap_revision = OMAP4430_REV_ES2_1;
571 break;
572 case 4:
573 omap_revision = OMAP4430_REV_ES2_2;
574 break;
575 case 6:
576 default:
577 omap_revision = OMAP4430_REV_ES2_3;
578 }
579 break;
580 case 0xb94e:
581 switch (rev) {
582 case 0:
583 omap_revision = OMAP4460_REV_ES1_0;
584 break;
585 case 2:
586 default:
587 omap_revision = OMAP4460_REV_ES1_1;
588 break;
589 }
590 break;
591 case 0xb975:
592 switch (rev) {
593 case 0:
594 default:
595 omap_revision = OMAP4470_REV_ES1_0;
596 break;
597 }
598 break;
599 default:
600
601 omap_revision = OMAP4430_REV_ES2_3;
602 }
603
604 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
605 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
606 (omap_rev() >> 8) & 0xf);
607 pr_info("%s %s\n", soc_name, soc_rev);
608}
609
610void __init omap5xxx_check_revision(void)
611{
612 u32 idcode;
613 u16 hawkeye;
614 u8 rev;
615
616 idcode = read_tap_reg(OMAP_TAP_IDCODE);
617 hawkeye = (idcode >> 12) & 0xffff;
618 rev = (idcode >> 28) & 0xff;
619 switch (hawkeye) {
620 case 0xb942:
621 switch (rev) {
622 case 0:
623
624 BUG();
625 case 1:
626 default:
627 omap_revision = OMAP5430_REV_ES2_0;
628 }
629 break;
630
631 case 0xb998:
632 switch (rev) {
633 case 0:
634
635 BUG();
636 case 1:
637 default:
638 omap_revision = OMAP5432_REV_ES2_0;
639 }
640 break;
641
642 default:
643
644 omap_revision = OMAP5430_REV_ES2_0;
645 }
646
647 sprintf(soc_name, "OMAP%04x", omap_rev() >> 16);
648 sprintf(soc_rev, "ES%d.0", (omap_rev() >> 12) & 0xf);
649
650 pr_info("%s %s\n", soc_name, soc_rev);
651}
652
653void __init dra7xxx_check_revision(void)
654{
655 u32 idcode;
656 u16 hawkeye;
657 u8 rev, package;
658 struct omap_die_id odi;
659
660 omap_get_die_id(&odi);
661 package = (odi.id_2 >> 16) & 0x3;
662 idcode = read_tap_reg(OMAP_TAP_IDCODE);
663 hawkeye = (idcode >> 12) & 0xffff;
664 rev = (idcode >> 28) & 0xff;
665 switch (hawkeye) {
666 case 0xbb50:
667 switch (rev) {
668 case 0:
669 default:
670 switch (package) {
671 case 0x2:
672 omap_revision = DRA762_ABZ_REV_ES1_0;
673 break;
674 case 0x3:
675 omap_revision = DRA762_ACD_REV_ES1_0;
676 break;
677 default:
678 omap_revision = DRA762_REV_ES1_0;
679 break;
680 }
681 break;
682 }
683 break;
684
685 case 0xb990:
686 switch (rev) {
687 case 0:
688 omap_revision = DRA752_REV_ES1_0;
689 break;
690 case 1:
691 omap_revision = DRA752_REV_ES1_1;
692 break;
693 case 2:
694 default:
695 omap_revision = DRA752_REV_ES2_0;
696 break;
697 }
698 break;
699
700 case 0xb9bc:
701 switch (rev) {
702 case 0:
703 omap_revision = DRA722_REV_ES1_0;
704 break;
705 case 1:
706 omap_revision = DRA722_REV_ES2_0;
707 break;
708 case 2:
709 default:
710 omap_revision = DRA722_REV_ES2_1;
711 break;
712 }
713 break;
714
715 default:
716
717 pr_warn("%s: unknown idcode=0x%08x (hawkeye=0x%08x,rev=0x%x)\n",
718 __func__, idcode, hawkeye, rev);
719 omap_revision = DRA752_REV_ES2_0;
720 }
721
722 sprintf(soc_name, "DRA%03x", omap_rev() >> 16);
723 sprintf(soc_rev, "ES%d.%d", (omap_rev() >> 12) & 0xf,
724 (omap_rev() >> 8) & 0xf);
725
726 pr_info("%s %s\n", soc_name, soc_rev);
727}
728
729
730
731
732
733
734
735
736void __init omap2_set_globals_tap(u32 class, void __iomem *tap)
737{
738 omap_revision = class;
739 tap_base = tap;
740
741
742 if (soc_is_omap34xx())
743 tap_prod_id = 0x0210;
744 else
745 tap_prod_id = 0x0208;
746}
747
748#ifdef CONFIG_SOC_BUS
749
750static const char * const omap_types[] = {
751 [OMAP2_DEVICE_TYPE_TEST] = "TST",
752 [OMAP2_DEVICE_TYPE_EMU] = "EMU",
753 [OMAP2_DEVICE_TYPE_SEC] = "HS",
754 [OMAP2_DEVICE_TYPE_GP] = "GP",
755 [OMAP2_DEVICE_TYPE_BAD] = "BAD",
756};
757
758static const char * __init omap_get_family(void)
759{
760 if (soc_is_omap24xx())
761 return kasprintf(GFP_KERNEL, "OMAP2");
762 else if (soc_is_omap34xx())
763 return kasprintf(GFP_KERNEL, "OMAP3");
764 else if (soc_is_omap44xx())
765 return kasprintf(GFP_KERNEL, "OMAP4");
766 else if (soc_is_omap54xx())
767 return kasprintf(GFP_KERNEL, "OMAP5");
768 else if (soc_is_am33xx() || soc_is_am335x())
769 return kasprintf(GFP_KERNEL, "AM33xx");
770 else if (soc_is_am43xx())
771 return kasprintf(GFP_KERNEL, "AM43xx");
772 else if (soc_is_dra7xx())
773 return kasprintf(GFP_KERNEL, "DRA7");
774 else
775 return kasprintf(GFP_KERNEL, "Unknown");
776}
777
778static ssize_t omap_get_type(struct device *dev,
779 struct device_attribute *attr,
780 char *buf)
781{
782 return sprintf(buf, "%s\n", omap_types[omap_type()]);
783}
784
785static struct device_attribute omap_soc_attr =
786 __ATTR(type, S_IRUGO, omap_get_type, NULL);
787
788void __init omap_soc_device_init(void)
789{
790 struct device *parent;
791 struct soc_device *soc_dev;
792 struct soc_device_attribute *soc_dev_attr;
793
794 soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
795 if (!soc_dev_attr)
796 return;
797
798 soc_dev_attr->machine = soc_name;
799 soc_dev_attr->family = omap_get_family();
800 soc_dev_attr->revision = soc_rev;
801
802 soc_dev = soc_device_register(soc_dev_attr);
803 if (IS_ERR(soc_dev)) {
804 kfree(soc_dev_attr);
805 return;
806 }
807
808 parent = soc_device_to_device(soc_dev);
809 device_create_file(parent, &omap_soc_attr);
810}
811#endif
812
