linux/arch/arm/mach-omap2/vc.c
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   1/*
   2 * OMAP Voltage Controller (VC) interface
   3 *
   4 * Copyright (C) 2011 Texas Instruments, Inc.
   5 *
   6 * This file is licensed under the terms of the GNU General Public
   7 * License version 2. This program is licensed "as is" without any
   8 * warranty of any kind, whether express or implied.
   9 */
  10#include <linux/kernel.h>
  11#include <linux/delay.h>
  12#include <linux/init.h>
  13#include <linux/bug.h>
  14#include <linux/io.h>
  15
  16#include <asm/div64.h>
  17
  18#include "iomap.h"
  19#include "soc.h"
  20#include "voltage.h"
  21#include "vc.h"
  22#include "prm-regbits-34xx.h"
  23#include "prm-regbits-44xx.h"
  24#include "prm44xx.h"
  25#include "pm.h"
  26#include "scrm44xx.h"
  27#include "control.h"
  28
  29/**
  30 * struct omap_vc_channel_cfg - describe the cfg_channel bitfield
  31 * @sa: bit for slave address
  32 * @rav: bit for voltage configuration register
  33 * @rac: bit for command configuration register
  34 * @racen: enable bit for RAC
  35 * @cmd: bit for command value set selection
  36 *
  37 * Channel configuration bits, common for OMAP3+
  38 * OMAP3 register: PRM_VC_CH_CONF
  39 * OMAP4 register: PRM_VC_CFG_CHANNEL
  40 * OMAP5 register: PRM_VC_SMPS_<voltdm>_CONFIG
  41 */
  42struct omap_vc_channel_cfg {
  43        u8 sa;
  44        u8 rav;
  45        u8 rac;
  46        u8 racen;
  47        u8 cmd;
  48};
  49
  50static struct omap_vc_channel_cfg vc_default_channel_cfg = {
  51        .sa    = BIT(0),
  52        .rav   = BIT(1),
  53        .rac   = BIT(2),
  54        .racen = BIT(3),
  55        .cmd   = BIT(4),
  56};
  57
  58/*
  59 * On OMAP3+, all VC channels have the above default bitfield
  60 * configuration, except the OMAP4 MPU channel.  This appears
  61 * to be a freak accident as every other VC channel has the
  62 * default configuration, thus creating a mutant channel config.
  63 */
  64static struct omap_vc_channel_cfg vc_mutant_channel_cfg = {
  65        .sa    = BIT(0),
  66        .rav   = BIT(2),
  67        .rac   = BIT(3),
  68        .racen = BIT(4),
  69        .cmd   = BIT(1),
  70};
  71
  72static struct omap_vc_channel_cfg *vc_cfg_bits;
  73
  74/* Default I2C trace length on pcb, 6.3cm. Used for capacitance calculations. */
  75static u32 sr_i2c_pcb_length = 63;
  76#define CFG_CHANNEL_MASK 0x1f
  77
  78/**
  79 * omap_vc_config_channel - configure VC channel to PMIC mappings
  80 * @voltdm: pointer to voltagdomain defining the desired VC channel
  81 *
  82 * Configures the VC channel to PMIC mappings for the following
  83 * PMIC settings
  84 * - i2c slave address (SA)
  85 * - voltage configuration address (RAV)
  86 * - command configuration address (RAC) and enable bit (RACEN)
  87 * - command values for ON, ONLP, RET and OFF (CMD)
  88 *
  89 * This function currently only allows flexible configuration of the
  90 * non-default channel.  Starting with OMAP4, there are more than 2
  91 * channels, with one defined as the default (on OMAP4, it's MPU.)
  92 * Only the non-default channel can be configured.
  93 */
  94static int omap_vc_config_channel(struct voltagedomain *voltdm)
  95{
  96        struct omap_vc_channel *vc = voltdm->vc;
  97
  98        /*
  99         * For default channel, the only configurable bit is RACEN.
 100         * All others must stay at zero (see function comment above.)
 101         */
 102        if (vc->flags & OMAP_VC_CHANNEL_DEFAULT)
 103                vc->cfg_channel &= vc_cfg_bits->racen;
 104
 105        voltdm->rmw(CFG_CHANNEL_MASK << vc->cfg_channel_sa_shift,
 106                    vc->cfg_channel << vc->cfg_channel_sa_shift,
 107                    vc->cfg_channel_reg);
 108
 109        return 0;
 110}
 111
 112/* Voltage scale and accessory APIs */
 113int omap_vc_pre_scale(struct voltagedomain *voltdm,
 114                      unsigned long target_volt,
 115                      u8 *target_vsel, u8 *current_vsel)
 116{
 117        struct omap_vc_channel *vc = voltdm->vc;
 118        u32 vc_cmdval;
 119
 120        /* Check if sufficient pmic info is available for this vdd */
 121        if (!voltdm->pmic) {
 122                pr_err("%s: Insufficient pmic info to scale the vdd_%s\n",
 123                        __func__, voltdm->name);
 124                return -EINVAL;
 125        }
 126
 127        if (!voltdm->pmic->uv_to_vsel) {
 128                pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
 129                       __func__, voltdm->name);
 130                return -ENODATA;
 131        }
 132
 133        if (!voltdm->read || !voltdm->write) {
 134                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 135                        __func__, voltdm->name);
 136                return -EINVAL;
 137        }
 138
 139        *target_vsel = voltdm->pmic->uv_to_vsel(target_volt);
 140        *current_vsel = voltdm->pmic->uv_to_vsel(voltdm->nominal_volt);
 141
 142        /* Setting the ON voltage to the new target voltage */
 143        vc_cmdval = voltdm->read(vc->cmdval_reg);
 144        vc_cmdval &= ~vc->common->cmd_on_mask;
 145        vc_cmdval |= (*target_vsel << vc->common->cmd_on_shift);
 146        voltdm->write(vc_cmdval, vc->cmdval_reg);
 147
 148        voltdm->vc_param->on = target_volt;
 149
 150        omap_vp_update_errorgain(voltdm, target_volt);
 151
 152        return 0;
 153}
 154
 155void omap_vc_post_scale(struct voltagedomain *voltdm,
 156                        unsigned long target_volt,
 157                        u8 target_vsel, u8 current_vsel)
 158{
 159        u32 smps_steps = 0, smps_delay = 0;
 160
 161        smps_steps = abs(target_vsel - current_vsel);
 162        /* SMPS slew rate / step size. 2us added as buffer. */
 163        smps_delay = ((smps_steps * voltdm->pmic->step_size) /
 164                        voltdm->pmic->slew_rate) + 2;
 165        udelay(smps_delay);
 166}
 167
 168/* vc_bypass_scale - VC bypass method of voltage scaling */
 169int omap_vc_bypass_scale(struct voltagedomain *voltdm,
 170                         unsigned long target_volt)
 171{
 172        struct omap_vc_channel *vc = voltdm->vc;
 173        u32 loop_cnt = 0, retries_cnt = 0;
 174        u32 vc_valid, vc_bypass_val_reg, vc_bypass_value;
 175        u8 target_vsel, current_vsel;
 176        int ret;
 177
 178        ret = omap_vc_pre_scale(voltdm, target_volt, &target_vsel, &current_vsel);
 179        if (ret)
 180                return ret;
 181
 182        vc_valid = vc->common->valid;
 183        vc_bypass_val_reg = vc->common->bypass_val_reg;
 184        vc_bypass_value = (target_vsel << vc->common->data_shift) |
 185                (vc->volt_reg_addr << vc->common->regaddr_shift) |
 186                (vc->i2c_slave_addr << vc->common->slaveaddr_shift);
 187
 188        voltdm->write(vc_bypass_value, vc_bypass_val_reg);
 189        voltdm->write(vc_bypass_value | vc_valid, vc_bypass_val_reg);
 190
 191        vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 192        /*
 193         * Loop till the bypass command is acknowledged from the SMPS.
 194         * NOTE: This is legacy code. The loop count and retry count needs
 195         * to be revisited.
 196         */
 197        while (!(vc_bypass_value & vc_valid)) {
 198                loop_cnt++;
 199
 200                if (retries_cnt > 10) {
 201                        pr_warn("%s: Retry count exceeded\n", __func__);
 202                        return -ETIMEDOUT;
 203                }
 204
 205                if (loop_cnt > 50) {
 206                        retries_cnt++;
 207                        loop_cnt = 0;
 208                        udelay(10);
 209                }
 210                vc_bypass_value = voltdm->read(vc_bypass_val_reg);
 211        }
 212
 213        omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
 214        return 0;
 215}
 216
 217/* Convert microsecond value to number of 32kHz clock cycles */
 218static inline u32 omap_usec_to_32k(u32 usec)
 219{
 220        return DIV_ROUND_UP_ULL(32768ULL * (u64)usec, 1000000ULL);
 221}
 222
 223struct omap3_vc_timings {
 224        u32 voltsetup1;
 225        u32 voltsetup2;
 226};
 227
 228struct omap3_vc {
 229        struct voltagedomain *vd;
 230        u32 voltctrl;
 231        u32 voltsetup1;
 232        u32 voltsetup2;
 233        struct omap3_vc_timings timings[2];
 234};
 235static struct omap3_vc vc;
 236
 237void omap3_vc_set_pmic_signaling(int core_next_state)
 238{
 239        struct voltagedomain *vd = vc.vd;
 240        struct omap3_vc_timings *c = vc.timings;
 241        u32 voltctrl, voltsetup1, voltsetup2;
 242
 243        voltctrl = vc.voltctrl;
 244        voltsetup1 = vc.voltsetup1;
 245        voltsetup2 = vc.voltsetup2;
 246
 247        switch (core_next_state) {
 248        case PWRDM_POWER_OFF:
 249                voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_RET |
 250                              OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
 251                voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_OFF;
 252                if (voltctrl & OMAP3430_PRM_VOLTCTRL_SEL_OFF)
 253                        voltsetup2 = c->voltsetup2;
 254                else
 255                        voltsetup1 = c->voltsetup1;
 256                break;
 257        case PWRDM_POWER_RET:
 258        default:
 259                c++;
 260                voltctrl &= ~(OMAP3430_PRM_VOLTCTRL_AUTO_OFF |
 261                              OMAP3430_PRM_VOLTCTRL_AUTO_SLEEP);
 262                voltctrl |= OMAP3430_PRM_VOLTCTRL_AUTO_RET;
 263                voltsetup1 = c->voltsetup1;
 264                break;
 265        }
 266
 267        if (voltctrl != vc.voltctrl) {
 268                vd->write(voltctrl, OMAP3_PRM_VOLTCTRL_OFFSET);
 269                vc.voltctrl = voltctrl;
 270        }
 271        if (voltsetup1 != vc.voltsetup1) {
 272                vd->write(c->voltsetup1,
 273                          OMAP3_PRM_VOLTSETUP1_OFFSET);
 274                vc.voltsetup1 = voltsetup1;
 275        }
 276        if (voltsetup2 != vc.voltsetup2) {
 277                vd->write(c->voltsetup2,
 278                          OMAP3_PRM_VOLTSETUP2_OFFSET);
 279                vc.voltsetup2 = voltsetup2;
 280        }
 281}
 282
 283/*
 284 * Configure signal polarity for sys_clkreq and sys_off_mode pins
 285 * as the default values are wrong and can cause the system to hang
 286 * if any twl4030 scripts are loaded.
 287 */
 288static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
 289{
 290        u32 val;
 291
 292        if (vc.vd)
 293                return;
 294
 295        vc.vd = voltdm;
 296
 297        val = voltdm->read(OMAP3_PRM_POLCTRL_OFFSET);
 298        if (!(val & OMAP3430_PRM_POLCTRL_CLKREQ_POL) ||
 299            (val & OMAP3430_PRM_POLCTRL_OFFMODE_POL)) {
 300                val |= OMAP3430_PRM_POLCTRL_CLKREQ_POL;
 301                val &= ~OMAP3430_PRM_POLCTRL_OFFMODE_POL;
 302                pr_debug("PM: fixing sys_clkreq and sys_off_mode polarity to 0x%x\n",
 303                         val);
 304                voltdm->write(val, OMAP3_PRM_POLCTRL_OFFSET);
 305        }
 306
 307        /*
 308         * By default let's use I2C4 signaling for retention idle
 309         * and sys_off_mode pin signaling for off idle. This way we
 310         * have sys_clk_req pin go down for retention and both
 311         * sys_clk_req and sys_off_mode pins will go down for off
 312         * idle. And we can also scale voltages to zero for off-idle.
 313         * Note that no actual voltage scaling during off-idle will
 314         * happen unless the board specific twl4030 PMIC scripts are
 315         * loaded. See also omap_vc_i2c_init for comments regarding
 316         * erratum i531.
 317         */
 318        val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
 319        if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
 320                val |= OMAP3430_PRM_VOLTCTRL_SEL_OFF;
 321                pr_debug("PM: setting voltctrl sys_off_mode signaling to 0x%x\n",
 322                         val);
 323                voltdm->write(val, OMAP3_PRM_VOLTCTRL_OFFSET);
 324        }
 325        vc.voltctrl = val;
 326
 327        omap3_vc_set_pmic_signaling(PWRDM_POWER_ON);
 328}
 329
 330static void omap3_init_voltsetup1(struct voltagedomain *voltdm,
 331                                  struct omap3_vc_timings *c, u32 idle)
 332{
 333        unsigned long val;
 334
 335        val = (voltdm->vc_param->on - idle) / voltdm->pmic->slew_rate;
 336        val *= voltdm->sys_clk.rate / 8 / 1000000 + 1;
 337        val <<= __ffs(voltdm->vfsm->voltsetup_mask);
 338        c->voltsetup1 &= ~voltdm->vfsm->voltsetup_mask;
 339        c->voltsetup1 |= val;
 340}
 341
 342/**
 343 * omap3_set_i2c_timings - sets i2c sleep timings for a channel
 344 * @voltdm: channel to configure
 345 * @off_mode: select whether retention or off mode values used
 346 *
 347 * Calculates and sets up voltage controller to use I2C based
 348 * voltage scaling for sleep modes. This can be used for either off mode
 349 * or retention. Off mode has additionally an option to use sys_off_mode
 350 * pad, which uses a global signal to program the whole power IC to
 351 * off-mode.
 352 *
 353 * Note that pmic is not controlling the voltage scaling during
 354 * retention signaled over I2C4, so we can keep voltsetup2 as 0.
 355 * And the oscillator is not shut off over I2C4, so no need to
 356 * set clksetup.
 357 */
 358static void omap3_set_i2c_timings(struct voltagedomain *voltdm)
 359{
 360        struct omap3_vc_timings *c = vc.timings;
 361
 362        /* Configure PRWDM_POWER_OFF over I2C4 */
 363        omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->off);
 364        c++;
 365        /* Configure PRWDM_POWER_RET over I2C4 */
 366        omap3_init_voltsetup1(voltdm, c, voltdm->vc_param->ret);
 367}
 368
 369/**
 370 * omap3_set_off_timings - sets off-mode timings for a channel
 371 * @voltdm: channel to configure
 372 *
 373 * Calculates and sets up off-mode timings for a channel. Off-mode
 374 * can use either I2C based voltage scaling, or alternatively
 375 * sys_off_mode pad can be used to send a global command to power IC.n,
 376 * sys_off_mode has the additional benefit that voltages can be
 377 * scaled to zero volt level with TWL4030 / TWL5030, I2C can only
 378 * scale to 600mV.
 379 *
 380 * Note that omap is not controlling the voltage scaling during
 381 * off idle signaled by sys_off_mode, so we can keep voltsetup1
 382 * as 0.
 383 */
 384static void omap3_set_off_timings(struct voltagedomain *voltdm)
 385{
 386        struct omap3_vc_timings *c = vc.timings;
 387        u32 tstart, tshut, clksetup, voltoffset;
 388
 389        if (c->voltsetup2)
 390                return;
 391
 392        omap_pm_get_oscillator(&tstart, &tshut);
 393        if (tstart == ULONG_MAX) {
 394                pr_debug("PM: oscillator start-up time not initialized, using 10ms\n");
 395                clksetup = omap_usec_to_32k(10000);
 396        } else {
 397                clksetup = omap_usec_to_32k(tstart);
 398        }
 399
 400        /*
 401         * For twl4030 errata 27, we need to allow minimum ~488.32 us wait to
 402         * switch from HFCLKIN to internal oscillator. That means timings
 403         * have voltoffset fixed to 0xa in rounded up 32 KiHz cycles. And
 404         * that means we can calculate the value based on the oscillator
 405         * start-up time since voltoffset2 = clksetup - voltoffset.
 406         */
 407        voltoffset = omap_usec_to_32k(488);
 408        c->voltsetup2 = clksetup - voltoffset;
 409        voltdm->write(clksetup, OMAP3_PRM_CLKSETUP_OFFSET);
 410        voltdm->write(voltoffset, OMAP3_PRM_VOLTOFFSET_OFFSET);
 411}
 412
 413static void __init omap3_vc_init_channel(struct voltagedomain *voltdm)
 414{
 415        omap3_vc_init_pmic_signaling(voltdm);
 416        omap3_set_off_timings(voltdm);
 417        omap3_set_i2c_timings(voltdm);
 418}
 419
 420/**
 421 * omap4_calc_volt_ramp - calculates voltage ramping delays on omap4
 422 * @voltdm: channel to calculate values for
 423 * @voltage_diff: voltage difference in microvolts
 424 *
 425 * Calculates voltage ramp prescaler + counter values for a voltage
 426 * difference on omap4. Returns a field value suitable for writing to
 427 * VOLTSETUP register for a channel in following format:
 428 * bits[8:9] prescaler ... bits[0:5] counter. See OMAP4 TRM for reference.
 429 */
 430static u32 omap4_calc_volt_ramp(struct voltagedomain *voltdm, u32 voltage_diff)
 431{
 432        u32 prescaler;
 433        u32 cycles;
 434        u32 time;
 435
 436        time = voltage_diff / voltdm->pmic->slew_rate;
 437
 438        cycles = voltdm->sys_clk.rate / 1000 * time / 1000;
 439
 440        cycles /= 64;
 441        prescaler = 0;
 442
 443        /* shift to next prescaler until no overflow */
 444
 445        /* scale for div 256 = 64 * 4 */
 446        if (cycles > 63) {
 447                cycles /= 4;
 448                prescaler++;
 449        }
 450
 451        /* scale for div 512 = 256 * 2 */
 452        if (cycles > 63) {
 453                cycles /= 2;
 454                prescaler++;
 455        }
 456
 457        /* scale for div 2048 = 512 * 4 */
 458        if (cycles > 63) {
 459                cycles /= 4;
 460                prescaler++;
 461        }
 462
 463        /* check for overflow => invalid ramp time */
 464        if (cycles > 63) {
 465                pr_warn("%s: invalid setuptime for vdd_%s\n", __func__,
 466                        voltdm->name);
 467                return 0;
 468        }
 469
 470        cycles++;
 471
 472        return (prescaler << OMAP4430_RAMP_UP_PRESCAL_SHIFT) |
 473                (cycles << OMAP4430_RAMP_UP_COUNT_SHIFT);
 474}
 475
 476/**
 477 * omap4_usec_to_val_scrm - convert microsecond value to SCRM module bitfield
 478 * @usec: microseconds
 479 * @shift: number of bits to shift left
 480 * @mask: bitfield mask
 481 *
 482 * Converts microsecond value to OMAP4 SCRM bitfield. Bitfield is
 483 * shifted to requested position, and checked agains the mask value.
 484 * If larger, forced to the max value of the field (i.e. the mask itself.)
 485 * Returns the SCRM bitfield value.
 486 */
 487static u32 omap4_usec_to_val_scrm(u32 usec, int shift, u32 mask)
 488{
 489        u32 val;
 490
 491        val = omap_usec_to_32k(usec) << shift;
 492
 493        /* Check for overflow, if yes, force to max value */
 494        if (val > mask)
 495                val = mask;
 496
 497        return val;
 498}
 499
 500/**
 501 * omap4_set_timings - set voltage ramp timings for a channel
 502 * @voltdm: channel to configure
 503 * @off_mode: whether off-mode values are used
 504 *
 505 * Calculates and sets the voltage ramp up / down values for a channel.
 506 */
 507static void omap4_set_timings(struct voltagedomain *voltdm, bool off_mode)
 508{
 509        u32 val;
 510        u32 ramp;
 511        int offset;
 512        u32 tstart, tshut;
 513
 514        if (off_mode) {
 515                ramp = omap4_calc_volt_ramp(voltdm,
 516                        voltdm->vc_param->on - voltdm->vc_param->off);
 517                offset = voltdm->vfsm->voltsetup_off_reg;
 518        } else {
 519                ramp = omap4_calc_volt_ramp(voltdm,
 520                        voltdm->vc_param->on - voltdm->vc_param->ret);
 521                offset = voltdm->vfsm->voltsetup_reg;
 522        }
 523
 524        if (!ramp)
 525                return;
 526
 527        val = voltdm->read(offset);
 528
 529        val |= ramp << OMAP4430_RAMP_DOWN_COUNT_SHIFT;
 530
 531        val |= ramp << OMAP4430_RAMP_UP_COUNT_SHIFT;
 532
 533        voltdm->write(val, offset);
 534
 535        omap_pm_get_oscillator(&tstart, &tshut);
 536
 537        val = omap4_usec_to_val_scrm(tstart, OMAP4_SETUPTIME_SHIFT,
 538                OMAP4_SETUPTIME_MASK);
 539        val |= omap4_usec_to_val_scrm(tshut, OMAP4_DOWNTIME_SHIFT,
 540                OMAP4_DOWNTIME_MASK);
 541
 542        writel_relaxed(val, OMAP4_SCRM_CLKSETUPTIME);
 543}
 544
 545/* OMAP4 specific voltage init functions */
 546static void __init omap4_vc_init_channel(struct voltagedomain *voltdm)
 547{
 548        omap4_set_timings(voltdm, true);
 549        omap4_set_timings(voltdm, false);
 550}
 551
 552struct i2c_init_data {
 553        u8 loadbits;
 554        u8 load;
 555        u8 hsscll_38_4;
 556        u8 hsscll_26;
 557        u8 hsscll_19_2;
 558        u8 hsscll_16_8;
 559        u8 hsscll_12;
 560};
 561
 562static const struct i2c_init_data omap4_i2c_timing_data[] __initconst = {
 563        {
 564                .load = 50,
 565                .loadbits = 0x3,
 566                .hsscll_38_4 = 13,
 567                .hsscll_26 = 11,
 568                .hsscll_19_2 = 9,
 569                .hsscll_16_8 = 9,
 570                .hsscll_12 = 8,
 571        },
 572        {
 573                .load = 25,
 574                .loadbits = 0x2,
 575                .hsscll_38_4 = 13,
 576                .hsscll_26 = 11,
 577                .hsscll_19_2 = 9,
 578                .hsscll_16_8 = 9,
 579                .hsscll_12 = 8,
 580        },
 581        {
 582                .load = 12,
 583                .loadbits = 0x1,
 584                .hsscll_38_4 = 11,
 585                .hsscll_26 = 10,
 586                .hsscll_19_2 = 9,
 587                .hsscll_16_8 = 9,
 588                .hsscll_12 = 8,
 589        },
 590        {
 591                .load = 0,
 592                .loadbits = 0x0,
 593                .hsscll_38_4 = 12,
 594                .hsscll_26 = 10,
 595                .hsscll_19_2 = 9,
 596                .hsscll_16_8 = 8,
 597                .hsscll_12 = 8,
 598        },
 599};
 600
 601/**
 602 * omap4_vc_i2c_timing_init - sets up board I2C timing parameters
 603 * @voltdm: voltagedomain pointer to get data from
 604 *
 605 * Use PMIC + board supplied settings for calculating the total I2C
 606 * channel capacitance and set the timing parameters based on this.
 607 * Pre-calculated values are provided in data tables, as it is not
 608 * too straightforward to calculate these runtime.
 609 */
 610static void __init omap4_vc_i2c_timing_init(struct voltagedomain *voltdm)
 611{
 612        u32 capacitance;
 613        u32 val;
 614        u16 hsscll;
 615        const struct i2c_init_data *i2c_data;
 616
 617        if (!voltdm->pmic->i2c_high_speed) {
 618                pr_warn("%s: only high speed supported!\n", __func__);
 619                return;
 620        }
 621
 622        /* PCB trace capacitance, 0.125pF / mm => mm / 8 */
 623        capacitance = DIV_ROUND_UP(sr_i2c_pcb_length, 8);
 624
 625        /* OMAP pad capacitance */
 626        capacitance += 4;
 627
 628        /* PMIC pad capacitance */
 629        capacitance += voltdm->pmic->i2c_pad_load;
 630
 631        /* Search for capacitance match in the table */
 632        i2c_data = omap4_i2c_timing_data;
 633
 634        while (i2c_data->load > capacitance)
 635                i2c_data++;
 636
 637        /* Select proper values based on sysclk frequency */
 638        switch (voltdm->sys_clk.rate) {
 639        case 38400000:
 640                hsscll = i2c_data->hsscll_38_4;
 641                break;
 642        case 26000000:
 643                hsscll = i2c_data->hsscll_26;
 644                break;
 645        case 19200000:
 646                hsscll = i2c_data->hsscll_19_2;
 647                break;
 648        case 16800000:
 649                hsscll = i2c_data->hsscll_16_8;
 650                break;
 651        case 12000000:
 652                hsscll = i2c_data->hsscll_12;
 653                break;
 654        default:
 655                pr_warn("%s: unsupported sysclk rate: %d!\n", __func__,
 656                        voltdm->sys_clk.rate);
 657                return;
 658        }
 659
 660        /* Loadbits define pull setup for the I2C channels */
 661        val = i2c_data->loadbits << 25 | i2c_data->loadbits << 29;
 662
 663        /* Write to SYSCTRL_PADCONF_WKUP_CTRL_I2C_2 to setup I2C pull */
 664        writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP +
 665                                OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2));
 666
 667        /* HSSCLH can always be zero */
 668        val = hsscll << OMAP4430_HSSCLL_SHIFT;
 669        val |= (0x28 << OMAP4430_SCLL_SHIFT | 0x2c << OMAP4430_SCLH_SHIFT);
 670
 671        /* Write setup times to I2C config register */
 672        voltdm->write(val, OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET);
 673}
 674
 675
 676
 677/**
 678 * omap_vc_i2c_init - initialize I2C interface to PMIC
 679 * @voltdm: voltage domain containing VC data
 680 *
 681 * Use PMIC supplied settings for I2C high-speed mode and
 682 * master code (if set) and program the VC I2C configuration
 683 * register.
 684 *
 685 * The VC I2C configuration is common to all VC channels,
 686 * so this function only configures I2C for the first VC
 687 * channel registers.  All other VC channels will use the
 688 * same configuration.
 689 */
 690static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
 691{
 692        struct omap_vc_channel *vc = voltdm->vc;
 693        static bool initialized;
 694        static bool i2c_high_speed;
 695        u8 mcode;
 696
 697        if (initialized) {
 698                if (voltdm->pmic->i2c_high_speed != i2c_high_speed)
 699                        pr_warn("%s: I2C config for vdd_%s does not match other channels (%u).\n",
 700                                __func__, voltdm->name, i2c_high_speed);
 701                return;
 702        }
 703
 704        /*
 705         * Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
 706         * erratum i531 "Extra Power Consumed When Repeated Start Operation
 707         * Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
 708         * Otherwise I2C4 eventually leads into about 23mW extra power being
 709         * consumed even during off idle using VMODE.
 710         */
 711        i2c_high_speed = voltdm->pmic->i2c_high_speed;
 712        if (i2c_high_speed)
 713                voltdm->rmw(vc->common->i2c_cfg_clear_mask,
 714                            vc->common->i2c_cfg_hsen_mask,
 715                            vc->common->i2c_cfg_reg);
 716
 717        mcode = voltdm->pmic->i2c_mcode;
 718        if (mcode)
 719                voltdm->rmw(vc->common->i2c_mcode_mask,
 720                            mcode << __ffs(vc->common->i2c_mcode_mask),
 721                            vc->common->i2c_cfg_reg);
 722
 723        if (cpu_is_omap44xx())
 724                omap4_vc_i2c_timing_init(voltdm);
 725
 726        initialized = true;
 727}
 728
 729/**
 730 * omap_vc_calc_vsel - calculate vsel value for a channel
 731 * @voltdm: channel to calculate value for
 732 * @uvolt: microvolt value to convert to vsel
 733 *
 734 * Converts a microvolt value to vsel value for the used PMIC.
 735 * This checks whether the microvolt value is out of bounds, and
 736 * adjusts the value accordingly. If unsupported value detected,
 737 * warning is thrown.
 738 */
 739static u8 omap_vc_calc_vsel(struct voltagedomain *voltdm, u32 uvolt)
 740{
 741        if (voltdm->pmic->vddmin > uvolt)
 742                uvolt = voltdm->pmic->vddmin;
 743        if (voltdm->pmic->vddmax < uvolt) {
 744                WARN(1, "%s: voltage not supported by pmic: %u vs max %u\n",
 745                        __func__, uvolt, voltdm->pmic->vddmax);
 746                /* Lets try maximum value anyway */
 747                uvolt = voltdm->pmic->vddmax;
 748        }
 749
 750        return voltdm->pmic->uv_to_vsel(uvolt);
 751}
 752
 753#ifdef CONFIG_PM
 754/**
 755 * omap_pm_setup_sr_i2c_pcb_length - set length of SR I2C traces on PCB
 756 * @mm: length of the PCB trace in millimetres
 757 *
 758 * Sets the PCB trace length for the I2C channel. By default uses 63mm.
 759 * This is needed for properly calculating the capacitance value for
 760 * the PCB trace, and for setting the SR I2C channel timing parameters.
 761 */
 762void __init omap_pm_setup_sr_i2c_pcb_length(u32 mm)
 763{
 764        sr_i2c_pcb_length = mm;
 765}
 766#endif
 767
 768void __init omap_vc_init_channel(struct voltagedomain *voltdm)
 769{
 770        struct omap_vc_channel *vc = voltdm->vc;
 771        u8 on_vsel, onlp_vsel, ret_vsel, off_vsel;
 772        u32 val;
 773
 774        if (!voltdm->pmic || !voltdm->pmic->uv_to_vsel) {
 775                pr_err("%s: No PMIC info for vdd_%s\n", __func__, voltdm->name);
 776                return;
 777        }
 778
 779        if (!voltdm->read || !voltdm->write) {
 780                pr_err("%s: No read/write API for accessing vdd_%s regs\n",
 781                        __func__, voltdm->name);
 782                return;
 783        }
 784
 785        vc->cfg_channel = 0;
 786        if (vc->flags & OMAP_VC_CHANNEL_CFG_MUTANT)
 787                vc_cfg_bits = &vc_mutant_channel_cfg;
 788        else
 789                vc_cfg_bits = &vc_default_channel_cfg;
 790
 791        /* get PMIC/board specific settings */
 792        vc->i2c_slave_addr = voltdm->pmic->i2c_slave_addr;
 793        vc->volt_reg_addr = voltdm->pmic->volt_reg_addr;
 794        vc->cmd_reg_addr = voltdm->pmic->cmd_reg_addr;
 795
 796        /* Configure the i2c slave address for this VC */
 797        voltdm->rmw(vc->smps_sa_mask,
 798                    vc->i2c_slave_addr << __ffs(vc->smps_sa_mask),
 799                    vc->smps_sa_reg);
 800        vc->cfg_channel |= vc_cfg_bits->sa;
 801
 802        /*
 803         * Configure the PMIC register addresses.
 804         */
 805        voltdm->rmw(vc->smps_volra_mask,
 806                    vc->volt_reg_addr << __ffs(vc->smps_volra_mask),
 807                    vc->smps_volra_reg);
 808        vc->cfg_channel |= vc_cfg_bits->rav;
 809
 810        if (vc->cmd_reg_addr) {
 811                voltdm->rmw(vc->smps_cmdra_mask,
 812                            vc->cmd_reg_addr << __ffs(vc->smps_cmdra_mask),
 813                            vc->smps_cmdra_reg);
 814                vc->cfg_channel |= vc_cfg_bits->rac;
 815        }
 816
 817        if (vc->cmd_reg_addr == vc->volt_reg_addr)
 818                vc->cfg_channel |= vc_cfg_bits->racen;
 819
 820        /* Set up the on, inactive, retention and off voltage */
 821        on_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->on);
 822        onlp_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->onlp);
 823        ret_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->ret);
 824        off_vsel = omap_vc_calc_vsel(voltdm, voltdm->vc_param->off);
 825
 826        val = ((on_vsel << vc->common->cmd_on_shift) |
 827               (onlp_vsel << vc->common->cmd_onlp_shift) |
 828               (ret_vsel << vc->common->cmd_ret_shift) |
 829               (off_vsel << vc->common->cmd_off_shift));
 830        voltdm->write(val, vc->cmdval_reg);
 831        vc->cfg_channel |= vc_cfg_bits->cmd;
 832
 833        /* Channel configuration */
 834        omap_vc_config_channel(voltdm);
 835
 836        omap_vc_i2c_init(voltdm);
 837
 838        if (cpu_is_omap34xx())
 839                omap3_vc_init_channel(voltdm);
 840        else if (cpu_is_omap44xx())
 841                omap4_vc_init_channel(voltdm);
 842}
 843
 844